CN101681255A - 通用数字块互连与通道布线 - Google Patents

通用数字块互连与通道布线 Download PDF

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CN101681255A
CN101681255A CN200880012232.1A CN200880012232A CN101681255A CN 101681255 A CN101681255 A CN 101681255A CN 200880012232 A CN200880012232 A CN 200880012232A CN 101681255 A CN101681255 A CN 101681255A
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CN101681255B (zh
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瓦伦·辛德
伯特·苏兰
哈尼夫·穆罕默德
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Cypress Semiconductor Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring

Abstract

本发明提供一种可编程布线方案，其在同一集成电路(IC)中在通用数字块(UDB)之间和在所述UDB与其它微控制器元件、外围设备及外部输入和输出(FO)之间提供改进的连接性。所述布线方案增加了函数的数目、灵活性和可编程架构的整体布线效率。所述UDB可成对地分组且共享相关联的水平布线通道。双向水平和垂直分段元件在不同UDB对之间水平地且垂直地延伸布线并到达其它外围设备和I/O。

Description

通用数字块互连与通道布线
本申请案主张2007年4月17日申请的第60/912,399号临时申请案和2007年12月27日申请的第11/965,291号待决的美国申请案的优先权，所述两个申请案均以引用的方式并入本文中。
技术领域
本发明大体上涉及可编程装置，且更明确地说，涉及可编程互连矩阵。
背景技术
现场可编程门阵列(FPGA)和可编程逻辑装置(PLD)已用于数据通信和电信系统中。常规的PLD和FPGA由可编程元件的阵列组成，其中所述元件经编程以实施固定函数或方程。一些当前可用的复杂PLD(CPLD)产品包括逻辑单元的阵列。常规的PLD装置具有若干缺陷，例如有限的速度和有限的数据处理能力。
在开发复杂的集成电路时，通常需要附加的外围单元，例如运算和仪用放大器、滤波器、定时器、数字逻辑电路、模/数和数/模转换器等。一般来说，这些额外的外围设备的实施产生附加的难题：用于新组件的额外空间、生产印刷电路板期间的附加维护以及增加的功率消耗。所有这些因素可显著影响工程项目的价格和开发周期。
可编程芯片上系统(PSoC)的引入特征在于数字和模拟可编程块，其允许实施大量外围设备。可编程互连允许组合模拟和数字块以形成广泛多种功能性模块。数字块由较小的可编程块组成且经配置以提供不同数字功能。模拟块用于开发模拟元件，例如模拟滤波器、比较器、反相放大器以及模/数和数/模转换器。当前的PSoC架构仅提供粗粒状的可编程性，其中仅少数固定函数可利用仅少量的连接选项。
发明内容
可编程互连矩阵包含将一个或一个以上数字块的不同群组可编程地耦合在一起的水平通道。互连矩阵可包含将不同水平通道可编程地互连在一起的分段元件。分段元件可包含水平分段开关，其将用于同一行中的不同数字块群组的水平通道可编程地耦合在一起。垂直分段开关可将用于不同行中的不同数字块群组的水平通道可编程地耦合在一起。
垂直通道可以可编程地连接不同行中的水平通道。与由连接不同行中的数字块的垂直通道提供的连接性相比，水平通道在位于相同行中的数字块之间提供更多连接性。同一数字块对中的两个数字块可紧密地耦合在一起以在同一相关联水平通道中共同布线，且不同数字块对可通过分段元件较不紧密地耦合在一起。
可编程开关经配置以将来自数字块的不同可选择信号连接到其相关联的水平通道。分段元件中的可编程三态缓冲器可经配置以将信号选择性地耦合在一起并在不同水平通道之间驱动所述信号。
随机存取存储器(RAM)可经配置以可编程地控制不同数字块如何通过互连矩阵而耦合在一起。未指定输入和输出(I/O)可通过互连矩阵中的不同可选择路线而可编程地耦合到不同可选择数字块中的不同可选择信号。未指定输入和输出是指集成电路(IC)上的到外部信号的连接。
微控制器系统通过互连矩阵而可编程地耦合到不同数字块，且通过互连矩阵而可编程地耦合到不同可编程输入/输出(I/O)。微控制器系统可包含微控制器、中断控制器和直接存储器存取(DMA)控制器。中断请求可通过互连矩阵而可编程地耦合在中断控制器与不同可选择数字块或不同可选择I/O之间。DMA请求也可通过互连矩阵而可编程地耦合在DMA控制器与不同可选择数字块或不同可选择I/O之间。在一个实施例中，微控制器、数字块、I/O和互连均位于同一集成电路中。
在一个实施例中，数字块包括可编程为不同逻辑功能的第一群组未委定逻辑元件，且还包含一起形成可编程算术定序器的第二群组结构性逻辑元件。
附图说明
图1为说明包含通用数字块(UDB)阵列的实例性PSoC架构的示意性框图；
图2为展示UDB阵列中的互连矩阵的示意性方框；
图3为展示一对UDB如何紧密地耦合到水平布线通道的示意性框图；
图4为展示将图3中的UDB连接到水平布线通道的可编程开关的示意性框图；
图5为展示互连矩阵中的分段元件的示意性框图；
图6为更详细地展示图5的分段元件中的不同可编程开关的示意性框图；
图7为展示图2的互连矩阵可如何将不同互连路径连接到微控制器系统的示意性框图；
图8为更详细地展示所述UDB中的一者的示意图；
图9为更详细地展示图8的UDB中的数据路径的示意图。
具体实施方式
介绍
新的可编程布线方案在同一集成电路(IC)中在通用数字块(UDB)之间和在UDB与其它微控制器元件、外围设备及外部输入和输出(I/O)之间提供改进的连接性。所述布线方案增加了函数的数目和可编程架构的整体布线效率。UDB可成对地分组且共享相关联的水平布线通道。双向水平和垂直分段元件在不同UDB对之间水平地且垂直地延伸布线并到达其它外围设备和I/O。
详细描述
图1是包含在可编程芯片上系统(PSoC)集成电路(IC)100内的通用数字块(UDB)阵列110的高级视图。UDB阵列110包含将不同UDB 120连接在一起的可编程互连矩阵130。个别UDB 120各自包含呈可编程逻辑装置(PLD)形式的未委定逻辑与形成在图8和图9中更详细展示的数据路径210的结构性指定逻辑元件的集合。
UDB阵列
UDB阵列110经布置成若干UDB对122，其各自包含可紧密地耦合到共享的水平布线通道132的两个UDB 120。所述UDB对122还可通过垂直布线通道134可编程地连接到同一水平行中或不同行中的其它UDB对122的水平布线通道132。水平和垂直布线通道以及其它开关元件统称为互连矩阵130。
数字系统互连(DSI)布线接口112将微控制器系统170和其它固定函数外围设备105连接到UDB阵列110。微控制器系统170包含微控制器102、中断控制器106和直接存储器存取(DMA)控制器108。其它外围设备105可为PSoC 100中的任何数字或模拟功能性元件。DSI 112为UDB阵列110的顶部和底部处的互连矩阵130的扩展。
图2更详细地展示互连矩阵130，且包含与一个或一个以上相关联的通用数字块(UDB)120可编程地连接的水平布线通道132。在此实例中，UDB 120的对122通过其相关联的水平布线通道132紧密地耦合在一起。然而，两个以上的UDB 120可通过同一水平布线通道132紧密地耦合在一起。
互连矩阵130还包含将不同水平布线通道132可编程地互连在一起的水平/垂直(H/V)分段元件125。分段元件125将用于相同行中的不同数字块对122的水平布线通道132耦合在一起。分段元件125还通过垂直布线通道134将用于不同行中的数字块对122的水平布线通道132可编程地耦合在一起。
图3更详细地展示UDB对122中的一者。UDB 120A与120B各自包含若干不同功能性块，其在一个实施例中包含两个可编程逻辑装置(PLD)200、数据路径210、状态和控制204以及时钟和复位控制202。这些不同功能性元件的操作以下在图8和图9中更详细地描述。
UDB对122中的两个UDB 120A与120B紧密地耦合在一起以在同一相关联水平布线通道132中共同布线。紧密耦合是指上部UDB 120A中的UDBI/O信号127与下部UDB 120B中的对应信号128均直接连接到同一相关联水平布线通道132。此紧密耦合提供所述两个UDB 120A与120B之间的高性能信令。举例来说，相对较短的连接127与128可以可编程地建立在上部UDB120A与下部UDB 120B之间。
在一个实施例中，与图2所示的垂直布线通道134相比，水平布线通道132还可具有连到UDB 120A与120B的较大数目的路线和连接。这允许水平布线通道132在UDB对122中的UDB 120A与120B之间提供较多互连性，且还在互连矩阵130的相同行中的不同UDB对122之间提供较多连接性。
因此，图1和图2中的互连矩阵130通过为较短/较高性能水平布线通道132提供比相对较长/较低性能垂直布线通道134多的迹线和连接性而更有效地使用芯片空间。
图4展示将图3中的UDB 120A与120B的不同I/O信号127与128连接到水平布线通道132的开关元件145。在此实例中，来自UDB对122中的上部UDB 120A的输出127A驱动下部UDB 120B中的输入128A。缓冲器138连接到UDB输出127A，且缓冲器140连接到UDB输入128A。输出127A与输入128A分别连接到垂直导线146与148，所述垂直导线146与148以规则图案与水平布线通道导线132A相交。
在开关点处，RAM位操作RAM单元136与138，所述RAM单元136与138又分别控制互补金属氧化物半导体(CMOS)传输门开关142与144。开关142与144当被激活时将UDB输出127A与UDB输入128A连接到水平布线通道导线132A。
可由微控制器102(图1)通过将值写入到配置RAM 410(图7)中而可编程地选择RAM单元136与137。这允许微控制器102选择性地激活或去激活门开关142与144中的任一者，并将来自两个通用数字块120A与120B中的任一者的任一I/O 127或128连接到水平通道132中的不同导线。
图5进一步详细展示图1和图2中先前所示的互连矩阵130。分段元件125可包含水平分段开关152和垂直分段开关154的不同组合。水平分段开关152将位于同一行中的邻近水平布线通道132可编程地耦合在一起。垂直分段开关152经由垂直布线通道134将垂直地位于邻近行中的水平布线通道132可编程地耦合在一起。
除了分段元件125之外，互连矩阵130包含图4中先前所示的开关元件145，其将上部和下部UDB 120A和120B与其相关联的水平布线通道132可编程地连接。
参看图5和图6，分段元件125包括耦合在不同水平布线通道132之间的水平分段开关152与耦合在垂直布线通道134之间的垂直分段开关154的阵列。每一分段开关152与154均由来自配置RAM 410(图7)的两个位162A与162B控制。所述两个位162A与162B一起控制三态缓冲器164。
当位162A被设定时，缓冲器164A将水平或垂直通道线路166中的一者从左向右驱动。当位162B被设定时，缓冲器164B将同一水平或垂直通道线路166从右向左驱动。如果位162A与位162B两者均不被设定，则缓冲器164A与164B将线路166驱动到高阻抗状态。
配置和可编程性
开关元件145、水平分段开关152和垂直分段开关154的任一组合可经可编程地配置以将外部I/O引脚104(图1)、UDB 120和微控制器系统元件170、固定外围设备105与UDB 120(图1)的几乎任何组合连接在一起。
图7展示不同类型的互连路径可如何通过互连矩阵130进行编程的不同实例。随机存取存储器(RAM)或一组配置寄存器410可由微控制器102直接读取和写入。出于说明的目的，配置寄存器410在图7中展示为独立RAM。然而，应理解，某些配置寄存器410可位于个别UDB 120内，而其它配置寄存器可为由多个不同功能性元件存取的独立寄存器。
RAM区段412中的第一组位与图4中所示的RAM单元136与137相关联，其控制UDB的输入和输出与其相关联的水平布线通道132之间的连接。RAM区段414中的第二组位控制图5和图6中的水平分段开关152如何将相同行中的水平布线通道132连接在一起，且RAM区段414中的其它位控制垂直分段开关154如何将不同行中的水平布线通道132连接在一起。
依据微控制器102编程RAM 410，互连矩阵130配置有将UDB 120C连接到中断控制器106的第一互连路径176。接着，UDB 120C可经由互连路径176将中断请求发送到DMA控制器108。第二互连路径178建立于PSoC芯片100(图1)中的外围设备(未图示)与DMA控制器108之间。外围设备经由互连路径178将DMA请求发送到DMA控制器108，所述互连路径178经由互连矩阵130建立。
还由微控制器102通过将位加载到RAM区段412与414中而配置第三互连路径180。DMA控制器108使用互连路径180将DMA终止信号发送到UDB120D。第四互连路径182可编程地配置在PSoC I/O引脚104中的一者与固定数字外围设备(例如，微控制器102)之间。互连路径182用于在微控制器102与I/O引脚104之间发送I/O信号。
互连路径176到182当然仅为可同时由互连矩阵130提供的许多不同互连配置的几个实例。此实例还展示不同I/O引脚104、UDB 120和其它外围设备可如何连接到中断控制器106上的同一中断线路或连接到DMA控制器108上的同一DMA线路。
通常，由中断控制器接收的中断请求和由DMA控制器接收的DMA请求可仅连接到一个指定引脚。互连矩阵130根据由微控制器102进行的对RAM410的编程而允许任何多种不同的可选择功能性元件或I/O引脚连接到中断控制器106或DMA控制器108的同一输入或输出。
互连矩阵130的可编程性还允许任何数目的或所有的I/O引脚104为未指定的且可完整地编程以连接到PSoC 100中的任何功能性元件。举例来说，引脚104可操作作为图7中的任何可选择功能性元件的输入引脚。在另一互连矩阵配置中，同一引脚104在连接到第一外围设备时可操作作为输出引脚，且在连接到不同外围设备时操作作为输出引脚。
通用数字块
图8为UDB 120中的一者的高级框图。主块包含一对可编程逻辑装置(PLD)200。所述PLD 200取得来自布线通道130的输入且形成经寄存的或组合的乘积和(sum-of-product)逻辑以实施状态机、对数据路径操作的控制、调节输入和驱动输出。
PLD块200实施状态机，执行输入或输出数据调节，且创建查找表。PLD200还可经配置以执行算术函数，定序数据路径210，且产生状态。PLD通常为所属领域的技术人员所已知，且因此不进一步详细描述。
数据路径块210包含高度结构化的指定逻辑，其实施可动态地编程的ALU、比较器和条件产生。状态和控制块204通过写入到控制输入并读取状态输出而允许微控制器固件与UDB 120交互并同步。
时钟和复位控制块202提供全局时钟选择、启用和复位选择。时钟和复位块202从可用全局系统时钟或总线时钟选择用于PLD块200、数据路径块210及状态和控制块204中的每一者的时钟。时钟和复位块202还向UDB 120供应动态和固件复位。
布线通道130通过可编程开关矩阵而连接到UDB I/O并在图7中的不同UDB之间提供连接。系统总线接口140将UDB 120中的所有寄存器和RAM映射到系统地址空间中，并可由微控制器102存取。
PLD 200和数据路径210分别具有链式信号212和214，所述链式信号212和214使相邻UDB 120能够链接在一起以创建较高精确度函数。从链中的先前邻近的UDB 120投送PLD进位链信号212，并通过两个PLD 200中的每一宏单元而路由所述信号。接着将进位输出路由到链中的下一个UDB 120。邻近UDB 120中的数据路径块210之间的数据路径链214提供类似的连接性。
参看图9，每一UDB 120包括由微控制器102加载到控制寄存器250中的用户定义的控制位的组合。控制寄存器250可为上文在图8中所描述的控制块202和204的部分。控制寄存器250馈入未委定可编程逻辑200。上文在图8中所描述的相同控制块202与204还包含相关联的状态寄存器256，其允许微控制器102可选择地读取数据路径210内的结构性算术元件254的不同内部状态。
数据路径210包括高度结构化的逻辑元件254，其包含可动态地编程的ALU 304、条件比较器310、累加器302和数据缓冲器300。ALU 304经配置以执行累加器302上的指令，并更新由序列存储器控制的序列。条件比较器310可与ALU 304并行地操作。数据路径210经进一步优化以实施例如定时器、计数器等典型的嵌入式功能。
指定数据路径模块210与未委定PLD 200的组合允许UDB 120提供具有较有效且较高速处理的嵌入式数字功能。指定的结构性算术元件254更有效地实施算术定序器操作以及其它数据路径功能。因为数据路径210为结构性的，所以需要较少门来实施结构性元件254，且需要较少互连来将结构性元件254一起连接到算术定序器中。对PLD实施同一数据路径210可能需要附加的组合逻辑和附加的互连。
数据路径210中的结构化逻辑也可高度地编程以提供广泛多种不同的可动态地选择的算术函数。因此，数据路径210不仅节省集成电路100(图1)上的空间，而且与其它结构化算术定序器相比还更易于存取和编程。
数据路径210的函数可配置性通过控制寄存器250而提供，且允许微控制器102任意地写入到系统状态中，且选择性地控制不同算术函数。状态寄存器256允许微控制器102还识别与不同的经配置算术运算相关联的不同状态。
由布线通道130提供的灵活的连接性方案选择性地将不同功能性元件250、200、254和256互连在一起并将这些功能性元件可编程地连接到其它UDB、I/O连接和外围设备。因此，未委定逻辑200、结构性逻辑254和可编程布线通道130的组合提供较多功能性、灵活性，且更有效地使用较少集成电路空间。
互连矩阵130还需要较少指定UDB块布线或者不需要任何指定UDB块布线。所有数据、状态、控制、信令等可通过UDB阵列110中的互连矩阵130而路由。阵列路由是有效的，因为在局部UDB网与跨越UDB阵列的网之间存在很小的差异或没有差异。水平和垂直分段允许阵列被分区以增加效率且对RAM 410的随机存取允许高速配置或运行中可重新配置性。
上文所描述的系统可使用指定的处理器系统、微控制器、可编程逻辑装置或执行一些或所有所述操作的微处理器。可以软件来实施上文所描述的一些操作，且可以硬件来实施其它操作。
为了方便起见，将操作描述为各种互连的功能性块或相异软件模块。然而，这不是必要的，且可为如下情况，这些功能性块或模块等效地聚集到单个逻辑装置、程序或操作中而没有清楚的边界。在任何情况下，功能性块和软件模块或柔性接口的特征可单独地或与其它操作结合地以硬件或软件来实施。
已以本发明的优选实施例描述和说明了本发明的原理，应明白，可在不脱离所述原理的情况下，在布置和细节上对本发明进行修改。主张在所附权利要求书的精神和范围内的所有修改和变化。

Claims (20)

1.一种设备，其包括：
数字块的阵列；以及
可编程互连矩阵，其包含将一个或一个以上数字块的不同群组可编程地耦合在一起的水平通道和将不同水平通道可编程地互连在一起的分段元件。
2.根据权利要求1所述的设备，其中所述分段元件包含：
水平分段开关，其将同一行中的所述水平通道可编程地耦合在一起；以及
垂直分段开关，其将不同行中的所述水平通道可编程地耦合在一起。
3.根据权利要求1所述的设备，其进一步包括垂直通道，所述垂直通道将不同行中的所述水平通道可编程地互连在一起，其中与位于不同行中的所述数字块之间的所述垂直通道所提供的连接性相比，所述水平通道在位于相同行中的所述数字块之间提供更多连接性。
4.根据权利要求1所述的设备，其中同一数字块对中的两个数字块紧密地耦合在一起以在同一相关联水平通道中共同布线，且不同数字块对通过所述分段元件较不紧密地耦合在一起。
5.根据权利要求1所述的设备，其进一步包括：
可编程地可选择通道开关，其经配置以将来自所述数字块的不同可选择信号连接到相关联的水平通道；以及
位于所述分段元件中的可编程三态缓冲器，其经配置以将信号选择性地耦合在一起并在所述不同水平通道之间驱动所述信号。
6.根据权利要求1所述的设备，其进一步包括随机存取存储器(RAM)，所述随机存取存储器(RAM)经配置以可编程地控制所述不同数字块如何通过所述互连矩阵耦合在一起。
7.根据权利要求1所述的设备，其包含输入和输出(I/O)，所述输入和输出(I/O)最初未指定到任何特定数字块，且通过所述互连矩阵中的不同可选择路线而可编程地耦合到不同可选择数字块。
8.根据权利要求1所述的设备，其进一步包括微控制器系统，所述微控制器系统通过所述互连矩阵而可编程地耦合到所述不同数字块且耦合到不同可选择输入和输出(I/O)。
9.根据权利要求8所述的设备，其中：
所述微控制器系统包含微控制器、中断控制器和直接存储器存取(DMA)控制器；
中断请求通过所述互连矩阵而可编程地耦合在所述中断控制器与不同可选择数字块或不同可选择I/O之间；且
DMA请求通过所述互连矩阵而可编程地耦合在所述DMA控制器与不同可选择数字块或不同可选择I/O之间。
10.根据权利要求9所述的设备，其中所述微控制器系统、数字块、I/O和互连矩阵均位于同一集成电路中。
11.根据权利要求1所述的设备，其中所述数字块各自包括：第一群组未委定逻辑元件，其可编程为不同逻辑功能；以及第二群组指定逻辑元件，其一起形成可编程算术定序器。
12.一种集成电路，其包括：
微控制器系统；
可编程互连，其包含水平通道和垂直通道；以及
存储器装置，其可由所述微控制器存取以控制所述集成电路中的功能性元件如何连接到所述水平通道且控制所述水平通道和垂直通道如何彼此连接。
13.根据权利要求12所述的集成电路，其进一步包括分段元件，所述分段元件具有：
水平分段开关，其将同一行中的所述水平通道可编程地耦合在一起；以及
垂直分段开关，其将不同行中的所述水平通道可编程地耦合在一起。
14.根据权利要求12所述的集成电路，其进一步包括：
可编程地可配置数字块，其根据加载到所述存储器装置中的位而选择性地耦合到所述水平通道。
15.根据权利要求14所述的集成电路，其进一步包括：
通道开关元件，其由所述存储器装置中的第一组存储器单元可编程地激活以用于将所述水平通道连接到所述数字块；以及
可编程三态缓冲器，其由所述存储器装置中的第二组存储器单元可编程地激活以用于将所述水平通道连接在一起。
16.根据权利要求14所述的集成电路，其进一步包括未指定外部输入和输出引脚，所述未指定外部输入和输出引脚通过所述可编程互连而可编程地耦合到所述微控制器系统中的不同输入和输出，且还通过所述可编程互连而可编程地耦合到所述不同数字块中的不同可选择功能性元件。
17.根据权利要求12所述的集成电路，其中所述微控制器系统进一步包括：
中断控制器，其通过所述可编程互连从不同可选择数字块或不同可选择I/O接收中断请求；以及
直接存储器存取(DMA)控制器，其通过所述可编程互连从不同可选择数字块或不同可选择I/O接收DMA请求。
18.一种方法，其包括：
提供互连矩阵；
对所述互连矩阵进行编程以将不同功能性元件连接到相关联的局部布线通道；
对所述互连矩阵进行编程以将不同局部布线通道互连在一起；以及
对所述互连矩阵进行编程以进一步通过全体布线通道将不同局部布线通道彼此连接。
19.根据权利要求18所述的方法，其进一步包括：
将第一组值写入到配置存储器中，所述第一组值控制所述功能性元件与所述相关联的局部布线通道之间的连接；
将第二组值写入到所述配置存储器中，所述第二组值控制不同局部布线通道之间的互连；以及
将第三组值写入到所述配置存储器中，所述第三组值控制所述局部布线通道与所述全体布线通道之间的互连。
20.根据权利要求18所述的方法，其进一步包括：
通过将不同外部引脚或不同内部功能性元件连接到内部中断控制器上的同一中断线路的所述互连矩阵对不同路径进行编程；或
通过将不同外部引脚或不同内部功能性元件连接到内部DMA控制器上的同一直接存储器存取(DMA)线路的所述互连矩阵对不同路径进行编程。
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US8482313B2 (en) 2013-07-09
CN101681255B (zh) 2014-06-18
US7737724B2 (en) 2010-06-15
US20140013022A1 (en) 2014-01-09
US20080258759A1 (en) 2008-10-23
US20110304354A1 (en) 2011-12-15

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