CN101567326B - Printed circuit board and method for forming same - Google Patents
Printed circuit board and method for forming same Download PDFInfo
- Publication number
- CN101567326B CN101567326B CN 200810095810 CN200810095810A CN101567326B CN 101567326 B CN101567326 B CN 101567326B CN 200810095810 CN200810095810 CN 200810095810 CN 200810095810 A CN200810095810 A CN 200810095810A CN 101567326 B CN101567326 B CN 101567326B
- Authority
- CN
- China
- Prior art keywords
- support plate
- electronic component
- film
- circuit board
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The embodiment of the invention discloses a printed circuit board and a method for forming the same. The method for forming the printed circuit board comprises the following steps: providing a supportplate, forming a first circuit on the support plate, settling a thin film on the support plate; using the thin film to arrange an electronic part on the support plate, enabling the electronic part to be electrically connected with the first circuit, forming a dielectric layer to cover the electronic part in a carpeting way, and removing the support plate. The embodiment of the invention is benefi cial to reducing the size of a finished electronic product.
Description
Technical field
The present invention relates to a kind of printed circuit board (PCB) and forming method thereof, especially about a kind of printed circuit board (PCB) that is embedded with electronic component and forming method thereof.
Background technology
Printed circuit board (PCB) (printed circuit board) is a kind of mechanism that consists of the circuit pattern that interconnects between each electronic component.Figure 1 shows that the schematic diagram of traditional printing circuit board 10 and electronic component such as integrated circuit 20 and passive device 30 interconnection.As described in Figure, known printed circuit board (PCB) 10 adopts the surface to glue the mode of dress with the interconnection system of integrated circuit 20, wherein integrated circuit 20 is to have encapsulated and have the electronic component of pin 21, sees through circuit 11 that welding makes pin 21 and printed circuit board (PCB) 10 and joins and finish interconnection.
The compact trend of electronic product is so that traditional printing circuit board 10 can not meet demand gradually now.For example, because electronic component is contained on the surface of printed circuit board (PCB) 10, so printed circuit board (PCB) 10 must provide enough surface area for it, thereby dwindling of its size is restricted.Moreover the known integrated circuit 20 that is installed on the printed circuit board (PCB) 10 all is the product of having finished encapsulation usually, so its volume will be more much larger than the volume of the former not naked core of encapsulation, this point makes too the size of final electronic product dwindle and is restricted.Therefore, need a kind of structure and method of improvement to solve known problem.
Summary of the invention
The invention provides a kind of printed circuit board (PCB) that is embedded with electronic component, its practice is to utilize printed circuit board technology to form first circuit at a temporary transient support plate, then directly build electronic component at temporary transient support plate, such as diode, transistor and other optoelectronic semiconductor etc., and make the therewith electronic component electrical connection of this circuit.Then, utilize suitable insulating material with this circuit therewith electronic component encapsulate simultaneously.After finishing, encapsulation more temporary transient support plate is removed.
The present invention has the following characteristics that help to dwindle the size of final electronic product at least: electronic component is embedded in the packaging insulating layer; Electronic component is directly to make at support plate, will encapsulate simultaneously with circuit after it completes; After circuit and electronic component are transferred to the packaging insulating layer, remove temporary transient support plate to reduce thickness.
According to an embodiment, the invention provides a kind of formation method of printed circuit board (PCB), comprising provides a support plate; Form one first circuit on support plate; Deposit a film on support plate; Utilize film to build an electronic component on support plate, electronic component is electrically connected the first circuit; Code-pattern ground forms a dielectric layer to coat electronic component; Remove dielectric layer a part so that a upper surface of electronic component expose; Form one second circuit on dielectric layer, the second line electricity connecting electronic part; Form an insulating barrier to cover the second circuit and dielectric layer; And remove support plate.
According to another embodiment, the invention provides a kind of formation method of printed circuit board (PCB), comprising provides a support plate; Form one first circuit on support plate; Build an electronic component on support plate, electronic component is electrically connected the first circuit; Code-pattern ground forms a dielectric layer to coat electronic component; Remove dielectric layer a part so that a upper surface of electronic component expose; Form one second circuit on dielectric layer, the second line electricity connecting electronic part; Form an insulating barrier to cover this second circuit and this dielectric layer; And remove this support plate.
Description of drawings
Fig. 1 shows the schematic diagram of known printed circuit board (PCB) and electronic component interconnection.
Fig. 2 A to 2I is the manufacturing process schematic diagram of the printed circuit board (PCB) that is embedded with electronic component of first embodiment of the invention.
Fig. 3 A to 3D is the manufacturing process schematic diagram of the printed circuit board (PCB) that is embedded with electronic component of second embodiment of the invention.
Fig. 4 A to 4C is the manufacturing process schematic diagram of the printed circuit board (PCB) that is embedded with electronic component of third embodiment of the invention.
Description of reference numerals
10 printed circuit board (PCB)s
11 circuits
20 integrated circuits
21 pins
30 passive devices
200 support plates
201 first circuits
202 films
202a one end
203 ray structure layers
The 203a upper surface
204 first electrical semiconductor layers
205 luminescent layers
206 second electrical semiconductor layers
210 dielectric layers
220 second circuits
230 insulating barriers
300 support plates
301 first circuits
302 films
302a one end
303 transistor arrangements
The 303a upper surface
304 source electrodes
305 drain electrodes
306 gate insulators
307 grids
310 dielectric layers
320 second circuits
330 look edge layers
400 support plates
401 first circuits
403 electroluminescence body structures
The 403a upper surface
404 electron injecting layers
405 electronic conductive layers
406 electroluminescence layers
407 hole transmission layers
408 hole injection layers
410 dielectric layers
420 second circuits
430 insulating barriers
Embodiment
Below with reference to appended diagram demonstration the preferred embodiments of the present invention.Similar components adopts identical component symbol in the appended diagram.Should note presenting the present invention for clear, each element in the appended diagram is not the scale according to material object, and for avoiding fuzzy content of the present invention, below known spare part, associated materials and correlation processing technique thereof are also omitted in explanation.
Fig. 2 A to 2I is the first embodiment of the present invention, and illustration has the making flow process of the printed circuit board (PCB) of flush type light-emitting diode.With reference to figure 2A, a support plate 200 is provided and forms one first circuit 201 on support plate 200.Support plate 200 can be any suitable substrate, especially take the conducting metal substrate as good, and for example copper clad laminate or stainless thin alloy sheets.The formation of the first circuit 201 can utilize known printed circuit board technology.For example, can be coated with dry film at support plate 200; Then with the surface of dry film patterning with the support plate 200 under exposing; On the surface of the support plate 200 that then plating conductor material such as copper nickel equal to expose take dry film as mask; And then dry film divested to form the first circuit 201.
With reference to figure 2B, deposit a film 202 on support plate 200.Preferred, film 202 is formed directly on the surface of support plate 200, and film 202 has an end 202a and connects the first circuit 201.Film 202 is the growth substrate of the follow-up light-emitting diode that will form.Take growth LED epitaxial layer as example, the material of film 202 can be GaAs (GaAs), indium phosphide (InP), gallium phosphide (GaP), sapphire (sapphire), carborundum (SiC) etc.Film 202 can have the patterning profile.The formation of film 202 can be adopted suitable thin film deposition and mask technique, and example is the techniques such as sputter, vapour deposition or screen printing as is known.
With reference to figure 2C, take film 202 as substrate, utilize known epitaxy technology and semiconductor deposition technology to form ray structure layer 203 on support plate 200.Ray structure layer 203 can comprise several epitaxial loayers such as one first electrical semiconductor layer 204, luminescent layer 205 and one second electrical semiconductor layer 206.For example, the first electrical semiconductor layer 204 can be N-shaped (Al
xGa
1-x)
0.5In
0.5The P epitaxial loayer; Luminescent layer 205 bags are the (Al of undoped
xGa
1-x)
0.5In
0.5The P epitaxial loayer, and the second electrical semiconductor layer 206 can be p-type (Al
xGa
1-x)
0.5In
0.5The P epitaxial loayer.The relative thickness of controlled made membrane 202, the first electrical semiconductor layer 204 and the first circuit 201 is so that the first electrical semiconductor layer 204 is electrically connected the first circuit 201.It should be noted that luminescent layer 205 and one second electrical semiconductor layer 206 can not touch the first circuit 201, otherwise will make ray structure layer 203 lose function.Except each above-mentioned epitaxial loayer, ray structure layer 203 also can comprise other functional structure, for example ohmic contact layer, barrier layer, and reflector etc.
With reference to figure 2D, code-pattern ground forms a dielectric layer 210 and coats ray structure layer 203 and the first circuit 201.Dielectric layer 210 is preferably then optional from spin coating glass, silicones, epoxy resin (Epoxy), pi (polyimide) or mistake fluorine cyclobutane (prefluorocyclobutane, PFCB) etc.Can utilize known accurate coating process to finish this step.Should note before carrying out this step ray structure layer 203 un-encapsulated.
With reference to figure 2E, the part with appropriate chemical mechanical polishing technology removal dielectric layer 210 is exposed a upper surface 203a of ray structure layer 203.Then, with reference to figure 2F, form one second circuit 220 on dielectric layer 210, and make the second circuit 220 be electrically connected ray structure layers 203 via suitably controlling.For example, can form first the dry film of patterning on the upper surface 203a of dielectric layer 210 and ray structure layer 203; Then with this patterning dry film as mask, utilize the sputter technology to inject the electric conducting material crystal seed; Then, see through this kind and carry out electroplating technology to form the second circuit 220 on the surface of dielectric layer 210, this second circuit 220 also contacts the upper surface 203a of ray structure layer 203 simultaneously to reach electrical connection.In addition, also can use screen printing technique, conductor material such as copper cream silver paste etc. is printed on the dielectric layer 210 to form the second circuit 220.
Then, with reference to figure 2G, code-pattern ground forms an insulating barrier 230 to link the second circuit 220, ray structure layer 203 and dielectric layer 210.The material of insulating barrier 230 can be polyesters, pi (polyimide) class, wherein can contain suitable organic supporting material.The mode that can be coated with forms insulating barrier 230, or the above-mentioned material pressing is affixed in flakes again on the surface of the second circuit 220 and ray structure layer 203.Can suitably adjust thickness and the intensity of insulating barrier 230, make it be enough to supporting layer as each above-mentioned element, so support plate 200 can be removed, form the structure shown in Fig. 2 H.Support plate 200 remove available known etching technique.
Fig. 2 I shows the selectivity step after Fig. 2 H.As shown in the figure, can utilize etching that film 202 is removed, because film 202 may be light absorbent, so it is removed the brightness that can increase light-emitting diode.In addition, as shown in the figure, can optionally suitably grind insulating barrier 230 and the second circuit 220 is exposed.
Should understand via above-mentioned, the present invention is not integrally sticking being loaded on the support plate of the electronic component that directly will complete (for example being the electronic component of generally having finished encapsulation).The present invention provides a kind of method of integrating printed circuit board technology and semiconductor technology or other electronic component technique.In brief, the present invention utilizes first printed circuit board technology to form one external circuit on support plate, then directly utilizes semiconductor technology or other electronic component technique progressively to set up the primary structure of electronic component at support plate; Recycling afterwards printed circuit board technology forms another road external circuit and is electrically connected with electronic component.The electronic component of first embodiment of the invention presents a demonstration with light-emitting diode, so should be appreciated that except light-emitting diode, the method that the first embodiment discloses also is applicable to other diodes, engages diode, photodiode (photodiode), reaches laser diode such as PN.
Fig. 3 A to 3D illustration second embodiment of the present invention.The difference of the second embodiment and the first embodiment is that its electronic component of imbedding is a transistor.In detail, as shown in Figure 3A, a support plate 300 is provided and forms one first circuit 301 on support plate 300.Then with reference to figure 3B, deposit a film 302 on support plate 300.Preferred, film 302 is formed directly on the surface of support plate 300, and film 302 has an end 302a and connects the first circuit 301.Film 302 is the growth substrate of the follow-up semiconductor transistor that will form.As example, the material of film 302 can be silicon (Si), GaAs (GaAs), indium phosphide (InP), gallium phosphide (GaP), sapphire (sapphire), carborundum (SiC) etc.The formation of film 302 can be adopted suitable known technology, techniques such as sputter, vapour deposition or screen printing.
With reference to figure 3C, take film 302 as substrate, utilize known semiconductor technology and suitable semi-conducting material to form transistor arrangement 303.Transistor arrangement 303 comprises source electrode 304, drain electrode 305, gate insulator 306 and grid 307, wherein source electrode 304 and drain and 305 connect respectively the first circuit 301.The subsequent step of Fig. 3 C is then similar with the first embodiment.Shown in Fig. 3 D, code-pattern ground forms a dielectric layer 310 to coat upside-down mounting lamellar body tubular construction 303 and the first circuit 301, should note before carrying out this step transistor arrangement 303 un-encapsulated.Then, the part with appropriate chemical mechanical polishing technology removal dielectric layer 310 is exposed a upper surface 303a of transistor arrangement 303.Then, form one second circuit 320 on dielectric layer 310, and make the second circuit 320 be electrically connected transistor arrangements 303 via suitably controlling.Then, code-pattern ground forms an insulating barrier 330 to link the second circuit 320, transistor arrangement 303 and dielectric layer 310.Can suitably adjust thickness and the intensity of insulating barrier 330, make it be enough to supporting layer as each above-mentioned element, again support plate 300 be removed at last.
The electronic component of second embodiment of the invention presents a demonstration with MOS transistor, should be appreciated that so other transistors such as bipolar transistor, the CMOS transistor etc. beyond the MOS transistor also are applicable to the present invention.
Fig. 4 A to 4C illustration third embodiment of the present invention.The difference of the 3rd embodiment and aforementioned two embodiment is that the manufacture method of its electronic component does not contain formation film 202 and 302 etc. as the step of growth substrate.In other words, make the also technique of available non high temperature of flush type electronic component of the present invention, for example vacuum vapour deposition, method of spin coating or typography (Printing Process), wire mark (Screen Printing), ink-jet seal (Inkjet Printing) and contact print (Contact Printing) etc.The electronic component of the 3rd embodiment is namely take electroluminor (Electroluminescence) as example.In detail, shown in Fig. 4 A, a support plate 400 is provided and forms one first circuit 401 on support plate 400.Then with reference to figure 4B, utilize above-mentioned evaporation, coating or printing technology to merge suitable mask technique and form electroluminescence body structure 403.Electroluminescence body structure 403 comprises electron injecting layer 404, electronic conductive layer 405, electroluminescence layer 406, hole transmission layer 407, reaches hole injection layer 408.The material of electron injecting layer 404 can be the organic material of doping alkalinous metal; Electronic conductive layer 405 can be oxadiazoles (Oxadiazole), triazole (Triazoles) or phenanthrolene (Phenanthroline); Electroluminescence layer 406 can be the macromolecule that contains various fluorchromes; Hole transmission layer 407 can be the allyl amine compounds; Hole injection layer 408 can be the organic material of doping lewis' acid.The subsequent step of Fig. 4 B is then similar with the first embodiment and the second embodiment.Shown in Fig. 4 C, code-pattern ground forms a dielectric layer 410 to coat electric electroluminescence body structure 403 and the first circuit 401, should note before carrying out this step electroluminescence body structure 403 un-encapsulated.Then, the part with appropriate chemical mechanical polishing technology removal dielectric layer 410 is exposed a upper surface 403a of electroluminescence body structure 403.Then, form one second circuit 420 on dielectric layer 410, and make the second circuit 420 be electrically connected electroluminescence body structures 403 via suitably controlling.Then, code-pattern ground forms an insulating barrier 430 binding the second circuit 420, electroluminescence body structure 403 and dielectric layers 410.Can suitably adjust the thickness of insulating barrier 430, make it be enough to supporting layer as each above-mentioned element, again support plate 400 be removed at last.
The electronic component of aforementioned each embodiment of the present invention presents a demonstration with light-emitting diode, transistor, electroluminor, so should be appreciated that except these electronic components, and other is fit to the electronic component of above-mentioned technique, and for example the fiber optic conduction part is also in scope of the present invention.
The above is the preferred embodiments of the present invention only, is not to limit claim of the present invention; All other do not break away from the equivalence of finishing under the disclosed spirit and changes or modification, all should be included in the following application thickness claim.
Claims (8)
1. the formation method of a printed circuit board (PCB) comprises:
One support plate is provided;
Form one first circuit on this support plate;
Deposit a film on this support plate;
Utilize this film to build an electronic component on this support plate, this electronic component is electrically connected this first circuit, and wherein this utilizes this film to build this electronic component to comprise take this film as substrate grown one epitaxial structure on this film in the step on this support plate;
Code-pattern ground forms a dielectric layer to coat this electronic component;
Remove this dielectric layer a part so that a upper surface of this electronic component expose;
Form one second circuit on this dielectric layer, this second line electricity connects this electronic component;
Form an insulating barrier and cover this second circuit and this dielectric layer; And
Remove this support plate,
Wherein the method does not comprise directly this electronic component sticking being loaded on this support plate integrally,
Wherein code-pattern ground form this dielectric layer with this step that coats this electronic component before, this electronic component un-encapsulated.
2. the method for claim 1, wherein this support plate is a metal substrate, and the step utilization that forms this first circuit is electroplated.
3. the method for stating such as claim 1, wherein the material of this film is selected from the group that following items forms: silicon, GaAs, indium phosphide, gallium phosphide, sapphire, and carborundum.
4. the method for claim 1, wherein this film of this deposition utilizes sputter, chemical vapour deposition (CVD) or screen printing in the step of this support plate.
5. the method for claim 1, wherein this electronic component is a diode.
6. method as claimed in claim 5, wherein this diode comprises PN junction diode, photodiode, light-emitting diode, and laser diode.
7. the method for claim 1, wherein this utilizes this film to build this electronic component to comprise take this film in the step on this support plate and utilize semiconductor technique to form a transistor arrangement on this support plate as substrate.
8. printed circuit board (PCB), this printed circuit board (PCB) is made with the method for claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810095810 CN101567326B (en) | 2008-04-24 | 2008-04-24 | Printed circuit board and method for forming same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810095810 CN101567326B (en) | 2008-04-24 | 2008-04-24 | Printed circuit board and method for forming same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101567326A CN101567326A (en) | 2009-10-28 |
| CN101567326B true CN101567326B (en) | 2013-04-17 |
Family
ID=41283427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810095810 Expired - Fee Related CN101567326B (en) | 2008-04-24 | 2008-04-24 | Printed circuit board and method for forming same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101567326B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI551207B (en) * | 2014-09-12 | 2016-09-21 | 矽品精密工業股份有限公司 | Substrate structure and fabrication method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4635356A (en) * | 1984-12-28 | 1987-01-13 | Kabushiki Kaisha Toshiba | Method of manufacturing a circuit module |
| US5497033A (en) * | 1993-02-08 | 1996-03-05 | Martin Marietta Corporation | Embedded substrate for integrated circuit modules |
| CN1477688A (en) * | 2002-07-31 | 2004-02-25 | 印芬龙科技股份有限公司 | Semiconductor module and method for mfg. semiconductor module |
| CN101102649A (en) * | 2006-07-06 | 2008-01-09 | 三星电机株式会社 | Buried pattern substrate and manufacturing method thereof |
-
2008
- 2008-04-24 CN CN 200810095810 patent/CN101567326B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4635356A (en) * | 1984-12-28 | 1987-01-13 | Kabushiki Kaisha Toshiba | Method of manufacturing a circuit module |
| US5497033A (en) * | 1993-02-08 | 1996-03-05 | Martin Marietta Corporation | Embedded substrate for integrated circuit modules |
| CN1477688A (en) * | 2002-07-31 | 2004-02-25 | 印芬龙科技股份有限公司 | Semiconductor module and method for mfg. semiconductor module |
| CN101102649A (en) * | 2006-07-06 | 2008-01-09 | 三星电机株式会社 | Buried pattern substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101567326A (en) | 2009-10-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105637636B (en) | Method for manufacturing opto-electronic semiconductor module and opto-electronic semiconductor module | |
| CN106409760B (en) | The method of semiconductor devices and encapsulation semiconductor element | |
| CN105977232B (en) | In a substrate the method for installing device, the board structure and electronic device of device are installed | |
| CN102194717B (en) | Semiconductor device and form the method for insulating barrier around semiconductor element | |
| CN102386113B (en) | A kind of semiconductor device and manufacture method thereof | |
| US7452751B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN103943553B (en) | The method that there is the low profile of perpendicular interconnection unit to be fanned out to formula encapsulation for semiconductor devices and formation | |
| CN102024716B (en) | The method of semiconductor device and manufacture semiconductor device | |
| CN102194740B (en) | Semiconductor device and method of forming the same | |
| CN105103314B (en) | Semiconductor devices and the method being used for producing the semiconductor devices | |
| US9082767B2 (en) | Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package | |
| US20120286240A1 (en) | Methods of Fabricating Light Emitting Diode Packages | |
| CN110010553A (en) | Form the semiconductor devices and method of ultra high density embedded semiconductor die package | |
| CN102412197A (en) | Semiconductor device and method of forming conductive tsv with insulating annular ring | |
| CN102194718A (en) | Semiconductor device and method of forming the same | |
| KR19990071551A (en) | Vertically integrated semiconductor device and manufacturing method | |
| CN104704632B (en) | Opto-electronic device with integrated protection diode and the method for its manufacture | |
| CN104701307B (en) | Planar high-voltage series LED integrated chip and its manufacturing method | |
| CN107534040A (en) | Arrangement of optoelectronic components and the method for manufacturing a large amount of arrangement of optoelectronic components | |
| CN110299376A (en) | Show equipment | |
| KR102598519B1 (en) | Semiconductor device and method for fabricating the same | |
| US20100025095A1 (en) | Device Carrying an Intergrated Circuit/Components and Method of Producing the Same | |
| US20230245944A1 (en) | Fan-out type package preparation method of fan-out type package | |
| WO2014142448A1 (en) | Wafer level chip scale light emitting diode package | |
| CN101567326B (en) | Printed circuit board and method for forming same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130417 Termination date: 20140424 |