CN101299223B - Emulation method and device of high speed serial duct receiver balance - Google Patents
Emulation method and device of high speed serial duct receiver balance Download PDFInfo
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- CN101299223B CN101299223B CN2008101114682A CN200810111468A CN101299223B CN 101299223 B CN101299223 B CN 101299223B CN 2008101114682 A CN2008101114682 A CN 2008101114682A CN 200810111468 A CN200810111468 A CN 200810111468A CN 101299223 B CN101299223 B CN 101299223B
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Abstract
A high speed serial channel receiver balanced emulation method includes: constructing a full chain circuit emulation file of the high speed serial channel; executing full chain circuit time-domain eye chart emulation aiming at the full chain circuit emulation file; extracting the excitation signal of the receiver according to the full chain circuit channel response; constructing every equalizing emulation file under different receiving balancing setting by the receiver circuit model according to the excitation signal, respectively extracting the receiver equalizing time-domain eye chart emulation aiming at every equalizing emulation file, thereby acquiring the optimum equalizing signal output of the receiver. After judging the pre-emphasis setting of the driver circuit model required to modify and executing accordingly modify, the steps are executed repeatly. the invention shortens the equalizing simulated time of the receiver, reduces the emulation internal memory occupation, thereby the high speed serial channel emulation efficiency can be boosted.
Description
Technical field
The present invention relates to high-speed serial channel signal integrity emulation technology, relate in particular to emulation mode and the device adjusted according to the receiver side parametric equalizer.
Background technology
Along with digital interconnect system speed and bandwidth constantly rise, the high-speed serial interconnect technology is more and more widely used, and the design of high-speed serial interconnect system and emulation just become the emphasis and the difficult point of current techniques.At present, the emulation of high-speed serial interconnect system all is based upon on the basis of full link, driver and receiver use the encrypted circuit model of chip manufacturer, passive interconnecting channel uses multiple model, as with scattering parameter, multi-thread coupling model, all-wave integrated circuit simulating program SPICE (Simulation Program withIntegrated Circuit Emphasis) model way of combining, because driver, receiver operation speed height has also used multiple signal processing technology, pre-emphasis as transmitter side, the equilibrium of receiver side, moreover, existing Model in Time Domain also has frequency-domain model in the model of passive interconnecting channel, and will obtain eye pattern and need carry out the emulation of a large amount of successive bits, so the eye pattern emulation of full link needs a large amount of simulation time and computer resource.
Because output pre-emphasis rank on the high speed serialization transceiver and input uniform rank are adjustable respectively, when carrying out emulation, find pre-emphasis an of the best and the balanced combination that is provided with, and the possibility of this combination fork is many, need emulation one by one to attempt, each trial all needs to carry out the emulation of (comprising drive circuit, interconnecting channel and acceptor circuit) of full link, just can obtain simulation result through for a long time calculating, and need a large amount of computer resource of cost.
Therefore, how to improve the high-speed serial channel simulation efficiency, shorten simulation time and also reduce computer resource, become a problem demanding prompt solution and put in face of the deviser.
Summary of the invention
Technical matters to be solved by this invention provides a kind of emulation mode and device of high speed serial duct receiver balance, can improve the simulation efficiency of high-speed serial channel, and need not spend a large amount of computer resources.
In order to solve the problems of the technologies described above, the invention provides a kind of emulation mode of high speed serial duct receiver balance, comprising: the full link simulation file that makes up described high-speed serial channel; Carry out full link time domain eye pattern emulation at full link simulation file, obtain full link channel response; Pumping signal according to this full link channel response extraction receiver; Construct different each balanced simulation document that receive under balanced the setting by the acceptor circuit model according to this pumping signal, carry out receiver balance time domain eye pattern emulation respectively, thereby obtain the best equalizing signal output of receiver at each balanced simulation document;
The full link simulation file of described structure high-speed serial channel is specially: according to the grammar request of time-domain-simulation device, drive circuit model, interconnecting channel model and described acceptor circuit model be connected successively and make up the full link simulation file of described high-speed serial channel;
Described constructing different receive balanced each the balanced simulation document down that are provided with and be specially: described acceptor circuit model constructs described each balanced simulation document according to described pumping signal and the ongoing described result who receives balanced setting.
Further, said method also comprises: after the pre-emphasis setting of judging needs modification drive circuit model and correspondingly revising, repeat each step of said method.
Further, the best equalizing signal output of receiver is to go out different receiver balance signals according to each receiver balance time domain eye pattern emulation to select to draw.
In order to solve the problems of the technologies described above, the invention provides a kind of simulator of high speed serial duct receiver balance, comprise the full link simulation circuit model of high speed, time domain eye pattern emulation device and the receiver side pumping signal extraction apparatus that connect successively, wherein:
At a high speed full link simulation circuit model is used for drive circuit model, interconnecting channel model and acceptor circuit model are connected successively, constructs the full link simulation file output of high speed serialization; Describedly construct the output of the full link simulation file of high speed serialization and be specially: the full link simulation circuit model of described high speed is according to the grammar request of time-domain-simulation device, described drive circuit model, described interconnecting channel model and described acceptor circuit model are carried out described connection, generate full link simulation net meter file, as described full link simulation file output;
Time domain eye pattern emulation device is connected with the acceptor circuit model, is used for carrying out full link time domain eye pattern emulation at this full link simulation file, obtains full link channel response and outputs to receiver side pumping signal extraction apparatus; And the balanced simulation document of receiver circuit model output carried out receiver balance time domain eye pattern emulation, obtain the best equalizing signal output of receiver;
Receiver side pumping signal extraction apparatus is connected with the acceptor circuit model, is used for the pumping signal output from this full link channel response extraction receiver;
The acceptor circuit model is used for constructing different each balanced simulation document that receive under balanced the setting according to the pumping signal of importing and outputs to time domain eye pattern emulation device; Described constructing different receive balanced each the balanced simulation document down that are provided with and be specially: described acceptor circuit model constructs described each balanced simulation document according to described pumping signal and the ongoing described result who receives balanced setting.
Further, at a high speed full link simulation circuit model also is used for the drive circuit model is carried out after pre-emphasis revises, rebuild full link simulation file and output to time domain eye pattern emulation device, thereby carry out the receiver balance time domain eye pattern emulation of different pre-emphasis under being provided with.
Further, time domain eye pattern emulation device obtains the best equalizing signal output of receiver, is to go out different receiver balance signals according to each receiver balance time domain eye pattern emulation to select to draw.
The present invention compares with classic method, only need carry out the once emulation of full link, after from the simulation result of full link, extracting the input signal of receiver, just can carry out repeatedly fast different receiver balances under being provided with emulation and obtain simulation result, so simulation time, emulation EMS memory occupation can be reduced into respectively less than original 1/3; Specific targets are relevant with the complexity of transceiver model, interconnecting channel model, and model is complicated more, use the improved efficiency of this method big more.Owing to shortened the time of receiver balance emulation, reduced the emulation EMS memory occupation, therefore reach the effect that improves the high-speed serial channel simulation efficiency.
Description of drawings
Fig. 1 is the simulator structured flowchart of high speed serial duct receiver balance of the present invention;
Fig. 2 is the emulation mode process flow diagram of high speed serial duct receiver balance of the present invention.
Embodiment
The emulation mode of high speed serial duct receiver balance of the present invention and device, comprise: with the drive circuit model, interconnecting channel model and acceptor circuit model connect successively according to the interconnected relationship of high-speed serial channel, the full link simulation file of the high speed serialization that constructs thus, send into and carry out full link time domain eye pattern emulation in the high speed serialization link time domain eye pattern emulation device, receiver side pumping signal extraction apparatus is sent in the full link channel response of obtaining, extraction obtains the receiver pumping signal, this pumping signal is connected with the acceptor circuit model, obtain balanced simulation document, send in the high speed serialization link time domain eye pattern emulation device and carry out receiver balance emulation, obtain the receiver balance signal.Revise if desired and receive balanced the setting, then after modification reception equilibrium is provided with, only need repeat and obtain balanced simulation document and later step thereof by the acceptor circuit model, and needn't carry out full link simulation, improved the high-speed serial channel simulation efficiency thus greatly.
Below in conjunction with accompanying drawing and preferred embodiment technique scheme of the present invention is described in further detail.
The structure of the simulator of high speed serial duct receiver balance of the present invention as shown in Figure 1, this device 100 comprises successively the full link simulation circuit model 110 of high speed, time domain eye pattern emulation device 120 and the receiver side pumping signal extraction apparatus 130 that connects; Wherein:
At a high speed full link simulation circuit model 110, be used for grammar request according to the time-domain-simulation device, drive circuit model 1101, interconnecting channel model 1102 and acceptor circuit model 1103 are connected, generate full link simulation net meter file, as the full link simulation file output of high speed serialization;
Time domain eye pattern emulation device 120 is connected with acceptor circuit model 1103, is used for full link simulation file is carried out the time domain eye pattern emulation, obtains full link channel response and outputs to receiver side pumping signal extraction apparatus 130; And the balanced simulation document of receiver circuit model 1103 output carried out receiver balance time domain eye pattern emulation, obtain the output of receiver balance signal;
Receiver side pumping signal extraction apparatus 130 is connected with acceptor circuit model 1103, is used for exporting to acceptor circuit model 1103 from the input waveform of full link channel response extraction receiver as the pumping signal of receiver;
At a high speed full link simulation circuit model 110, after can also carrying out the pre-emphasis modification to drive circuit model 1101, regenerate full link simulation net meter file and output to time domain eye pattern emulation device 120, carry out the receiver balance time domain eye pattern emulation of different pre-emphasis under being provided with.
The emulation mode of high speed serial duct receiver balance of the present invention comprises step: make up the full link simulation file of high-speed serial channel; Carry out the time domain eye pattern emulation at this full link simulation file, obtain full link channel response; Pumping signal according to this full link channel response extraction receiver; Construct different each balanced simulation document that receive under balanced the setting by the acceptor circuit model according to this pumping signal, carry out receiver balance time domain eye pattern emulation respectively, thereby obtain the best equalizing signal output of receiver at each balanced simulation document.
Fig. 2 has represented the process flow diagram of the emulation mode embodiment of high speed serial duct receiver balance of the present invention, and this flow process comprises the steps:
201:, drive circuit model, interconnecting channel model and acceptor circuit model are connected the full link simulation net meter file of structure successively according to the grammar request of time-domain-simulation device;
202: carry out the time domain eye pattern emulation at full link simulation net meter file;
203: the input waveform of the full link channel response extraction receiver that obtains according to emulation outputs to the acceptor circuit model as the pumping signal of receiver;
204: the acceptor circuit model is provided with the balanced simulation document output of structure according to this pumping signal and reception equilibrium;
205: carry out receiver balance time domain eye pattern emulation, obtain the output of receiver balance signal;
206: judge whether need to change to receive balanced the setting, if execution in step 207, execution in step 208 then if not;
207: revise receiving balanced the setting, change step 204 then and carry out;
208: judge whether need to change to drive the pre-emphasis setting, if execution in step 209, process ends then if not;
209: revise driving the pre-emphasis setting, change step 201 then and carry out.
By above embodiment as can be seen, the present invention compares with classic method, only need carry out the once emulation of full link, just can carry out repeatedly the emulation of different receiver balances under being provided with fast, promptly from the simulation result of full link, extract the input signal of receiver, only receiver is carried out direct-drive emulation and just can obtain balanced simulation result, so simulation time, emulation EMS memory occupation can be reduced into respectively less than original 1/3; And model is complicated more, uses the improved efficiency of this method big more.Shorten the time of receiver balance emulation, reduced the emulation EMS memory occupation, thereby reached the effect that improves the high-speed serial channel simulation efficiency.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the emulation mode of a high speed serial duct receiver balance is characterized in that, described method comprises: the full link simulation file that makes up described high-speed serial channel; Carry out full link time domain eye pattern emulation at described full link simulation file, obtain full link channel response; Pumping signal according to described full link channel response extraction receiver; Construct different each balanced simulation document that receive under balanced the setting by the acceptor circuit model according to described pumping signal, carry out receiver balance time domain eye pattern emulation respectively at described each balanced simulation document, thereby obtain the best equalizing signal output of described receiver;
The full link simulation file of described structure high-speed serial channel is specially: according to the grammar request of time-domain-simulation device, drive circuit model, interconnecting channel model and described acceptor circuit model be connected successively and make up the full link simulation file of described high-speed serial channel;
Described constructing different receive balanced each the balanced simulation document down that are provided with and be specially: described acceptor circuit model constructs described each balanced simulation document according to described pumping signal and the ongoing described result who receives balanced setting.
2. in accordance with the method for claim 1, it is characterized in that described method also comprises: after judging that needs are revised the pre-emphasis setting of described drive circuit model and carried out correspondingly described modification, repeat each step of described method.
3. according to claim 1 or 2 described methods, it is characterized in that the best equalizing signal output of described receiver is to go out different described receiver balance signals according to each described receiver balance time domain eye pattern emulation to select to draw.
4. the simulator of a high speed serial duct receiver balance comprises the full link simulation circuit model of high speed, time domain eye pattern emulation device and the receiver side pumping signal extraction apparatus that connect successively, wherein:
The full link simulation circuit model of described high speed is used for drive circuit model, interconnecting channel model and acceptor circuit model are connected successively, constructs the full link simulation file output of high speed serialization; Describedly construct the output of the full link simulation file of high speed serialization and be specially: the full link simulation circuit model of described high speed is according to the grammar request of time-domain-simulation device, described drive circuit model, described interconnecting channel model and described acceptor circuit model are carried out described connection, generate full link simulation net meter file, as described full link simulation file output;
Described time domain eye pattern emulation device is connected with described acceptor circuit model, is used for carrying out full link time domain eye pattern emulation at described full link simulation file, obtains full link channel response and outputs to described receiver side pumping signal extraction apparatus; And the balanced simulation document of described acceptor circuit model output carried out receiver balance time domain eye pattern emulation, obtain the best equalizing signal output of described receiver;
Described receiver side pumping signal extraction apparatus is connected with described acceptor circuit model, is used for the pumping signal output from the described receiver of described full link channel response extraction;
Described acceptor circuit model is used for constructing different each balanced simulation document that receive under balanced the setting according to the pumping signal of importing and outputs to described time domain eye pattern emulation device; Described constructing different receive balanced each the balanced simulation document down that are provided with and be specially: described acceptor circuit model constructs described each balanced simulation document according to described pumping signal and the ongoing described result who receives balanced setting.
5. according to the described device of claim 4, it is characterized in that, the full link simulation circuit model of described high speed, also be used for described drive circuit model is carried out after pre-emphasis revises, rebuild described full link simulation file and output to described time domain eye pattern emulation device, thereby carry out the described receiver balance time domain eye pattern emulation of different pre-emphasis under being provided with.
6. according to claim 4 or 5 described devices, it is characterized in that, described time domain eye pattern emulation device obtains the best equalizing signal output of described receiver, is to go out different described receiver balance signals according to each described receiver balance time domain eye pattern emulation to select to draw.
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| CN2008101114682A CN101299223B (en) | 2008-06-19 | 2008-06-19 | Emulation method and device of high speed serial duct receiver balance |
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| CN2008101114682A CN101299223B (en) | 2008-06-19 | 2008-06-19 | Emulation method and device of high speed serial duct receiver balance |
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| CN101299223B true CN101299223B (en) | 2010-06-16 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106155950B (en) * | 2015-03-23 | 2019-07-05 | 中兴通讯股份有限公司 | Parameter processing method and device |
| CN105701304B (en) * | 2016-01-18 | 2019-05-07 | 苏州芯禾电子科技有限公司 | Pass through the method for table rapid build high-speed link |
| CN107273602A (en) * | 2017-06-09 | 2017-10-20 | 郑州云海信息技术有限公司 | A kind of emulation mode of lifting PCIE eye pattern allowances |
| CN109542416B (en) * | 2018-11-16 | 2021-07-27 | 西安电子科技大学 | High-speed waveform equalization method |
| CN112052465B (en) * | 2020-08-27 | 2024-04-05 | 中国科学院微电子研究所 | Protection method for integrated circuit diagram design |
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| CN1791035A (en) * | 2005-12-22 | 2006-06-21 | 西安交通大学 | Design method for distributed wireless communication transmission technique test platform |
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Patent Citations (7)
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| US4414432A (en) * | 1981-09-21 | 1983-11-08 | Zenith Radio Corporation | Pseudo-full duplex television/telephone loudspeaker system |
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