CN101183675B - 一种用于多个个体的芯片的晶片级封装的方法和系统 - Google Patents
一种用于多个个体的芯片的晶片级封装的方法和系统 Download PDFInfo
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Abstract
本发明提供了一种对器件进行气密密封的方法。该方法包括提供包括多个个体芯片的衬底。每个芯片包括多个器件,并且每个芯片以空间方式被布置成第一阵列。该方法还提供预定厚度的透明构件,所述透明构件包括以空间方式布置成第二阵列的多个凹入区域和支座区域。该方法还包括以将多个凹入区域的每个结合到所述多个芯片的相应一个上的方式对准透明构件。该方法还包括通过使用至少一种接合工艺来气密密封相应凹入区域中的一个内的每个芯片,以隔离凹入区域中的一个内的每个芯片。
Description
本申请是中国专利申请200410086332.2的分案申请。
技术领域
本发明一般地涉及产品制造。具体而言,本发明提供了用于将透明罩气密地接合到半导体衬底的一种方法和结构。仅作为示例,本发明被应用于被气密地接合到包含了微机电系统的半导体晶片的透明玻璃罩。该方法和结构可以被应用于显示技术以及,例如电荷耦合显示照相阵列和红外阵列。
背景技术
硅集成电路的封装已经达到了一个较高的成熟水平。图1图示了传统硅集成电路封装件的简化示图。硅集成电路管芯110被安装在具有球栅阵列120的基座115上。线接合125被连接(attach)至硅管芯110以提供至基座115的电连接。一般地,硅管芯110和线接合125被用塑料包封物130包封。得到的封装件坚固耐用而且便宜。
图1所图示的封装件在应用中存在几个缺点,这些缺点通常需要更多的硅集成电路的电操作。这种应用的一个示例就是从微镜阵列或者其它微机电系统(MEMS)结构的光反射。例如,这些应用一般需要用光能量照射硅集成电路的顶部并然后以高效率从硅集成电路的顶部反射光能量的能力。塑料包封物的光学特性,包括透明度不足、折射率不均一以及表面粗糙度,使得这些封装件不适合用于这样的应用。另外,很多MEMS经常需要位于硅集成电路的表面上方的开放空间,以使得微机电结构能够沿平行于MEMS平面的方向以及垂直于MEMS的平面的方向移动。因此,塑料包封物与集成电路表面的物理接触使得该封装件不适合于很多MEMS应用。
发明内容
本发明一般地涉及产品制造。具体而言,本发明提供了气密地将透明罩接合到半导体衬底上的方法和结构。仅作为示例,本发明被应用于被气密地接合到半导体晶片上的透明玻璃罩,所述半导体晶片包含微机电系统。该方法和结构可以应用于显示技术以及,例如电荷耦合显示照相阵列和红外阵列。
在根据本发明的具体实施例中,提供了一种用于晶片级密封多个个体芯片的方法,该方法包括:提供衬底,所述衬底包括多个个体芯片,所述个体芯片以空间方式被布置成第一阵列;提供预定厚度的盖衬底,所述盖衬底包括:多个凹入区域,具有小于所述预定厚度的高度,所述高度大于所述个体芯片的高度,其中所述凹入区域以空间方式布置成与所述第一阵列对应的第二阵列;以及围绕所述凹入区域的支座区域,所述支座区域具有接合表面;以及将所述接合表面接合到所述衬底,以形成密封界面,其中所述密封界面被构造成包围每个所述个体芯片并单独地将每个所述个体芯片密封在所述凹入区域中的一个内。
在替代的具体实施例中,本发明提供了一种用于多个个体芯片的晶片级封装的系统,所述系统包括衬底,其包括多个个体芯片;所述个体芯片以空间方式被布置成第一阵列。该系统还包括预定厚度的盖衬底,其包括:多个凹入区域,具有小于所述预定厚度的高度,所述高度大于所述个体芯片的高度,其中所述凹入区域以空间方式布置成与所述第一阵列对应的第二阵列;以及围绕所述凹入区域的支座区域,所述支座区域具有接合表面。该系统还包括所述接合表面和所述衬底之间的密封界面,其中所述密封界面被构造成包围每个所述个体芯片并单独地将每个所述个体芯片密封在所述凹入区域中的一个内。
通过结合附图阅读以下详细描述,本领域的技术人员可以明白本发明的这些以及其它目的和特征,以及实现它们的方式,并且本发明被最好地理解。
附图说明
图1是传统硅集成电路封装件的简化示图。
图2是传统的气密密封的透明集成电路封装件的简化示图。
图3A-3D是根据本发明实施例的晶片级气密密封封装件的简化示图。
图4A和4B是由两个透明部件形成的根据本发明实施例的透明构件的简化示图。
图5A是根据本发明实施例的透明构件和衬底在气密密封时的简化俯视图。
图5B是根据本发明替代的实施例的四个透明构件和衬底在气密密封时的简化示图。
图6是根据本发明实施例的在气密密封之后的单个微镜芯片的简化示图。
图7是根据本发明实施例的包括了气密密封的管芯的管芯级封装件的简化示图。
图8是图示了根据本发明实施例的反射系统的操作的简化示图。
具体实施方式
根据本发明,提供用于产品制造的技术。具体而言,本发明提供了用于气密密封产品封装件的方法和系统。仅作为示例,本发明被应用于光学微镜封装件的气密密封。该方法和系统可以被应用于传感器技术以及需要气密封装的其它MEMS器件。
图2图示了传统的气密密封透明集成电路封装件的简化示图,该封装件可用于微镜阵列的光学照明。在图2中,具有微镜阵列215的硅MEMS管芯210被安装在基座220上。该管芯被使用管芯连接工序连接到基座上,本领域的技术人员都知道,所述管芯粘接工序符合气密密封封装技术的要求。与图1中所示封装件一样,线接合225被连接到硅管芯和基座。
为了在微镜阵列215的上方提供空间,一般在基座的外侧边缘附近设置固体支座230。该支座一般形状为方形环,由柯伐合金(covar)或者其它适合的材料制成。支座通常在接触点235被用铜焊接至基座。玻璃罩板240一般在接触点245被用铜焊接至支座的顶部,以密封封装件。
图2所示的封装件的成本一般较高,在一些情况下在$70左右。另外,通常必须在洁净的室内环境中组装封装件,以防止可能出现的操作损坏和污染。因此,需要改善用于气密密封产品封装件的方法和系统。
图3A-3D是根据本发明实施例的晶片级气密密封封装件的简化示图。这些示图图示了根据具体实施例的示例。本领域的一个普通技术人员可以认识到各种修改、替代和变化。优选地,封装件的形成发生在将有源器件分离成管芯形式之前。这里,经常使用晶片切割和/或划线并切断处理等工艺来进行分离。贯穿本说明书以及下面更具体地给出本方法的其它细节。
在图3A中所示的实施例中,根据本方法处理衬底310,以在该衬底上形成个体芯片315的阵列。在根据本发明的一个实施例中,衬底310是互补金属氧化物半导体(CMOS)的半导体晶片,例如为硅,而芯片315是MEMS。在共同所有的美国专利申请序列No.60/390,389中描述了一种形成这样的MEMS的方法的示例,这里因各种目的通过引用而结合于此。在图3A所示的实施例中,芯片包括多个器件。另外,CMOS晶片被处理以形成集成电路312、用于电导线314的金属迹线和其它CMOS结构。在根据本发明的一个实施例中,器件为布置成例如二维阵列的多维阵列的微镜。在替代的实施例中,该多个器件包括多个电荷耦合器件(CCD)、多个偏转器件、多个传感器件、集成电路器件、这些器件的任何组合以及类似物。
在图3B中所示的实施例中,透明构件320被设置为在透明构件的下表面中包括多个凹入区域325。透明构件具有预定厚度330。在根据本发明的实施例中,透明构件的厚度为1.2mm。或者,在其它实施例中厚度范围从大约0.5mm到大约3mm。当然,厚度要取决于具体的应用。
优选地,凹入区域是在构件内定义出的体积空间。该体积空间具有由从透明构件的底部324到凹入区域339的顶部的距离所定义的深度332。凹入区域的外侧边缘由支座335的竖直边缘定义。在根据本发明的实施例中,凹入区域的体积在整个透明构件上是均一的。
根据本发明的实施例,个体的支座335包括定位在平行于x-y平面的平面内的环状矩形圈,该环状矩形圈具有高度332。在根据本发明的实施例中,支座的下表面被加工成配合于衬底,并形成足以形成气密密封封装件的接合,以下将对此详细讨论。
在根据本发明的实施例中,凹入区域的深度是一个预定的深度。在图3B所示的实施例中,凹入区域的深度332为0.5mm。或者,在其它实施例中,深度范围从大约0.1mm到1mm。当然,凹入区域的深度要取决于具体的应用。另外,在根据本发明的实施例中,个体的凹入区域的面积会是预定的大小。在图3B中所示的实施例中,个体的凹入区域的面积约为14mm×18mm。根据具体应用,该面积的大小会变化。
形成在透明构件中的凹入区域被以空间方式布置,以形成x-y平面中的多维阵列。在根据本发明的一些实施例中,凹入区域被布置以形成x-y平面中的二维阵列。在图3A-3D中所示的实施例中,凹入区域339的深度和x-y尺寸大于芯片315的高度和x-y尺寸。因此,芯片装配在凹入区域内,并且凹入区域的边缘在所有三个维度上与芯片的外侧边缘分离。而且,在图3A和3B所示的实施例中,凹入区域在x和y维度上的中心到中心间距分别超过凹入区域在x和y维度上的大小,提供用于相邻芯片之间的支座区域335的空间。支座区域的横向尺寸具有预定的大小。在根据本发明的实施例中,支座区域的横向尺寸的范围在0.5mm到1.0mm之间。
在根据本发明的实施例中,透明构件是由销售名称为康宁显示级玻璃衬底的产品形成的,所述产品由纽约康宁公司制造。该玻璃衬底的特征在于光学性能高,包括但不限于,可见光区域中的光功率透射率高于90%。如以下将描述的那样,光线通过构件的透射率可以通过向衬底的光学表面涂敷抗反射(AR)涂层而提高。另外,康宁显示级玻璃被用在根据本发明的一些实施例中,因为该玻璃衬底的热膨胀系数接近于硅的热膨胀系数。
对于材料来说,根据定义,温度T下的热应变是由于温度变化(T-Tref)引起的构件长度变化除以该构件的原始长度l。用eT(T)表示温度T下的热应变,则:
同样,根据定义,用a(T)表示的材料热膨胀系数为:
在根据本发明的实施例中,其中预期温度变化作为时间的函数,这对透明罩的热膨胀系数(CTE)与衬底的CTE匹配是有帮助的。这些CTE的匹配限制了由于温度变化而在衬底中引入的应力和翘曲的量。
在图3A-3D中所示的实施例中,透明构件被设计和制造成减少光吸收,从而提高所感兴趣波长范围的光能量的透射。在根据本发明的实施例中,所感兴趣的波长范围是400nm和700nm之间的可见光谱。另外,在这个实施例中,构件337的顶表面和凹入区域339的顶表面被抛光或者磨光,以提供光学性能表面。此外,AR涂层可以被涂敷于透明构件的顶表面和凹入区域的顶表面。涂敷于透明构件顶表面的AR涂层当光线照射在封装件上时会减少从透明构件的顶部被反射的量,从而增加到达微镜阵列315的光线的量。此外,涂敷于凹入区域的顶部的AR涂层当光线离开封装件时会减少从透明构件被反射的量。通过使用这些AR涂层,将提高系统总的通过量。MgF2或者其它适合的电介质材料的四分之一波(λ/4)涂层可以被用来形成宽带AR涂层。例如,沉积在康宁显示级玻璃衬底上的中心位于550nm的λ/4 MgF2涂层(550nm处的折射率为1.38),得到在整个可见光谱(400nm-700nm)上每个表面小于2%的功率反射比。
透明构件可以以各种方法处理以形成凹入区域。例如,在根据本发明的一个实施例中,凹入区域可以通过使用干法或者湿法化学刻蚀、激光加工、声加工、喷水加工(water jet machining)或类似技术被刻蚀到透明构件中。
在根据本发明的替代的实施例中,如图4所示,通过加工第一平面部件并随后将分立的透明部件接合到该第一部件而形成透明构件。第一平面部件410是被加工或者以其它方式处理从而在凹入区域415所处的位置形成开口的平面衬底。在位置417形成另外的开口,以形成被用于将线接合连接至芯片互连区域的通孔,以下将对此进行描述。第一平面部件的未被加工部分将形成支座区域420。第二平面透明部件430被接合到第一平面部件的顶部以形成完整的透明构件。在根据本发明的一个具体实施例中,第一平面部件和第二平面透明部件都是透明的。沿图4A的平面A-A所取的完整的透明构件的侧视图在图4B中示出。如图4B中所示,示出了支座区域420和顶部的透明部件430。
这种可选择的制造工艺所带来的好处之一就是两个部件的光学特性并不总是近似的。实际上,对于一些应用,图4A和4B中所示的第一部件的光学特性不影响系统的性能。例如,根据穿过封装件的光路,光线永远不会照射在第一部件上。在根据本发明的其它实施例中,希望吸收照射在下侧部件上的所有的光线。
在根据本发明的实施例中,透明构件的光学特性是预定的。在具体实施例中,透明构件的透射率和吸收系数作为x-y平面中的位置的函数是一样的。
在根据本发明的实施例中,通过低温玻璃熔合接合或者本领域的技术人员所知道的其它方法来完成两个透明部件的接合。另外,在接合之前,在第二透明部件的顶部和底部涂敷AR涂层以提高光通量。如上所述,在根据本发明的这个实施例中,第二透明构件的光学性能会控制经过凹入区域的顶部的光线的光学性能,使得可以使用抛光和涂层方法,而这些方法在由单个衬底形成透明构件的实施例中是不适用的。
在根据本发明的实施例中,气密密封的管芯级封装件通过将透明构件结合到衬底上而形成的。图3C是透明构件和衬底在气密密封时的简化示图。以将支座区域335定位于迹道(street)区域344和346上方的方式对准透明构件。个体的芯片315位于相关联的凹入区域339之下并与之连通,并且在位于支座区域335的基部的接触点356处被构件337所气密密封。通孔348提供了到位于CMOS晶片上的接合焊盘358的通道。
透明构件与衬底的气密密封是根据本领域的技术人员所公知的几种方法来进行的。例如,在根据本发明的实施例中,通过等离子激活共价晶片接合技术(PACWB)来进行气密密封。PACWB是在衬底和透明构件已经在60℃下的SCl(NH3∶H2O2∶H2O,1∶4∶20)中被清洁、在去离子(DI)水中漂洗、在2%的HF中浸没20秒、在DI水中漂洗并用N2或者空气干燥之后在室温下进行的。然后将衬底和透明构件暴露于例如室压约为35毫托的反应式离子刻蚀机中的氧等离子体。在根据本发明的另外实施例中,衬底和透明构件被暴露于氩等离子体。经过等离子体处理之后,二氧化硅的表面为亲水性的,促进接合。在预先选定的周围环境中,在室温下使衬底和透明构件接触。在根据本发明的替代实施例中,其它的接合技术可以被使用,例如,共熔低温接合技术和阳极接合技术。
在根据本发明的实施例中,图3C中所示的气密密封处理是在包含惰性气体的环境中进行的。惰性气体的例子有N2和Ar等等。在惰性气体环境中进行气密密封所带来的好处包括但不限于,衰减器件中出现的振荡和防止电弧。例如,如果器件是布置成阵列的微镜,惰性气体的出现就会衰减和减弱在对微镜操作和移动过程中出现的振荡。另外,惰性气体的出现还减小了驱动电子器件和/或微镜阵列的元件之间的电弧的可能性。
图5A是图3C中所示的器件在气密密封时的俯视图。沿y方向伸展的支座区域335位于平行的迹道区域344(346)的上方,而沿x方向伸展的支座区域335位于平行的迹道区域344(346)上方。接合焊盘358位于有源器件522的左右侧。如图3C中所示,透明构件中的通孔348提供了至接合焊盘的通道。
在根据本发明的实施例中,气密密封处理是通过将单个透明构件接合到单个衬底上来进行的。在这个实施例中,单个透明构件的大小被选择为符合衬底的大小。例如,长和宽约30cm的透明构件被接合到直径为30cm的衬底上。或者,透明构件可以是矩形的并且在大小上大于衬底。在根据本发明的替代的实施例中,透明衬底的大小仅仅是衬底大小的一小部分。在这个替代的实施例中,在气密密封之前,多个透明构件被布置成与衬底表面上的配合区对准。多个透明构件随后被接合到衬底上。例如,图5B图示了在位于衬底上的芯片560阵列的上方以二维阵列布置的四个透明构件552、554、556和558的简化示图。在图5B所示的替代的实施例中,透明构件被制造成使得相邻透明构件在平面570和572处相互抵靠。但是,这并不是必须的。根据本发明的其它替代实施例可以以不同方式对准透明构件。
图3D根据本发明实施例图示了在气密密封完成之后的个体管芯的分离。在图3D中所示的实施例中,个体管芯360沿着位于相邻接合焊盘之间在y方向上伸展的线被分离。在x方向上分离管芯,使得分离面与位于凹入区域339外部的透明构件中的通孔348对准。为了区别,y方向和x方向上的线在图5A中分别被示为线530和535。
在根据本发明的具体实施例中,通过使用金刚石锯将衬底切割成管芯来分离个体管芯。在一个替代实施例中,通过使用金刚石划线器划刻衬底来分离管芯。在本发明实施例中,其中衬底为硅晶片,管芯分离是通过用旋转圆形磨料锯片锯割硅衬底来进行的。
图6是根据本发明实施例的单个管芯的俯视图。芯片和凹入区域的横向尺寸是预定的大小。在图6中所示的实施例中,芯片610的横向尺寸约为17mm×13mm。芯片的中心到中心间距在x方向上约为21mm,在y方向上约为17mm。在这个具体实施例中,芯片包括微镜615的1024×768阵列。微镜的边缘在x和y方向上与支座区域620分开0.5mm。支座区域在宽度上为0.5mm。支座区域左右的通孔625和627分别提供了至接合焊盘630的通道,大小为100μm,并间隔150μm设置。或者,芯片610的中心到中心间距为16mm×12mm,使得芯片与支座区域之间分开0.25mm。当然,这些尺寸要取决于具体的应用。
在根据本发明的实施例中,与衬底接触的支座区域的表面粗糙度被减小到预定水平。一般使用原子力显微镜(AFM)来鉴定支座区域的下表面的表面粗糙度。例如,可以使用威科仪器有限公司(Veeco Instruments,Inc.)的Digital Instruments EnviroScopeTM。
图7是根据本发明实施例的管芯级封装的简化示图,该管芯级封装可用于制作至气密密封的封装件的电连接并安装该封装件。
图7图示了根据本发明的一个实施例,其中气密密封封装件被安装在引线框架结构上,例如球栅阵列。前述的经分离的CMOS管芯、芯片和气密密封的封装件被示为705。在根据本发明的实施例中,至少一个互连区域与衬底上的每个芯片相关联。在图7中所示的实施例中,互连区域或者接合焊盘710位于,例如,晶片顶面上或者附近。在根据本发明的实施例中,互连焊盘被电连接到多个器件,以根据MEMS规则驱动机械器件。因此,互连区域710出现的电信号导致器件715的机械运东。如前所述,在根据本发明的一个具体实施例中,互连区域710出现的电信号使微镜阵列中的一些或者所有微镜偏转,以有选择地反射经过透明构件717并入射到微镜阵列上的光线。
为了将互连区域(进而将该器件)电连接到外部驱动器,线接合720从互连焊盘710被连接到位于引线框架结构725上的电连接。在根据本发明的实施例中,使用直径约25μm的金线制作线接合,所述金线能够承载超过500mA的电流。在图7中所示的根据本发明的实施例中,线接合被包封在包封物730中。对于本领域的技术人员来说,使用例如塑料的包封物来保护电学部件不受环境损坏是公知的。在一些实施例中,将引线框架用铜焊接到散热器742上,以减小气密密封的封装件上的热负载。
在图7中,包封物被用来包封引线框架、线接合、互连区域和透明构件邻近通孔的侧面中的至少一部分,而保持透明构件位于凹入区域上方的表面区域735不被包封。因此,表面区域735的光学特性就不受包封物的使用的影响。在图7中所示的实施例中,管芯级封装件的总厚度740是1.27mm。因此,图7中所示的封装件结合了可用于光学MEMS的气密密封封装件与非气密密封塑料包封的封装件两者。
图8图示了采用本发明具体实施例的反射系统的操作。在根据本发明的实施例中,希望对入射在封装件上以及从其被反射的光线进行空间过滤。在图8中所示的实施例中,来自光源810的光束入射在透明构件815的顶面上。经过透明构件的光线的一部分830入射到多个器件的表面上,所述器件在这个实施例中为微镜阵列820。来自灯810的光线835的其它部分被位于透明构件周围的过滤掩模825所遮挡或过滤。被过滤掩模825的左侧、顶侧和底侧所遮挡的光线不能到达微镜阵列。另外,被芯片的除了微镜阵列之外的部分所反射的光线被过滤掩模的右侧遮挡。这样,通过使用过滤掩模825,传到检测器840的反射光线被限制于入射在封装件上的原始光束选定部分。
在图8中所示的实施例中,过滤掩模位于透明构件的上表面上,但是,这不是必须的。在替代实施例中,过滤掩模位于透明构件的下表面或者侧面上。在根据本发明的另一个实施例中,在透明构件的制作中使用非透明材料可以实现过滤掩模。在根据本发明的实施例中,过滤掩模包括铬层。在替代实施例中,过滤掩模由其它反射或者吸收材料制成。
在图8所示实施例中,过滤掩模形成开口区域,其遮挡照射在管芯的上除微镜之外的部分或者从该处反射的光线。在替代实施例中,过滤掩模仅仅被用来遮挡图8中的入射(左)侧的光线,而不遮挡出射(右)侧的光线。
尽管以上是对本发明具体实施例的完整描述,但是以上描述不应视为限制由权利要求所定义的本发明的范围。
Claims (30)
1.一种用于多个个体芯片的晶片级封装的系统,所述系统包括:
衬底,包括多个个体芯片;所述个体芯片以空间方式被布置成第一阵列构造,所述个体芯片包括互连区域;
预定厚度的盖衬底,包括:
多个凹入区域,具有小于所述预定厚度的高度,所述高度大于所述个体芯片的高度,其中所述凹入区域以空间方式布置成与所述第一阵列构造对应的第二阵列构造;以及
围绕所述凹入区域的支座区域,所述支座区域具有接合表面;以及
所述接合表面和所述衬底之间的密封界面,其中所述密封界面被构造成包围每个所述个体芯片并单独地将每个所述个体芯片密封在所述凹入区域中的一个内,并且所述互连区域位于所述密封界面的外部。
2.如权利要求1所述的系统,其中所述第一阵列构造包括带状布置的多个第一迹道区域和带状布置的多个第二迹道区域,所述第二迹道区域和所述第一迹道区域相交,以形成所述第一阵列构造。
3.如权利要求2所述的系统,其中所述接合表面接合到所述第一迹道区域和所述第二迹道区域。
4.如权利要求1所述的系统,其中所述密封表面为共价接合表面或共熔接合表面。
5.如权利要求1所述的系统,其中所述盖衬底包括硅构件。
6.如权利要求1所述的系统,其中每个所述个体芯片包括多个微机电器件。
7.如权利要求6所述的系统,其中所述微机电器件包括多个多晶硅器件。
8.如权利要求1所述的系统,其中所述盖衬底的所述预定厚度为0.5mm到3.0mm。
9.如权利要求8所述的系统,其中所述盖衬底的所述预定厚度为2.0mm到3.0mm。
10.如权利要求1所述的系统,其中所述凹入区域的所述高度为0.1mm到1.0mm。
11.如权利要求10所述的系统,其中所述凹入区域的所述高度为0.5mm到1.0mm。
12.如权利要求6所述的系统,其中每个所述微机电器件保持在每个所述凹入区域内的惰性环境内。
13.如权利要求12所述的系统,其中所述惰性环境选择氮、氩、或氮和氩的混合气体。
14.如权利要求1所述的系统,其中所述衬底包括含硅材料。
15.如权利要求1所述的系统,其中所述衬底包括CMOS电路。
16.如权利要求6所述的系统,其中所述微机电器件包括偏转器件。
17.一种用于晶片级密封多个个体芯片的方法,该方法包括:
提供衬底,所述衬底包括多个个体芯片,所述个体芯片以空间方式被布置成第一阵列构造,所述个体芯片包括互连区域;
提供预定厚度的盖衬底,所述盖衬底包括:
多个凹入区域,具有小于所述预定厚度的高度,所述高度大于所述个体芯片的高度,其中所述凹入区域以空间方式布置成与所述第一阵列构造对应的第二阵列构造;以及
围绕所述凹入区域的支座区域,所述支座区域具有接合表面;以及
将所述接合表面接合到所述衬底以形成密封界面,其中所述密封界面被构造成包围每个所述个体芯片并单独地将每个所述个体芯片密封在所述凹入区域中的一个内,并且所述互连区域位于所述密封界面的外部。
18.如权利要求17所述的方法,其中所述第一阵列构造包括带状布置的多个第一迹道区域和带状布置的多个第二迹道区域,所述第二迹道区域和所述第一迹道区域相交,以形成所述第一阵列构造。
19.如权利要求18所述的方法,其中将所述接合表面接合到所述衬底以形成所述密封界面包括将所述接合表面结合到所述第一迹道区域和所述第二迹道区域。
20.如权利要求17所述的方法,其中将所述接合表面接合到所述衬底以形成所述密封界面包括进行共价接合处理和共熔接合处理中的至少一种。
21.如权利要求17所述的方法,其中所述盖衬底包括硅构件。
22.如权利要求17所述的方法,其中每个所述个体芯片包括多个微机电器件。
23.如权利要求22所述的方法,其中所述微机电器件包括多个多晶硅器件。
24.如权利要求17所述的方法,其中所述盖衬底的所述预定厚度为0.5mm到3.0mm。
25.如权利要求17所述的方法,其中所述凹入区域的所述高度为0.1mm到1.0mm。
26.如权利要求17所述的方法,其中每个所述微机电器件保持在每个所述凹入区域内的惰性环境内。
27.如权利要求26所述的方法,其中所述惰性环境选择氮、氩、或氮和氩的混合气体。
28.如权利要求17所述的方法,其中所述衬底包括含硅材料。
29.如权利要求17所述的方法,其中所述衬底包括CMOS电路。
30.如权利要求22所述的系统,其中所述微机电器件包括偏转器件。
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DE102004051361A1 (de) | 2006-01-19 |
US8022520B2 (en) | 2011-09-20 |
CN101202272A (zh) | 2008-06-18 |
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US20070128818A1 (en) | 2007-06-07 |
CN101202272B (zh) | 2010-06-02 |
JP2005167209A (ja) | 2005-06-23 |
US8288851B2 (en) | 2012-10-16 |
US20060284295A1 (en) | 2006-12-21 |
CN1638115A (zh) | 2005-07-13 |
CN101183675A (zh) | 2008-05-21 |
US20080014682A1 (en) | 2008-01-17 |
GB2408145A (en) | 2005-05-18 |
TW200525769A (en) | 2005-08-01 |
CN101252122A (zh) | 2008-08-27 |
US20070235852A1 (en) | 2007-10-11 |
US7671461B2 (en) | 2010-03-02 |
CN100454535C (zh) | 2009-01-21 |
GB2408145B (en) | 2007-06-06 |
US7948000B2 (en) | 2011-05-24 |
GB0423507D0 (en) | 2004-11-24 |
US20110186839A1 (en) | 2011-08-04 |
US20050101059A1 (en) | 2005-05-12 |
US20070072328A1 (en) | 2007-03-29 |
JP5043297B2 (ja) | 2012-10-10 |
CN101252122B (zh) | 2012-01-25 |
TWI253182B (en) | 2006-04-11 |
KR20050039635A (ko) | 2005-04-29 |
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