CN101140861A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN101140861A
CN101140861A CNA2007101821759A CN200710182175A CN101140861A CN 101140861 A CN101140861 A CN 101140861A CN A2007101821759 A CNA2007101821759 A CN A2007101821759A CN 200710182175 A CN200710182175 A CN 200710182175A CN 101140861 A CN101140861 A CN 101140861A
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layer
semiconductor substrate
sacrifice layer
groove
substrate
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CN101140861B (zh
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小野秀树
谷口理
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Sony Corp
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Sony Corp
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Abstract

本发明公开了一种制造半导体器件的方法，该方法包括步骤：在生长在半导体衬底的器件层中形成预定器件，在器件层和半导体衬底之间具有牺牲层；在支撑衬底接合在器件层的侧面的同时，通过蚀刻移除牺牲层以分离半导体衬底和器件层，其中在移除牺牲层的步骤中，在牺牲层移除之前形成从器件层延伸到牺牲层的凹槽，以及使用蚀刻溶液经由凹槽渗透到牺牲层。

Description

半导体器件的制造方法
技术领域
本发明涉及一种通过在半导体衬底上生长器件层，在器件层中形成预定器件并且从半导体衬底分离器件层的半导体器件的制造方法。
背景技术
迄今，已经应用了包括化合物半导体材料的下列半导体器件和其制造方法。
高铟含量(High-In-Content)器件
每个包含生长在InP衬底上、晶格匹配的InGaAs的异质结双极晶体管(HBT)和每个包含InGaAs/InAlAs的高电子迁移率晶体管(HEMT)在高速性能和高电场强度之间存在平衡。促进了用于大容量通讯系统的作为关键器件的HBT和HEMT的发展。但是，InP衬底是昂贵的。这是限制InP器件被应用于消费电器的因素。
为了提供低成本的高铟含量器件，发展出了包括在与InP衬底相比便宜的GaAs衬底或Si衬底上提供的在阻挡层上生长高铟含量器件的变质生长。每个包含在GaAs衬底上的变质InGaAs/InAlAs的HEMT接近实际应用。然而，变质HBT仍然不能实际应用。
外延剥离(epitaxial lift-off)方法
在低成本的情况下提供化合物半导体器件的另一种方法是外延剥离(ELO)。令人满意的是采用ELO可以重复使用衬底。已经进行了关于采用ELO制造III/V族半导体器件的方法的研究。ELO包括在器件层和衬底之间形成牺牲层；在器件的制造工艺完成之后或在器件的制造工艺开始之前将衬底浸入在合适的溶液中；溶解牺牲层将器件层和衬底分离。被分离的衬底可以重复使用。
ELO的要点是牺牲层的刻蚀，也就是，在横向方向获得高蚀刻率的牺牲层，以及超薄器件层的处理，也就是，转移被剥离的超薄器件层到另一个衬底上而不对超薄器件层造成破坏。
在ELO中，通过横向蚀刻溶解牺牲层，因此需要相应的时间完成剥离。衬底的直径增大需要更长的时间完成剥离。例如，根据衬底的直径、牺牲层的材料、厚度、蚀刻条件等，需要好几十小时至几天的时间来完成具有两英寸直径的衬底的分离。
已尝试增加横向蚀刻率(J.J.Schermer et al.“Epitaxial Lift-OFF for largearea thin film III/V器件”，Phys.Stat.sol.202，No.4.(2005)，501-508(非专利文档1))。在该情形，柔性支撑衬底接合到器件层并向上卷曲从而为蚀刻溶液开一个入口，因此显著地增加了蚀刻率。然而，如非专利文档1所描述，弯曲器件层可能会损害器件层。
已报道了具有几个微米至几个十微米厚度的超薄器件层的处理(T.Morfet al.“RF and 1/F noise investigations on MESFETs and circuit transplanted byEpitaxial Lift OFF”.Electron device 43(1996)1489-1494(非专利文档2))。非专利文档2描述了一种利用蜡作为支撑体的简单方法。剥离之后，提供了一种方法，其包括安装器件层至具有清洁表面的支撑衬底，例如玻璃或硅；并从上方对器件层施加恰当的负荷以通过分子间力将器件层接合到支撑衬底上(范德华结合；例如参见E.Yablonovltch et al.“Vander Waals bonding ofGaAs epitaxial liftoff flims onto arbitrary substrates”，Appl.Phys.Lett.56(1990)2419-2421(非专利文档3))。在这个方法中，缺点是难以进行背侧工艺。即，通过适当地进行背侧处理，可以改进元件特性。然而，当蜡用作支撑体以及进行背侧工艺时，需要进行多个将器件层转移到衬底的步骤，因此增加了损害超薄器件层的危险。
器件层厚度的减小
减小器件层(半导体芯片)的厚度是为了改善芯片的散热性能而进行的普通工艺。通常，在器件工艺之后，研磨衬底的背侧将厚度减至大约100μm。在背侧上形成金属薄膜。对器件层进行切割。将得到的芯片安装到IC壳体。近年来，在厚度的减小中取得了更多的进步。其中将器件层研磨至具有大约50μm厚度的研磨技术以及处理超薄芯片的技术已经取得了发展。迄今，通过背侧研磨来减小芯片的厚度。衬底通过研磨而消失。因此，难以重复应用。通过ELO取得的器件层的厚度最多是大约10μm；因此，可以获得通过公知的研磨技术不能取得的超薄芯片。
背侧工艺
在减小器件层的厚度之后进行背侧工艺改善了包括InGaAs/InP的HBT的特性(参见M.J.W.Rodwell et al.“Submicron Scaling of HBT”，IEEEElectron Devices 48(2001)2606-2624(非专利文档4)和Q.Lee et al，“Submicron transferred-substrate heterojunction bipolar transistors”，IEEEElectron Device Lett.20(1999)396-399(非专利文档5))。即，把经过器件处理的衬底表面接合在支撑衬底上。对InP衬底进行背侧研磨和湿法蚀刻。然后在背侧形成集电极。这种方法被指为“转换衬底”。因此，减小了基极和集电极之间的电容从而获得高fmax。通过这种方式，如果在减小器件层的厚度之后对背侧进行光刻工艺，则可以改善HBT的高速性能。
发明内容
然而，上述制造半导体器件的方法具有以下几个缺点。在制造包含昂贵化合物半导体器件中，通过ELO需要很长的时间蚀刻牺牲层。从该观点来看，虽然非专利文档1公开了使用柔性支撑衬底的技术，但是弯曲器件层会损坏器件。在非专利文档4和5中，采用背侧工艺是困难的。因此，难以改进器件的特性。
根据本发明的一个实施例，提供了一种制造半导体器件的方法，该方法包括步骤：在生长在半导体衬底上的器件层中形成预定器件，在器件层和半导体衬底之间提供有牺牲层；和在支撑衬底接合在器件层的侧面的同时，通过蚀刻去除牺牲层以分离半导体衬底和器件层，其中在移除牺牲层的步骤中，在移除牺牲层之前，形成从器件层延伸到牺牲层的凹槽，使得蚀刻溶液经由凹槽渗透到牺牲层。
根据本发明的另一个实施例，支撑衬底接合到包括器件的器件层，通过蚀刻去除牺牲层以分离半导体衬底和器件。使得蚀刻溶液通过从器件层延伸到牺牲层的凹槽渗透到整个牺牲层。因此，确保蚀刻溶液从牺牲层的中部渗透至外围，因而快速地分离器件层和半导体衬底。
根据本发明的一个实施例，提供了一种制造半导体器件的方法，该方法包括步骤：在形成在半导体衬底上的器件层中形成相应于多个芯片的器件，在半导体衬底和器件层之间提供有牺牲层；形成每个位于相邻的芯片之间的凹槽，每个凹槽从器件层延伸至牺牲层；接合半导体衬底至器件层的侧面；通过允许蚀刻溶液经由凹槽渗透到牺牲层来移除牺牲层以分离半导体衬底和器件层；将半导体衬底分成每个对应于多个芯片中的相应的一个的多个片以形成单个芯片。
根据本发明的一个实施例，支撑衬底接合到包括器件的器件层，通过蚀刻去除牺牲层以分离半导体衬底和器件。使得蚀刻溶液通过每个从器件层延伸到牺牲层的多个凹槽渗透到整个牺牲层。因此，确保蚀刻溶液从牺牲层的中部渗透至外围，因而快速地分离器件层和半导体衬底。
此时，凹槽为格子形状，每个凹槽位与相邻芯片之间。因此，有效地使得蚀刻溶液从牺牲层的中部渗透至外围。此外，当形成芯片时，凹槽可以用作切割线。
关于每个从器件层延伸到牺牲层的凹槽的深度，每个凹槽可以从器件层延伸到牺牲层的底部。每个凹槽可以从器件层延伸到牺牲层的厚度的中间位置。可选择的，每个凹槽可以从器件层延伸到牺牲层的表面。即，经由凹槽蚀刻溶液的渗透增加了牺牲层被浸入到蚀刻溶液的面积。
当使得蚀刻溶液经由凹槽渗透时，在器件层和牺牲层之间形成器件保护层以抑制对形成在器件层中的器件的破坏。
在通过使蚀刻溶液经由凹槽渗透以移除牺牲层的过程中，在半导体衬底和牺牲层之间形成衬底保护薄膜以抑制对半导体衬底的破坏。
根据本发明的一个实施例，采用化合物半导体衬底例如InP衬底或GaAs衬底特别有效。牺牲层优选由AlAs或AlAsSb组成。
附图说明
图1是举例说明本发明的一个实施例的示意图(No.1)。
图2是举例说明本发明的一个实施例的示意图(No.2)。
图3A和3B是举例说明本发明的一个实施例的每个自示意图(No.3)。
图4是举例说明本发明的一个实施例的示意图(No.4)。
图5是举例说明本发明的一个实施例的示意图(No.5)。
图6A和6B是举例说明本发明的一个实施例的每个自示意图(No.6)。
图7A，7B和7C是举例说明本发明的一个实施例的每个自示意图(No.7)。
图8是举例说明本发明的一个实施例的示意图(No.8)。
图9是举例说明本发明的一个实施例的示意图(No.9)。
图10A，10B是举例说明本发明的一个实施例的每个自示意图(No.10)。
图11是举例说明本发明的一个实施例的示意图(No.11)。
图12是举例说明本发明的一个实施例的示意图(No.12)。
图13是通过蚀刻形成的多个凹槽中每个具有比计划深的深度情况下的横截面示意图。
图14是举例说明一个尺寸的横截面示意图(No.1)。
图15是举例说明一个尺寸的横截面示意图(No.2)。
图16A，16B和16C是举例说明在形成器件之前形成凹槽的方法的例子的每个横截面示意图(No.1)。
图17A，17B和17C是举例说明在形成器件之前形成凹槽的方法的例子的每个横截面示意图(No.2)。
图18A和18B举例说明在形成器件之前形成凹槽的方法的另一个例子的每个横截面示意图(No.1)。
图19A和19B是举例说明在形成器件之前形成凹槽的方法的另一个例子的每个横截面示意图(No.2)。
具体实施方式
根据一个实施例的制造半导体器件的方法，以每个包括通过外延剥离方法(ELO)制造的高铟含量器件的单片微波IC(MMIC)芯片作为例子。根据本实施例的制造MMIC芯片的方法具有以下优点。
1.通过ELO分离器件层和衬底以形成MMIC芯片。
2.为格子形状且每个位于相邻的芯片之间的凹槽在器件衬底接合到支撑衬底之前形成在器件衬底侧。为格子形状的凹槽起到蚀刻溶液注入口的功能，该蚀刻溶液在随后的ELO步骤中蚀刻牺牲层。在ELO步骤中，经由凹槽的蚀刻溶液的渗透导致牺牲层的蚀刻快速完成。
3.将器件层转移到支撑衬底上，同时保持器件衬底上的芯片布置。
4.支撑衬底对MMIC芯片起到散热片的作用。
5.在某些情况下，在ELO步骤结束之后，执行背侧工艺。然后对支撑衬底进行切割。得到的芯片被安装到IC框架上。
以下在附图的基础上对本发明的具体实施方式进行说明。如图1所示，由AlAs组成且具有约2nm厚度的牺牲层2形成在由InP组成的半导体衬底1上。由InP组成的器件保护层3形成于其上。器件层4外延生长在器件保护层3上。器件层4形成为与半导体衬底1晶格匹配。在该实施例中器件层4从半导体衬底1侧起具有顺序形成的n+InGaAs/n-InP/u-InGaAs/p+InGaAs/n-InP/n+InP/n+InGaAs结构。
如图2所示，采用光刻法等在外延生长的器件层4中形成所需要器件。在图2中例如示出了具有接地的发射极的异质节双极晶体管(HBT)。
由苯环丁烯(benzocyclobutene，BCB)组成并具有大约2μm厚度的绝缘薄膜5形成在HBT的周围。绝缘薄膜5也可以为通过离子增强化学气相淀积(CVD)形成的无机薄膜，例如SiO2薄膜或SiN薄膜，或可以为有机膜，例如聚酰亚胺膜。优选绝缘薄膜5为很容易地具有几微米厚度的有机涂覆薄膜，例如BCB薄膜或聚酰亚胺薄膜。无源元件与HBT形成在同一平面。接地过孔恰当地形成。由Au等组成并与接地过孔相通的连接金属膜7形成在绝缘薄膜5的表面上。
如图3A和3B所示，将光阻层6施加到器件层上。形成与器件尺寸相应的栅格图案。即，在相应于芯片外围的光阻层6的部分区域中通过光刻法形成开口。
如图4所示，经设置在器件层上的光阻层6中的开口，通过由CF4/O2组成的混合气体，干法蚀刻由BCB组成的绝缘薄膜5。
如图5所示，经由蚀刻绝缘层5形成的开口，通过例如由稀释的盐酸湿法蚀刻器件保护层3和牺牲层2，由此在衬底表面上形成栅格形式的从器件层4延伸至牺牲层2的凹槽。器件层4被器件保护层3和绝缘薄膜5包围，器件保护层3牢固地接合到绝缘薄膜5，因此防止在蚀刻时蚀刻溶液渗透至器件层4。
如图6A和6B所示，移除图5中所示的光阻层6。得到的凹槽d沿着位于芯片的外围的切割线排列。每个凹槽具有大约为100μm的宽度A。在后来的切割步骤中进行切割时，沿着切割线设置的凹槽d用做参考线。在每个凹槽d侧面和相应的一个器件有源区之间的距离B设置成大约为10μm。从器件保护的观点来看，优选更大的距离B。
如图7A，7B和7C所示，具有由Au组成并在整个表面上通过蒸镀形成的薄膜11的支撑衬底10(例如由Cu或AlN组成)接合至半导体衬底1的器件层4侧。由Au组成的连接金属薄膜7形成在器件层4侧面上。接合支撑衬底10将支撑衬底10上的薄膜11连接到设置在器件层4上的连接金属薄膜7。在这种情况下，采用Au来连接。可选择的，连接可以通过加热焊料来进行。也可以采用Cu。
当将半导体衬底1接合到支撑衬底10时，形成在器件层4中的凹槽d表现为位于接合衬底的周围的开口。
如图8所示，将在先前步骤中形成的接合衬底(通过接合半导体衬底1至支撑衬底10获得)浸入到HF溶液(蚀刻溶液)中。HF溶液例如具有10％至50％的浓度。接合衬底浸入在HF溶液中导致牺牲层2分解，由此从连接到器件层4的支撑衬底10分离半导体衬底1。
HF溶液通过在器件层4中形成的凹槽d渗透。即，通过具有栅格形状的凹槽d，HF溶液快速地从接合衬底中间部分渗透至末端部分。凹槽d延伸至牺牲层2。因此，经由凹槽d，HF溶液在少量的时间内渗透到牺牲层2，导致衬底的快速分离。在分离步骤中，支撑衬底10略微地弯曲。
如图9所示，在连接到器件层4的支撑衬底10从半导体衬底1分离之后，半导体衬底1变成独立的了。因此，半导体衬底1可以在表面清洁之后重新使用。
如图10A和10B所示，支撑衬底10在下放置。器件根据需要经过背侧处理以形成电极8。
如图11所示，支撑衬底10上的器件(芯片)经过切割形成单独的芯片100。如图12所示，将每个芯片100安装到例如为低温共烧陶瓷封装(LTCC)101上。采用连接线102建立互连以完成半导体器件。
根据本实施例，形成每个从器件层4延伸到牺牲层2的沟槽；因此，在分离半导体衬底1和器件层4时，蚀刻溶液经由凹槽有效地渗透至牺牲层2并在少量的时间内溶解牺牲层2，因此将半导体衬底1分离。
从重复利用被分离的半导体衬底1的观点来看，将描述在形成凹槽的工艺的最后的阶段中应用的湿法蚀刻。图13是其中通过湿法蚀刻形成的凹槽每个具有比计划深的深度情况下的横截面示意图。即，在形成凹槽d的过程中，通过从器件保护层3到牺牲层2的蚀刻来挖出凹槽。在控制蚀刻深度失败的情况下，不利地蚀刻了半导体衬底1。如果半导体衬底1被蚀刻，半导体衬底1可能不能再重复利用，除非移除不规则表面。
因此，在本实施例中，为了防止在形成凹槽时半导体衬底1被蚀刻，采用以下步骤(参见图14)：
(1)器件保护层3由InGaAs组成。
(2)由InP组成的阻挡层1a形成在牺牲层2的下方。
(3)使用磷酸和过氧化氢溶液的混合溶液蚀刻器件保护层3和牺牲层2。
在这种情况下，使用磷酸和过氧化氢溶液的混合溶液不会蚀刻设置在牺牲层2下方的由InP组成的阻挡层1a，由此结束蚀刻。因此，仅仅器件保护层3和牺牲层2被蚀刻，导致阻止了半导体衬底1的蚀刻。
下面将描述另一个方法(参见图15)；
(1)器件保护层3由InP组成。
(2)例如InGaAs或InAlAs的含As的混合结晶层1b形成在牺牲层2的下方。
(3)通过稀释的盐酸溶液蚀刻器件保护层3和牺牲层2。
在这种情况下，通过稀释的盐酸溶液不能蚀刻设置在牺牲层2的下方的例如InGaAs或InAlAs的含As的混合结晶层1b，因此结束蚀刻。因而，仅仅器件保护层3和牺牲层2被蚀刻，导致阻止了半导体衬底1的蚀刻。当留在分离的半导体衬底1的表面上例如InGaAs或InAlAs的含As的混合结晶层1b由以磷酸为基础的蚀刻溶液溶解时，可以获得一个平坦、可重复利用的InP表面。
在上面所提到的实施例中，以MMICs为例作为目标半导体器件。本发明并不以此为限。本发明可以适用另外的半导体器件。每层的成分仅仅是示例而不限制于该实施例。凹槽优选为栅格形状并沿芯片之间的切割线设置。可选择的，为了使蚀刻溶液经由凹槽渗透至牺牲层2，凹槽可以形成在衬底上所需要的位置。在这种情况下，当比半导体衬底1大的支撑衬底10被接合时，凹槽需要与半导体衬底1的末端相通。这防止了由于接合支撑衬底10与半导体衬底1而闭塞了用于蚀刻溶液的凹槽d的入口。
在上述提到的实施例中，关于凹槽d的深度，描述了每个凹槽从器件层4延伸到牺牲层2底部的情况。可选择地，每个凹槽可以从器件层4延伸到牺牲层2的厚度的中间位置。每个凹槽可以从器件层4延伸到牺牲层2的表面。即，当蚀刻溶液经由凹槽渗透时，需要增加蚀刻溶液和牺牲层2之间的接触面积。因而，优选地，每个凹槽从器件层4延伸到牺牲层2的厚度的中间位置。更优选地，每个凹槽从器件层4延伸到牺牲层2的表面。更优选地，如上述实施例所描述的那样，每个凹槽从器件层4延伸到牺牲层2的底部。
在上述实施例中，在器件层4中形成器件之后形成凹槽。可选择地，生长了器件层4之后，凹槽d可以在器件形成之前形成。在凹槽形成在器件形成之前的情况下，从防止在器件形成期间凹槽d对器件层4的内部破坏的观点出发，优选凹槽d填充有绝缘材料或凹槽d的内壁覆盖有绝缘膜。
图16A至17C是举例说明在器件形成之前形成凹槽的方法的例子的每个横截面示意图。如图16A所示，由AlAs组成并具有大约2nm厚度的牺牲层2形成在由InP组成的半导体衬底1上。其上形成由InP组成的器件保护层3。器件层4外延生长在器件保护层3上。器件层4与半导体衬底1晶格匹配。在本实施例中，器件层4具有自半导体衬底1侧以如下顺序形成的n+InGaAs/n-InP/u-InGaAs/p+InGaAs/n-InP/n+InP/n+InGaAs结构。光阻层6施加到器件层4。形成与芯片尺寸相应的栅格图案。即，在光阻层6相应于芯片外围部分通过光刻法形成开口。
如图16B所示，经由形成在光阻层6中的开口通过例如稀释的盐酸湿法蚀刻形成凹槽d。在衬底的表面形成栅格形状的凹槽d，并使之经由器件层4和器件保护层3延伸到牺牲层2。
在分离光阻层6之后，如图16C所示，通过例如离子增强CVD沉积氧化硅薄膜9以覆盖凹槽d的表面。这防止了在凹槽d的器件层4的暴露。应该使用能够溶解在随后步骤中蚀刻牺牲层2时使用的蚀刻溶液中的材料作为沉积薄膜的材料。
如图17A所示，通过反应离子蚀刻(RIE)移除与芯片的上表面相应的部分氧化硅薄膜9以形成开口。然后执行常规的器件形成工艺。如图17B所示，在器件层4中形成器件。在每个芯片的表面上形成连接金属薄膜7。如图17C所示，具有由Au组成并在整个表面上通过蒸镀形成的薄膜11的支撑衬底10(例如由Cu或AlN组成)接合到半导体衬底1的器件层4侧。
随后的步骤与附图8至12所示出的步骤相同。HF溶液(蚀刻溶液)经由凹槽d渗透至牺牲层2，因此快速地分离衬底。并且，在蚀刻时氧化硅薄膜9消失。
图18A至19B是说明在形成器件之前形成凹槽的方法的另一个例子的每个横截面示意图。如图18A所示，具有条形图形的氧化硅薄膜12形成在与由InP组成的半导体衬底1上的芯片外围相应的部分。应该使用能够溶解在随后步骤中蚀刻牺牲层2时使用的蚀刻溶液中的材料作为形成薄膜的材料。
如图18B所示，具有大约2nm的厚度并由AlAs组成的牺牲层2形成在半导体衬底1上的氧化硅薄膜12之间。其上形成由InP组成的器件保护层3。器件层4外延生长在器件保护层3上。器件层4与半导体衬底1的晶格匹配。在本实施例中，器件层4具有自半导体衬底1侧以如下顺序形成的n+InGaAs/n-InP/u-InGaAs/p+InGaAs/n-InP/n+InP/n+InGaAs结构。器件层4和氧化硅薄膜12构成凹槽d。
如图19A所示，器件形成在器件层4中。连接金属薄膜7形成在芯片的表面上。如图19B所示，具有由Au组成并在整个表面上通过蒸镀形成的薄膜11的支撑衬底10(例如由Cu或AlN组成)接合到半导体衬底的器件层4侧。
随后的步骤与图8至12的步骤相同。HF溶液(蚀刻溶液)经由凹槽d渗透至牺牲层2，因此快速地分离衬底。并且，在蚀刻时氧化硅薄膜12消失。
在本实施例中，可以采用在器件层4中形成器件之前形成凹槽d的方法和在凹槽d形成之后形成器件的方法。
本领域的普通技术人员可以理解，根据设计要求和在本发明的权利要求及其等同特征的范围内的其它因素可以作各种变型、结合、子结合和改变。
本申请包括于2006年8月22日在日本专利局提出的申请专利申请JP2006-224845的主题，在此引入其整个全部内容作为参考。

Claims (10)

1.一种制造半导体器件的方法，包括如下步骤：
在生长在半导体衬底上的器件层中形成预定器件，在所述器件层和半导体衬底之间具有牺牲层；以及
在支撑衬底接合在所述器件层的侧面的同时，通过蚀刻移除所述牺牲层以从所述器件层分离所述半导体衬底，
其中在移除所述牺牲层的步骤中，在移除所述牺牲层之前，形成从所述器件层延伸到所述牺牲层的凹槽，以及
使蚀刻溶液经由所述凹槽渗透到所述牺牲层。
2.一种制造半导体器件的方法，包括如下步骤：
在生长在半导体衬底上的器件层中形成相应于多个芯片的器件，在所述半导体衬底和器件层之间形成有牺牲层；
形成每个位于相邻芯片之间的凹槽，每个所述凹槽从所述器件层延伸到所述牺牲层；
将支撑衬底接合到所述器件层的侧面；
经由所述凹槽通过使用蚀刻溶液渗透到所述牺牲层来移除所述牺牲层以将所述半导体衬底和器件层分离；以及
将所述支撑衬底分成多块，每块对应于多个芯片中的相应一个从而形成单个芯片。
3.如权利要求2所述的制造半导体器件的方法，
其中所述凹槽具有栅格形状，每个所述凹槽位于相邻的芯片之间。
4.如权利要求2所述的制造半导体器件的方法，还包括步骤：
在所述牺牲层和所述器件层之间形成器件保护层，所述器件保护层防止器件与用来形成从所述器件层延伸到所述牺牲层的凹槽的蚀刻溶液接触。
5.如权利要求2所述的制造半导体器件的方法，还包括步骤：
形成位于所述半导体衬底和所述牺牲层之间的衬底保护膜，所述衬底保护膜在用于形成所述凹槽的蚀刻溶液中不可溶解。
6.如权利要求2所述的制造半导体器件的方法，
其中所述半导体衬底为化合物半导体衬底。
7.如权利要求2所述的制造半导体器件的方法，
其中所述半导体衬底为InP衬底。
8.如权利要求2所述的制造半导体器件的方法，
其中所述半导体衬底为GaAs衬底。
9.如权利要求2所述的制造半导体器件的方法，
其中所述牺牲层由AlAs组成。
10.如权利要求2所述的制造半导体器件的方法，
其中所述牺牲层由AlAsSb组成。
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