CN101095102B - 压缩伽罗瓦域计算系统 - Google Patents

压缩伽罗瓦域计算系统 Download PDF

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CN101095102B
CN101095102B CN2005800453231A CN200580045323A CN101095102B CN 101095102 B CN101095102 B CN 101095102B CN 2005800453231 A CN2005800453231 A CN 2005800453231A CN 200580045323 A CN200580045323 A CN 200580045323A CN 101095102 B CN101095102 B CN 101095102B
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詹姆斯·威尔逊
约瑟夫·斯坦
乔舒亚·凯布洛特斯基
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Abstract

一种压缩伽罗瓦域计算系统包括:乘法器电路,用于在伽罗瓦域上将带有系数的第一和第二多项式相乘来获得它们的乘积;和伽罗瓦域线性变换器电路,用于将n次幂的不可约多项式应用于所述乘积,该电路包括:部分结果生成器,它响应于乘积中的n次幂和更高次幂的项以提供折叠的部分结果;以及伽罗瓦域加法器,用于压缩折叠的部分结果和乘积中低于n次幂的项以获得所述乘积的n次幂的伽罗瓦域变换。

Description

压缩伽罗瓦域计算系统
技术领域
本发明涉及一种压缩伽罗瓦域计算系统。
背景技术
伽罗瓦域(GF)中具有系数的多项式的乘法被广泛用于通信系统中以进行里德-索罗门(RS)编码和用于高级加密中。对于传统的数字信号处理器(DSP)来说执行伽罗瓦域乘法是困难的并且耗时的:DSP被优化用于有限脉冲响应(FIR)滤波和其他乘法-累加(MAC)密集运算,但是不能有效地处理伽罗瓦域类型的运算。一种方法使用一次处理一个比特的线性反馈移位寄存器(LFSR)在伽罗瓦域上使用直接多项式乘法和除法。这是非常慢的处理过程。例如,在用于比特率达到每秒100兆比特的AES类型应用的宽带通信中,将有高达每秒12.5百万次GF乘法(MPS),且每次乘法可能需要许多次例如60-100次运算。另一种方法使用查找表执行伽罗瓦域乘法。典型地,这种方法需要10-20次或更多次循环,这对于12.5mps导致有些减少但是仍然非常大量的运算例如20×12.5=250mps或更多。里德-索罗门编码已经被广泛接受为宽带网络的优选差错控制编码方案。因为给系统设计者提供了根据信道条件对于数据带宽和所期望的纠错能力进行折衷的独特灵活性,里德-索罗门编码器和解码器的可编程实现是一种具有吸引力的解决方案。里德-索罗门解码的第一步骤是计算并发位。该并发位能够形式上定义为Si=R mod G,这里i=(0,1...15)。接收的码字可以以多项式形式表示为Ri=roXN-1+r1XN-2+...rN-1,这里接收的码字的长度是N。能够看出计算并发位相当于在伽罗瓦域上以如由生成多项式的i’次方根的j’次幂所定义的根进行多项式求值。对于里德-索罗门算法中的每个接收码字,将要计算16个并发位,这些并发位将运算次数增至16倍达400mps-在当前微处理器上是不实际的。使用直接乘法替代查找表将运算速率提高到每秒1.6gigs。随着通信领域的扩展和对通信数据施加的加密要求,对于伽罗瓦域乘法的需要正显著增加。这进一步使得问题复杂化,因为每一个域的差错检验、加密需要在需要不同查找表集合的不同伽罗瓦域上的伽罗瓦域乘法。
发明内容
因此,本发明的一个目的是提供一种改进的压缩伽罗瓦域计算系统。
本发明的再一个目的是提供这种改进的需要更低次幂和较少领域的压缩伽罗瓦域计算系统。
本发明的又一个目的是提供这种改进的比当前的查找表和线性反馈移位寄存器(LFSR)实现快得多的压缩伽罗瓦域计算系统。
本发明的又一个目的是提供这种改进的减小所需要的存储量的压缩伽罗瓦域计算系统。
本发明的又一个目的是提供这种改进的显著地减小每秒所需要运算次数的压缩伽罗瓦域计算系统。
本发明得自以下实现:能够作为需要更低次幂和较少领域的乘法器、乘法器-加法器、和乘法器-累加器操作的改进的压缩伽罗瓦域计算系统能够通过在伽罗瓦域上将带有系数的第一和第二多项式相乘以获得它们的乘积并且然后使用伽罗瓦域线性变换器电路将n次幂的不可约多项式应用到所述乘积而获得,其中所述电路包括部分结果生成器,它响应于所述乘积中的n次幂和更高次幂的项以提供折叠的部分结果;以及伽罗瓦域加法器,它用于压缩折叠的部分结果和乘积中低于n次幂的项以获得乘积的n次幂的伽罗瓦域变换。
但是,在其他实施例中,本发明不需要实现所有这些目的以及本发明的权利要求不应该局限于能够实现这些目的的结构或方法。
本发明特征在于压缩伽罗瓦域计算系统,包括用于在伽罗瓦域上将带有系数的第一和第二多项式相乘来获得它们乘积的乘法器电路。存在用于将n次幂的不可约多项式应用于所述乘积的伽罗瓦域线性变换器电路,该电路包括:部分结果生成器,它响应于所述乘积中的n次幂和更高次幂的项以提供折叠的部分结果;以及伽罗瓦域加法器,它用于组合折叠的部分结果和乘积中低于n次幂的项以获得乘积的n次幂的伽罗瓦域变换。
在优选实施例中,所述产生的部分结果可以包括查找表。所述查找表可以包括用于n次幂或更高次幂的组合的折叠的部分结果。所述查找表可以包括地址生成器。所述地址生成器可以提供统计上独立的地址访问。伽罗瓦域加法器可以包括三输入加法器。到所述三输入加法器的第三输入可以是0以及伽罗瓦域计算系统可以作为伽罗瓦域乘法器操作。伽罗瓦域输入或输出可以被反馈到伽罗瓦域计算系统以及该伽罗瓦域计算系统可以作为乘法器-累加器操作。所述伽罗瓦域加法器输出可以被反馈到具有第一和第二多项式之一的乘法器电路,该第一和第二多项式中的另一个多项式可以构成伽罗瓦域加法器的第三输入,以便伽罗瓦域计算系统作为乘法器-加法器操作。伽罗瓦域加法器可以包括“异或”电路。
本发明特征还在于压缩伽罗瓦域乘法器系统,包括:在伽罗瓦域上将带有系数的第一和第二多项式相乘来获得它们乘积的乘法器电路;以及将n次幂的不可约多项式应用于所述乘积的伽罗瓦域线性变换器电路,该电路包括:部分结果生成器,它响应于所述乘积中n次幂和更高次幂的项以提供折叠的部分结果;以及伽罗瓦域加法器,它用于组合折叠的部分结果和乘积中低于n次幂的项以执行伽罗瓦域乘法运算。
本发明特征还在于压缩伽罗瓦域乘法-累加系统,包括:在伽罗瓦域上将带有系数的第一和第二多项式相乘来获得它们乘积的乘法器电路;以及将n次幂的不可约多项式应用于所述乘积的伽罗瓦域线性变换器电路,该电路包括:部分结果生成器,它响应于所述乘积中的n次幂和更高次幂的项以提供折叠的部分结果;以及伽罗瓦域加法器,它用于组合折叠的部分结果、乘积中低于n次幂的项以及该伽罗瓦域加法器的反馈以执行伽罗瓦域乘法-累加运算。
本发明特征还在于压缩伽罗瓦域乘法器-加法器系统,包括:在伽罗瓦域上将带有系数的第一和第二多项式相乘来获得它们乘积的乘法器电路;以及将n次幂的不可约多项式应用于所述乘积的伽罗瓦域线性变换器电路,该电路包括:部分结果生成器,它响应于所述乘积中的n次幂和更高次幂的项以提供折叠的部分结果;以及伽罗瓦域加法器,该加法器的输出被反馈到具有第一和第二多项式其中之一的所述乘法器电路,这两个多项式中的另一个多项式是伽罗瓦域加法器的第三输入,另两个输入为折叠的部分结果以及乘积中低于n次幂的项,以执行伽罗瓦域乘法-加法运算。
附图说明
根据以下对优选实施例和附图的描述本发明的其他目的、特征和优点对于本领域的普通技术人员来说将会显而易见,其中:
图1是根据本发明的压缩伽罗瓦域计算系统的示意方框图;
图2是图1的折叠的部分结果查找表的示意方框图;
图3是类似于图1的示意方框图,其中伽罗瓦域加法器具有为作为伽罗瓦域乘法器操作而设置的第三输入;
图4是类似于图1的示意方框图,其中伽罗瓦域加法器具有为作为伽罗瓦域乘法器-累加器操作而连接的第三输入;以及
图5是类似于图1的示意方框图,其中伽罗瓦域加法器具有为作为伽罗瓦域乘法器-加法器操作而连接的第三输入。
具体实施方式
除以下公开的优选实施例之外,本发明还能够有其他实施例并且能够以各种方式实践或实现。因此,应该明白本发明在其应用中并不局限于在以下描述中阐述或在附图中图示的构造和组件配置的细节。如果这里仅描述一个实施例,其权利要求并不局限于该实施例。而且,本发明的权利要求不应该被限制性地阅读,除非有明确和令人信服的表明某种排除、限制或放弃的证据。
如在图1中所示根据本发明的压缩伽罗瓦域计算系统10包括多项式乘法器12、以及包含查找表(LUT)14和诸如具有两个输入18和20的“异或”门16的伽罗瓦域加法器的伽罗瓦域变换器13。
在运算中在多项式乘法器12中将在GF(28)上具有系数的8比特多项式X(x7-x0)乘以8比特多项式Y(y7-y0)。该多项式乘积是14比特数字。取代如将会是通常程序的、用n次幂的域不可约多项式除该14比特多项式乘积以得到模余数,根据本发明,直接传送该多项式乘积的低于不可约多项式的幂次n的那些项到“异或”OR门16的伽罗瓦域加法器输入18。所述乘积中具有n次幂或更高次幂的那些项被用于访问在查找表14中存储的部分结果,当在输入20被提供给“异或”OR门16和通过“异或”OR门16进行“异或”运算或伽罗瓦域相加时,产生8比特z7-z0的伽罗瓦域变换Z。本发明的实现在于低于n次幂的项不受缩减处理(用不可约多项式除所述乘积,其中n是该不可约多项式的幂次)的影响,因此能够直接地传送它们到伽罗瓦域加法器16的输入18而没有另外的运算或操作。n次幂或更高次幂的那些项必须经过缩减处理,其中使用查找表用折叠的部分结果替换它们,然后所述部分结果在加法器16中与来自输入18的更低次幂的项相加以产生正确的伽罗瓦域输出(通过以n-1次幂或更低次幂的项表示n次幂或更高次幂的所有乘积项和累加所有的项而产生部分结果查找表值)。例如,如果所选择的不可约多项式具有8次幂,将会直接传送来自多项式乘法器12的所述乘积中具有7次幂或更低次幂的所有那些项到输入18,而具有8次幂或更高次幂的那些项将在线22上被使用以访问查找表14中折叠的部分结果,当被加到在输入18上的更低次幂的项上时产生正确的伽罗瓦域输出。
伽罗瓦域多项式乘法能够以两个基本步骤实现。第一步骤是计算多项式乘积 c ( x ) = a ( x ) * b ( x ) , 该乘积被代数展开,相同的幂被汇集(加法对应于相应项之间的“异或”运算)以给出c(x)。
例如,
c(x)=(a7x7+a6x6+a5x5+a4x4+a3x3+a2x2+a1x1+a0)*(b7x7+b6x6+b5x5+b4x4+b3x3+b2x3+b1x1+b0)
C(x)=c14x14+c13x13+c12x12+c11x11+c10x10+c9x9+c8x8+c7x7+c6x6+c5x5+c4x4+c3x3+c2x2+c1x1+c0
其中:
表I
c14=a7*b7
c 13 = a 7 * b 6 ⊕ a 6 * b 7
c 12 = a 7 * b 5 ⊕ a 6 * b 6 ⊕ a 5 * b 7
c 11 = a 7 * b 4 ⊕ a 6 * b 5 ⊕ a 5 * b 6 ⊕ a 4 * b 7
c 10 = a 7 * b 3 ⊕ a 6 * b 4 ⊕ a 5 * b 5 ⊕ a 4 * b 6 ⊕ a 3 * b 7
c 9 = a 7 * b 2 ⊕ a 6 * b 3 ⊕ a 5 * b 4 ⊕ a 4 * b 5 ⊕ a 3 * b 6 ⊕ a 2 * b 7
c 8 = a 7 * b 1 ⊕ a 6 * b 2 ⊕ a 5 * b 3 ⊕ a 4 * b 4 ⊕ a 3 * b 5 ⊕ a 2 * b 6 ⊕ a 1 * b 7
c 7 = a 7 * b 0 ⊕ a 6 * b 1 ⊕ a 5 * b 2 ⊕ a 4 * b 3 ⊕ a 3 * b 4 ⊕ a 2 * b 5 ⊕ a 1 * b 6 ⊕ a 0 * b 7
c 6 = a 6 * b 0 ⊕ a 5 * b 1 ⊕ a 4 * b 2 ⊕ a 3 * b 3 ⊕ a 2 * b 4 ⊕ a 1 * b 5 ⊕ a 0 * b 6
c 5 = a 5 * b 0 ⊕ a 4 * b 1 ⊕ a 3 * b 2 ⊕ a 2 * b 3 ⊕ a 1 * b 4 ⊕ a 0 * b 5
c 4 = a 4 * b 0 ⊕ a 3 * b 1 ⊕ a 2 * b 2 ⊕ a 1 * b 3 ⊕ a 0 * b 4
c 3 = a 3 * b 0 ⊕ a 2 * b 1 ⊕ a 1 * b 2 ⊕ a 0 * b 3
c 2 = a 2 * b 0 ⊕ a 1 * b 1 ⊕ a 0 * b 2
c 1 = a 1 * b 0 ⊕ a 0 * b 1
c0=a0*b0
第二步骤是计算d(x)=c(x)模p(x)。
为了例示,执行利用多项式相乘对不可约多项式求模的乘法。例如:(如果m(x)=x8+x4+x3+x+1)
{57)*{83}={c1},因为,
第一步
( x 6 + x 4 + x 2 x + 1 ) + ( x 7 + x + 1 ) = x 13 ⊕ x 11 ⊕ x 9 ⊕ x 8 ⊕ x 7
x 7 ⊕ x 5 ⊕ x 3 ⊕ x 2 ⊕ x
x 6 ⊕ x 4 ⊕ x 2 ⊕ x ⊕ x
= x 13 ⊕ x 11 ⊕ x 9 ⊕ x 8 ⊕ x 6 ⊕ x 5 ⊕ x 4 ⊕ x 3 ⊕ 1
第二步
对于不可约多项式x8+x4+x3+x+l如果多项式乘积
= x 13 ⊕ x 11 ⊕ x 9 ⊕ x 8 ⊕ x 6 ⊕ x 5 ⊕ x 4 ⊕ x 3 ⊕ 1
那么n(8)次幂或更高次幂的项中的每一项以n-1=7次或更低次幂的项表示:
x8=x4+x3+x+1
x9=x·x8=x(x4+x3+x+1)=x5+x4+x2+x
x11=x3·x8=x3(x4+x3+x+1)=x7+x6+x4+x3
x13=x5·x8=x5(x4+x3+x+1)=x9+x8+x6+x5
这简化成x6+x3+x2+1。
赋值1给每个项以表示n次幂和更高次幂的项:
Figure S05845323120070702D000071
通过所述乘积中低于n次幂的项与LUT14的折叠的部分结果进行伽罗瓦域加法(“异或”16),获得第一伽罗瓦域输出:
在这种情况中使用的不可约多项式x8+x4+x3+x+1仅仅是可使用的许多多项式之一。例如,可以使用表II中所示多项式中的任何一个:
表II
:GF(21)
0x3(x+1)
:GF(22)
0x7(x2+x+1)
:GF(23)
0xB(x3+x+1)
0xD(x3+x2+1)
:GF(24)
0x13(x4+x+1)
0x19x4+x3+1)
:GF(25)
0x25(x5+x2+1)
0x29(x5+x3+1)
0x2F(x5+x3+x2+x+1)
0x37(x5+x4+x2+x+1)
0x3B(x5+x4+x3+x+1)
0x3D(x5+x4+x3+x2+1)
:GF(26)
0x43(x6+x+1)
0x5B(x6+x4+x3+x+1)
0x61(x6+x5+1)
0x67(x6+x5+x2+x+1)
0x6D(x6+x5+x3+x2+1)
0x73(x6+x5+x4+x+1)
:GF(27)
Ox83(x7+x+1)
0x89(x7+x3+1)
0x8F(x7+x3+x2+x+1)
0x91(x7+x4+1)
0x9D(x7+x4+x3+x2+1)
0xA7(x7+x5+x2+x+1)
0xAB(x7+x5+x3+x+1)
0xB9(x7+x5+x4+x3+1)
0xBF(x7+x5+x4+x3+x2+x+1)
0xC1(x7+x6+1)
0xCB(x7+x6+x3+x+1)
0xD3(x7+x6+x4+x+1)
0xE5(x7+x6+x5+x2+1)
0xF1(x7+x6+x5+x4+1)
0xF7(x7+x6+x5+x4+x2+x+1)
0xFD(x7+x6+x5+x4+x3+c2+1)
:GF(28)
0x11D(x8+x4+x3+x2+1)
0x12B(x8+x5+x3+x+1)
0x12D(x8+x5+x3+x2+1)
0x14D(x8+x6+x3+x2+1)
0x15F(x8+x6+x4+x3+x2+x+1)
0x163(x8+x6+x5+x+1)
0x165(x8+x6+x5+x2+1)
0x169(x8+x6+x5+x3+1)
0x171(x8+x6+x5+x4+1)
0x187(x8+x7+x2+x+1)
0x18D(x8+x7+x3+x2+1)
0x1A9(x8+x7+x5+x3+1)
0x1C3(x8+x7+x6+x+1)
0x1CF(x8+x7+x5+x3+x2+x+1)
0x1E7(x8+x7+x6+x5+x2+x+1)
0x1F5(x8+x7+x5+x4+x2+1)
总而言之,应用具有n=8次幂的不可约多项式Ox11b(x8+x4+x3+x+1)到图2中来自多项式乘法器12的多项式乘积30,该乘积能够被看作有两个部分32和34。部分32包含低于n次幂的所有那些项,其中n=8,以及部分34代表多项式乘积30中具有8次幂或更高次幂的所有那些项。由于我们选择进行处理的不可约多项式具有n=8次幂,因此将会有128种可能的组合或折叠的部分结果在查找表14中存储。通过构成n次幂或更高次幂部分34的各项的不同组合寻址每一种。有关伽罗瓦域变换器和乘法器的更多信息可以在2003年7月1日授予Stein等人的题为“GALOIS FIELD LINEARTRANSFORMER”的第6587864B2号美国专利、2004年7月20日授予Stein等人的题为“GALOIS FIELD MULTIPLIER SYSTEM”的第6766345B2号美国专利、以及Stein等人在2003年3月24日申请的题为“COMPACT GALOIS FIELD MULTIPLIER ENGINE”的第10/395620号美国专利申请中找到,其中的每一篇文献其全部内容被在此包含引作参考。
根据本发明,当压缩伽罗瓦域计算系统10a作为乘法器(MPY)操作时,压缩伽罗瓦域计算系统10a可以使用伽罗瓦域加法器、包括三个输入(第三输入36可以是0)的“异或”门16a被更加一般化。还可以提供包括加法器电路38和基地址电路40的地址生成器。然后,例如,对于高级加密标准(AES)查找表14a可以具有被加到在线22a上进入的地址上的基地址0以便所述地址将会从0到127,而对于里德-索罗门运算基地址电路40可以将数128相加到在线22a上进入的地址上以访问从128到255的地址。通过这种方式,基于不同的不可约多项式的伽罗瓦域乘法器能够共存在同一个系统中。基于基地址是27的倍数(保证最后7个最低有效位是“零”)的事实,能够将地址生成器的加法器38简化成简单的“或”电路。在图4中,根据本发明的压缩伽罗瓦域计算系统10b通过将来自伽罗瓦域加法器、“异或”门16b的输出向回施加到“异或”门16b,能够作为乘法器-累加器操作。
此外,在图5中,通过应用一个多项式X到多项式乘法器12c而应用另一个多项式Y到伽罗瓦域加法器、“异或”门16c的输入36c,它可以作为乘法器-加法器(MP/Add)10c操作。伽罗瓦域加法器16c的输出在线50上反馈给多项式乘法器12c的另一个输入。伽罗瓦域乘法-加法和其他伽罗瓦域运算的进一步讨论在Stein等人于2002年8月26日申请的题为“GALOIS FIELDMULTIPLY/MULTIPLY-ADD/MULTIPLY ACCUMULATE”的第10/228526号美国专利申请、以及Stein等人在2003年5月16日申请的题为“COMPOUND GALOIS FIELD ENGINE AND GALOISFIELD DIVIDER AND SQUARE ROOT ENGINE AND METHOD”的第10/440330号美国专利申请中进行讨论,其中的每一篇文献其全部内容被在此包含引作参考。
尽管在部分附图而没有在其他附图中显示本发明的具体特征,但是这仅仅是为了方便起见,根据本发明,每个特征可以与其他任何或全部的特征相组合。这里使用的单词“包括”、“包含”、“具有”和“带有”应该作广泛和全面地理解,并不局限于任何物理互连。此外,在本申请中公开的任何实施例并不应该认为是仅有的可能实施例。
其他实施例对于本领域普通技术人员来说是显而易见的并且包含在附属权利要求中。
另外,在针对本专利的专利申请过程中提出的任何修改并不是对在提交的本申请中出现的任何权利要求单元的放弃:本领域的普通技术人员不能合理地被期望描述在字面上包含所有可能等效物的权利要求,在修改时,许多等效物将是不可能预见的并且超出了将要放弃的权利要求单元(如果有的话)的公平解释,以及支持修改的基本原理可能具有仅仅与许多等效物的离题关系,和/或有申请人不能够被期望描述对于所修改的任何权利要求单元的某种非实质性替换的许多其他理由。

Claims (10)

1.一种压缩伽罗瓦域计算系统,包括:
乘法器电路,用于在伽罗瓦域上将带有系数的第一和第二多项式相乘来获得它们的乘积;
部分结果生成器,它响应于所述乘积中的n次幂和更高次幂的项以把n次幂的不可约多项式应用于所述乘积并且提供折叠的部分结果,其中所述部分结果生成器包括查找表,所述查找表包括用于n次幂或更高次幂的组合的折叠的部分结果;以及
包括三输入加法器的伽罗瓦域加法器,其中所述三输入加法器用于组合所述折叠的部分结果、所述乘积中低于n次幂的项和第三输入以获得所述乘积的n次幂的伽罗瓦域变换。
2.根据权利要求1所述的压缩伽罗瓦域计算系统,其中所述查找表包括至少一个折叠的部分结果表。
3.根据权利要求2所述的压缩伽罗瓦域计算系统,其中所述查找表包括用于选择所述的折叠的部分结果表之一的地址生成器。
4.根据权利要求3所述的压缩伽罗瓦域计算系统,其中所述地址生成器提供统计上独立的地址访问。
5.根据权利要求1所述的压缩伽罗瓦域计算系统,其中到所述三输入加法器的第三输入是零,以及所述伽罗瓦域计算系统作为伽罗瓦域乘法器操作。
6.根据权利要求1所述的压缩伽罗瓦域计算系统,其中到所述三输入加法器的第三输入是反馈的伽罗瓦域加法器输出,以及所述伽罗瓦域计算系统作为乘法器-累加器操作。
7.根据权利要求1所述的压缩伽罗瓦域计算系统,其中所述第一和第二多项式之一与被反馈的伽罗瓦域加法器输出一起输入到所述乘法器电路,所述第一和第二多项式中的另一个多项式是到所述伽罗瓦域加法器的第三输入,以及所述伽罗瓦域计算系统作为乘法器-加法器操作。
8.根据权利要求1所述的压缩伽罗瓦域计算系统,其中所述伽罗瓦域加法器包括“异或”电路。
9.根据权利要求3所述的压缩伽罗瓦域计算系统,其中所述地址生成器包括用于组合n次幂和更高次幂的所述项和基地址的值以产生查找表地址的“或”电路。
10.一种压缩伽罗瓦域计算系统,包括:
乘法器电路,用于在伽罗瓦域上将带有系数的第一和第二多项式相乘来获得它们的乘积;
部分结果生成器,它响应于所述乘积中的n次幂和更高次幂的项以把n次幂的不可约多项式应用于所述乘积并且提供折叠的部分结果,其中所述部分结果生成器包括查找表,所述查找表包括用于n次幂或更高次幂的组合的折叠的部分结果;以及
包括三输入加法器的伽罗瓦域加法器,其中所述三输入加法器用于组合所述折叠的部分结果、所述乘积中低于n次幂的项和第三输入以执行伽罗瓦域乘法运算。
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Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140055290A1 (en) 2003-09-09 2014-02-27 Peter Lablans Methods and Apparatus in Alternate Finite Field Based Coders and Decoders
US7865806B2 (en) * 2006-03-03 2011-01-04 Peter Lablans Methods and apparatus in finite field polynomial implementations
DE102007002230A1 (de) * 2007-01-10 2008-07-17 Benecke-Kaliko Ag Thermoplastische Folie
US8312551B2 (en) * 2007-02-15 2012-11-13 Harris Corporation Low level sequence as an anti-tamper Mechanism
US7937427B2 (en) 2007-04-19 2011-05-03 Harris Corporation Digital generation of a chaotic numerical sequence
US8611530B2 (en) * 2007-05-22 2013-12-17 Harris Corporation Encryption via induced unweighted errors
US7921145B2 (en) * 2007-05-22 2011-04-05 Harris Corporation Extending a repetition period of a random sequence
US7995757B2 (en) * 2007-05-31 2011-08-09 Harris Corporation Closed galois field combination
US7974413B2 (en) * 2007-06-07 2011-07-05 Harris Corporation Spread spectrum communications system and method utilizing chaotic sequence
US7970809B2 (en) * 2007-06-07 2011-06-28 Harris Corporation Mixed radix conversion with a priori defined statistical artifacts
US7962540B2 (en) 2007-06-07 2011-06-14 Harris Corporation Mixed radix number generator with chosen statistical artifacts
US8005221B2 (en) * 2007-08-01 2011-08-23 Harris Corporation Chaotic spread spectrum communications system receiver
US7995749B2 (en) * 2007-10-30 2011-08-09 Harris Corporation Cryptographic system configured for extending a repetition period of a random sequence
US20090157788A1 (en) * 2007-10-31 2009-06-18 Research In Motion Limited Modular squaring in binary field arithmetic
US8923510B2 (en) 2007-12-28 2014-12-30 Intel Corporation Method and apparatus for efficiently implementing the advanced encryption standard
US8180055B2 (en) * 2008-02-05 2012-05-15 Harris Corporation Cryptographic system incorporating a digitally generated chaotic numerical sequence
US8363830B2 (en) * 2008-02-07 2013-01-29 Harris Corporation Cryptographic system configured to perform a mixed radix conversion with a priori defined statistical artifacts
US8040937B2 (en) * 2008-03-26 2011-10-18 Harris Corporation Selective noise cancellation of a spread spectrum signal
US8139764B2 (en) * 2008-05-06 2012-03-20 Harris Corporation Closed galois field cryptographic system
US8320557B2 (en) * 2008-05-08 2012-11-27 Harris Corporation Cryptographic system including a mixed radix number generator with chosen statistical artifacts
CN102084335B (zh) * 2008-05-12 2015-01-07 高通股份有限公司 任意伽罗瓦域算术在可编程处理器上的实施
CN101587433B (zh) * 2008-05-22 2011-09-21 中兴通讯股份有限公司 一种基于多级查表的压缩伽罗华域的执行方法及系统
US8145692B2 (en) * 2008-05-29 2012-03-27 Harris Corporation Digital generation of an accelerated or decelerated chaotic numerical sequence
US8064552B2 (en) * 2008-06-02 2011-11-22 Harris Corporation Adaptive correlation
US8068571B2 (en) * 2008-06-12 2011-11-29 Harris Corporation Featureless coherent chaotic amplitude modulation
US8325702B2 (en) 2008-08-29 2012-12-04 Harris Corporation Multi-tier ad-hoc network in which at least two types of non-interfering waveforms are communicated during a timeslot
US8165065B2 (en) 2008-10-09 2012-04-24 Harris Corporation Ad-hoc network acquisition using chaotic sequence spread waveform
US8150031B2 (en) * 2008-12-19 2012-04-03 Intel Corporation Method and apparatus to perform redundant array of independent disks (RAID) operations
US8406276B2 (en) * 2008-12-29 2013-03-26 Harris Corporation Communications system employing orthogonal chaotic spreading codes
US8351484B2 (en) * 2008-12-29 2013-01-08 Harris Corporation Communications system employing chaotic spreading codes with static offsets
US8457077B2 (en) * 2009-03-03 2013-06-04 Harris Corporation Communications system employing orthogonal chaotic spreading codes
US8428102B2 (en) * 2009-06-08 2013-04-23 Harris Corporation Continuous time chaos dithering
US8509284B2 (en) * 2009-06-08 2013-08-13 Harris Corporation Symbol duration dithering for secured chaotic communications
US8428103B2 (en) * 2009-06-10 2013-04-23 Harris Corporation Discrete time chaos dithering
US8363700B2 (en) 2009-07-01 2013-01-29 Harris Corporation Rake receiver for spread spectrum chaotic communications systems
US8340295B2 (en) 2009-07-01 2012-12-25 Harris Corporation High-speed cryptographic system using chaotic sequences
US8406352B2 (en) * 2009-07-01 2013-03-26 Harris Corporation Symbol estimation for chaotic spread spectrum signal
US8379689B2 (en) * 2009-07-01 2013-02-19 Harris Corporation Anti-jam communications having selectively variable peak-to-average power ratio including a chaotic constant amplitude zero autocorrelation waveform
US8385385B2 (en) * 2009-07-01 2013-02-26 Harris Corporation Permission-based secure multiple access communication systems
US8369376B2 (en) * 2009-07-01 2013-02-05 Harris Corporation Bit error rate reduction in chaotic communications
US8428104B2 (en) 2009-07-01 2013-04-23 Harris Corporation Permission-based multiple access communications systems
US8848909B2 (en) 2009-07-22 2014-09-30 Harris Corporation Permission-based TDMA chaotic communication systems
US8369377B2 (en) * 2009-07-22 2013-02-05 Harris Corporation Adaptive link communications using adaptive chaotic spread waveform
US8345725B2 (en) 2010-03-11 2013-01-01 Harris Corporation Hidden Markov Model detection for spread spectrum waveforms
CN102314330B (zh) * 2011-09-09 2013-12-25 华南理工大学 一种复合有限域乘法器
JP5840086B2 (ja) * 2012-07-17 2016-01-06 日本電信電話株式会社 縮約装置、縮約方法、およびプログラム
CN103729162A (zh) * 2012-10-15 2014-04-16 北京兆易创新科技股份有限公司 伽罗瓦域运算系统和方法
US9513906B2 (en) 2013-01-23 2016-12-06 International Business Machines Corporation Vector checksum instruction
US9471308B2 (en) 2013-01-23 2016-10-18 International Business Machines Corporation Vector floating point test data class immediate instruction
US9778932B2 (en) 2013-01-23 2017-10-03 International Business Machines Corporation Vector generate mask instruction
US9715385B2 (en) 2013-01-23 2017-07-25 International Business Machines Corporation Vector exception code
US9823924B2 (en) 2013-01-23 2017-11-21 International Business Machines Corporation Vector element rotate and insert under mask instruction
US9804840B2 (en) 2013-01-23 2017-10-31 International Business Machines Corporation Vector Galois Field Multiply Sum and Accumulate instruction
US9417848B2 (en) * 2014-03-28 2016-08-16 Storart Technology Co. Ltd. Serial multiply accumulator for galois field
US9619207B1 (en) * 2014-10-27 2017-04-11 Altera Corporation Circuitry and methods for implementing Galois-field reduction
US9740456B2 (en) * 2015-04-23 2017-08-22 Altera Corporation Circuitry and methods for implementing Galois-field reduction
US10763861B2 (en) 2016-02-13 2020-09-01 HangZhou HaiCun Information Technology Co., Ltd. Processor comprising three-dimensional memory (3D-M) array
US10700686B2 (en) 2016-03-05 2020-06-30 HangZhou HaiCun Information Technology Co., Ltd. Configurable computing array
US11527523B2 (en) 2018-12-10 2022-12-13 HangZhou HaiCun Information Technology Co., Ltd. Discrete three-dimensional processor
US10075169B2 (en) 2016-03-05 2018-09-11 Chengdu Haicun Ip Technology Llc Configurable computing array based on three-dimensional vertical writable memory
US10312917B2 (en) 2016-03-05 2019-06-04 HangZhou HaiCun Information Technology Co., Ltd. Configurable computing array for implementing complex math functions
US11080229B2 (en) 2016-02-13 2021-08-03 HangZhou HaiCun Information Technology Co., Ltd. Processor for calculating mathematical functions in parallel
US10075168B2 (en) 2016-03-05 2018-09-11 XiaMen HaiCun IP Technology LLC Configurable computing array comprising three-dimensional writable memory
US10141939B2 (en) 2016-03-05 2018-11-27 Chengdu Haicun Ip Technology Llc Configurable computing array using two-sided integration
US11966715B2 (en) 2016-02-13 2024-04-23 HangZhou HaiCun Information Technology Co., Ltd. Three-dimensional processor for parallel computing
US9838021B2 (en) 2016-03-05 2017-12-05 HangZhou HaiCun Information Technology Co., Ltd. Configurable gate array based on three-dimensional writable memory
US10848158B2 (en) 2016-02-13 2020-11-24 HangZhou HaiCun Information Technology Co., Ltd. Configurable processor
US9948306B2 (en) 2016-03-05 2018-04-17 HangZhou HaiCun Information Technology Co., Ltd. Configurable gate array based on three-dimensional printed memory
US10148271B2 (en) 2016-03-05 2018-12-04 HangZhou HaiCun Information Technology Co., Ltd. Configurable computing array die based on printed memory and two-sided integration
US10305486B2 (en) 2016-03-05 2019-05-28 HangZhou HaiCun Information Technology Co., Ltd. Configurable computing array package based on printed memory
US10230375B2 (en) 2016-03-05 2019-03-12 HangZhou HaiCun Information Technology Co., Ltd. Configurable gate array comprising three-dimensional printed memory
US10116312B2 (en) 2016-03-05 2018-10-30 HangZhou HaiCun Information Technology Co., Ltd. Configurable gate array based on three-dimensional writable memory
US10084453B2 (en) 2016-03-05 2018-09-25 Chengdu Haicun Ip Technology Llc Configurable computing array
US10445067B2 (en) 2016-05-06 2019-10-15 HangZhou HaiCun Information Technology Co., Ltd. Configurable processor with in-package look-up table
US10372359B2 (en) 2016-05-10 2019-08-06 Chengdu Haicun Ip Technology Llc Processor for realizing at least two categories of functions
US11032061B2 (en) * 2018-04-27 2021-06-08 Microsoft Technology Licensing, Llc Enabling constant plaintext space in bootstrapping in fully homomorphic encryption
US11734550B2 (en) 2018-12-10 2023-08-22 HangZhou HaiCun Information Technology Co., Ltd. Discrete three-dimensional processor
US11296068B2 (en) 2018-12-10 2022-04-05 HangZhou HaiCun Information Technology Co., Ltd. Discrete three-dimensional processor
US11632231B2 (en) * 2020-03-05 2023-04-18 Novatek Microelectronics Corp. Substitute box, substitute method and apparatus thereof
CN113922943B (zh) * 2021-09-29 2023-09-19 哲库科技(北京)有限公司 Sbox电路、运算方法及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278781A (en) * 1987-11-12 1994-01-11 Matsushita Electric Industrial Co., Ltd. Digital signal processing system
US20030110196A1 (en) * 2001-11-30 2003-06-12 Yosef Stein Galois field multiply/ multiply-add/multiply accumulate
US20030135530A1 (en) * 2001-09-20 2003-07-17 Stmicroelectronics, Inc. Flexible galois field multiplier
CN1589429A (zh) * 2001-11-30 2005-03-02 阿纳洛格装置公司 伽罗瓦域乘法器系统

Family Cites Families (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1181461B (de) 1963-10-08 1964-11-12 Telefunken Patent Adressenaddierwerk einer programm-gesteuerten Rechenmaschine
DE1905101C3 (de) 1969-02-01 1978-06-22 Bayer Ag, 5090 Leverkusen Siloxanmodifizierte Carbamidsäurederivate
US3805037A (en) 1972-02-22 1974-04-16 J Ellison N{40 th power galois linear gate
US4722050A (en) 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
US4918638A (en) 1986-10-15 1990-04-17 Matsushita Electric Industrial Co., Ltd. Multiplier in a galois field
FR2605769B1 (fr) 1986-10-22 1988-12-09 Thomson Csf Operateur polynomial dans les corps de galois et processeur de traitement de signal numerique comportant un tel operateur
US5073864A (en) 1987-02-10 1991-12-17 Davin Computer Corporation Parallel string processor and method for a minicomputer
US4847801A (en) 1987-10-26 1989-07-11 Cyclotomics, Inc. Compact galois field multiplier
DE68925840T2 (de) 1988-04-27 1996-09-12 Nec Corp Speicherzugriffssteuerungsvorrichtung, die aus einer verringerten Anzahl von LSI-Schaltungen bestehen kann
US5062057A (en) 1988-12-09 1991-10-29 E-Machines Incorporated Computer display controller with reconfigurable frame buffer memory
US5095525A (en) 1989-06-26 1992-03-10 Rockwell International Corporation Memory transformation apparatus and method
US5214763A (en) 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
US5577262A (en) 1990-05-22 1996-11-19 International Business Machines Corporation Parallel array processor interconnections
US5446850A (en) 1991-01-15 1995-08-29 International Business Machines Corporation Cross-cache-line compounding algorithm for scism processors
US5182746A (en) 1991-03-28 1993-01-26 Intel Corporation Transceiver interface
US5386523A (en) 1992-01-10 1995-01-31 Digital Equipment Corporation Addressing scheme for accessing a portion of a large memory space
US5745563A (en) * 1992-02-25 1998-04-28 Harris Corporation Telephone subscriber line circuit, components and methods
US5379243A (en) 1992-08-31 1995-01-03 Comstream Corporation Method and apparatus for performing finite field division
US5528526A (en) 1993-02-02 1996-06-18 Motorola, Inc. Arbitrary repeating pattern detector
US5383142A (en) 1993-10-01 1995-01-17 Hewlett-Packard Company Fast circuit and method for detecting predetermined bit patterns
KR0135846B1 (ko) 1994-02-02 1998-06-15 김광호 룩-업-테이블장치
US5832290A (en) 1994-06-13 1998-11-03 Hewlett-Packard Co. Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems
US5689452A (en) 1994-10-31 1997-11-18 University Of New Mexico Method and apparatus for performing arithmetic in large galois field GF(2n)
US5754563A (en) 1995-09-11 1998-05-19 Ecc Technologies, Inc. Byte-parallel system for implementing reed-solomon error-correcting codes
US6317819B1 (en) 1996-01-11 2001-11-13 Steven G. Morton Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction
US5768168A (en) 1996-05-30 1998-06-16 Lg Semicon Co., Ltd. Universal galois field multiplier
US5996066A (en) 1996-10-10 1999-11-30 Sun Microsystems, Inc. Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions
US6078937A (en) 1996-12-19 2000-06-20 Vlsi Technology, Inc. Barrel shifter, circuit and method of manipulating a bit pattern
GB9627069D0 (en) 1996-12-30 1997-02-19 Certicom Corp A method and apparatus for finite field multiplication
KR100322468B1 (ko) * 1997-02-12 2002-04-22 윤종용 컴퓨터의팬고정장치와컴퓨터의팬고정장치를사용하는휴대용컴퓨터
US6173429B1 (en) * 1997-03-14 2001-01-09 Harris Corporation Apparatus for providing error correction data in a digital data transfer system
US6002728A (en) 1997-04-17 1999-12-14 Itt Manufacturing Enterprises Inc. Synchronization and tracking in a digital communication system
GB9707861D0 (en) 1997-04-18 1997-06-04 Certicom Corp Arithmetic processor
US5894427A (en) 1997-11-12 1999-04-13 Intel Corporation Technique for concurrent detection of bit patterns
US6199086B1 (en) 1997-12-24 2001-03-06 Motorola, Inc. Circuit and method for decompressing compressed elliptic curve points
US6223320B1 (en) 1998-02-10 2001-04-24 International Business Machines Corporation Efficient CRC generation utilizing parallel table lookup operations
US5999959A (en) 1998-02-18 1999-12-07 Quantum Corporation Galois field multiplier
GB9806687D0 (en) 1998-03-27 1998-05-27 Memory Corp Plc Memory system
US6138208A (en) 1998-04-13 2000-10-24 International Business Machines Corporation Multiple level cache memory with overlapped L1 and L2 memory access
US5996057A (en) 1998-04-17 1999-11-30 Apple Data processing system and method of permutation with replication within a vector register file
KR100296958B1 (ko) 1998-05-06 2001-09-22 이석우 블록 데이터 암호화 장치
US6199087B1 (en) 1998-06-25 2001-03-06 Hewlett-Packard Company Apparatus and method for efficient arithmetic in finite fields through alternative representation
US6631466B1 (en) 1998-12-31 2003-10-07 Pmc-Sierra Parallel string pattern searches in respective ones of array of nanocomputers
JP4177526B2 (ja) * 1999-08-05 2008-11-05 富士通株式会社 乗算剰余演算方法および乗算剰余回路
US6434662B1 (en) 1999-11-02 2002-08-13 Juniper Networks, Inc. System and method for searching an associative memory utilizing first and second hash functions
US6539477B1 (en) 2000-03-03 2003-03-25 Chameleon Systems, Inc. System and method for control synthesis using a reachable states look-up table
US6384713B1 (en) 2000-04-21 2002-05-07 Marvell International, Ltd. Serial comparator
US6480845B1 (en) 2000-06-14 2002-11-12 Bull Hn Information Systems Inc. Method and data processing system for emulating virtual memory working spaces
US6389099B1 (en) * 2000-11-13 2002-05-14 Rad Source Technologies Inc. Irradiation system and method using X-ray and gamma-ray reflector
US6738794B2 (en) 2001-04-10 2004-05-18 Analog Devices, Inc. Parallel bit correlator
WO2002093745A2 (en) 2001-05-16 2002-11-21 Koninklijke Philips Electronics N.V. Reconfigurable logic device
US6957243B2 (en) * 2001-10-09 2005-10-18 International Business Machines Corporation Block-serial finite field multipliers
US7269615B2 (en) 2001-12-18 2007-09-11 Analog Devices, Inc. Reconfigurable input Galois field linear transformer system
US6587864B2 (en) 2001-11-30 2003-07-01 Analog Devices, Inc. Galois field linear transformer
US7177891B2 (en) 2002-10-09 2007-02-13 Analog Devices, Inc. Compact Galois field multiplier engine
US7508937B2 (en) 2001-12-18 2009-03-24 Analog Devices, Inc. Programmable data encryption engine for advanced encryption standard algorithm
US7000090B2 (en) 2002-01-21 2006-02-14 Analog Devices, Inc. Center focused single instruction multiple data (SIMD) array system
US6865661B2 (en) 2002-01-21 2005-03-08 Analog Devices, Inc. Reconfigurable single instruction multiple data array
US6941446B2 (en) 2002-01-21 2005-09-06 Analog Devices, Inc. Single instruction multiple data array cell
US6829694B2 (en) * 2002-02-07 2004-12-07 Analog Devices, Inc. Reconfigurable parallel look up table system
US7693928B2 (en) 2003-04-08 2010-04-06 Analog Devices, Inc. Galois field linear transformer trellis system
US7526518B2 (en) * 2004-10-13 2009-04-28 Cisco Technology, Inc. Galois field multiplication system and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278781A (en) * 1987-11-12 1994-01-11 Matsushita Electric Industrial Co., Ltd. Digital signal processing system
US20030135530A1 (en) * 2001-09-20 2003-07-17 Stmicroelectronics, Inc. Flexible galois field multiplier
US20030110196A1 (en) * 2001-11-30 2003-06-12 Yosef Stein Galois field multiply/ multiply-add/multiply accumulate
CN1589429A (zh) * 2001-11-30 2005-03-02 阿纳洛格装置公司 伽罗瓦域乘法器系统

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