CN101027634A - 数据传送机制 - Google Patents
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Abstract
一种用于在程序主体和存储资源之间传送数据的方法。该方法包括在一个数据处理主体和一个存储资源之间传送数据,指定这个存储资源用于经由一根推入总线将数据推入该数据处理代理中,并指定这个存储资源用于经由一根拉出总线接收来自该数据处理代理的数据,其中,该推入总线具有若干仲裁其使用的信号源,该拉出总线具有若干仲裁其使用的目标。
Description
背景
典型的计算机处理系统具有使不同的组件之间能够互相通信的总线。这些组件之间的总线通信允许公共地通过一条数据通路的数据传送。一般说来,该数据通路使一个数据处理代理,例如,中央处理器(CPU)或处理器,与像硬磁盘驱动器、设备适配器、等等这样的其它的组件互连。
附图的简要说明
图1是一个数据处理系统的框图。
图2是图1中的数据处理系统的详细框图。
图3是图1中的数据处理系统中的读出过程的流程图。
图4是图1中的数据处理系统中的写入过程的流程图。
图5是图1中的数据处理系统的推入操作的流程图。
图6是图1中的数据处理系统的拉出操作的流程图。
说明
结构:
参考图1,数据处理系统10包括一个并行的、基于硬件的多线程网络处理器12。基于硬件的多线程网络处理器12与存储系统或存储资源14耦合。存储系统14包括动态随机存储器(DRAM)14a和静态随机存储器14b(SRAM)。数据处理系统10对于可分成并行的子任务或函数的任务特别有用。尤其是,基于硬件的多线程网络处理器12对于基于带宽而不是基于等待时间的任务特别有用。基于硬件的多线程网络处理器12具有若干微引擎或编程引擎16,它们中的每一个都具有若干硬件控制的线程,其中,这些线程同时有效并且独立地对一个特定的任务起作用。
每一个编程引擎16在与该程序计数器相关的硬件和位置中提供程序计数器。有效地,相应的上下文或线程能够在每一个编程引擎16上同时有效,虽然在任何一个时间实际上只有一个在运行。
在这个例子中,八个编程引擎16在图1被示出了。每一个编程引擎16具有处理八个硬件线程或上下文的能力。这八个编程引擎16合包括存储资源14和总线接口的共享的资源一起运行。基于硬件的多线程网络处理器12包括一个动态随机存储器(DRAM)控制器18a和一个静态随机存储器(SRAM)控制器18b。DRAM存储器14a和DRAM控制器18a通常用于处理大量数据,例如,处理来自网络数据包的有效负载的处理。SRAM存储器14b和SRAM控制器18b被用在用于低等待时间、快速访问的任务的网络实现中,例如访问查找表、用于核心处理器20的存储器,等等。
推入总线26a-26b和拉出总线28a-28b被用来在编程引擎16与DRAM存储器14a和SRAM存储器14b之间传送数据。特别地,推入总线26a-26b是单向总线,它将来自存储资源14的数据传送到编程引擎16,而拉出总线28a-28b将来自编程引擎16的数据传送到存储资源14。
这八个编程引擎16根据数据的特性访问DRAM存储器14a或是SRAM存储器14b。因此,低等待时间、低带宽的数据存储在SRAM存储器14b中并从其中读取,而那些等待时间对它们不是那么重要的高带宽数据,存储在DRAM存储器14a中并从其中读取。编程引擎16可以对DRAM控制器18a或是SRAM控制器18b执行存储器访问指令。
基于硬件的多线程网络处理器12还包括一个用于对基于硬件的多线程网络处理器12的其它资源载入微指令控制的核心处理器20,。在这个例子中,核心处理器20是基于XScaleTM的结构。
核心处理器20执行通用计算机类型的函数,例如处理协议、异常事件以及对数据包处理的额外支持,其中,在数据包处理中,编程引擎16把数据包当作像是在边界条件中那样的更复杂的数据处理。核心处理器20具有一个操作系统(未示出)。通过操作系统(OS),核心处理器20可以调用函数来对编程引擎16进行操作。核心处理器20可以使用任何支持的OS,特别是实时OS。对于作为XScaleTM的结构来实现的核心处理器20来说,可以使用像Microsoft NT实时、VXWorks和μCOS,或能在因特网上使用的免费软件OS这样的操作系统。
硬件多线程的优点可以通过SRAM或DRAM存储器的访问来说明。作为一个例子,来自编程引擎16之一的,一个通过上下文(例如,Thread_0)来请求的SRAM访问,会使该SRAM控制器18b启动一个对SRAM存储器14b的访问。SRAM控制器18b访问SRAM存储器14b,读取来自SRAM存储器14b的数据,并将数据返回给请求的编程引擎16。
在SRAM的访问过程中,如果编程引擎16中的一个仅有单独的一个可以操作的线程,那么编程引擎便会处于睡眠状态直到数据从SRAM存储器14b返回。
通过使用在编程引擎16中间的每一个之内的硬件关联对换,该硬件关联对换使得在那同一个编程引擎中,其它具有唯一程序计数器的上下文能够运行。因此,在第一个线程,Thread_0,在等待要返回所读取的数据时,另一个线程,例如,Thread_1可以运行。在运行过程中,Thread_1可以访问DRAM存储器14a。在Thread_1对DRAM单元进行操作,并且Thread_0正在对SRAM单元进行操作的时候,一个新的线程,例如,Thread_2现在可以在编程引擎16中进行操作。Thread_2可以操作某一数量的时间,直到它需要访问存储器或是执行一些其它长等待时间的操作,例如对总线接口进行访问。因此,同时地,处理器12可以具有总线操作、全部由编程引擎16中的一个完成或对其进行操作的SRAM操作以及DRAM操作,以及具有一个以上的可以用来处理更多工作的线程。
硬件关联对换也使任务的完成同步。例如,两个线程可以命中共享的存储器资源,例如,SRAM存储器14b。分开的功能装置中的每一个,例如,SRAM控制器18b,以及DRAM控制器18a,当他们完成一个来自编程引擎线程或上下文的请求的任务的时候,报告返回一个通知操作完成的标志。当编程引擎16接收到这个标志的时候,编程引擎16可以决定启动哪一个线程。
一个用于该基于硬件的多线程处理器12的应用的例子是作为网络处理器。作为网络处理器,该基于硬件的多线程处理器12连接到像媒体访问控制器(MAC)设备,例如,10/100BaseT Octal MAC13a或吉比特以太网(未示出)这样的网络设备。总之,作为网络处理器,基于硬件的多线程处理器12可以连接到任何类型的通信设备或是接收或发送大量数据的接口。在网络应用中运行的计算机处理系统10可以接收网络数据包并以并行方式处理它们。
编程引擎上下文:
如上所述,编程引擎16中的每一个都支持八个上下文的多线程运行。这允许一个线程可以正好在另一个线程发出了存储器访问,并且在进行更多工作之前必须等待直到访问结束之后开始运行。多线程运行是达到编程引擎16的高效率的硬件运行的关键,因为存储器的等待时间非常重要。多线程运行允许编程引擎16通过执行跨越几个线程的有效的独立的工作来隐藏存储器的等待时间。
这编程引擎16的八个上下文中的每一个,为了允许高效率的上下文对换,具有它自己的寄存器组、程序计数器、以及上下文具体的局部寄存器。具有一个副本的每一个上下文消除了为每一个上下文对换,将上下文具体的信息传送到共享存储器和编程引擎并从它们中传送上下文具体的信息的需要。快速上下文对换允许上下文执行计算当其它上下文等待输出输入(I/O),通常是,外部存储器访问结束或是等待来自其它上下文或硬件装置的信号时执行计算。
例如,编程引擎16通过提供八个程序计数器和八个上下文相关的寄存器组来运行八个上下文。有许多不同类型的上下文相关寄存器,例如通用寄存器(GPRs)、交互编程代理寄存器、静态随机存储器(SRAM)输入传送寄存器、动态随机存储器(DRAM)输入传送寄存器、SRAM输出传送寄存器、DRAM输出传送寄存器。也可以使用局部存储器寄存器。
例如,GPRs被用于通用编程用途。只能在程序控制下读写GPRs。该GPRs,当在指令中用作一个信号源的时候,提供操作数给一个运行数据通路(未示出)。当GPRs在指令中用作一个目标的时候,用运行逻辑单元数据通路的结果写入它。如前所述,编程引擎16也包括IO传送寄存器。IO传送寄存器被用于传送数据到编程引擎16并从中读取以及其外部的位置,例如DRAM存储器14a和SRAM存储器14b等,
总线的结构:
参考图2,基于硬件的多线程处理器12被非常详细地示出了。DRAM存储器14a和SRAM存储器14b分别连接到DRAM存储器控制器18a和SRAM存储器控制器18b。DRAM存储器控制器18a被连接到与编程引擎16a连在一起的拉出总线仲裁器30a和推入总线仲裁器32a。SRAM存储器控制器18b被连接到与编程引擎16b连在一起的拉出总线仲裁器30b和推入总线仲裁器32b。总线26a-26b和28a-28b组成了用于在编程引擎16a-16b与DRAM存储器14a和SRAM存储器14b之间传送数据的主总线。来自编程引擎16a-16b的任何线程都可以访问DRAM控制器18a和SRAM控制器18b。
特别地,推入总线26a-26b具有多个像存储器控制器通道和内部读寄存器(未示出)这样的存储器资源,它们经由推入仲裁器32a-32b仲裁来使用推入总线26a-26b。任何推入数据传送的目标(例如,编程引擎16)通过对随推入数据一起被驱动或发送的Push_ID进行解码,来识别该数据是什么时候被“推入”到它里面的。该拉出总线28a-28b也具有为了使用拉出总线28a-28b而进行仲裁的多个目标(例如,将数据写入不同的存储器控制器通道或是可写入的内部寄存器)。该拉出总线28a-28b具有一个Pull_ID,例如是在拉出数据两周期之前被驱动或发送的。
数据函数分布在编程引擎16之中。DRAM存储器14a和SRAM存储器14b的连通是通过命令请求来实现的。一个命令请求可以是一个存储器请求。例如,命令请求可以将数据从位于编程引擎16a中的寄存器传送到一个共享资源中,例如DRAM存储器14a、SRAM存储器14b。命令或请求被发送到功能单元和共享资源中的每一个。像I/O命令(例如,SRAM的读出、SRAM的写入、DRAM的读出、DRAM的写入、载入来自接收存储缓冲器的数据、将数据传送到发送存储缓冲器)这样的命令指定在编程引擎16中的上下文相关源或是目标寄存器。
总之,编程引擎和存储器资源之间的数据传送指定了用于经由推入总线来将数据推入到一个数据处理代理的存储器资源,并指定了用于经由拉出总线来接收来自该数据处理代理的数据的存储器资源,其中,该推入总线具有若干仲裁其使用的信号源,该拉出总线具有若干仲裁其使用的目标。
读出过程:
参考图3,数据读出过程50是由推入总线26a-26b在编程引擎16的读出阶段期间来执行的。作为读出过程50的一部分,编程引擎执行(52)一个上下文。编程引擎16发出(54)一个读出命令到存储器控制器18a-18b,而存储器控制器18a-18b处理(56)关于存储器资源中的一个的请求,该存储器资源也就是DRAM存储器14a或SRAM存储器14b。在读出指令发出后(54),编程引擎16就检查(58)该读出命令所读出数据是否需要来继续该程序上下文。如果需要该读出数据来继续该程序上下文或线程,就换出该上下文(60)。编程引擎16检查(62)以保证存储器控制器18a-18b已经完成了该请求。当存储器控制器已经完成了该请求的时候,将该上下文换回进来(64)。
如果不需要该请求来继续该上下文的执行,编程引擎16检查(68)存储器控制器18a-18b是否已经完成了该请求。如果存储器控制器18a-18b还没有完成该请求,回送发生并且进行进一步的检查(58)。如果存储器控制器18a-18b已经完成了该请求,当读取数据已经从存储器资源中获得的时候,存储器控制器18a-18b将该数据推入(70)到由该读出命令指定的上下文相关的输入传送寄存器中。存储器控制器在编程引擎16中设置一个使发出该读出命令的上下文变得有效的信号。编程引擎16读出(72)在输入传送寄存器中的被请求数据,并继续(74)该上下文的执行。
写入过程:
参考图4,数据写入过程80是由拉出总线28a-28b在编程引擎16的写入阶段期间来执行的。在写入过程80期间,编程引擎执行(82)一个上下文。编程引擎16a将该数据载入(84)到输出传送寄存器中并发出(86)一个写入命令或请求到存储器控制器18a-18b。将输出传送寄存器设置(88)为只读状态。在将输出传送寄存器设置(88)为只读状态后,编程引擎16检查来自编程引擎16的写入命令是否需要该请求来继续该程序上下文或线程。如果是,就换出(92)该上下文。
如果不需要该请求来继续该上下文或线程,存储器控制器18a-18b从输出传送寄存器中提取或拉出(94)数据,并用信号来通知(96)编程引擎16对输出传送寄存器进行解锁。然后编程引擎16检查(98)该上下文是否被换出了。如果是被换出了,将该上下文换回来,而如果不是这样的话,编程引擎16继续(102)该上下文的执行。从而,该发出信号的上下文可以再使用输出传送寄存器。该信号也可以用来使该上下文变得有效,如果它在写入命令中被换出了。
数据推入操作:
参考图5,发生在计算机处理系统的推入总线26a-26b中的数据推入操作110,被以不同处理周期的方式示出了,例如周期0至周期5。每一个目标,例如,DRAM存储器14a或SRAM存储器14b,发送或驱动(112)一个Target_#_Push_ID到推入仲裁器中,在这里#表示不同上下文的编号,像上下文#0至上下文#7这样。该Target_#_Push_ID是从该读出命令和一个关于它要推入到推入仲裁器32a-32b中的信息的数据差错位(例如,在Push_ID中,跟在目标后,表示信号源地址递增的编号)中得到的。至于Push_ID,每一个字母表示一个对特定目标的推入操作。目标的Push_ID“无”表示Push_ID为空值。目标也将该Target_#_Push_Data发送到推入仲裁器。
Push_ID和Push_Data被登记(114)并入队(116)到推入仲裁器32a-32b中的先进先出(FIFOs)中,除非确定了确定Target_#_Push_Q_Full信号。这个信号表示,在推入仲裁器32a-32b中,用于那个特定目标的Push_ID和Push_Data FIFOs差不多满了。载这种情况中,推入仲裁器32a-32b不曾登记一个Push_ID或Push_Data,并且该目标不改变它。这个通道将由推入仲裁器32a-32b占有的Push_ID和Push_Data变换为用于下一个字传送的那些,或空值如果它没有其它有效的传送。由于在Push_Q_Full信号中的等待时间,推入仲裁器32a-32b必须适应每个目标正在处理的Push_ID和Push_Data的编号的最坏情况。
推入仲裁器32a-32b可以在每一个周期在所有有效Push_IDs之间进行仲裁(118)并发送中间Push_ID。仲裁策略可以是循环的,一个优先方案或甚至是可编程的。若干从推入仲裁器32a-32b到目标的数据推入并不保证在连续的周期内。推入仲裁器32a-32b发送(12)中间Push_Data,而Push_ID被发送(120)到该目标。是由该目标来更新每一个它为每一个它想要推入的数据字发出的Push_ID的目的地址。Push_Data被发送(122)到该目标。在该目标,从目标得到Push_ID到目标得到Push_Data的时间是通过一个处理周期来调节的。
数据拉出操作:
参考图6,发生在计算机处理系统的拉出总线28a-28b中的数据拉出操作130,被以不同处理周期的方式示出了,(例如周期0至周期7)。每一个目标,例如,DRAM存储器14a或SRAM存储器14b,将关于它要拉出的信息的完整的Target_#_Pull_ID(例如,在Pull_ID中,跟在目标后,表示信号源地址递增的编号)和长度(从写命令中得到的)发送或驱动(132)到目标。对于Pull_ID,每一个字母表示一个来自例如存储资源14这样的特定信号源的拉出操作。信号源的Pull_ID“无”表示Pull_ID为空值。当该目标确定它的Pull_ID的时候,它必须具有供拉出数据用的缓冲空间。
Pull_ID被登记(134)并入队(136)到拉出仲裁器30a-30b中的先进先出(FIFO)中,除非确定了Target#Pull_Q_Full信号。这个信号表示,在拉出仲裁器30a-30b中,用于那个特定目标的Pull_ID的队差不多满了。载这种情况中,拉出仲裁器30a-30b不曾登记一个Pull_ID,并且该目标不改变它。这个目标将由拉出仲裁器30a-30b占有的Pull_ID,变换为用于下一个字符组传送的那些,或空值如果它没有其它有效的Pull_ID。由于在Pull_Q_Full信号中的等待时间,拉出仲裁器30a-30b必须适应每个目标正在处理的Pull_ID的编号的最坏情况。
拉出仲裁器30a-30b可以仲裁(138)当前有效的Pull_ID中的每个周期。仲裁策略可以是循环的,一个优先方案或甚至是可编程的。
拉出仲裁器30a-30b发送(140)选中的Pull_ID到该信号源。从拉出仲裁器30a-30b发送Pull_ID到该信号源提供数据的时间被调节为在三个处理周期内。拉出仲裁器30a-30b为每一个新的数据条目更新该Pull_ID的“信号地址”字段。该Pull_Data被从该信号源拉出(142)并被发送到目标。
拉出仲裁器30a-30b也确定(146)一个关于选中的目标的Target_#_Take_Data。确定该信号是为了在每一个周期一个有效数据字被发送到目标。然而,该确定并不保证是在连续的处理周期中。拉出仲裁器30a-30b每次仅确定至多一个Target_#_Take_Data信号。
对于在具有不同总线宽度的目标和主导装置之间的传送,需要拉出仲裁器30a-30b来进行调整。例如,SRAM控制器18b可以每个处理周期接收八个字节的数据,但是编程引擎16可以每个周期仅输送四个字节。假若这样,拉出仲裁器30a-30b可以用来每个处理周期接收四个字节,将它们合并组装为八个字节,并将该数据发送到DRAM控制器18a。
其它实施方式:
可以理解,只要已经结合其中详细的说明来说明了上面的例子,上述的描述是用来说明而不是限制发明的范围,该发明的范围由附加的权利要求的范围来规定。其它的方面、优点、以及修改是在接下来的权利要求的范围内的。
Claims (29)
1.一种用于在处理代理和存储资源之间传送数据的方法包括:
指定这个存储资源用于使用推入总线将数据推入处理代理中,其中,该推入总线具有若干仲裁推入总线的使用的源;以及
指定这个存储资源用于使用拉出总线接收来自处理代理的数据,其中,该拉出总线具有若干仲裁拉出总线的使用的目标。
2.权利要求1中的方法,其中,传送包括:
在程序代理上建立若干上下文并维持程序计数器和上下文相关寄存器。
3.权利要求2中的方法,其中,在读出阶段,程序代理执行上下文并发出读出命令到存储器控制器。
4.权利要求3中的方法,其中,存储器控制器处理要发送到存储器资源的读出命令。
5.权利要求4中的方法,其中,如果需要读出数据来继续上下文的执行,就换出上下文。
6.权利要求5中的方法,其中,在存储器控制器已完成了读出命令的处理之后,存储器控制器将数据推入到该程序代理的输入传送寄存器。
7.权利要求6中的方法,其中,在数据已经被推入之后,该程序代理读出在输入传送寄存器中的数据,并且该程序代理继续上下文的执行。
8.权利要求2中的方法,其中,在写入阶段中,该程序代理执行一上下文并将数据载入程序代理的输出传送寄存器。
9.权利要求8中的方法,其中,程序代理发出一写入命令到存储器控制器,并且输出传送寄存器被设置为只读状态。
10.权利要求9中的方法,其中,如果需要写入命令来继续上下文的执行,就换出上下文。
11.权利要求10中的方法,其中,存储器控制器推入来自输出传送寄存器的数据,且存储器控制器发送一信号到程序代理来对输出传送寄存器进行解锁。
12.权利要求11中的方法,其中,如果在输出传送寄存器已经被解锁之后,该上下文已经被换出,那么就将该上下文换回进去,并且程序代理继续该上下文的执行。
13.一种系统包括:
存储器资源;
配置用来在处理代理和存储器资源之间传送数据的处理代理;
用于将数据推入处理代理中的推入总线,其具有若干仲裁推入总线的使用的源;
用于接收来自处理代理的数据的拉出总线,其具有若干仲裁该拉出总线的使用的目标;
若干执行多个查找处理代理的资源的上下文的微引擎。
14.权利要求13中的系统进一步包括一用于从存储器资源到处理代理的数据传送的读出阶段,其中该传送是单向的。
15.权利要求13中的系统进一步包括一用于从处理代理到存储器资源的数据的传送的写入阶段,其中该传送是单向的。
16.权利要求13中的系统进一步包括若干程序计数器和若干上下文相关寄存器。
17.权利要求16中的系统,其中,上下文相关寄存器是从包括通用寄存器、交互编程代理寄存器、静态随机访问存储器(SRAM)输入传送寄存器、动态随机访问存储器(DRAM)输入传送寄存器、SRAM输出传送寄存器、DRAM输出传送寄存器以及局部存储器寄存器的组中选择出来的。
18.权利要求17中的系统,其中,程序代理被配置用来执行上下文,并发出读出命令到存储器控制器。
19.权利要求18中的系统,其中,存储器控制器被配置用来处理要发送到存储器资源的读出命令。
20.权利要求19中的系统,其中,程序代理被配置成如果需要读出命令来继续上下文的执行,则将上下文换出来。
21.权利要求20中的系统,其中,在处理了读出命令之后,该存储器控制器被配置用来将数据推入到程序代理的输入传送寄存器,而该程序代理被配置用来读出输入传送寄存器中的数据并继续上下文的执行。
22.权利要求15中的系统,其中,程序代理被配置用来执行上下文并将数据载入到程序代理的一个输出传送寄存器中。
23.权利要求22中的系统,其中,程序代理被配置用来发出写入命令到存储器控制器,且其中,该输出传送寄存器被设置为只读状态。
24.权利要求23中的系统,其中,程序代理被配置成如果需要写入命令来继续上下文的执行,则换出上下文。
25.权利要求24中的系统,其中,存储器控制器被配置用来推入来自输出传送寄存器的数据并发送信号到程序代理来对输出传送寄存器进行解锁。
26.一种驻留在计算机可读介质上的计算机程序产品,用于使并行处理器执行函数,包括指令使得处理器:
指定存储资源用于使用推入总线将数据推入处理代理,其中,该推入总线具有若干仲裁该推入总线的使用的源;以及
指定存储资源用于使用拉出总线接收来自处理代理的数据,其中,该拉出总线具有若干仲裁该拉出总线的使用的目标。
27.权利要求26中的计算机程序产品进一步包括使处理器在程序代理上建立若干上下文并维持程序计数器和上下文相关寄存器的指令。
28.权利要求26中的计算机程序产品,其中,在读出阶段,程序代理执行上下文并发出读出命令到存储器控制器。
29.权利要求26中的计算机程序产品,其中,存储器控制器处理要发送到存储器资源的读出命令,并且如果需要读出数据来继续上下文的执行,就换出上下文。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106796546A (zh) * | 2015-01-27 | 2017-05-31 | 华为技术有限公司 | 通过推测优化同步写入 |
CN106796546B (zh) * | 2015-01-27 | 2020-12-25 | 华为技术有限公司 | 数据处理系统中实施的方法和装置 |
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HK1070704A1 (en) | 2005-06-24 |
WO2003065205A8 (en) | 2004-10-28 |
TWI236595B (en) | 2005-07-21 |
EP1493081B1 (en) | 2010-11-03 |
ATE487179T1 (de) | 2010-11-15 |
CA2473548A1 (en) | 2003-08-07 |
US20030145155A1 (en) | 2003-07-31 |
TW200302417A (en) | 2003-08-01 |
KR100895536B1 (ko) | 2009-04-30 |
DE60334784D1 (de) | 2010-12-16 |
US7610451B2 (en) | 2009-10-27 |
KR20040017822A (ko) | 2004-02-27 |
CN101027634B (zh) | 2015-09-09 |
WO2003065205A2 (en) | 2003-08-07 |
EP1493081A2 (en) | 2005-01-05 |
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