CN100578775C - Fabrication structure for protecting electronic chip joint and manufacturing method thereof - Google Patents

Fabrication structure for protecting electronic chip joint and manufacturing method thereof Download PDF

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Publication number
CN100578775C
CN100578775C CN200510128717A CN200510128717A CN100578775C CN 100578775 C CN100578775 C CN 100578775C CN 200510128717 A CN200510128717 A CN 200510128717A CN 200510128717 A CN200510128717 A CN 200510128717A CN 100578775 C CN100578775 C CN 100578775C
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dielectric layer
protective layer
parts
cover
assembling structure
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CN1971900A (en
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张世明
林基正
陈守龙
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

This invention provides one electron package joint protection structure and its method, which can improve chip electrode joint and distribution conductivity connection hole stress integration phenomena to improve electron structure wire reliability. This invention protection layer structure is fulfilled of transistor by coating, depositing and print with higher procedure suitable for each electron package structure.

Description

The assembling structure of protection electronic chip contact and the manufacture method of assembling structure
Technical field
The present invention refers to a kind of manufacture method of protecting the assembling structure and the assembling structure of electronic chip contact especially about the manufacture method of a kind of electronic packaging structure and assembling structure.
Background technology
Along with the electronic product demand develops towards multifunction, signal transmitting high speedization and circuit unit densification, the function that IC presented is strong more, the passive component quantity of collocation also hurriedly increases thereupon, consumption electronic products particularly, therefore emphasize gently at electronic product, thin, short, little when, how in limited structure dress space, to hold the huge electronic building brick of number, become the technical bottleneck that the electronic packaging dealer is anxious to be solved and overcome.In order to solve this problem, the structure packing technique moves towards package system mode (SiP gradually, system in package) the system combination stage, and embedded master, passive component technology (embedded technology) and surperficial laminating technique (build up) become key technology, by burying in the assembly, structure dress area is dwindled significantly, make unnecessary space can add more high functionality assemblies.Surperficial laminating technique then can improve line density, dwindle component thickness, improves the structure dress density of product integral body whereby.
Yet when structure dress area dwindles significantly, contactor density is more and more higher, makes that the size and the spacing that connect up on the chip are also more and more littler thereupon.Therefore, when environment changes or is subjected to external force and influences, cause easily often at chip electrode contact or the wire through-hole of rewiring and should stand concentrated zone.And the bigger place of this stress can make the chip electrode contact damage or conductor cord disconnection usually, and then causes chip failure.
See also Fig. 1; it is United States Patent (USP) US5; 757; propose in HDI structure 10 in No. 072; be covered in the main passive component 12 that chip 12a or any sensitivity are subject to external interference with over cap 16; protecting it in operation, not polluted, and make in HDI and to finish the back and protect assembly to make it not be subjected to external influence.But the over cap 16 in this patent needs to make in addition and is quite complicated, and cost is also higher.
See also Fig. 2, it is United States Patent (USP) US6, proposes to reduce with symmetrical structure 162 warpage (warpage) phenomenon of built-in type chip 102 in 586, No. 836, to improve the stress concentration phenomenon that produces because of warpage, causes chip failure.Yet, the structure that such mode can only be applied to the multicore sheet and can symmetry make.Therefore its scope applicatory is less relatively, and operation is also comparatively complicated.
See also Fig. 3, it is United States Patent (USP) US5,866, form before the polymeric substrates 24 around being set forth in the chip 14 and 20 in the HDI structure 26 in No. 952, can reduce earlier the toughness material 17 of stress, so can improve the chip failure that the stress concentration phenomenon is caused in the chip in this chip 14 and 20 placed around one.
Summary of the invention
Of the present invention mainly being contemplated that provides a kind of assembling structure of protecting the electronic chip contact, and it comprises:
A plurality of chips, described a plurality of chips have a plurality of electrodes; A plurality of connecting holes are positioned on described a plurality of electrode; One first dielectric layer is in order to cover described a plurality of chip and not cover described a plurality of connecting hole; One protective layer, it has a plurality of parts, and described a plurality of parts are positioned on described first dielectric layer, do not cover described a plurality of connecting hole and not exclusively cover whole described first dielectric layer; One second dielectric layer is in order to cover described first dielectric layer, coat described a plurality of parts of described protective layer and not cover described a plurality of connecting hole; And a plurality of vertical conduction connection lines, be formed in described a plurality of connecting hole and be connected on described a plurality of electrode, in order to connect a signal of telecommunication; Wherein, described a plurality of parts of described protective layer be formed at described a plurality of vertical conduction connection lines around.
According to above-mentioned conception, the material of wherein said protective layer is a compressible macromolecular material, and described protective layer not exclusively covers described a plurality of chips.Described protective layer is coated on around described a plurality of vertical conduction connection line, but does not contact with described a plurality of vertical conduction connection lines.
Of the present invention another is contemplated that provides a kind of assembling structure of protecting the electronic chip contact, and it comprises:
A plurality of chips, described a plurality of chips have a plurality of electrodes; One substrate, the side that it is positioned at described a plurality of chips is used to support described a plurality of chip and assists described a plurality of chip cooling; A plurality of connecting holes are positioned on described a plurality of electrode; One first dielectric layer is in order to cover described a plurality of chip and not cover described a plurality of connecting hole; One protective layer, it has a plurality of parts, and described a plurality of parts are positioned on described first dielectric layer, do not cover described a plurality of connecting hole and not exclusively cover whole described first dielectric layer; One second dielectric layer is in order to cover described first dielectric layer, coat described a plurality of parts of described protective layer and not cover described a plurality of connecting hole; And a plurality of vertical conduction connection lines, be formed in described a plurality of connecting hole and be connected on described a plurality of electrode, in order to connect a signal of telecommunication; Wherein, described a plurality of parts of described protective layer be formed at described a plurality of vertical conduction connection lines around.
According to above-mentioned conception, wherein said protective layer not exclusively covers described a plurality of chips, and described protective layer is coated on around described a plurality of vertical conduction connection line, but does not contact with described a plurality of vertical conduction connection lines.
Another being contemplated that of the present invention provides a kind of manufacture method of protecting the assembling structure of electronic chip contact, and this method comprises the following steps: to provide a plurality of chips, and described a plurality of chips have a plurality of electrodes; Form one first dielectric layer, described first dielectric layer covers described a plurality of chip; Remove the various piece of described first dielectric layer on described a plurality of electrodes; Form a protective layer, described protective layer has a plurality of parts, and described a plurality of parts not exclusively cover whole described first dielectric layer; Form one second dielectric layer, described second dielectric layer is in order to cover described first dielectric layer and to coat described a plurality of parts of described protective layer; Form a plurality of vertical wire connection holes in described a plurality of parts of described protective layer and described second dielectric layer; And form a plurality of vertical conduction connection lines in described a plurality of vertical wire connection holes.
The invention provides a kind of protective layer structure; when assembling structure is subjected to external force or environmental change; this protective layer structure can effectively be protected lead and the connecting hole on the chip, avoids the conductor cord disconnection of damage of chip electrode contact or rewiring, and then improves the lead reliability of assembling structure.
Description of drawings
Fig. 1 is United States Patent (USP) US5, the cross-sectional schematic of utilizing over cap to be covered in chip 757, No. 072;
Fig. 2 is United States Patent (USP) US6, the cross-sectional schematic of utilizing symmetrical structure to reduce the warping phenomenon of built-in type chip 586, No. 836;
Fig. 3 is United States Patent (USP) US5, the cross-sectional schematic of utilizing toughness material to reduce the stress of chip 866, No. 952;
Fig. 4 is the stress simulation analytical model cross-sectional schematic of semiconductor subassembly of the present invention;
Fig. 5 is the analog result cross-sectional schematic that does not have protective layer in the model configuration of the present invention;
Fig. 6 is the analog result cross-sectional schematic that has protective layer in the model configuration of the present invention;
Fig. 7 is the graph of a relation of protective layer thickness of the present invention and stress;
Fig. 8 (a) (b) (c) (d) (e) (f) (g) be the making flow process cross-sectional schematic of first embodiment of the present invention assembling structure;
Fig. 9 is the schematic top plan view of first embodiment of the present invention assembling structure;
Figure 10 is the cross-sectional schematic of second embodiment of the present invention assembling structure;
Figure 11 is the schematic top plan view of second embodiment of the invention assembling structure;
Figure 12 is the schematic top plan view of third embodiment of the invention assembling structure; And
Figure 13 is the schematic top plan view of fourth embodiment of the invention assembling structure.
Embodiment
The present invention can be understood fully by following embodiment explanation, make the personage who is familiar with this method can implement the present invention according to this, yet enforcement of the present invention be not can be limited it by the following example to implement kenel.
See also Fig. 4, it is the stress simulation analytical model cross-sectional schematic of semiconductor subassembly of the present invention.This model comprises semiconductor chip 101, substrate 104, connecting hole inside conductor 108, protective layer 105, second dielectric layer 106 and dielectric layer 109; Wherein semiconductor chip 101 is attached on the substrate 104 with glue material 111, and substrate 104 can be an organic circuit substrate or a metal substrate.Coat with protective layer 105 around the connecting hole inside conductor 108, and second dielectric layer 106 and second dielectric layer 109 are arranged on the protective layer.
See also Fig. 5, it is the analog result cross-sectional schematic that does not have protective layer in the model configuration of the present invention.When not having protective layer of the present invention in the structure when being coated on around the lead, will form area of stress concentration, as arrow indication among the figure.
See also Fig. 6, it is the analog result cross-sectional schematic that has protective layer in the model configuration of the present invention.When having protective layer of the present invention in the structure when being coated on around the lead, can effectively reduce the suffered stress of lead, as arrow indication among the figure.
See also Fig. 7, it is the graph of a relation of protective layer thickness of the present invention and stress.By among the figure as can be known, good more if the thickness of protective layer increases the effect of its dispersive stress.
See also (b) (c) (d) (e) (f) (g) of Fig. 8 (a), it is the making flow process cross-sectional schematic of first embodiment of the present invention assembling structure.One has the semiconductor chip 101 of integrated circuit, and it contains I/O electrode 102 and first dielectric layer 103 covers on the semiconductor chip 101, shown in Fig. 8 (a).On the semiconductor chip 101 with the printing, deposit or utilize rotary coating after again the mode of lithography form protective layer 105 on electrode 102; and cover part first dielectric layer 103; shown in Fig. 8 (b); above this step protective layer only is formed at connection electrode; be not coated on whole package area; so not only can avoid causing the warpage of semiconductor chip 101, can also save material cost owing to the coating of protective layer 105.Protective layer material can be macromolecular materials such as polyimides (Polyimide) and BCB, and the protective layer shape can be circle, square, irregular shape or arbitrary mixing shape.Semiconductor chip 101 is placed on organic substrate 104, shown in Fig. 8 (c) then.Mode with coating, deposition, pressing or printing forms second dielectric layer 106, the second dielectric layers, 106 covering first dielectric layers 103 and coats protective layer 105, shown in Fig. 8 (d).Then can adopt modes such as laser drill, dry ecthing or wet etching that the protective layer 105 and second dielectric layer 106 of electrode 102 tops are left connecting hole 107, shown in Fig. 8 (e).In the connecting hole of being left 107, form lead 108 in modes such as plating, deposition or printings, formed lead 108 is positioned at the protective layer 105 and second dielectric layer 106, and protective layer 105 cover part lead 108 at least, shown in Fig. 8 (f).Then can make second dielectric layer 109 and conductive projection 110, shown in Fig. 8 (g).
See also Fig. 9, it is the schematic top plan view of first embodiment of the present invention assembling structure.As shown in the figure, semiconductor chip 101 is on organic substrate 104, and it contains I/O electrode 102; Protective layer structure 105 be formed at vertical conducting circuit 113 around.
See also Figure 10, it is the cross-sectional schematic of second embodiment of the present invention assembling structure.One semiconductor chip 201 with integrated circuit is on organic substrate 204, and it contains I/O electrode 202 and first dielectric layer 203 covers on electrode 202 and the semiconductor chip 201.Except the ground floor protective layer 205 of first kind of embodiment, can also make second layer protective layer structure 212 and be surrounded on around vertical connection lead 213, and between lead rewiring 208 and conductive projection 210.
See also Figure 11, it is the schematic top plan view of second embodiment of the invention assembling structure.As shown in the figure, semiconductor chip 201 is on organic substrate 204, and it contains I/O electrode 202; Protective layer structure 205 and 212 be formed at vertical conducting circuit 213 and 214 around.Because protective layer structure of the present invention can be used for protecting vertical conducting circuit, therefore, quite is fit to be applied to the wiring wire through-hole of multilayer laminated boards (build up) circuit, a plurality of protective layer structures are made in the lamination structure dress with multilayer dielectric layer.
See also Figure 12, it is the schematic top plan view of third embodiment of the invention assembling structure.As shown in the figure, semiconductor chip 201 is on organic substrate 204, and it contains I/O electrode 202; Protective layer structure 305 and 312 be formed at vertical conducting circuit 313 and 314 around, but not only only surround single vertical conducting circuit 313 and 314.
See also Figure 13, it is the schematic top plan view of fourth embodiment of the invention assembling structure.As shown in the figure, semiconductor chip 201 is on organic substrate 204, and it contains I/O electrode 202; Protective layer structure 405 and 412 be formed at vertical conducting circuit 413 and 414 around, but do not touch single vertical conducting circuit 413 and 414.
In sum, utilize this protective layer structure can improve the stress concentration phenomenon of the electrode contact on the chip and the conduction connecting hole that connects up, and then improve the lead reliability of electronic packaging structure.Protective layer structure among the present invention can be finished in the chip-scale production process with the mode of coating, deposition or printing, and itself and operation compatibility are higher, and applicable to various electronic packaging structures.
Can be made the change or the replacement of all equivalences by person skilled in the art scholar even if the present invention has been described in detail by the above embodiments, the change of these equivalences or replacement all should be included in down in attached the application's claim scope.

Claims (10)

1. assembling structure of protecting the electronic chip contact, it comprises:
A plurality of chips, described a plurality of chips have a plurality of electrodes;
A plurality of connecting holes are positioned on described a plurality of electrode;
One first dielectric layer is in order to cover described a plurality of chip and not cover described a plurality of connecting hole;
One protective layer, it has a plurality of parts, and described a plurality of parts are positioned on described first dielectric layer, do not cover described a plurality of connecting hole and not exclusively cover whole described first dielectric layer; One second dielectric layer is in order to cover described first dielectric layer, coat described a plurality of parts of described protective layer and not cover described a plurality of connecting hole; And
A plurality of vertical conduction connection lines are formed in described a plurality of connecting hole and are connected on described a plurality of electrode, in order to connect a signal of telecommunication;
Wherein, described a plurality of parts of described protective layer be formed at described a plurality of vertical conduction connection lines around.
2. the assembling structure of protection electronic chip contact as claimed in claim 1, the material that it is characterized in that described protective layer are a compressible macromolecular material.
3. the assembling structure of protection electronic chip contact as claimed in claim 1 is characterized in that described protective layer not exclusively covers described a plurality of chips.
4. the assembling structure of protection electronic chip contact as claimed in claim 1 is characterized in that described protective layer is coated on around described a plurality of vertical conduction connection line, but does not contact with described a plurality of vertical conduction connection lines.
5. assembling structure of protecting the electronic chip contact, it comprises:
A plurality of chips, described a plurality of chips have a plurality of electrodes;
One substrate, the side that it is positioned at described a plurality of chips is used to support described a plurality of chip and assists described a plurality of chip cooling;
A plurality of connecting holes are positioned on described a plurality of electrode;
One first dielectric layer is in order to cover described a plurality of chip and not cover described a plurality of connecting hole;
One protective layer, it has a plurality of parts, and described a plurality of parts are positioned on described first dielectric layer, do not cover described a plurality of connecting hole and not exclusively cover whole described first dielectric layer;
One second dielectric layer is in order to cover described first dielectric layer, coat described a plurality of parts of described protective layer and not cover described a plurality of connecting hole; And
A plurality of vertical conduction connection lines are formed in described a plurality of connecting hole and are connected on described a plurality of electrode, in order to connect a signal of telecommunication;
Wherein, described a plurality of parts of described protective layer be formed at described a plurality of vertical conduction connection lines around.
6. the assembling structure of protection electronic chip contact as claimed in claim 5 is characterized in that this substrate is an organic circuit substrate or a metal substrate.
7. manufacture method of protecting the assembling structure of electronic chip contact, this method comprises the following steps:
A plurality of chips are provided, and described a plurality of chips have a plurality of electrodes;
Form one first dielectric layer, described first dielectric layer covers described a plurality of chip;
Remove the various piece of described first dielectric layer on described a plurality of electrodes;
Form a protective layer, described protective layer has a plurality of parts, and described a plurality of parts not exclusively cover whole described first dielectric layer;
Form one second dielectric layer, described second dielectric layer is in order to cover described first dielectric layer and to coat described a plurality of parts of described protective layer;
Form a plurality of vertical wire connection holes in described a plurality of parts of described protective layer and described second dielectric layer; And
Form a plurality of vertical conduction connection lines in described a plurality of vertical wire connection holes.
8. the manufacture method of the assembling structure of protection electronic chip contact as claimed in claim 7, it is characterized in that described protective layer with mode of printing, utilize after the rotary coating again the lithography mode or form with depositional mode.
9. the manufacture method of the assembling structure of protection electronic chip contact as claimed in claim 7 is characterized in that described vertical wire connection hole is in the laser drill mode, form in the dry ecthing mode or in the wet etching mode.
10. the manufacture method of the assembling structure of protection electronic chip contact as claimed in claim 7 is characterized in that described vertical conduction connection line forms with plating mode, depositional mode or with mode of printing.
CN200510128717A 2005-11-25 2005-11-25 Fabrication structure for protecting electronic chip joint and manufacturing method thereof Active CN100578775C (en)

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CN200510128717A CN100578775C (en) 2005-11-25 2005-11-25 Fabrication structure for protecting electronic chip joint and manufacturing method thereof

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CN100578775C true CN100578775C (en) 2010-01-06

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