CN100555600C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN100555600C
CN100555600C CNB2004800319524A CN200480031952A CN100555600C CN 100555600 C CN100555600 C CN 100555600C CN B2004800319524 A CNB2004800319524 A CN B2004800319524A CN 200480031952 A CN200480031952 A CN 200480031952A CN 100555600 C CN100555600 C CN 100555600C
Authority
CN
China
Prior art keywords
semiconductor substrate
gap
layer
strained layer
type device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004800319524A
Other languages
English (en)
Other versions
CN101164157A (zh
Inventor
安·L.·斯蒂根
海宁·S.·杨
张郢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101164157A publication Critical patent/CN101164157A/zh
Application granted granted Critical
Publication of CN100555600C publication Critical patent/CN100555600C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel

Abstract

一种制造器件的方法，所述器件包括n型和p型器件。在本发明的一方面中，该方法涉及对半导体衬底的一部分掺杂、以及通过去除半导体衬底的该掺杂部分的至少一部分而在半导体衬底中形成间隙。该方法还涉及在半导体衬底的至少一部分间隙中生长应变层。对于n型器件，应变层生长在位于n型器件沟道基本上正下方的至少一部分上。对于p型器件，应变层生长在位于p型器件的源区或漏区基本上正下方但基本上不位于p型器件的沟道下方的至少一部分上。

Description

半导体器件及其制造方法
技术领域
本发明一般涉及制造器件性能改善的半导体器件的方法，并且更具体地说涉及在器件制造期间在该器件衬底中施加张应力和压应力的制造半导体器件的方法。
背景技术
一般来说，金属氧化物半导体晶体管包括由诸如硅的半导体材料制成的衬底。该晶体管在衬底内典型地包括源区、沟道区和漏区。沟道区位于源区和漏区之间。一般在沟道区上方提供栅叠层，该栅叠层通常包括导电材料、栅氧化物层和侧壁间隔。更具体地说，栅氧化物层典型地被提供在沟道区上方的衬底上，而栅导体通常被提供在该栅氧化物层的上方。侧壁间隔有助于保护栅导体的侧壁。
公知流过其间具有给定电场的沟道的电流的量一般直接与该沟道中载流子的迁移率成正比。因此，通过增加沟道中载流子的迁移率，可以增加晶体管的操作速度。
还公知半导体器件衬底内的机械应力可以例如通过增加该半导体器件中载流子的迁移率来调制器件性能。也就是说，半导体器件内的应力被认为能提高半导体器件的特性。因此，为了提高半导体器件的特性，可以在n型器件(例如NFETs)和/或p型器件(例如PFETs)的沟道中创造张应力和/或压应力。但是，相同的应力分量(stresscomponent)，例如张应力或压应力，提高一种类型器件(即n型器件或p型器件)的器件特性，同时有区别地影响另一种类型器件的特性。
为了使NFETs和PFETs二者的性能在集成电路(IC)器件中达到最大，对于NFETs和PFETs应该不同地设计和施用应力分量。也就是说，因为对于NFET的性能有利的应力类型一般对于PFET的性能是不利的。尤其当器件处于张力(在平面器件中电流的方向中)下时，NFET的工作特性被增强，而PFET的工作特性被减小。为了选择性地在NFET中产生张应力并且在PFET中产生压应力，使用不同的工艺和不同的材料组合。
举例来说，已经建议了沟槽隔离结构来分别在NFETs和PFETs中形成适当的应力。当使用该方法时，NFET器件的隔离区包含在纵向(与电流方向平行)和横向(与电流方向垂直)中对NFET器件施加第一种类型机械应力的第一种隔离材料。此外，对于PFET提供第一种隔离区和第二种隔离区，并且PFET器件的每种隔离区在横向和纵向中对PFET器件施加独特的机械应力。
可选地，已经建议了用栅侧壁上的衬层(liners)在FET器件的沟道中选择性地诱导适当的应变(例如参见Ostsuka等，IEDM 2000，第575页)。通过提供衬层，可以比沟槽隔离填充技术施加的应力更接近器件地施加适当的应力。
当这些方法的确提供了具有张应力和压应力的结构，该张应力被施加到NFET器件上并且该压应力被沿着PFET器件的纵向施加时，它们可能需要附加的材料和/或更复杂的工艺，因此导致更高的成本。此外，可以在这些情况中施加的应力水平典型地是适度的(即在100MPa的量级)。因此，需要提供成本上更有效的并且更简单的方法来分别在NFETs和PFETs沟道中产生大的张应力和压应力。
发明内容
在本发明的第一个方面中，本发明提供了一种制造器件的方法，该器件包括n型器件和p型器件。该方法涉及对半导体衬底的一部分掺杂和通过去除该半导体衬底的该掺杂部分的至少一部分在该半导体衬底中形成间隙。该方法还涉及在该半导体衬底的间隙的至少一部分中生长应变层。
在本发明的各方面中，对于n型器件，应变层生长在位于n型器件的沟道基本上正下方的至少一部分上。对于p型器件，应变层生长在位于p型器件的源区或漏区基本上正下方并且基本上不位于该p型器件的沟道下方的至少一部分上。
在本发明的另一方面中，本发明提供了一种制造器件的方法，该器件包括n型器件和p型器件。该方法涉及在半导体衬底上生长应变层和在该应变层上方生长硅层。通过从该半导体衬底上方去除该硅层和该应变层的至少一部分，在该半导体衬底和该硅层之间形成间隙，并且应变层生长在间隙的至少一部分上。对于n型器件，应变层生长在位于n型器件的沟道基本上正下方的至少一部分上。对于p型器件，应变层生长在位于p型器件的源区或漏区基本上正下方并且基本上不位于该p型器件的沟道下方的至少一部分上。
本发明单独提供了一种半导体器件，该器件具有至少具有一个间隙的半导体衬底，该间隙在该半导体衬底的一部分的下方延伸。该器件包括在该半导体衬底上的栅叠层和在该间隙的至少一部分中形成的应变层，其中通过对该半导体衬底的一部分掺杂、然后蚀刻该半导体衬底的该掺杂部分而形成该间隙。
在本发明的另一方面中，本发明提供了一种半导体器件，该器件具有至少具有一个间隙的半导体衬底，该间隙在该半导体衬底的一部分的下方延伸。该器件包括在该半导体衬底上的栅叠层和仅在该半导体器件的源区和漏区的至少一部分下方形成的应变层。
附图说明
图1说明NFETs和PFETs的所需应力状态；
图2(a)到2(j)说明形成根据本发明的p型晶体管的示例性过程；
图3(a)到3(d)说明形成根据本发明的n型晶体管的示例性过程；
图4说明根据本发明的晶体管的俯视图；
图5说明使用扫描电子显微镜观察的根据本发明的半导体衬底的横截面；
具体实施方式
本发明提供了制造具有改善的工作特性的器件的方法。当在硅层上外延生长应力层，例如SiGe层、Si3N4层、SiO2层或SiOxNy层时，在SiGe层内形成压应力并且在硅层中形成张应力。在本发明的一方面中，硅衬底具有其中生长了应变层的间隙。该间隙包括位于该半导体衬底上部和该半导体衬底下部之间的隧道状部分。更具体地说，所述上部具有下表面并且所述下部具有上表面，并且该上部的下表面面对所述下部的上表面。通过在基本上位于半导体器件源区和/或漏区下方的半导体衬底的区域中具有基本上位于沟道和/或应变层下方的应变层，可以在晶体管的沟道中形成应力。在本发明的一方面中，通过选择性蚀刻硅衬底、然后在该硅衬底上外延生长SiGe而在该硅衬底中形成间隙。
根据生长的SiGe与晶体管沟道的邻近程度，可以在晶体管的沟道中提供张应力和/或压应力。通过选择性蚀刻晶体管下方的硅层并且在硅层的该蚀刻部分上选择性生长SiGe，可以在NFETs的沟道中提供张应力并且在PFETs的沟道中提供压应力。此外，通过在生长SiGe之前选择性蚀刻晶体管下方的硅的一部分而实现应力，本发明在栅极下面的硅(例如沟道区)中提供了远大于基于隔离或基于衬层途径的应力水平。
在本发明中，使用应力层，例如SiGe层，在半导体器件的沟道中形成应力。当在半导体层上生长了SiGe层时，周围的半导体材料遭受张应力，而所生长的SiGe层遭受压应力。具体地说，因为SiGe层具有与硅层不同的晶格结构，半导体器件的一部分被置于张应力下并且SiGe层遭受压应力。此外，源于SiGe应力层的应力水平是较高的(在1-2GPa的量级)。
但是，如上所述，沟道区中的张应力对于NFET激励电流是有利的，而沟道区中的压应力对于PFET激励电流是有利的。具体地说，张应力显著地阻碍了PFET激励电流。在本发明中，为了提高PFET的性能，PFET中的应力被制造成压应力而不是张应力。因此，本发明提供了一种沿PFET沟道提供纵向压应力，而沿NFET沟道提供张应力，从而提高了该器件性能的方法。
图1说明用来提高PFETs和NFETs性能的所需应力状态(参见Wang等，IEEE Tran.Electron Dev.，第50卷，第529页，2003年)。在图1中，NFET和PFET被表示为具有源区、栅区和漏区。NFET和PFET被表示为具有用来显示张应力的从活性区向外延伸的箭头。指向PFET器件向内延伸的箭头表示压应力。更具体地说，表示从NFET延伸的向外延伸的箭头显示了在该器件横向和纵向中所需的张应力。另一方面，表示与PFET相关的向内延伸的箭头显示了所需的纵向压应力。
影响器件激励电流所需的应力范围在几百MPa至几GPa的量级。每个器件的活性区的宽度和长度分别由“W”和“L”代表。应当理解纵向或横向应力分量中每个都可以被单独裁剪以提高两个器件(即NFET和PFET)的性能。
图2(a)到2(j)描述了形成根据本发明的n型器件的示例性过程。如图2(a)所示，在硅衬底200上方沉积图案化的光抗蚀剂层205，并且举例来说采用Ge、As、B、In或Sb对硅衬底200的暴露部分掺杂。举例来说，Ge的掺杂浓度例如可以为大约1×1014Ge/cm2至大约1×1016Ge/cm2。掺杂区207在半导体衬底200中形成。
然后，如图2(b)所示，去除图案化的光抗蚀剂层205并且在半导体衬底200的表面上沉积例如由氮化物制成的掩模210。掩模210保护其下面的半导体衬底在反应性离子蚀刻(RIE)期间不被蚀刻。一般来说，掩模210暴露出半导体衬底要借助RIE形成浅沟槽的部分。
如图2(c)所示，实施RIE以在半导体衬底200中形成凹槽/沟槽215。作为RIE步骤的结果，形成掺杂的半导体区域的侧壁部分217。具体地说，所形成的凹槽/沟槽的位置至少部分覆盖掺杂的半导体区域的一部分，使得当凹槽/沟槽215被形成时，暴露出掺杂的半导体衬底区域。此外，如下所述，在应变层被形成后，沉积氧化物材料以填充所述沟槽，使得半导体衬底200上彼此相邻的器件彼此被电学隔离。
在形成凹槽/沟槽215后，实施湿法蚀刻和/或干法蚀刻以选择性地去除掺杂的半导体207。一般来说，沟槽的深度从半导体衬底的上表面231(图2(f))将为大约1000埃至大约5000埃，并且晶体管沟道区的厚度典型地为大约30埃至大约200埃。
如图2(d)所示，进行蚀刻，直到在半导体衬底200的上部221和半导体衬底200的下部223之间形成隧道状间隙219。典型地，从半导体衬底200蚀刻出具有大约300埃至大约5000埃的深度的部分。在n型晶体管的情况中，需要形成位于器件沟道基本上正和/或正下方的应变层。因此，对于n型晶体管而言，在器件沟道下方有至少一个间隙。
接下来，如图2(e)所示，在半导体衬底200的上方沉积间隔材料225。该间隔材料举例来说可以是非保形(non-conformal)的膜(例如碳化硅SiC、氧氮化物)或者膜叠层(例如氧化物膜和氮化物膜)。该间隔材料225形成在上部221下方的半导体衬底部分以外的半导体衬底200的暴露部分上。
如图2(f)所示，在半导体衬底200的隧道状间隙219中外延生长应变层227。如图2(f)所示，该应变层227一般被形成在半导体衬底200的上部221和下部223之间，其中半导体衬底200的上部221是原始半导体衬底(即未被去除/干扰和沉积)的部分。也就是说，应变层227一般借助选择性沉积来形成，使得应变层227被形成在半导体衬底200的暴露的表面上。此外，因为应变层227被形成为隧道状间隙，所以上部221的上表面231是未被干扰的(即原始的)和基本上平坦的。
举例来说，应变层可以是硅锗或碳化硅。应当理解应变层可以由任何公知的适当材料制成。
在应变层227被形成后，使用湿化学方法去除间隔材料225。应当理解可以使用任何公知的可用方法来去除间隔材料225。所得不含间隔材料的器件表示在图2(g)中。
如上所述，并且如图2(h)所示，然后沉积氧化物材料233来填充沟槽并且使器件与任何相邻的器件电学隔离。在用氧化物材料填充了沟槽后，使用任何公知的适当方法去除掩模210。在去除了掩模210后，实施化学机械抛光(CMP)以使半导体衬底200的上表面231基本上为平面。
接下来，再使用公知的方法制造半导体器件。举例来说，如图2(i)所示，在半导体衬底200的上表面231上生长栅氧化物层235。一般生长大约10埃至大约100埃的栅氧化物层235。在栅氧化物层235上面，一般使用化学气相沉积(CVD)沉积大约500埃至大约1500埃厚的多晶硅层236，以形成栅极237。使用图案化的光抗蚀剂层(未显示)来限定栅极。然后，在剩下的多晶硅上面生长氧化物薄层(不是氧化物)。使用后来被去除的图案化的光抗蚀剂层(未显示)来连续地尖端(tip)(和晕圈反掺杂注入(halo countering doping implants))注入n型和p型晶体管。对于n型晶体管，举例来说可以使用非常浅且低剂量的砷离子注入来形成p-尖端(而举例来说硼注入可以用于晕圈)。对于p型晶体管，(如下面就图3(a)-3(d)所述)，举例来说可以使用非常浅且低剂量的BF2离子注入来形成n-尖端(而举例来说砷注入可以用于晕圈)。
接下来，如图2(j)所示，可以通过使用CVD沉积厚度大约100埃至大约1000埃的氮化硅层(未显示)、然后从栅极侧壁以外的区域蚀刻掉氮化物来形成间隔238。栅氧化物层235、栅极237和间隔238的组合可以被称作栅叠层。
使用在下一工艺阶段前被去除的图案化的光抗蚀剂层(未显示)来连续地产生晶体管的源/漏区。对于n型晶体管，举例来说使用浅并且高剂量的砷离子来形成源/漏区240和241，而用相应的光抗蚀剂层覆盖p型晶体管。如上所述，在根据本发明的方法中，源区和漏区240和241被形成在半导体衬底200的上部中(即未去除并且再形成)。对于p型晶体管，(下面关于图3(a)-3(d)所述)，举例来说可以使用浅并且高剂量的BF2离子来形成源/漏区30，而用相应的光抗蚀剂层覆盖n型晶体管。然后，使用退火来活化注入物。为了暴露出晶体管源区、栅区和漏区中的裸硅，再通过将所述结构浸入HF中而剥离该结构上暴露的氧化物。
再参考图2(j)，在基片表面上沉积厚度大约30埃至大约200埃的金属以形成硅化物242。该硅化物应该从底层与任何沉积金属(例如Co、Hf、Mo、Ni、Pd2、Pt、Ta、Ti、W和Zr)的反应来形成。在沉积的金属与硅接触的区域(例如源、漏和栅区)中，沉积的金属与硅反应，形成硅化物。接下来，将该结构加热至大约300℃至大约1000℃的温度，以使沉积的硅化物材料与暴露的多晶硅或硅反应。在烧结期间，仅在金属与硅或多晶硅直接接触的区域中形成硅化物。在其它区域(即沉积的金属不与硅接触的区域)中，沉积的金属保持不变。该过程使硅化物与暴露的硅对准，并且被称为“自对准的硅化物”或salicide。然后，使用湿法蚀刻去除未反应的金属而保留所形成的硅化物。
在根据本发明的方法中，因为半导体衬底的源区和漏区被形成在未干扰(即未蚀刻和再形成的)的半导体衬底部分上，所以表面更有助于硅化钴的形成。此外，一般使用氧化物填充，接着用化学机械抛光来平面化表面。根据设计规格按照需要继续制造过程。
图3(a)到3(d)说明形成根据本发明的p型器件的示例性过程。形成p型器件的过程与上面就图2(a)-2(j)所讨论的形成n型器件的过程相似，因此下面的讨论将主要集中于两个过程的差异。下面没有讨论的形成p型器件的方法的细节可以在上面形成n型器件的方法的说明中发现。
如图3(a)所示，沉积图案化的光抗蚀剂层305。对于p型器件，将位于半导体器件沟道下方的半导体衬底300的部分307也用图案化的光抗蚀剂层305覆盖。因此，对于p型器件，如图3(b)所示，当选择性蚀刻半导体衬底的掺杂区以形成间隙315时，半导体衬底300的一部分308保留。在形成了该结构后，半导体衬底300的该部分308位于半导体器件的沟道基本上正下方。
接下来，如图3(c)所示，在半导体衬底300残留的上部301和下部302之间生长应变层327。然后，如图3(d)所示，沉积氧化物材料以填充所述间隙/沟槽315。与形成n型器件的过程相似，在半导体衬底的上表面上沉积栅氧化物335，并且形成栅极337、间隔338、源/漏区340和341以及硅化物接触342。
图4描述了根据本发明的晶体管的俯视图。沿图4的线A-A观察的横截面是图2(i)中表示的结构，并且沿图4的线B-B观察的横截面是图2(j)中表示的结构。如图4所示，带有间隔238的栅极242位于半导体衬底200上方。氧化物填充233(即浅沟槽隔离结构)隔离半导体衬底200的源区和漏区240和241。
图5表示根据本发明的半导体衬底的横截面。使用扫描电子显微镜获得图5中所示的半导体衬底的表示。具体地说，图5表示了已经选择性地去除了掺杂硅，从而在半导体衬底中形成隧道状间隙219后的硅衬底。如图5所示，半导体衬底上部的下表面和半导体衬底下部的上表面定义了该半导体衬底中的间隙的一部分。半导体衬底中的该间隙可以包括沿半导体衬底上表面的开口。
在根据本发明方法的另一个实施方案中，举例来说用Ge代替对半导体衬底选择性地掺杂，使得可以借助蚀刻去除半导体衬底的该选择部分，可以在该半导体衬底上面生长层，例如SiGe层，接着举例来说生长硅外延层。然后，与上述的掺杂方法相似，可以暴露出该SiGe的侧壁、然后选择性蚀刻以在半导体衬底中形成所述间隙。
如上面参照图1所述，在PFETs中，需要纵向压应力。所需压应力/张应力的典型范围在几百MPa至几GPa的量级。举例来说，一般需要大约100MPa至大约2或3GPa的应力。本发明可以在PFET和NFET器件的沟道中分别产生非常高的压应力和张应力。
通过对NFET的沟道提供张应力并且对PFET的沟道提供压应力，沿每个器件的沟道的电荷迁移率被提高。因此，如上所述，本发明提供了用来通过或者在位于半导体器件的沟道基本上正下方或者位于该半导体器件的源区和/或漏区的基本上正下方提供应变层而沿所述沟道的纵向提供压应力的方法。本发明还提供了用来通过调节形成了应变层的间隙的位置和/或深度而在晶体管沟道中使应力水平最优化的方法。
当已经就实施方案说明了本发明时，本领域技术人员将认识到可以在附加权利要求的精神和范围内的变化下实践本发明。

Claims (26)

1.一种制造器件的方法，该器件包括n型器件和p型器件，所述方法包括：
对半导体衬底的一部分掺杂；
在半导体衬底中形成沟槽，从而选择性地暴露所述半导体衬底的掺杂区的至少一部分的侧壁；
通过去除所述半导体衬底的掺杂部分的至少一部分在所述半导体衬底的上部(221、301)和下部(223、303)之间形成间隙；以及
沉积间隔材料，从而在半导体衬底的除所述上部下方的半导体衬底部分以外的暴露部分上形成所述间隔材料；
在所述间隙的至少一部分中生长应变层。
2.根据权利要求1的方法，其中所述应变层生长在位于所述n型器件的沟道正下方的至少一部分上。
3.根据权利要求1的方法，其中所述应变层生长在位于所述p型器件的源区或漏区至少之一的正下方的至少一部分上。
4.根据权利要求3的方法，其中所述应变层未生长在所述p型器件的沟道下方。
5.根据权利要求1的方法，还包括在所述对半导体衬底的一部分掺杂之前，在半导体衬底上沉积图案化的光抗蚀剂层，其中该沉积步骤包括：
沉积光抗蚀剂层，所述光抗蚀剂层覆盖将位于所述p型器件的沟道下方的一部分所述半导体衬底。
6.根据权利要求5的方法，其中所述光抗蚀剂层暴露将位于所述n型器件的沟道下方的一部分所述半导体衬底。
7.根据权利要求1的方法，其中所述间隙是在n型器件的沟道下方形成的隧道。
8.根据权利要求5的方法，还包括：在所述掺杂之后，去除所沉积的图案化光抗蚀剂层。
9.根据权利要求8的方法，还包括：在去除所沉积的图案化光抗蚀剂层之后，但在去除所述半导体衬底的掺杂部分的至少一部分之前，在所述半导体衬底上沉积掩模。
10.根据权利要求9的方法，还包括：在沉积掩模之后，图案化所沉积的掩模，使得所述半导体衬底的一部分被覆盖，以及所述半导体衬底的一部分被暴露。
11.根据权利要求1的方法，其中所述应变层生长在所述间隙的没有所述间隔材料的部分上。
12.根据权利要求11的方法，还包括：在形成应变层之后，采用氧化物材料填充所述沟槽和所述间隙。
13.根据权利要求1的方法，其中所述掺杂的步骤包括采用Ge对所述半导体衬底掺杂。
14.根据权利要求13的方法，其中所述Ge的掺杂浓度为1×1014Ge/cm2至1×1016Ge/cm2。
15.根据权利要求1的方法，其中所述掺杂的步骤包括采用As、B、In和Sb的至少之一对所述半导体衬底掺杂。
16.根据权利要求1的方法，其中所述生长应变层的步骤包括在所述半导体衬底的间隙的至少一部分中生长SiGe、Si3N4、SiO2和SiOxNy至少之一。
17.一种半导体器件，包括：
具有至少一个间隙的半导体衬底，该间隙在该半导体衬底的一部分下方延伸；
在该半导体衬底上的栅叠层；以及
在该至少一个间隙的至少一部分中生长的应变层，其中所述间隙和应变层是通过如权利要求1所述的方法形成的，其中间隔材料在应变层形成之后被去除，并且该应变层仅被形成在该半导体器件的源区和漏区至少之一的下方。
18.根据权利要求17的器件，其中所述半导体器件是p型器件。
19.根据权利要求17的器件，其中所述应变层由碳化硅制成，或者由硅锗和碳化硅制成。
20.根据权利要求17的器件，其中所述应变层在彼此面对的、所述半导体衬底的较下部分的表面和所述半导体衬底的较上部分的表面之间。
21.根据权利要求17的器件，其中所述应变层具有1000埃至5000埃的厚度。
22.根据权利要求21的器件，其中沟道的厚度为30埃至200埃。
23.根据权利要求17的器件，其中所述应变层被形成在所述半导体器件的源区和漏区二者的下方。
24.根据权利要求20的器件，其中所述间隙具有沿所述半导体衬底的所述较上部分的表面的第一宽度和在所述半导体衬底的所述较上部分的表面之下的第二宽度，该第二宽度大于该第一宽度。
25.根据权利要求17的器件，其中在所述器件的沟道内存在着100MPa至3GPa的压应力。
26.根据权利要求17的器件，其中所述应变层是SiGe、Si3N4、SiO2和SiOxNy至少之一。
CNB2004800319524A 2003-11-05 2004-11-05 半导体器件及其制造方法 Expired - Fee Related CN100555600C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/605,906 US7129126B2 (en) 2003-11-05 2003-11-05 Method and structure for forming strained Si for CMOS devices
US10/605,906 2003-11-05

Publications (2)

Publication Number Publication Date
CN101164157A CN101164157A (zh) 2008-04-16
CN100555600C true CN100555600C (zh) 2009-10-28

Family

ID=34549690

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800319524A Expired - Fee Related CN100555600C (zh) 2003-11-05 2004-11-05 半导体器件及其制造方法

Country Status (6)

Country Link
US (5) US7129126B2 (zh)
EP (1) EP1680804A4 (zh)
JP (1) JP4959337B2 (zh)
KR (1) KR100866826B1 (zh)
CN (1) CN100555600C (zh)
WO (1) WO2005045901A2 (zh)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7037770B2 (en) * 2003-10-20 2006-05-02 International Business Machines Corporation Method of manufacturing strained dislocation-free channels for CMOS
US7129126B2 (en) * 2003-11-05 2006-10-31 International Business Machines Corporation Method and structure for forming strained Si for CMOS devices
US7029964B2 (en) * 2003-11-13 2006-04-18 International Business Machines Corporation Method of manufacturing a strained silicon on a SiGe on SOI substrate
US20050287747A1 (en) * 2004-06-29 2005-12-29 International Business Machines Corporation Doped nitride film, doped oxide film and other doped films
US7176481B2 (en) * 2005-01-12 2007-02-13 International Business Machines Corporation In situ doped embedded sige extension and source/drain for enhanced PFET performance
US7078285B1 (en) * 2005-01-21 2006-07-18 Sony Corporation SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material
US8972300B2 (en) * 2006-04-27 2015-03-03 Panasonic Corporation Content distribution system
US7781839B2 (en) * 2007-03-30 2010-08-24 Freescale Semiconductor, Inc. Structure and method for strained transistor directly on insulator
US7572689B2 (en) * 2007-11-09 2009-08-11 International Business Machines Corporation Method and structure for reducing induced mechanical stresses
US7678634B2 (en) * 2008-01-28 2010-03-16 International Business Machines Corporation Local stress engineering for CMOS devices
US8115194B2 (en) * 2008-02-21 2012-02-14 United Microelectronics Corp. Semiconductor device capable of providing identical strains to each channel region of the transistors
FR2934416B1 (fr) * 2008-07-24 2011-09-02 Inst Nat Sciences Appliq Substrat semi-conducteur contraint et procede de fabrication associe.
US8368125B2 (en) 2009-07-20 2013-02-05 International Business Machines Corporation Multiple orientation nanowires with gate stack stressors
US20110031503A1 (en) * 2009-08-10 2011-02-10 International Business Machines Corporation Device with stressed channel
US8138523B2 (en) 2009-10-08 2012-03-20 International Business Machines Corporation Semiconductor device having silicon on stressed liner (SOL)
CN102315126A (zh) * 2010-07-07 2012-01-11 中国科学院微电子研究所 半导体器件及其制作方法
US20130137235A1 (en) * 2010-07-15 2013-05-30 University Of Electronic Science And Technology Of China Mos transistor using stress concentration effect for enhancing stress in channel area
CN104425280B (zh) * 2013-09-09 2018-08-14 中芯国际集成电路制造(上海)有限公司 半导体器件结构及其形成方法
US9368626B2 (en) 2013-12-04 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with strained layer
US9515181B2 (en) 2014-08-06 2016-12-06 Qualcomm Incorporated Semiconductor device with self-aligned back side features
GB201415119D0 (en) * 2014-08-27 2014-10-08 Ibm Method for fabricating a semiconductor structure
US10079233B2 (en) * 2016-09-28 2018-09-18 International Business Machines Corporation Semiconductor device and method of forming the semiconductor device
DE102019122987A1 (de) 2019-08-27 2021-03-04 Zf Airbag Germany Gmbh Diffusor für einen Gasgenerator, Gasgenerator mit einem solchen Diffusor und Herstellungsverfahren für einen solchen Diffusor
US11502106B2 (en) * 2020-02-11 2022-11-15 Globalfoundries U.S. Inc. Multi-layered substrates of semiconductor devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material

Family Cites Families (109)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602841A (en) * 1970-06-18 1971-08-31 Ibm High frequency bulk semiconductor amplifiers and oscillators
US4853076A (en) * 1983-12-29 1989-08-01 Massachusetts Institute Of Technology Semiconductor thin films
JPS61198743A (ja) * 1985-02-28 1986-09-03 New Japan Radio Co Ltd 半導体装置の製造方法
US4665415A (en) * 1985-04-24 1987-05-12 International Business Machines Corporation Semiconductor device with hole conduction via strained lattice
DE3676781D1 (de) * 1985-09-13 1991-02-14 Siemens Ag Integrierte bipolar- und komplementaere mos-transistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung.
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
NL8800847A (nl) * 1988-04-05 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een soi-struktuur.
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5459346A (en) * 1988-06-28 1995-10-17 Ricoh Co., Ltd. Semiconductor substrate with electrical contact in groove
US5006913A (en) * 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5108843A (en) * 1988-11-30 1992-04-28 Ricoh Company, Ltd. Thin film semiconductor and process for producing the same
US5241197A (en) * 1989-01-25 1993-08-31 Hitachi, Ltd. Transistor provided with strained germanium layer
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5310446A (en) 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
US5060030A (en) * 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
US5129882A (en) * 1990-12-27 1992-07-14 Novoste Corporation Wound clotting device and method of using same
US5081513A (en) * 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5371399A (en) * 1991-06-14 1994-12-06 International Business Machines Corporation Compound semiconductor having metallic inclusions and devices fabricated therefrom
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5679965A (en) * 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5557122A (en) * 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
US5830040A (en) * 1995-09-07 1998-11-03 S&S Industries, Inc. Cushion tips for brassiere frames
US6403975B1 (en) * 1996-04-09 2002-06-11 Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates
US5880040A (en) * 1996-04-15 1999-03-09 Macronix International Co., Ltd. Gate dielectric based on oxynitride grown in N2 O and annealed in NO
US5861651A (en) * 1997-02-28 1999-01-19 Lucent Technologies Inc. Field effect devices and capacitors with improved thin film dielectrics and method for making same
US5940736A (en) * 1997-03-11 1999-08-17 Lucent Technologies Inc. Method for forming a high quality ultrathin gate oxide layer
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US6025280A (en) * 1997-04-28 2000-02-15 Lucent Technologies Inc. Use of SiD4 for deposition of ultra thin and controllable oxides
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
JP3139426B2 (ja) * 1997-10-15 2001-02-26 日本電気株式会社 半導体装置
FR2770503B1 (fr) * 1997-11-06 2000-01-21 Darlet Marchante Tech Sa Machine d'enroulement de produit continu sous forme de feuille, pour former des bobines
US6066545A (en) * 1997-12-09 2000-05-23 Texas Instruments Incorporated Birdsbeak encroachment using combination of wet and dry etch for isolation nitride
US6274421B1 (en) * 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
KR100275908B1 (ko) * 1998-03-02 2000-12-15 윤종용 집적 회로에 트렌치 아이솔레이션을 형성하는방법
US6165383A (en) 1998-04-10 2000-12-26 Organic Display Technology Useful precursors for organic electroluminescent materials and devices made from such materials
US6361885B1 (en) * 1998-04-10 2002-03-26 Organic Display Technology Organic electroluminescent materials and device made from such materials
JP4258034B2 (ja) * 1998-05-27 2009-04-30 ソニー株式会社 半導体装置及び半導体装置の製造方法
US5989978A (en) * 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
JP4592837B2 (ja) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6319794B1 (en) * 1998-10-14 2001-11-20 International Business Machines Corporation Structure and method for producing low leakage isolation devices
DE19848480A1 (de) * 1998-10-21 2000-05-04 Degussa Verfahren zur Verbesserung der Stabilität von Polymeren
US6235598B1 (en) * 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
US20030087492A1 (en) * 2001-11-02 2003-05-08 Promos Technologies, Inc. Semiconductor device and method of manufacturing the same
US6117722A (en) * 1999-02-18 2000-09-12 Taiwan Semiconductor Manufacturing Company SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
US6255169B1 (en) * 1999-02-22 2001-07-03 Advanced Micro Devices, Inc. Process for fabricating a high-endurance non-volatile memory device
FR2791180B1 (fr) * 1999-03-19 2001-06-15 France Telecom Dispositif semi-conducteur a courant de fuite reduit et son procede de fabrication
US6284626B1 (en) * 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6656822B2 (en) * 1999-06-28 2003-12-02 Intel Corporation Method for reduced capacitance interconnect system using gaseous implants into the ILD
US6281532B1 (en) * 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
KR100332108B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 및 그 제조 방법
TW426940B (en) * 1999-07-30 2001-03-21 United Microelectronics Corp Manufacturing method of MOS field effect transistor
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6423615B1 (en) * 1999-09-22 2002-07-23 Intel Corporation Silicon wafers for CMOS and other integrated circuits
US6284623B1 (en) * 1999-10-25 2001-09-04 Peng-Fei Zhang Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect
SE515480C2 (sv) * 1999-12-15 2001-08-13 Permanova Lasersystem Ab Metod och anordning för att mäta förlusteffekten i ett fiberoptiskt kontaktdon
US6476462B2 (en) * 1999-12-28 2002-11-05 Texas Instruments Incorporated MOS-type semiconductor device and method for making same
US6221735B1 (en) * 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices
US6531369B1 (en) * 2000-03-01 2003-03-11 Applied Micro Circuits Corporation Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
US6368931B1 (en) * 2000-03-27 2002-04-09 Intel Corporation Thin tensile layers in shallow trench isolation and method of making same
JP2001338988A (ja) * 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
US6493497B1 (en) 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6501121B1 (en) 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
US7312485B2 (en) * 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US6563152B2 (en) * 2000-12-29 2003-05-13 Intel Corporation Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
US20020086497A1 (en) * 2000-12-30 2002-07-04 Kwok Siang Ping Beaker shape trench with nitride pull-back for STI
US6265317B1 (en) * 2001-01-09 2001-07-24 Taiwan Semiconductor Manufacturing Company Top corner rounding for shallow trench isolation
JP2002299568A (ja) * 2001-04-02 2002-10-11 Fujitsu Ltd Ｉｃチップ
US6403486B1 (en) * 2001-04-30 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for forming a shallow trench isolation
US6531740B2 (en) * 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6498358B1 (en) 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
JP4086272B2 (ja) * 2001-07-26 2008-05-14 株式会社東芝 半導体装置
US20030032661A1 (en) * 2001-08-02 2003-02-13 Boehringer Ingelheim Pharma Kg Pramipexole as an anticonvulsant
US6908810B2 (en) * 2001-08-08 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
US6831292B2 (en) 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US20030057184A1 (en) * 2001-09-22 2003-03-27 Shiuh-Sheng Yu Method for pull back SiN to increase rounding effect in a shallow trench isolation process
US6656798B2 (en) * 2001-09-28 2003-12-02 Infineon Technologies, Ag Gate processing method with reduced gate oxide corner and edge thinning
US6631740B1 (en) * 2001-10-24 2003-10-14 Eaton Corporation Brazing joint for tubes and the like
US6461936B1 (en) * 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
FR2838237B1 (fr) 2002-04-03 2005-02-25 St Microelectronics Sa Procede de fabrication d'un transistor a effet de champ a grille isolee a canal contraint et circuit integre comprenant un tel transistor
US6703293B2 (en) * 2002-07-11 2004-03-09 Sharp Laboratories Of America, Inc. Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates
GB0218417D0 (en) * 2002-08-08 2002-09-18 Seagate Technology Llc Combined atomic layer deposition and damascene processing for definition of narrow trenches
US6703648B1 (en) * 2002-10-29 2004-03-09 Advanced Micro Devices, Inc. Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US7388259B2 (en) * 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US6787423B1 (en) * 2002-12-09 2004-09-07 Advanced Micro Devices, Inc. Strained-silicon semiconductor device
US6825529B2 (en) * 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US6717216B1 (en) * 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US6974981B2 (en) 2002-12-12 2005-12-13 International Business Machines Corporation Isolation structures for imposing stress patterns
US6991192B2 (en) * 2003-01-07 2006-01-31 Itt Manufacturing Enterprises, Inc. Apparatus for adapting waste disposal pump to waste discharge ports of RV's, RV park systems, trains, airplanes, buses, boats and portable toilet applications, for easy and sanitary disposal of waste holding tanks
US6825086B2 (en) * 2003-01-17 2004-11-30 Sharp Laboratories Of America, Inc. Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner
US6887798B2 (en) 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7279746B2 (en) 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7119403B2 (en) * 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US6977194B2 (en) 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US8008724B2 (en) * 2003-10-30 2011-08-30 International Business Machines Corporation Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
US7129126B2 (en) * 2003-11-05 2006-10-31 International Business Machines Corporation Method and structure for forming strained Si for CMOS devices
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7122849B2 (en) * 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7205206B2 (en) * 2004-03-03 2007-04-17 International Business Machines Corporation Method of fabricating mobility enhanced CMOS devices
US7504693B2 (en) * 2004-04-23 2009-03-17 International Business Machines Corporation Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering
US7354806B2 (en) * 2004-09-17 2008-04-08 International Business Machines Corporation Semiconductor device structure with active regions having different surface directions and methods

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material

Also Published As

Publication number Publication date
US20080003735A1 (en) 2008-01-03
EP1680804A4 (en) 2008-07-09
US20050093076A1 (en) 2005-05-05
US20100109048A1 (en) 2010-05-06
US7429752B2 (en) 2008-09-30
WO2005045901A8 (en) 2006-02-02
EP1680804A2 (en) 2006-07-19
KR100866826B1 (ko) 2008-11-04
JP4959337B2 (ja) 2012-06-20
JP2007511078A (ja) 2007-04-26
CN101164157A (zh) 2008-04-16
US20080283824A1 (en) 2008-11-20
KR20060108663A (ko) 2006-10-18
US7700951B2 (en) 2010-04-20
US20070020806A1 (en) 2007-01-25
US7129126B2 (en) 2006-10-31
US7550338B2 (en) 2009-06-23
WO2005045901A2 (en) 2005-05-19
WO2005045901A3 (en) 2006-08-17
US7928443B2 (en) 2011-04-19

Similar Documents

Publication Publication Date Title
CN100555600C (zh) 半导体器件及其制造方法
US9842897B2 (en) Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide
US7026232B1 (en) Systems and methods for low leakage strained-channel transistor
US7060579B2 (en) Increased drive current by isotropic recess etch
US7585711B2 (en) Semiconductor-on-insulator (SOI) strained active area transistor
US7514309B2 (en) Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process
US8114727B2 (en) Disposable spacer integration with stress memorization technique and silicon-germanium
US7384861B2 (en) Strain modulation employing process techniques for CMOS technologies
US7566609B2 (en) Method of manufacturing a semiconductor structure
TW200824007A (en) Stressed field effect transistor and methods for its fabrication
CN100536090C (zh) 形成cmos半导体器件的方法
US9564488B2 (en) Strained isolation regions
KR20060130098A (ko) 변형된 핀펫 채널 제조 방법
US7169659B2 (en) Method to selectively recess ETCH regions on a wafer surface using capoly as a mask
US20060134873A1 (en) Tailoring channel strain profile by recessed material composition control
US20090152670A1 (en) Semiconductor device and method of fabricating the same
US7098095B1 (en) Method of forming a MOS transistor with a layer of silicon germanium carbon
CN116387355A (zh) 具有多层集电极的双极晶体管
CN101192538A (zh) 用于应变硅mos晶体管的使用硬掩模的刻蚀方法和结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091028

Termination date: 20161105

CF01 Termination of patent right due to non-payment of annual fee