CN100550629C - A kind of full differential BiCMOS comparer - Google Patents
A kind of full differential BiCMOS comparer Download PDFInfo
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- CN100550629C CN100550629C CNB2006101697210A CN200610169721A CN100550629C CN 100550629 C CN100550629 C CN 100550629C CN B2006101697210 A CNB2006101697210 A CN B2006101697210A CN 200610169721 A CN200610169721 A CN 200610169721A CN 100550629 C CN100550629 C CN 100550629C
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Abstract
A kind of full differential BiCMOS comparer comprises: regeneration input stage, buffer stage circuit, latch cicuit and output driving circuit, the input stage of wherein regenerating comprises: the bipolar amplifying circuit and controlled tail current three parts of MOS of MOS switch, band sampling capacitance, and latch cicuit comprises: current switch latchs and source follower; Input signal enters the bipolar amplifying circuit of band sampling capacitance by the MOS switch, the MOS switch was opened in the circuit sampling stage, the regenerative amplification stage turn-offs, input signal amplifies input signal after entering the bipolar amplifier of being with sampling capacitance, and being connected and disconnection by the controlled tail current source of MOS control tail current and the amplifier of being with sampling capacitance, the process amplifying signal enters in the electric current latch cicuit after improving carrying load ability by the buffer stage circuit, the electric current latch cicuit carries out once more the amplification of latching to signal, through source follower signal is outputed to drive circuit, be converted to the output of ECL level by drive circuit.The present invention has low-power consumption, characteristics at a high speed.
Description
Technical field
The present invention relates to a kind of comparator circuit that can be used in the A/D converter, particularly a kind of full differential BiCMOS comparer.
Background technology
Chinese patent publication number CN 200510025424, open day is on October 5th, 2005, the name be called disclose in " comparator and analog to digital converter " a kind of by the sampling (Sampling), amplify (Amplify), regeneration (Regenarate), relatively (Compare) realizes the comparator (being called for short the SARC comparator) of comparator function, be used for analog to digital converter, this comparator is realized sampled input signal and sampling reference signal respectively by two pairs of switches and inverter, and to sampling differential wave realization amplification, regeneration and latch the function of comparison obtains higher comparison precision and comparison speed.This relatively the employing is CMOS technology, though have precision and speed preferably, its weak point is: under identical comparator precision, specific rate is low mutually with the comparator that adopts BiCMOS technology.
Summary of the invention
Technology of the present invention is dealt with problems: overcome the deficiencies in the prior art, a kind of low-power consumption, full differential BiCMOS comparer at a high speed are provided, adopted the BiCMOS technology, the low-power consumption high-speed and CMOS technology of bipolar process is combined, eliminated the preamplifier that adopts in the bipolar process comparator, under the situation of sacrifice circuit speed not, reduced the power consumption of circuit, improved speed.
Technical solution of the present invention: a kind of full differential BiCMOS comparer comprises: regeneration input stage, buffer stage circuit, latch cicuit and output driving circuit, the input stage of wherein regenerating comprises: the bipolar amplifying circuit and controlled tail current three parts of MOS of MOS switch, band sampling capacitance, and latch cicuit comprises: current switch latchs and source follower; Input signal enters the bipolar amplifying circuit of band sampling capacitance by the MOS switch, this MOS switch was opened in the circuit sampling stage, the regenerative amplification stage turn-offs, come control input signals whether to enter the bipolar amplifier of band sampling capacitance, input signal enters in the bipolar amplifier of being with sampling capacitance input signal is amplified, what the tail current source of the bipolar amplifier of band sampling capacitance adopted is the controlled tail current source of MOS, controlled tail current source control tail current source is connected and disconnection with the amplifier of being with sampling capacitance, thereby reduce unnecessary power consumption penalty, reduce the circuit total power consumption, enter the buffer stage circuit through amplifying signal subsequently, improve carrying load ability by the buffer stage circuit, the signal of buffer stage circuit output is sent in the electric current latch cicuit, the current switch latch cicuit to signal carry out once more latch amplification after through source follower signal is outputed to drive circuit, will be converted to ECL level output by drive circuit.
Described MOS control switch is managed M1 and M2 by two NMOS and is connect, by a clock control break-make.
The bipolar amplifying circuit of described band sampling capacitance comprises: sampling capacitance C1～C4, transistor Q1～Q2, resistance R 3 and PMOS pipe M3, M4 and M8, the collector electrode of transistor Q1 and Q2 is connected to the drain electrode of PMOS pipe M3 and M4, the source electrode of M3 and M4 is connected on the power supply, grid links to each other and constitutes constant-current source, collector current is provided for transistor Q1 and Q2, wherein PMOS pipe M8 is connected across between the collector electrode of Q1 and Q2, and is connected by resistance R 3 on the grid of PMOS pipe M3 and M4; Capacitor C 3 and C4 link together the base stage of Q1 and the collector electrode of Q2 and the base stage of Q2 and the collector electrode of Q1 respectively, constitute the feedback capacity of bipolar amplifier together, the base stage of transistor Q1 and Q2 links to each other with C2 with capacitor C 1 respectively, and the other end of C1 and C2 links to each other with power supply.
The controlled tail current source of described MOS comprises: metal-oxide-semiconductor M5～M7, M13, M14 and be connected the grid of NMOS pipe M7 and the capacitor C 5 between the drain electrode, the emitter-base bandgap grading of transistor Q1 and Q2 links to each other and is connected with PMOS pipe M5, the drain electrode of PMOS pipe M5 simultaneously links to each other with NMOS pipe M7, the source electrode of M7 links to each other with the drain electrode of NMOS pipe M6, it is identical that the grid of M5 and M6 is connected the cycle respectively, signal psi all the time 2 that direction is opposite and φ 1, PMOS pipe M13 and NMOS pipe M14 constitute the CMOS inverter φ 2 signal inversion are offered NMOS pipe M7 as signal, and the break-make of controlled tail current source 3 is subjected to the control of clock signal φ 1 and φ 2.
Described capacitor C 1～C5 all adopts grid oxygen electric capacity, or links together by the source of metal-oxide-semiconductor is leaked, and applies voltage and form between grid and diffusion region.
Described buffer stage circuit is made of source follower, i.e. metal-oxide-semiconductor M11, M12, M17 and M18, and wherein the collector electrode of Q1 is connected on the grid of NMOS pipe M11, and the source electrode of M11 pipe is connected with a tail current source, and M17 constitutes by the NMOS pipe; The collector electrode of Q2 is connected on the grid of NMOS pipe M12, and the source electrode of M12 pipe is connected with a tail current source, and M18 constitutes by the NMOS pipe, and the source electrode output from M11 and M12 pipe of buffer circuit enters the latch cicuit.
Described current switch latch cicuit comprises: transistor Q3～Q6, resistance R 1 and R2, metal-oxide-semiconductor M9, M10 and M19, the emitter of Q3 and Q5 link together and are connected on the tail current source by NMOS pipe M9, and M19 constitutes by the NMOS pipe.The collector electrode of Q3 and Q5 is connected on the power supply by resistance R 1 and R2, and the collector electrode output signal of transistor Q3 and Q5 is sent on the base stage of transistor Q4 and Q6 as input signal after by source follower, and the annexation of Q4 and Q6 is identical with Q3 and Q5; The emitter of Q4 and Q6 links together and is connected on the tail current source by NMOS pipe M10, and tail current source is made of NMOS pipe M19; The collector electrode of Q4 and Q6 is connected on the power supply by resistance R 1 and R2.
Described output driving circuit is made of emitter follower, comprises transistor Q7～Q10, M21, M22; The base stage of Q7 and Q8 receives the output signal from the source class follower of latch cicuit, wherein Q7 and Q8 pipe constitutes two emitter followers respectively, wherein the source output of NMOS pipe M15 is connected on the base stage of transistor Q7, the emitter of Q7 pipe is connected with a tail current source, and M22 constitutes by the NMOS pipe; The source output of NMOS pipe M16 is connected on the base stage of transistor Q8, the emitter of Q8 pipe is connected with a tail current source, M23 constitutes by the NMOS pipe, the signal of exporting by the emitter of Q7 and Q8 pipe is connected on the base stage of transistor Q9 and Q10, and last circuit is by the emitter output of Q9 and Q10 pipe.
The present invention's beneficial effect compared with prior art is:
(1) bipolar being amplified in its regeneration input circuit among the present invention, avoid having used preamplifier, eliminated the recovery time of overdriving, because the input stage of circuit part only consumes power consumption in the regenerative amplification pattern, have only half period to have power consumption consumption, thereby reduced the overall power consumption of circuit, improved speed.
(2) the present invention has adopted the controlled tail current source of MOS, by being connected and disconnection of controlled tail current source control tail current source and bipolar amplifier, thereby reduces unnecessary power consumption penalty, reduces the circuit total power consumption.
(3) the present invention has adopted the MOS switch, has cut off the cascode end of differential pair tube of amplifier and the path between the ground, avoids making transistor to enter saturated mode, also prevents to produce simultaneously extra power consumption.
(4) all electric capacity all adopts grid oxygen electric capacity among the present invention, also can link together by the source of metal-oxide-semiconductor is leaked, and applies suitable voltage and constitute electric capacity between grid and diffusion region, and this electric capacity can be produced on the digital circuit district, and area occupied is little.
(5) latch signal of the latch cicuit among the present invention is finished by the MOS differential pair, can directly adopt the CMOS level, output then is to export under the buffering of two emitter followers, provide ECL output level to the next stage circuit, make circuit in the process of using, reach CMOS level and the compatible use of ECL level.
Description of drawings
Fig. 1 is a structured flowchart of the present invention;
Fig. 2 is an electrical schematic diagram of the present invention;
Fig. 3 is in two kinds of reduced graphs under the different operating state for regeneration input stage circuit of the present invention, and wherein Fig. 3 a is the reduced graph under the sampling configuration, and Fig. 3 b is the reduced graph under the regenerative amplification pattern.
Embodiment
As shown in Figure 1, the present invention includes the output driving circuit of buffer stage circuit, latch cicuit and emitter follower 7 compositions of regeneration input stage, source follower 4 compositions, the input stage circuit of wherein regenerating is divided into the bipolar amplifying circuit 2 and controlled tail current source 3 three parts of MOS of MOS switch 1, band sampling capacitance again, and latch cicuit comprises current switch latch cicuit 5 and source follower 6.Input signal enters the bipolar amplifying circuit 2 that band is adopted electric capacity by MOS switch 1, and MOS switch 1 was opened in the circuit sampling stage, and the regenerative amplification stage turn-offs, and comes control input signals whether to enter band and adopts in the amplifier 2 of electric capacity.Input signal amplifies by the bipolar amplifier 2 of band sampling capacitance, what the tail current source of this bipolar amplifier 2 adopted is the controlled tail current source 3 of MOS, controlled tail current source 3 control tail current sources are connected and disconnection with amplifier 2, thereby reduce unnecessary power consumption penalty, reduce the circuit total power consumption.To enter source class follower 4 through amplifying signal subsequently, improve the carrying load ability of circuit by source class follower 4, output signal is sent in the latch cicuit, carry out latching after the amplification through source follower 6 signal is outputed to drive circuit once more by 5 pairs of signals of current switch latch cicuit, drive circuit adopts emitter follower 7, by emitter follower 7 conversion of signals is the output of ECL level.
Be illustrated in figure 2 as circuit diagram of the present invention.The control signal of MOS control switch 1 is a pair of reciprocal clock level φ 1, the φ 1 among the φ 2 in this circuit diagram, and MOS control switch 1 is made up of NMOS pipe M1 and M2; The bipolar amplifying circuit 2 of band sampling capacitance comprises capacitor C 1～C4, transistor Q1～Q2, resistance R 3 and PMOS pipe M3, M4 and M8, adopts metal-oxide-semiconductor to provide constant-current source for circuit in the bipolar amplifying circuit 2 of band sampling capacitance.The controlled tail current source 3 of MOS comprises metal-oxide-semiconductor M5～M7, M13 and M14 and capacitor C 5, and the break-make of its controlled tail current source 3 also is subjected to the control of clock signal φ 1 and φ 2.The course of work of circuit is: differential input signal Vin1 and Vin2 signal are connected on M1 and the M2, after M1 and M2 open, input signal enters into the bipolar amplifier 2 of capacitor sampling, and on capacitor C 1 and C2, this moment, controlled tail current source 3 was closed with signal sampling.When closing, M1 and M2 have no progeny, controlled tail current source 3 is opened, be connected on Q1 and the Q2, the input signal of capacitor C 1 and C2 up-sampling is amplified the back in its collector electrode output through transistor Q1 and Q2, wherein PMOS pipe M3, M4 and M8 resistance R 3 constitute the constant-current source of amplifier 2, collector current are provided for transistor Q1 and Q2.Capacitor C 3 and C4 are respectively the coupling capacitances of differential pair tube Q1 and Q2, respectively the base stage of Q1 and the collector electrode of Q2 and the base stage of Q2 and the collector electrode of Q1 are linked together, and constitute the feedback capacity of differential amplifier together.Signal after bipolar amplifier 2 outputs of capacitor sampling enters in the source class follower 4, source class follower 4 is made of metal-oxide-semiconductor M11, M12, M17 and M18, source class follower 4 enters the current switch latch cicuit 5 from the source electrode output of M11 and M12, the output signal of source class follower 4 enters in the current switch latch cicuit 5, and this current switch latch cicuit 5 comprises transistor Q3～Q6, resistance R 1 and R2, metal-oxide-semiconductor M9, M10 and M19.Transistor Q3 and Q5 constitute a pair of amplifier tube, and the output signal of source class follower 4 is amplified, and Q4 and Q6 constitute a pair of amplifier tube and by the control of switch M9 and M10 the output signal of Q3 and Q5 carried out regenerative amplification, and wherein the M19 pipe uses as tail current source.Output signal after this amplification enters in the source class follower 6, source class follower 6 is made of M15, M16, M20 and M21, send in the emitter follower 7 after the signal output, emitter follower 7 is made of transistor Q7～Q10, metal-oxide-semiconductor M22 and M23, base stage by Q7 and Q8 receives the output signal from source class follower 6, wherein Q7 and Q8 pipe constitutes two emitter followers respectively, in the emitter output through Q9 and Q10 pipe.
Fig. 3 has provided regeneration input stage circuit of the present invention and has been operated in two kinds of circuit reduction figure under the different mode, wherein Fig. 3 a is the reduced graph under the sampling configuration, during sampling configuration, switch controlling signal φ 1 opens metal-oxide-semiconductor M1 and M2 for high level, capacitor C 1～C4 samples to input voltage, the collector potential of transistor Q1 and Q2 is drawn high to positive supply, and φ 2 charges to positive voltage for low level with capacitor C 5.Metal-oxide-semiconductor M7 and M6 open, and the other end of capacitor C 5 is connected on the GND.Because the differential pair tube Q1 and the Q2 of cascode pattern open a way, thereby differential pair tube is not worked under sampling configuration.Along with the effect of switch controlling signal, circuit enters the regenerative amplification pattern, shown in Fig. 3 b, disconnect between input signal and the sampling capacitance, the collector electrode of Q1 and Q2 and power supply disconnect, and switch controlling signal is connected to the cascode end with an end and the GND disconnection of capacitor C 5, be pre-charged to positive supply, at φ
2Link to each other with GND under the effect of signal.Be precharged on the C5 of supply voltage this moment and have certain quantity of electric charge, this electric weight will be transferred on the bipolar differential pair tube.Under the regenerative amplification pattern, sample phase is stored in capacitor C 1, C3 and C2, and the electric weight on the C4 is stored on the base stage of transistor Q1 and Q2 through the form of the overdischarge initial differential voltage with input signal.Because cross coupling capacitor C3 and C4, the initial differential voltage on Q1 and the Q2 base stage obtains regenerative amplification on this transistorized collector electrode, and the regeneration input stage is by the collector electrode output of Q1 and Q2.
If input voltage from+1V～-1mV changes, the frequency of clock signal is 100MHz.Under the regeneration mode of first clock cycle, the 1V signal that is stored in transistor base in advance by electric capacity under the sampling configuration makes the whole flow of charge on the C5 export through Q1.Therefore, the collector voltage of Q1 reduces, and the collector voltage of Q2 keeps high level constant.
The output signal of regeneration input stage of the present invention is exported under the buffering through two source class followers subsequently, sends into a low-power consumption then, in the current switch latch cicuit 5.This current switch latch cicuit 5 latchs circuit by MOS differential pair M9 and M10, and its output through the output of two emitter follower bufferings, provides ECL output level to the next stage circuit again.All electric capacity all are grid oxygen electric capacity among the present invention, link together by the source of metal-oxide-semiconductor is leaked, and apply suitable voltage and form between grid and diffusion.Metal-oxide-semiconductor M7 is arranged between M5 and the M6, has cut off the emitter-base bandgap grading of Q1 and Q1 and the path between the ground, and this path can be introduced extra power consumption, makes transistor enter saturated mode.
Claims (9)
1, a kind of full differential BiCMOS comparer, comprise: regeneration input stage, buffer stage circuit, latch cicuit and output driving circuit, it is characterized in that: described regeneration input stage comprises: the bipolar amplifying circuit and controlled tail current source three parts of MOS of MOS switch, band sampling capacitance; Latch cicuit comprises: current switch latch cicuit and source follower; Input signal enters the bipolar amplifying circuit of band sampling capacitance by the MOS switch, the MOS switch was opened in the circuit sampling stage, the regenerative amplification stage turn-offs, input signal amplifies input signal after entering the bipolar amplifying circuit of being with sampling capacitance, and being connected and disconnection by the controlled tail current source of MOS control tail current and the bipolar amplifying circuit of being with sampling capacitance, the process amplifying signal enters in the latch cicuit after improving carrying load ability by the buffer stage circuit, the current switch latch cicuit carries out once more the amplification of latching to signal, through source follower signal is outputed to drive circuit, be converted to the output of ECL level by drive circuit.
2, full differential BiCMOS comparer according to claim 1 is characterized in that: described MOS switch is managed M1 and M2 by two NMOS and is connect, by a clock control break-make.
3, full differential BiCMOS comparer according to claim 1, it is characterized in that: the bipolar amplifying circuit of described band sampling capacitance comprises: sampling capacitance C1～C4, transistor Q1～Q2, resistance R 3 and PMOS pipe M3, M4 and M8, the collector electrode of transistor Q1 and Q2 is connected to the drain electrode of PMOS pipe M3 and M4, the source electrode of PMOS pipe M3 and M4 is connected on the power supply, grid links to each other and constitutes constant-current source, collector current is provided for transistor Q1 and Q2, wherein PMOS pipe M8 is connected across between the collector electrode of transistor Q1 and Q2, and is connected by resistance R 3 on the grid of PMOS pipe M3 and M4; Sampling capacitance C3 and C4 link together the base stage of transistor Q1 and the collector electrode of transistor Q2 and the base stage of transistor Q2 and the collector electrode of transistor Q1 respectively, constitute the feedback capacity of bipolar amplifier together, the base stage of transistor Q1 and Q2 links to each other with C2 with sampling capacitance C1 respectively, and the other end of sampling capacitance C1 and C2 links to each other with power supply.
4, full differential BiCMOS comparer according to claim 1, it is characterized in that: the controlled tail current source of described MOS comprises: PMOS pipe M 5 and M13, NMOS manages M6, M7 and M14 and be connected the grid of NMOS pipe M7 and the capacitor C 5 between the drain electrode, the emitter-base bandgap grading of transistor Q1 and Q2 links to each other and is connected with PMOS pipe M5, the drain electrode of PMOS pipe M5 simultaneously links to each other with NMOS pipe M7, the source electrode of NMOS pipe M7 links to each other with the drain electrode of NMOS pipe M6, it is identical that the grid of PMOS pipe M5 and NMOS pipe M6 is connected the cycle respectively, clock signal φ 2 that direction is opposite and φ 1, PMOS pipe M13 and NMOS pipe M14 constitute the CMOS inverter clock signal φ 2 anti-phase NMOS that offer are managed M7 as signal, and the break-make of the controlled tail current source of MOS is subjected to the control of clock signal φ 1 and φ 2.
5, full differential BiCMOS comparer according to claim 3 is characterized in that: described capacitor C 1～C4 all adopts grid oxygen electric capacity.
6, full differential BiCMOS comparer according to claim 1, it is characterized in that: described buffer stage circuit is made of source follower, be NMOS pipe M11, M12, M17 and M18, wherein the collector electrode of transistor Q1 is connected on the grid of NMOS pipe M11, the source electrode of NMOS pipe M11 is connected with a tail current source, and this tail current source is made of NMOS pipe M17; The collector electrode of transistor Q2 is connected on the grid of NMOS pipe M12, and the source electrode of NMOS pipe M12 is connected with a tail current source, and this tail current source is made of NMOS pipe M18, and buffer circuit enters the latch cicuit from the source electrode output of NMOS pipe M11 and M12.
7, full differential BiCMOS comparer according to claim 1, it is characterized in that: described current switch latch cicuit comprises: transistor Q3～Q6, resistance R 1 and R2, NMOS pipe M9, M10 and M19, the emitter of transistor Q3 and Q5 links together and is connected on the tail current source by NMOS pipe M9, and this tail current source is made of NMOS pipe M19; The collector electrode of transistor Q3 and Q5 is connected on the power supply by resistance R 1 and R2, and the collector electrode output signal of transistor Q3 and Q5 is sent on the base stage of transistor Q4 and Q6 as input signal after by source follower; The emitter of transistor Q4 and Q6 links together and is connected on the tail current source by NMOS pipe M10, and this tail current source is made of NMOS pipe M19; The collector electrode of transistor Q4 and Q6 is connected on the power supply by resistance R 1 and R2.
8, full differential BiCMOS comparer according to claim 1 is characterized in that: described output driving circuit is made of emitter follower, comprises transistor Q7～Q10, NMOS pipe M22 and M23; The base stage of transistor Q7 and Q8 receives the output signal from the source class follower of latch cicuit, wherein transistor Q7 and Q8 constitute two emitter followers respectively, wherein the source output of NMOS pipe M15 is connected on the base stage of transistor Q7, the emitter of transistor Q7 is connected with a tail current source, and this tail current source is made of NMOS pipe M22; The source output of NMOS pipe M16 is connected on the base stage of transistor Q8, the emitter of transistor Q8 is connected with a tail current source, this tail current source is made of NMOS pipe M23, the signal of exporting by the emitter of transistor Q7 and Q8 is connected on the base stage of transistor Q9 and Q10, and last circuit is by the emitter output of transistor Q9 and Q10.
9, full differential BiCMOS comparer according to claim 4 is characterized in that: described capacitor C 5 adopts grid oxygen electric capacity.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101697210A CN100550629C (en) | 2006-12-28 | 2006-12-28 | A kind of full differential BiCMOS comparer |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101697210A CN100550629C (en) | 2006-12-28 | 2006-12-28 | A kind of full differential BiCMOS comparer |
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| CN1996752A CN1996752A (en) | 2007-07-11 |
| CN100550629C true CN100550629C (en) | 2009-10-14 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102111126B (en) * | 2009-12-24 | 2012-10-03 | 上海华虹Nec电子有限公司 | Circuit structure of differential comparator |
| CN102386897A (en) * | 2010-09-02 | 2012-03-21 | 国民技术股份有限公司 | Device and method for comparing signals |
| CN102768852B (en) * | 2012-08-01 | 2015-03-18 | 北京大学 | Sensitive amplifier |
| US9397624B2 (en) * | 2014-07-11 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Unity gain buffers and related method |
| CN106569008A (en) * | 2016-11-13 | 2017-04-19 | 天津大学 | Novel broadband peak detection circuit |
| CN108306646B (en) * | 2018-04-26 | 2023-12-12 | 南京邮电大学 | Comparator circuit applied to ultra-high speed analog-to-digital converter |
| US11128287B1 (en) | 2020-03-23 | 2021-09-21 | Analog Devices, Inc. | Comparator with configurable operating modes |
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