CN100530620C - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN100530620C
CN100530620C CNB2006101214094A CN200610121409A CN100530620C CN 100530620 C CN100530620 C CN 100530620C CN B2006101214094 A CNB2006101214094 A CN B2006101214094A CN 200610121409 A CN200610121409 A CN 200610121409A CN 100530620 C CN100530620 C CN 100530620C
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CN
China
Prior art keywords
coil
semiconductor device
substrate
electrode
electrically connected
Prior art date
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Expired - Fee Related
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CNB2006101214094A
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Chinese (zh)
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CN1893052A (en
Inventor
佐藤明弘
关口智
镰土清和
坪野谷诚
三田清志
锅田洋一
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Application filed by Kanto Sanyo Semiconductors Co Ltd, Sanyo Electric Co Ltd filed Critical Kanto Sanyo Semiconductors Co Ltd
Publication of CN1893052A publication Critical patent/CN1893052A/en
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Publication of CN100530620C publication Critical patent/CN100530620C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

A semiconductor apparatus having a semiconductor chip, a first coil electrically connected to the semiconductor chip and a first electrode electrically connected to the first coil is comprised of a second electrode which can be electrically connected to the first electrode as well as which can be electrically connected to a second coil on the outside of the semiconductor apparatus, and is characterized by that inductance composed of the first coil and the second coil is obtained by electrically connecting the second electrode to the first electrode and the second coil.

Description

Semiconductor device
The cross reference of related application
The application's requirement on January 24th, 2005 and the Japanese patent application No.2005-15818 of submission on November 14th, 2005 and the priority of 2005-329185, is introduced above-mentioned Japanese patent application at this by reference respectively.
Technical field
The present invention relates to a kind of semiconductor device with coil.
Background technology
Recently, the small-size electronic equipment that is widely current, these small-size electronic equipments are cell phone, portable audio device, PDA, digital camera etc.Require these electronic equipments to become littler, have greater functionality, have more high-performance or the like.Therefore, if make electronic equipment, then require packaging technology etc. can reach higher density (for example, referring to Japanese Patent Application Laid-Open No.2002-93847).
In order to meet this requirement, recently, for example to make up the AM/FM tuner and this AM/FM tuner is provided as the commodity that can be installed on the portable electric appts by one (1) encapsulation (semiconductor device).Although having stored the encapsulation of the nearly all parts of tuner exists as (1) IC chip (semiconductor chip) usually, but, for example still must the inductance (coil), variable capacitance diode etc. of local oscillator circuit be installed as external component on the printed circuit board of electronic equipment with this encapsulation.In the encapsulation described here, the IC chip is electrically connected to the conductive path that forms on resin substrate one side, annotates resin (insulating resin) with its sealing by mould then.On the contrary, recently, for external component being stored in one (1) encapsulation, on the opposite side (i.e. the downside of this encapsulation) of the substrate of this encapsulation, be formed for the pattern of coil, perhaps the capacitor group is attached in the IC chip, replaces having large-sized relatively variable capacitance diode.Make up capacitor group (capacitorbank) by a plurality of capacitors that are connected in parallel, and change frequency by using software sequentially to change these capacitors with electric capacity of distinguishing by preliminary dimension.In this mode,, can easily be portable electric appts equipment radio function equally by using the encapsulation that is called " chip " recently.
Incidentally, usually for the good frequency characteristic of the lc circuit of keeping above-mentioned local oscillator circuit etc., must with the induction coefficient property settings of coil predetermined value, for example this predetermined value maximizes the Q value of lc circuit, to keep this predetermined value when the operation of electronic equipment etc., wherein encapsulation is installed to this electronic equipment.For example, the induction coefficient of the coil that provides in the encapsulation that induction coefficient described here is represented to install on printed circuit board with IC chip etc.
Yet because the mutual inductance of the coupling circuit element around the coil etc., the induction coefficient of coil can be offset predetermined value, and for example this predetermined value can be that single encapsulation is set by the manufacturer of this encapsulation when delivering.When operating electronic equipment etc., because the induced noise from circuit element etc. around the coil is disturbed the predetermined value when this induction coefficient may be offset delivery.
Summary of the invention
Consider these problems, conceived the present invention.Therefore the object of the present invention is to provide a kind of semiconductor device, can set and keep induction coefficient when mounted is predetermined value.
In order to realize above purpose, according to a first aspect of the invention, provide a kind of semiconductor device, it comprises: semiconductor chip; First coil, it is electrically connected to semiconductor chip; First electrode, it is electrically connected to first coil; With second electrode, it can be electrically connected to first electrode, and second electrode can be electrically connected to second coil on the outside of semiconductor device, and wherein second electrode is electrically connected to first electrode and second coil, with the inductance that obtains to be made up of first coil and second coil.
In order to realize above purpose, according to a second aspect of the invention, provide a kind of semiconductor device, it comprises: substrate; Semiconductor chip, it is arranged on substrate one side; First coil, it is formed on the substrate opposite side and is electrically connected to semiconductor chip by spiral-shaped; First electrode, it is formed on the substrate opposite side and is electrically connected to first coil; With second electrode, it is formed on the opposite side of substrate and can be electrically connected to first electrode, second electrode can be electrically connected to second coil on the outside of semiconductor device, and wherein second electrode is electrically connected to first electrode and second coil, with the inductance that obtains to be made up of first coil and second coil.
In order to realize above purpose, according to a third aspect of the invention we, provide a kind of semiconductor device, it comprises: substrate; Semiconductor chip, it is arranged on substrate one side; First coil, it is formed on substrate one side surface of semiconductor chip by spiral-shaped, and first coil is electrically connected to semiconductor chip; First electrode, it is formed on the substrate opposite side surface and is electrically connected to first coil; With second electrode, it is formed on the opposite side surface of substrate and can be electrically connected to first electrode, second electrode can be electrically connected to second coil on the outside of semiconductor device, wherein second electrode is electrically connected to first electrode and second coil, with the inductance that obtains to be made up of first coil and second coil.
Therefore, provide and to have set and to have kept the semiconductor device that induction coefficient is a predetermined value when mounted.
Feature of the present invention except above and purpose will become obvious from the description of this specification and accompanying drawing.
Description of drawings
When in conjunction with the accompanying drawings, above and other purpose of the present invention, aspect, feature and advantage will become more obvious from following detailed description, wherein:
Figure 1A is the upper side plane figure of the semiconductor device of embodiment;
Figure 1B is the end view of the semiconductor device of embodiment;
Fig. 1 C is the basiscopic perspective view of the semiconductor device of embodiment when upside is seen;
Fig. 2 is a circuit diagram, and its expression is used for the example of resonator equivalent electric circuit of the semiconductor device of embodiment;
Fig. 3 A is the plane graph that amplifies the semiconductor device part of embodiment;
Fig. 3 B is the sectional view that amplifies the semiconductor device part of embodiment;
Fig. 3 C is the perspective view that amplifies the semiconductor device part of embodiment;
Fig. 4 A is the plane graph of the circuit arrangement part of embodiment;
Fig. 4 B is the sectional view of the circuit arrangement part of embodiment;
Fig. 5 is a circuit diagram, and its expression is used for the example of equivalent electric circuit of resonator of the circuit arrangement of this embodiment;
Fig. 6 is another circuit diagram, and its expression is used for the example of equivalent electric circuit of resonator of the circuit arrangement of this embodiment;
Fig. 7 A is the sectional view that amplifies the cross section be installed to coil insulated substrate, that be made up of rolled copper foil;
Fig. 7 B is the sectional view that amplifies the cross section of the coil that forms by the plating insulated substrate;
Fig. 8 A is another plane graph of example on the semiconductor device of this embodiment;
Fig. 8 B is the opposite side view of the semiconductor device of this embodiment;
Fig. 8 C is another perspective view of the semiconductor device downside of this embodiment when upside is seen;
Fig. 9 is the plane graph of the substrate upside of this embodiment;
Figure 10 is the opposite side view of the semiconductor device of this embodiment; With
Figure 11 is the structure chart of topology example of the FM wireless receiver of this embodiment of expression.
Embodiment
By the description of explanation in this specification and accompanying drawing, Yi Xia problem will become clearer at least.
The structure of＜＜semiconductor device〉〉
The topology example of the semiconductor device 1 of embodiment is described to 1C in conjunction with Figure 1A.Figure 1A is the plane graph of semiconductor device 1 upside; Figure 1B is the end view of semiconductor device 1; And Fig. 1 C is the perspective view of semiconductor device 1 downside when upside is seen.Hereinafter, in this semiconductor device 1, the IC chip side of describing later is called " upside ", and in semiconductor device 1, the coil sides of describing later is called " downside ".As illustrating among Figure 1A and Fig. 1 C, the semiconductor device 1 of this embodiment is the encapsulation with for example approximate foursquare upside and downside.For example, the length of an approximate square side is approximately 5mm.For example, the thickness of the encapsulation that illustrates among Figure 1B (length on the Z direction) is approximately 1mm.Therefore, the semiconductor device 1 of this embodiment has formed and has had the plate shaped of approximate foursquare upside and downside.Yet semiconductor device 1 is not limited to have the approximate foursquare plate shaped of above-mentioned size.
As described in the 1C, constitute semiconductor device 1 as Figure 1A by mainly comprising substrate 10, IC chip (semiconductor chip) 20, coil (first coil) 30 and dummy pattern (conductive pattern) 40.On substrate 10, form coil electrode (first electrode) 127b, 128b and adjustment terminal (second electrode) L1, L2.As described later, " adjustment " of adjusting terminal L1, L2 is illustrated in total induction coefficient adjustment of the semiconductor device 1 in the circuit arrangement 100 (Fig. 4) on the user side.
About substrate 10, main material is the insulated substrate of for example being made up of glass-epoxy 11 (Figure 1B), and predetermined conductive path 12a (Figure 1B) is connected thereto side, is coated with insulation solder resist pattern 13a (Figure 1B) on this conductive path 12a.Predetermined conductive path 12b (Figure 1B) is connected to insulated substrate 11 downsides, is coated with insulation solder resist pattern 13b (Figure 1B) on this conductive path 12b.In insulated substrate 11, get out through hole (Fig. 3 A is to 3C), penetrate between upside and the downside.
Described in Figure 1A, for example, the predetermined conductive path 12a that is connected to upside constitutes by comprising 26 IC chip designs and (a 1) coil pattern.Each IC chip design constitutes by via openings electrode (for example opening electrode 121a), wiring (122a for example connects up) and internal electrode (for example internal electrode 123a).Coil pattern constitutes by via openings electrode 301a, 302a and the cross wiring 303a that is used for coil.
Described in Fig. 1 C, the predetermined conductive path 12b that is connected to downside constitutes by comprising corresponding to the pattern of above-mentioned 26 IC chip designs with corresponding to being used for above-mentioned opening electrode 301b, the 302b that is used for via openings electrode 301a, the 302a of coil.Except coil electrode 127b, 128b and adjustment terminal L1, L2, each pattern all passes through opening electrode (for example opening electrode 121b), wiring (122b for example connects up) and outside terminal (for example outside terminal 123b) and constitutes.
On the other hand, arrange coil electrode 127b and adjustment terminal L1 adjacent to each other.Similarly, arrange coil electrode 128b and adjustment terminal L2 adjacent to each other.In this embodiment, relation between coil electrode 127b, 128b and adjustment terminal L1, the L2 is equivalent to opening electrode 121b in for example above-mentioned IC chip design and the structure of outside terminal 123b, is separated from each other for these structures provide therebetween wiring 122b and these structures.By this mode, coil electrode 127b, 128b and adjustment terminal L1, L2 are adjacent one another are when electric insulation.Identical with situation with opening electrode 121b, 124b, because coil electrode 127b, 128b have the opening of through hole at the center, so the essence zone as conductor is little, and therefore coil electrode 127b, 128b are not used as the input/output terminal that is used for the outside on semiconductor device 1 downside.On the contrary, adjusting terminal L1, L2 has by soldered ball etc. to be electrically connected to outside more large-area conductor.
Relatively arranging opening electrode 121a on the upside and the opening electrode 121b on the through hole downside on each side.Similarly, opening electrode 127a and coil electrode 127b are the relations of the upside and the downside of same through hole, and opening electrode 128a and coil electrode 128b are the relations of the upside and the downside of same through hole.
For example, IC chip 20 (Figure 1A and 1B) is the inner coil that forms the semiconductor device 1 of part rather than this embodiment of supporting chip.As described in Figure 1A, for example IC chip 20 is included on the left of the Y-axis and 13 electrodes 201,202 on each side on right side.These 26 electrodes 201,202 are electrically connected to 26 internal electrode 123a by metal fine 22 respectively.Although the IC chip 20 of the present embodiment has for example approximate rectangular plate shaped, this approximate rectangular plate shaped size that has less than approximate foursquare aforesaid substrate 10 the invention is not restricted to this.For the IC chip 20 of this embodiment, the quantity of the corresponding electrode of determining 201,202 and the quantity of internal electrode, outer electrode etc. are not limited to above-described 26.
Described in Fig. 1 C, coil 30 is made up of two (2) the individual spiral planar coils 301,302 that are connected to insulated substrate 10, with the part as above-mentioned downside conductive path 12b.Coil 301 and coil 302 are connected to criss-cross wiring 303a, so that above-mentioned opening electrode 301b, 302b (Fig. 1 C) have identical electromotive force with opening electrode 301a, 302a (Figure 1A).Cross wiring 303a is electrically connected to the electrode 202 of IC chip 20 by wiring 125a, internal electrode 126a and metal fine 22.On the other hand, this cross wiring 303a is connected to outside terminal VCC (Fig. 1 C) by opening electrode 124a (Figure 1A) and opening electrode 124b (Fig. 1 C), to have identical electromotive force.
In this embodiment, the electrode of two (2) individual coils 301,302 on the side is opening electrode 301b, 302, and the electrode on the opposite side is coil electrode 127b, 128b.
Except 24 above-mentioned outside terminals, two (2) individual adjustment terminal and coil electrode 127b, 128b, the whole surface of substrate 10 downsides also is coated with above-mentioned solder resist pattern 13b.
For example dummy pattern 40 can be made up of the integral planar conductor.Yet,, realize the described special-effect in back by the dummy pattern 40 that a plurality of conductors of arranging with predetermined narrow clearance gap constitute.
Described in Figure 1A, on the upside of insulated substrate 10, relatively form the dummy pattern 40 of this embodiment with the coil 301,302 on insulated substrate 10 downsides.Particularly, the dummy pattern 40 of this embodiment constitutes by arranging the conductor 401 of isolating, for example, the conductor 401 of this isolation mainly is made of according to narrow gap (predetermined space) 402 approximate square at interval copper (Cu), so that a side of the rectangular IC chip 20 of its phase pairing approximation forms about miter angle.Approximate square and 45 degree are a kind of examples.For example a plurality of gaps 402 have orthogonal linearity configuration.Because the profile of dummy pattern 40 is aimed at the approximate rectangular profile of combination two (2) individual coils 301,302, so the part of approximate foursquare conductor 401 has subtriangular shape near this profile.Because the distance of the conductor 401 of dummy pattern 40 in this narrow gap centers on above-mentioned opening electrode 301a, 302a and cross wiring 303a, so the part of approximate foursquare conductor 401 has subtriangular shape, for example near opening electrode 301a, 302a and wiring 303a subtriangular shape is arranged.These conductors 401 are connected to the upside of insulated substrate 10 and apply solder resist pattern 13a for it.By insulating cement (insulating binder) 21 IC chip 20 is fixed to solder resist pattern 13a.
Incidentally, because conductor 401 relative gaps 402 of dummy pattern 40 form convex on the z of Figure 1B direction, so the solder resist pattern 13a that applies on it also forms similarly protruding/spill.When on printed circuit board 500 described later semiconductor device 1 being installed, this protruding/spill causes reducing the stress that acts on the semiconductor device 1.Described in Figure 1A, because the gap 402 of conductor 401 formation spills has from the shape of the XY planar central radiation of substrate 10 relatively, so above-mentioned insulating cement 21 can easily be used, when using, strengthened the fugitiveness (fugitivity of voids) in space, therefore, sealing and viscosity between dummy pattern 40 and IC chip 20 have been improved.Therefore, when producing semiconductor device 1, can be easily and IC chip 20 is installed far and away.
In this embodiment, after on substrate 10, IC chip 20 being installed, annotate the upside of resin (insulating resin) 50 hermetic sealing substrates 10 by mould by the dummy pattern 40 that forms.
Described in the circuit diagram of Fig. 2, for example, the semiconductor device 1 of this embodiment can be a tuner apparatus, so that the resonator that a part of IC chip 20 and coil 301,302 are equivalent in the local oscillator circuit.In the equivalent electric circuit described in Fig. 22, the coil described in Fig. 1 C (conductor) 301,302 and each conductor 311a, 312a of stemming from this encapsulation are connected in series, such as conductive path 12a, 12b.Each strip metal fine rule 22 grade is connected in series to these conductors 311a, 312a as the conductor that stems from the line bonding.Yet in this embodiment, for example these conductors approximately are 25% to the contribution of coil 301,302.
As shown in Figure 2, internal body diodes 210 and capacitor group 220 are connected to each conductor 301,311a, 22 and conductor 302,312a, 22.Internal body diodes 210 and capacitor group 220 integrally are formed into IC chip 20.10 capacitors with electric capacity of distinguishing according to preliminary dimension constitute the capacitor group 220 of this embodiment by for example being connected in parallel, and change frequency by using software sequentially to change these capacitors.
The semiconductor device 1 of this embodiment is not limited to above-mentioned tuner apparatus.In this embodiment, for the coil 301,302 that forms with spirality, the coil in the equivalent electric circuit 2 that comprises above-mentioned conductor 311a, 312a, metal fine 22 etc. can be corresponding to first coil.
For the example that is electrically connected between conductive path 12a, 12b in the semiconductor device 1 of this embodiment and the IC chip 20, made more detailed description to 3C with reference to figure 3A.Fig. 3 A is the amplification view of the semiconductor device 1 bottom left-hand component of Figure 1A; Fig. 3 B is the amplification view of semiconductor device 1 left-hand component of Figure 1B; And Fig. 3 C is the enlarged perspective of the semiconductor device 1 bottom left-hand component of Fig. 1 C.
Described in Fig. 3 A, above-mentioned opening electrode 121a, the wiring 122a and the internal electrode 123a that are connected to insulated substrate 11 upsides are the conductor of one.When along this conductor of curvilinear cut from the A of Fig. 3 A to A ' and when directions X is observed this conductor, this cross section is corresponding to the part of the A-A ' of Fig. 3 B.Described in Fig. 3 B, expose this internal electrode 123a from the gap of this solder resist pattern 13a, and under the coating of solder resist pattern 13a, wiring 122a and opening electrode 121a are connected to the through hole 1201 that wherein is coated with the class quasi-conductor.
Described in Fig. 3 C, above-mentioned opening electrode 121b, the wiring 122b and the outside terminal 123b that are connected to insulated substrate 11 downsides are the conductor of one.When along this conductor of curvilinear cut from the B of Fig. 3 C to B ' and when directions X is observed this conductor, this cross section is corresponding to the part of the B-B ' of Fig. 3 C.Described in Fig. 3 B, expose this outside terminal 123b from the gap of this solder resist pattern 13b, and under the coating of solder resist pattern 13b, wiring 122b and opening electrode 121b are connected to above-mentioned through hole 1201.
From above description,, be electrically connected internal electrode 123a and outside terminal 123b by on each opposite side of substrate 10, having the through hole 1201 of opening 1201a, 1201b.On the other hand, described in Fig. 3 B, internal electrode 123a is electrically connected to the electrode 201 of IC chip 20 by metal fine 22.Therefore, outside terminal 123b is as the terminal of the IC chip 20 in the semiconductor device 1.
Identical to the example described in the 3C via the connection example between conductive path 12a, the 12b of another through hole with Fig. 3 A.In this embodiment, relevant with the opening electrode 124a, 127a, 128a, 301a, the 302a that illustrate among Figure 1A through hole is corresponding to the through hole that is electrically connected coil 30 and IC chip 20.Seal the inside of each through hole of this embodiment by solder resist.
＜＜circuit arrangement〉〉
---induction coefficient adjustment---
According to equivalent electric circuit 2 (Fig. 2), because 301,302 input only exists as the input via outside terminal VCC from the outside to the coil, so when the semiconductor device 1 that will have said structure is attached in portable electron device etc. and operates on it, in principle, only this outside terminal VCC will be to the electrical connection target of coil 301,302 from printed circuit board for example.Yet, if this semiconductor device 1 also is electrically connected to printed circuit board by other outside terminal (for example outside terminal 123b), then this induction coefficient may depart from only comprise conductor 311a, 312a, the metal fine 22 etc. that stem from this encapsulation (it is first coil, the induction coefficient Fig. 2) induction coefficient of semiconductor device 1 factory settings (promptly by).Therefore, as described later, in semiconductor device 1,, can adjust this induction coefficient by outside first coil that connects second coil, 801,802 (see figure 5)s and user side in parallel with said structure.
With reference to figure 4A and 4B, be installed to the situation of printed circuit board for the semiconductor device 1 that will have said structure with other circuit element etc. with one (1) the individual circuit arrangement that forms portable electric appts etc., made description.Fig. 4 A is the plane graph that is installed to semiconductor device 1 upside of printed circuit board 500, and Fig. 4 B is the sectional view that is installed to the semiconductor device 1 of printed circuit board 500.In other words, Fig. 4 A is the plane graph of circuit arrangement 100 parts of expression embodiment, and Fig. 4 B is the sectional view of circuit arrangement 100 parts of this embodiment of expression.Described in Fig. 4 B, this semiconductor device 1 is installed so that its downside to printed circuit board 500.On printed circuit board 500, depend on the arrangement of the outside terminal (for example outside terminal 123b) on semiconductor device 1 downside, be pre-formed predetermined conductive path, and these outside terminals are electrically connected to predetermined conductive path by soldered ball etc.Soldered balls etc. also are used as at printed circuit board 500 upper support semiconductor devices 1.
Described in Fig. 4 A, on printed circuit board 500, connect predetermined conductive path 524 in advance, this predetermined conductive path 524 should be electrically connected to the outside terminal VCC of semiconductor device 1.Although the conductive path 524 of Fig. 4 A and Fig. 4 B is relatively short, this is for convenience of description.In fact, because voltage etc. must be input to semiconductor device 1 via conductive path 524 and outside terminal VCC from the outside, so conductive path 524 must extend to another circuit element on the printed circuit board 500 etc.Described in Fig. 4 A, conductive path 527 and conductive path 528 are connected on the printed circuit board 500 in advance, and they should be electrically connected to the adjustment terminal L1 of semiconductor device 1 respectively and adjust terminal L2.
On the other hand, on semiconductor device 1, coil electrode 127b and adjustment terminal L1 are by metal fine 1271 line bondings.Coil electrode 128b and adjustment terminal L2 are by metal fine 1281 line bondings.By this mode, between coil electrode 127b, the 128b of electric insulation and adjustment terminal L1, L2, form respectively and be electrically connected.
Semiconductor device 1 is installed on printed circuit board 500 so that: outside terminal 124b is electrically connected conductive paths 524 by soldered ball 64; Adjust terminal L1 and be electrically connected to conductive path 527 by soldered ball 67; L2 is electrically connected to conductive path 528 by soldered ball 68 with the adjustment terminal.Fig. 4 B is the sectional view from the C of Fig. 4 A to the cross section of C ' in the indication circuit device 100.As shown in this Fig, coil electrode 128b is electrically connected to adjustment terminal L2 by metal fine 1281 and this adjustment terminal L2 is electrically connected to conductive path 528 by soldered ball 68.Similarly, coil electrode 127b is electrically connected to conductive path 527 by metal fine 1271, adjustment terminal L1 and soldered ball 67.Outside terminal VCC is electrically connected to conductive path 524 by soldered ball 64.On printed circuit board 500, in order to form the part of second coil, 801,802 (see figure 5)s described later, conductive path 524 and conductive path 527 are electrically connected by coil 701, and conductive path 524 and conductive path 528 are electrically connected by coil 702.
Above structure and equivalent electric circuit illustrated in fig. 5, be understood that the part of second coil 801 corresponding to Fig. 4, from coil terminals 127b via metal fine 1271, adjust terminal L1, soldered ball 67, conductive path 527, coil 701, conductive path 524, soldered ball 64 and outside terminal VCC to opening electrode 124b.Similarly, second coil 802 is corresponding to the part of Fig. 4, from coil terminals 128b via metal fine 1281, adjust terminal L2, soldered ball 68, conductive path 528, coil 702, conductive path 524, soldered ball 64 and outside terminal VCC to opening electrode 124b.
According to this structure, by adjusting the induction coefficient of the coil 701,702 self on semiconductor device 1 user side for example, i.e. length, diameter, coil turn, material etc. can be adjusted the induction coefficient of each second coil 801,802.By this mode, adjust total induction coefficient of semiconductor device 1 in can the circuit arrangement 100 on user side.
If above-mentioned semiconductor device 1 is a tuner apparatus, this tuner apparatus has a part of IC chip 20 and the coil 301,302 of the resonator that is equivalent in the local oscillator circuit, can be predetermined value for example then, so that the Q value is got maximum by the induction coefficient of the single semiconductor device 1 of factory settings.If by the user this semiconductor device 1 is installed on electronic equipment etc., so because the mutual inductance of the circuit element around the coupling etc., the induction coefficient of this semiconductor device 1 can depart from when delivery the predetermined value by factory settings.Since when operating electronic equipment etc. from the interference of the induced noise of peripheral circuits element etc., the predetermined value when this induction coefficient can depart from delivery.In contrast, according to the semiconductor device 1 of this embodiment, by when mounted or when operation accurately measure induction coefficient and, can easily eliminate this skew by adjusting the induction coefficient of above-mentioned coil 701,702 self.Therefore, provide and to have set and to have kept the semiconductor device 1 that this induction coefficient is a predetermined value when mounted.
If when being installed to above-mentioned semiconductor device 1 on the printed circuit board 500, induction coefficient can not be offset predetermined value, what being used for of then illustrating among Fig. 4 A and the 4B, induction coefficient adjusted is connected not necessarily.In this case, compare with the situation of adjustment terminal L1, L2 to be electrically connected coil electrode 127b, 128b with composition in advance, coil electrode 217b, the 218b that exposes on semiconductor device 1 downside has the littler openend of area as circuit that expose.Therefore, actual in addition when operation induced noise etc. nearly all do not influence the semiconductor device 1 of this embodiment.
Incidentally, in above-mentioned induction coefficient is adjusted, although two (2) individual second coils 801,802 are respectively applied for two (2) individual coils 301,302,, the invention is not restricted to this.
Described in the circuit diagram of Fig. 6 A, for example, can form equivalent electric circuit 2b only to adjust one (1) individual coil 301.In this case, do not carry out the line bonding that the metal fine 1281 by Fig. 4 carries out at least.Described in the circuit diagram of Fig. 6 B,, can form equivalent electric circuit 2c by increasing capacitor (electric capacity) 803 to this equivalence circuit 2a (Fig. 5).
---stability of induction coefficient characteristic---
In this embodiment, conductor does not exist on printed circuit board 500 surfaces of the coil 30 of facing semiconductor device 1 such as conductive path.On the other hand, in this embodiment, between IC chip 20 and coil 30, dummy pattern 40 is arranged.Because so the induced noises when having stopped operation IC chip 20 by this dummy pattern 40 etc. are can be so that the induction coefficient stability of characteristics of coil 30.For example, the induction coefficient stability of characteristics represents that the induction coefficient that the induction coefficient of coil 30 maintains predetermined value or coil 30 maintains in the preset range.Therefore, for single semiconductor device 1, if in the manufacturing of semiconductor device, the installation site of IC chip 20 relative substrates 10 etc. has produced error, and then the operation of IC chip 20 influences induction coefficient characteristic and its stability of coil 30 littlelyr.Owing on printed circuit board 500, do not have conductor, can mainly form the mutual inductance of coupling coil 30 by dummy pattern 40 near coil 30.Therefore, the coil 30 of single semiconductor device 1 has predetermined induction coefficient characteristic if producer designs dummy pattern 40 in advance, as long as the user of semiconductor device 1 carries out installation on the zone that does not have conductor of printed circuit board 500, just kept the predetermined induction coefficient characteristic of coil 30 so.
---rolling conductive foil---
The coil 301,302 that is connected to insulated substrate 11 in the semiconductor device 1 of this embodiment is made by rolling conductive foil.For example the main material of rolling conductive foil is copper (Cu), and by repeating the cathode copper that rolling and annealing in process has been cast into the ingot bar form, rolling conductive foil is formed the paper tinsel form.This rolled copper foil is fixed to the downside of insulated substrate 11, and suitably forms the spiral pattern of coil 301,302.Not only coil 301,302, and whole conductive path 12a, 12b can be made by this rolled copper foil.
Described in the sectional view of Fig. 7 A, in the coil of being made by rolled copper foil 301, crystal is stretching on will be by the direction of insulated substrate 11 downside surfaces of lamination.On the other hand, described in the sectional view of Fig. 7 B, if at this coil 301 ' middle execution plating, these crystal are arranged perpendicular to insulated substrate 11 downside surfaces so.Fig. 7 A is the amplification sectional view of cross section of coil 301 (being made by rolled copper foil) that is connected to this embodiment of insulated substrate 11 downside surfaces, and Fig. 7 B be by be plated to the coil 301 that insulated substrate 11 downside surfaces form ' the amplification sectional view of cross section.
For the coil of making by the rolled copper foil that illustrates among Fig. 7 A 301, the crystal grain boundary area less than the coil 301 that forms by the plating that illustrates among Fig. 7 B ' the crystal grain boundary area, therefore, in this embodiment, suppressed via diffusion and the phenomenon of osmosis of crystal grain boundary from the impurity of outside.Therefore, compare with the coil that forms by plating and since kept this embodiment coil 301 better purity and resistance can be controlled at littler level, so the induction coefficient of semiconductor device 1 maintains predetermined value easily.
Described in Fig. 7 A, if because the difference between the thermal coefficient of expansion of coil 301 and insulated substrate 11 has produced stress, if and coil 301 and therefore bending of insulated substrate 11, then in the coil of being made by rolled copper foil 301, being arranged so that of these crystal is difficult to break.In the coil of being made by rolled copper foil 301, when being installed to semiconductor device 1 on the printed circuit board 500, tensile stress and bending stress owing to acting on the insulated substrate 11 are difficult to break equally.On the other hand, described in Fig. 7 b, the coil 301 that forms by plating ' in, between crystal, be easy to generate crack S.Therefore, compare with the coil that forms by plating, because the coil 301 of this embodiment has more high strength and resistance can be controlled to littler level, therefore, the induction coefficient of semiconductor device 1 maintains predetermined value easily.
From above description, in the semiconductor device 1 of this embodiment, can set induction coefficient when mounted is predetermined value, and keeps the stability of this induction coefficient characteristic when operation.By this mode, obtained better frequency characteristic such as the Q value from this semiconductor device 1, therefore, obtained more performance from the electronic equipment that is equipped with semiconductor device 1.
The semiconductor device 1 of this embodiment has IC chip 20, be electrically connected to first coil 301 of IC chip 20,302,311a, 312a, 22 and be electrically connected to first coil 301,302,311a, 312a, 22 coil electrode 127b, 128b, comprise and to be electrically connected to coil electrode 127b, 128b and can on semiconductor device 1 outside, be electrically connected to second coil 801,802 adjustment terminal L1, L2, and it is characterized in that by adjusting terminal L1, L2 is electrically connected to coil electrode 127b, the 128b and second coil 801,802, obtain by first coil 301,302,311a, 312a, 22 and second coil 801,802 inductance of forming.According to semiconductor device 1, by when mounted or when operation correct measurement induction coefficient and by adjusting the induction coefficient of coil for example 701,702 self, coil 701,702 is parts of second coil 801,802, for example can easily eliminate departing from the inductance of being arranged to single assembly.Therefore, provide and to have set and to have kept the semiconductor device 1 that induction coefficient is a predetermined value when mounted.
The semiconductor device 1 of this embodiment comprises: substrate 10; The IC chip 20 that on the substrate upside, provides, on substrate 10 downsides with spirality form and coil 301,302 that be electrically connected to IC chip 20; Coil electrode 127b, 128b, it forms and is electrically connected to coil 301,302 on substrate 10 downsides; With adjustment terminal L1, L2, it is formed on substrate 10 downsides, can be electrically connected to coil electrode 127b, 128b and can be connected to second coil 801,802 in semiconductor device 1 external electric, it is characterized in that: be electrically connected to coil electrode 127b, 128b and second coil 801,802 by adjusting terminal L1, L2, obtain the inductance of forming by the coil 301,302 and second coil 801,802.According to semiconductor device 1, predetermined value can be set and maintain to this induction coefficient when installing.
Preferably, above-mentioned semiconductor device 1 also comprises dummy pattern 40, and it is formed on facing on the surface of IC chip 20, to be used for the induction coefficient characteristic of ballast coil 301,302 on substrate 10 upsides.For single semiconductor device 1, if in the manufacturing of semiconductor device, the installation site of IC chip 20 relative substrates 10 etc. has produced error, and then the operation of IC chip 20 influences induction coefficient characteristic and its stability of coil 30 littlelyr.The coil 30 of single semiconductor device 1 has predetermined induction coefficient characteristic if producer designs dummy pattern 40 in advance, as long as the user of semiconductor device 1 carries out installation on the zone that does not have conductor of printed circuit board 500, just kept the predetermined induction coefficient characteristic of coil 30 so.
In above-mentioned semiconductor device 1, preferably, IC chip 20 is fixed to dummy pattern 40 by insulating cement 21.By this mode and since IC chip 20 can be fixed on dummy pattern 40 near, so the induced noise can stop operation IC chip 20 effectively time the etc.
In above-mentioned semiconductor device 1, preferably,, constitute dummy pattern 40 by arranging the conductor 401 of a plurality of isolation with predetermined gap 402 reservation shape at interval.By this mode, in the time of on semiconductor device 1 being installed to for example printed circuit board 500, this causes acting on the stability that stress on the semiconductor device 1 reduces and improved the induction coefficient characteristic.
In above-mentioned semiconductor device 1, preferably, by arranging that according to approximate rectangle the conductor 401 of a plurality of separation constitutes dummy pattern 40, so that approximately linear ground is to arrange that a plurality of predetermined gaps 402 make it to intersect.By this mode, because predetermined gap 402 for example can form the spill of conductor 401 relatively, so can easily use insulating cement 21.
In above-mentioned semiconductor device 1, preferably, IC chip 20 is for rectangle and IC chip 20 outward flanges have predetermined angle, approximately linear ground arranges that a plurality of predetermined gaps 402 make it to intersect relatively.By this mode, because predetermined gap 402 can have radial from substrate 10 centers, so when using insulating cement 21, strengthened the fugitiveness in space.
Preferably, above-mentioned semiconductor device 1 also comprises: through hole, and it penetrates between the upside of substrate 10 and downside and is electrically connected electrode 124b, 127b, 128b, 301b, the 302b of IC chip 20 and coil; And mould is annotated resin 50, the upside of its hermetic sealing substrate 10.In this semiconductor device 1, can set and keep induction coefficient when mounted is predetermined value.
In above-mentioned semiconductor device 1, coil the 301, the 302nd is fixed to the rolling conductive foil of substrate 10 downsides.Because the crystal grain boundary area of the coil of being made by rolling conductive foil 301,302 is less than the crystal grain boundary area in the situation that forms by plating, so suppressed from the outside diffusion and phenomenon of osmosis via the impurity of crystal grain boundary.Therefore, kept this embodiment coil 301,302 better purity and resistance can be controlled at littler level.If because the difference between the thermal coefficient of expansion of coil 301,302 and insulated substrate 11 has produced stress, if and bend in the coil of making by rolled copper foil 301,302, then the layout of these crystal makes to compare with the situation that forms by plating and is difficult to break.In the coil of being made by rolled copper foil 301, when being installed to semiconductor device 1 on the printed circuit board 500, tensile stress and bending stress owing to acting on the insulated substrate 11 are difficult to that equally magnetic takes place and split.Therefore, coil 301,302 has more high strength and resistance can be controlled to littler level.Therefore, the induction coefficient of semiconductor device 1 maintains predetermined value easily.
Coil is in the substrate upside exists and conductive pattern exists at downside situation
In the semiconductor device 1 of above-mentioned embodiment, although form conductive pattern (dummy pattern 40) and form coil (coil 30) at substrate 10 downsides at upside, this upside is the IC chip side of substrate (substrate 10), but can put upside down this relative positioning relation between conductive pattern on substrate upside and the downside and coil.
As Fig. 8 A to described in the 8C, at semiconductor device 1 " in, at substrate 10 " on the upside form coil 30 ", and " form dummy pattern 40 on the downside " at substrate 10.Fig. 8 A is the semiconductor device 1 " plane graph of upside; Fig. 8 B is a semiconductor device 1 " end view; Fig. 8 C is the semiconductor device 1 " perspective view of downside when upside is seen.Hereinafter, at this semiconductor device 1 " in, IC chip side (+Z side) is called " upside ", and at this semiconductor device 1 " in, a side opposite with the IC chip side is called " downside ".
" be a kind of encapsulation, except above-mentioned relative positioning relation, this encapsulation has the approximate surface structure that is equivalent to Figure 1A to the semiconductor device 1 of 1C explanation to semiconductor device 1 in this embodiment.By mainly comprising substrate 10 ", IC chip (semiconductor chip) 20 ", coil 30 " and dummy pattern (conductive pattern) 40, coil electrode (first electrode) 127 ", 128b " and adjust terminal (second electrode) L1, L2, constitute semiconductor device 1 ".This semiconductor device 1 " is not limited to this structure and can comprise dummy pattern 40.
" be connected thereto side, this conductive path 12a " on be coated with insulation solder resist pattern 13a " described in Fig. 8 B, about substrate 10 ", main material is the insulated substrate of for example being made up of glass-epoxy 11 ", and with predetermined conductive path 12a.With the predetermined conductive path 12b downside that " is connected to insulated substrate 11 ", this conductive path 12b " on be coated with insulation solder resist pattern 13b ".At insulated substrate 11 " in get out through hole, penetrate between upside and the downside.
Described in Fig. 8 A, for example, the via openings electrode 301a ", 302a ", the 304a that are connected to the predetermined conductive path 12a " by comprising 26 IC chip designs and the bridge thread path 303b that is used for described later " (Fig. 8 C) of upside " constitute.Each IC chip design is by opening electrode (for example opening electrode 121a ", 124a "), wiring (122a that for example connects up ", 125a ") and internal electrode (for example internal electrode 123a ", 126a ") formation.Especially, each IC chip design that is connected to coil 301 ", 302 " has opening electrode 127a ", 128a " respectively in the wiring of connecting coil 301 ", 302 " and internal electrode.Opening electrode 127a ", 128a " adjusts terminal L1, L2 (Fig. 8 C) by the aftermentioned that through hole is connected on the downside.In the explanation of Fig. 8 A, the IC chip design that is connected to outside terminal VCC (Fig. 8 C) by through hole is also included within on the upside along Y direction and extends to opening electrode 304a " circuit 305a ".
Described in Fig. 8 C, the predetermined conductive path 12b " by comprising pattern and the bridge thread path 303b corresponding to above-mentioned 26 IC chip designs " that is connected to downside constitutes.Each IC chip design is by opening electrode (for example opening electrode 121b ", 124b "), wiring (122b that for example connects up ", 125b ") and outside terminal (electrode, for example outside terminal 123b ", 126b ") formation.On each side, relatively be arranged in the above-mentioned via openings electrode 121a " and the opening electrode 121b on downside " on the upside.
Bridge thread path 303b " is used to connect two (2) individual coils 301 ", 302 ".Be arranged in through hole, the circuit 305a of opening electrode 304b along the X-direction center " and opening electrode 304a " (Fig. 8 A) " through hole of (Fig. 8 A) and above-mentioned IC chip design (Fig. 8 A), bridge thread path 303b " is connected to outside terminal VCC to have same potential by connection." (Fig. 8 A), the electrode that bridge thread path 303b " is electrically connected to IC chip 20 " (for example electrode 201 ", 202 ") by above-mentioned IC chip design and metal fine 22.
" (Fig. 8 A and 8B) is supporting chip to IC chip 20, and it is identical with the IC chip 20 that Figure 1A illustrates in the 1C.
Described in Fig. 8 A, two (2) individual spiral planar coils 301 of coil 30 " by being connected to insulated substrate 10 " ", 302 " are formed, with as above-mentioned upside conductive path 12a " a part.Described in Fig. 8 B, the coil 301 of this embodiment " and 302 " is connected to insulated substrate 10 " upside and be coated with solder resist pattern 13a ".IC chip 20 " by insulating cement (insulating binder) 21 " is fixed to solder resist pattern 13a ".According to the explanation of Fig. 8 A, two (2) individual coils 301 ", 302 " form with identical shape, and it is at substrate 10 " on the surface therefrom the mind-set outside coils with being rotated counterclockwise.
Described in Fig. 8 C, the coil 301 on dummy pattern 40 " with insulated substrate 10 " upside ", 302 " relatively is formed on insulated substrate 10 " on the downside.Particularly, the approximate rectangular copper (Cu) of the dummy pattern 40 of the present embodiment " be made of single conductor, for example, this single conductor is mainly by the above-mentioned bridge thread path 303b that is centered around its core " constitutes.By this mode, because conductor is at bridge thread path 303b " around exist, so bridge thread path 303b " as so-called complanar line path.Therefore, " generate an electromagnetic field, then dummy pattern 40 " absorbs this electromagnetic field if from bridge thread path 303b.
The dummy pattern 40 of this embodiment " profile aim at combination two (2) individual coils 301 ", 302 " approximate rectangular profile.In other words, the position that exceeds outer rim under the situation of this dummy pattern 40 " in same position or with two (2) individual coils 301 ", 302 " being considered to overall coil 30 " has outward flange.By this mode, if when operating coil 30 " time from the coil 30 " downside that generates an electromagnetic field (Z side), dummy pattern 40 so " absorbs this electromagnetic field.
Dummy pattern 40 " is connected to a plurality of earth terminals described later 15 " to be in same potential.
As described in Fig. 8 C, for example go up with as above-mentioned downside conductive path 12b when be installed in printed circuit board 500 (Fig. 4 B) along 26 above-mentioned outside terminals " a part of the time, a plurality of earth terminals (electrode) 15 " are connected to the insulated substrate 10 that is used for ground connection ".Yet earth terminal 15 " be not limited to be used for ground connection, and it can be to be used to keep dummy pattern 40 " is any electrode of identical voltage.For example, the magnitude of voltage of identical voltage is determined by the voltage on the precalculated position of printed circuit board 500.In this mode, be that same voltage makes its electromotive force stable by the mutual inductance of keeping dummy pattern 40 " with coil 30 " coupling, this coil 30 " the induction coefficient characteristic more stable.For example, the induction coefficient of coil 30 " induction coefficient stability of characteristics represent coil 30 " maintains predetermined value or coil 30 " induction coefficient maintain in the preset range.
Described in Fig. 8 C, coil electrode 127b ", 128b " is corresponding to last side opening electrode 127a ", 128a ", as above-mentioned downside conductive path 12b " a part.Coil electrode 127b ", 128b " is connected to side opening electrode 127a ", 128a " by through hole respectively.
As described in Fig. 8 C, form to adjust terminal L1, L2 respectively, with coil electrode 127b ", 128b " become a pair of, as above-mentioned downside conductive path 12b " a part." adjustment " of adjusting terminal L1, L2 is illustrated in the semiconductor device 1 in the circuit arrangement 100 on the above-mentioned user side (for example circuit arrangement 100 of Fig. 4) " total induction coefficient.Although when each interval and when insulation, near coil electrode 127b ", 128b " and adjusting terminal L1, L2 be positioned at the invention is not restricted to this, for example, and near coil electrode 127b ", 128b " and adjustment terminal L1, L2 can not be positioned at.In fact, as mentioned above, as long as wait by the line bonding at user side and to realize being electrically connected, coil electrode 127b ", 128b " and adjust terminal L1, L2 and just can have the space distance of the explanation of being longer than or being shorter than Fig. 8 C, and can have another conductive path etc. in the interval betwixt.
In this embodiment, except above-mentioned a plurality of outside terminals, coil electrode 127b ", 128b " with adjust terminal L1, L2, substrate 10 " the whole surface of downside all is coated with above-mentioned solder resist pattern 13b ".
In this embodiment, " after going up, annotate the upside of resin (insulating resin) 50 " hermetic sealing substrates 10 " by mould at the substrate 10 that IC chip 20 " is installed to and is formed with coil 30 ".
In the semiconductor device 1 of this embodiment, the input of ", 302 " only exists as the input via outside terminal VCC because from the outside to the coil 301, " be attached in portable electron device etc. and when operating on it; in principle, only this outside terminal VCC will be the electrical connection target of from printed circuit board for example to coil 301 ", 302 " so when with semiconductor device 1.Yet, if this semiconductor device 1 " also by other outside terminal (for example outside terminal 123b ") be electrically connected to printed circuit board, then this induction coefficient may depart from stem from this encapsulation only comprise conductor (for example conductor 311a, the 312a of Fig. 2), metal fine 22 " etc. the induction coefficient induction coefficient of factory settings (promptly by the semiconductor device 1 ") of (it is first coil).Therefore, in the situation of Figure 1A illustrated semiconductor device, at semiconductor device 1 to 1C " in, by outside first coil that connects second coil (for example the 2 801,802 of Fig. 5) and user side in parallel, can adjust this induction coefficient.Particularly, in the situation of Figure 1A illustrated semiconductor device to 1C, for example, coil electrode 127b " and adjust terminal L1 by metal fine (for example; the metal fine 1271 of Fig. 4 A and 4B) line bonding; and coil electrode 128b " and adjusts terminal L2 by metal fine (for example, the metal fine 1281 of Fig. 4 A and 4B) line bonding.By being electrically connected coil electrode 127b ", 128b " respectively and adjusting terminal L1, L2, can adjust semiconductor device 1 in the electronic equipment on user side " total induction coefficient.
In the situation of the semiconductor device 1 that Figure 1A illustrates in the 1C, the semiconductor device 1 of this embodiment " can be tuner apparatus, tuner apparatus has a part of IC chip 20 " and coil 301 ", 302 of the resonator that is equivalent in the local oscillator circuit ".In this case, for example by the single semiconductor device 1 of factory settings " induction coefficient be that predetermined value is so that the Q value is got maximum.The predetermined value of factory settings when the induction coefficient that " is installed on the electronic equipment etc., so because the mutual inductance of coupling peripheral circuits element etc., so semiconductor device 1 " if the user is with this semiconductor device 1 can be offset delivery.Since when the operation of electronic equipment etc. from around the induced noise of circuit element etc. disturb, so the predetermined value when this induction coefficient may be offset delivery.
For this " skew ", according to the semiconductor device 1 of this embodiment ", by when mounted or when operation correct measurement induction coefficient and by adjusting the induction coefficient of second coil 801,802 (Fig. 5), can easily eliminate this skew.Therefore, provide and to have set and to have kept the semiconductor device 1 that induction coefficient is a predetermined value when mounted ".
According to this semiconductor device 1 ", if generate an electromagnetic field the electromagnetic interference of the electronic equipment that dummy pattern 40 so " absorb this electromagnetic field, therefore, can suppress being equipped with semiconductor device 1 " etc. from coil 30 ", bridge thread path 303b " etc.Therefore, from acquisition more performance such as electronic equipments.
---two line symmetric coil---
Semiconductor device 1 in above-mentioned embodiment " in (Fig. 8 A), although two (2) individual coils 301 ", 302 " form with identical shape, it is at substrate 10 " on the surface therefrom the mind-set outside coils with being rotated counterclockwise, the invention is not restricted to this.
For example, as shown in Figure 9, two (2) individual coils 8301,8302 of semiconductor device 81 can form the line symmetric figure with respect to the border along Y-axis.This figure is the plane graph of substrate 810 upsides.In the explanation of this figure, with respect to will be towards the IC chip (border that is divided into two of substrate 810 uper side surfaces of the IC chip 20 ") of Fig. 8 A for example; for example pass mid point on the X-direction and be parallel to the border of Y-axis, the shape of two (2) individual coils 8301,8302 is mirror each other." (Fig. 8 circuit 8305a a) is positioned on this border corresponding to above-mentioned circuit 305a.
As mentioned above, (metal fine 22 ") of Fig. 8 B for example, two (2) individual coils (tertiary coil and the 4th coil) 8301,8302 are connected to the IC chip by two (2) individual IC chip designs 8121,8122 and two (2) strip metal fine rules respectively.Therefore, when two (2) individual coils 8301,8302 are the line symmetry with respect to above-mentioned border, if form two (2) individual IC chip designs 8121,8122 and two (2) strip metal fine rules respectively, the inductance value of two (2) the individual coils 8301,8302 that comprise wiring is equated to have same structure.In this mode, because the easily encapsulation of designing semiconductor device 81 and simplified the structure of the coil 830 that comprises wiring, so therefore reduced the production cost of semiconductor device 81.
---additional conductive pattern---
Semiconductor device 1 in above-mentioned embodiment " in (Fig. 8 B), although only " form dummy pattern 40 on the downside " at substrate 10, the invention is not restricted to this.Semiconductor device 1 in above-mentioned embodiment " in, " provide IC chip 20 " by insulated substrate 10 " the solder resist pattern 13a on the upside " and insulating cement 21, two coils 301 ", 302 " are connected to this insulated substrate 10 ".For example, have and dummy pattern 40 " approximate identical shaped additional conductive pattern can be present in solder resist pattern 13a " and insulating cement 21 " between.
As shown in Figure 10, for the substrate 910 of semiconductor device 91, main material is the insulated substrate of for example being made up of glass-epoxy 911, and: (1) is connected thereto side with predetermined conductive path 912a (comprising coil 9301,9302); (2) the solder resist pattern 913a that will insulate is coated on its upside; (3) dummy pattern (additional conductive pattern) 941 is connected thereto on the side, this dummy pattern has approximate rectangular shape and it is made of single conductor; (4) the solder resist pattern 914a that will insulate is coated on its upside.On insulated substrate 911 downsides: (5) are connected to insulated substrate 911 downsides with predetermined conductive patterns 912b and dummy pattern (conductive pattern) 942; (6) will insulate solder resist pattern 913b coating thereon.Figure 10 is the end view of semiconductor device 91.
In semiconductor device 91,, between IC chip 920 and solder resist pattern (it can be thought of as insulating binder) 913a, also there is another dummy pattern 941 except the dummy pattern 942 that on substrate 910 downsides, provides.
Because so the induced noises when having stopped operation IC chip 920 by dummy pattern 941 etc. are can be so that the induction coefficient stability of characteristics of coil 930 ( coil 9301,9302).Therefore, for single semiconductor device 91, for example, aspect manufacturer, if the installation site of the substrate 910 of IC chip 920 relative semiconductor devices 91 etc. has produced error, then the operation of IC chip 920 influences induction coefficient characteristic and its stability of coil 930 littlelyr.
---rolling conductive foil---
In the situation of semiconductor device 1 illustrated in fig. 1, at the coil 30 of the semiconductor device 1 of this embodiment ", 81,91 in be connected to insulated substrate 11 ", 911 upsides ", 830,930 make by rolling conductive foil.This rolled copper foil is connected to insulated substrate 11 ", 911 downsides, and correctly form coil 30 ", 830,930 spiral pattern.Not only coil 30 ", 830,930, and whole conductive path 12a ", 12b ", 912a, 912b can be made by this rolled copper foil.
As mentioned above, for example, compare, owing to kept the coil 30 of this embodiment with the coil that forms by plating ", 830,930 better purity and resistance can be controlled at littler level; therefore, semiconductor device 1 ", 81,91 induction coefficient maintains predetermined value easily.As mentioned above, for example, and compare, because the coil 30 of this embodiment by the coil that electroplate to form ", 830,930 have more high strength and resistance can be controlled at littler level; therefore, semiconductor device 1 ", 81,91 induction coefficient maintains predetermined value easily.
---wireless receiver---
For example, with above-mentioned semiconductor device 1,1 ", 81,91 be installed on the printed circuit board 500 (Fig. 4 B) with other semiconductor device, to constitute portable FM wireless receiver 700 (Figure 11) as tuner apparatus.Figure 11 is the block diagram of the topology example of expression FM wireless receiver 700.
As shown in Figure 11, the FM wireless receiver 700 of this embodiment constitutes by comprising antenna 701, RF amplifier 702, frequency mixer 703, local oscillator 704, first intermediate frequency amplifier 705, first intermediate-frequency filter 706, second intermediate-frequency filter 707, selector 708, second intermediate frequency amplifier 709, FM wave detector 710 and lead-out terminal 711.
The broadcasting station signal that receives by antenna 701 amplify by RF amplifier 702 and by frequency mixer 703 with from the local oscillator signal mixing of local oscillator 704 to be converted to intermediate-freuqncy signal.First intermediate-frequency filter 706 or second intermediate-frequency filter 707 and selector 708 limit bands are amplified and passed through to intermediate-freuqncy signal by first intermediate frequency amplifier 705.The intermediate-freuqncy signal of limit band is amplified or the limit amplitude by second intermediate frequency amplifier 709, and carries out the FM modulation to output to outside terminal 711 by FM wave detector 710.
At semiconductor device 1,1 as the tuner apparatus of this embodiment ", in 81,91; for example; by soldered ball 68, the outside terminal on its downside (for example VCC) is electrically connected to the conductive path 527,528 on the printed circuit board 500 (Fig. 4 B), to constitute above-mentioned local oscillator 704.As mentioned above, owing to obtain better frequency characteristic such as the Q value from tuner apparatus, so obtained more performance from the FM wireless receiver 700 of this embodiment.
The semiconductor device 1,1 that comprises this embodiment ", 81,91 circuit arrangement is not limited to FM wireless receiver 700.For example, this circuit arrangement can be a portable receiver, i.e. cell phone etc., coil 30,30 in this portable receiver ", 830,930 as antenna to receive for example radio signal.
---being provided with and keeping the possibility of induction coefficient when mounted---
The semiconductor device 1 of this embodiment " comprising: substrate 10 "; At substrate 10 " the IC chip 20 that provides on the upside "; Spiral coil 30 ", it is formed on the surface of substrate 10 " upside towards IC chip 20 " and is electrically connected to IC chip 20 "; Coil electrode 127b ", 128b ", it " forms and is electrically connected to coil 30 " at substrate 10 on the downside; With adjustment terminal L1, L2, it is formed on substrate 10 " on the downside surface; can be electrically connected to coil electrode 127b ", 128b " and it can " external electric be connected to second coil 801,802 at semiconductor device 1, it is characterized in that: be electrically connected to the coil electrode 127b ", 128b " and second coil 801,802 by adjusting terminal L1, L2, obtain " and the inductance that is fine into of second coil 801,802 by coil 30.According to semiconductor device 1 ", for example, by when mounted or when operation correct measurement induction coefficient and by adjusting the induction coefficient of second coil 801,802, can easily eliminate skew to the inductance of setting single assembly for.Therefore, provide and to have set and to have kept the semiconductor device 1 that induction coefficient is a predetermined value when mounted ".
Preferably, above-mentioned semiconductor device 1 " also comprises dummy pattern 40 ", and it is formed on substrate 10 " on the downside with the coil 30 " facing surfaces, to be used for ballast coil 30 " the induction coefficient characteristic.Can suppress this electromagnetic interference according to semiconductor device 1 in the electronic equipment of ", " produced electromagnetic field, dummy pattern 40 so " absorb this electromagnetic field if from coil 30, therefore, semiconductor device 1 are being installed " etc.
At above-mentioned semiconductor device 1 " in, preferably, be fixed to substrate 10 by solder resist pattern 13a " with IC chip 20 " ".By this mode, because IC chip 20 " with conductive path 12a " electric insulation, the basis of this conductive path 12a " being solder resist pattern 13a " is so stablized the operation of coil 30 " and IC chip 20 ".
At above-mentioned semiconductor device 1 " in, preferably, semiconductor device 1 " also comprises and is formed on substrate 10 " a plurality of earth terminals 15 on the downside surface ", " be identical voltage to be used to keep dummy pattern 40.By keep in this mode with coil 30 " coupling mutual inductance in dummy pattern 40 " electromotive force, this coil 30 " the induction coefficient characteristic more stable.For example, the magnitude of voltage of this identical voltage depends on the voltage on the precalculated position of printed circuit board 500 (Fig. 4 B).
At above-mentioned semiconductor device 1 " in, preferably, a plurality of earth terminal 15 " ground connection.For example, if above-mentioned precalculated position ground connection, semiconductor device 1 so " fitting operation for example will be more prone at user side.
In above-mentioned semiconductor device 81, coil 830 can be made up of coil 8301 and coil 8302, and coil 8301 and coil 8302 can have the line symmetric shape with respect to the border, and this border will (substrate 810 uper side surfaces that for example the IC chip 20 ") be divided into two towards the IC chip.For example, (for example metal fine 22 "), and two (2) individual coils 8301,8302 are connected respectively to the IC chip, and (for example the IC chip 20 ") by two (2) individual IC chip designs 8121,8122 and two (2) strip metal fine rules.Therefore, when two (2) individual coils 8301,8302 are the line symmetry with respect to above-mentioned border, if form two (2) individual IC chip designs 8121,8122 and two (2) strip metal fine rules respectively, the inductance value of two (2) the individual coils 8301,8302 that comprise wiring is equated to have same structure.In this mode, because the easily encapsulation of designing semiconductor device 81 and simplified the structure of the coil 830 that comprises wiring, so therefore reduced the production cost of semiconductor device 81.
Semiconductor device 91 also can comprise dummy pattern 941, and it is present between the IC chip 920 and solder resist pattern 913a on substrate 910 upsides, is used for the induction coefficient characteristic of ballast coil 930.Because so the induced noises when having stopped operation IC chip 920 by this dummy pattern 941 etc. are can be so that the induction coefficient stability of characteristics of coil 930.
Preferably, above-mentioned semiconductor device 1 ", 81,91 also comprise: through hole, it penetrates substrate 10 ", between 810,910 upside and the downside and be electrically connected coil 30 ", 830,930 and the electrode 127b of coil ", 128b "; And mould is annotated resin 50 ", 950 ", its hermetic sealing substrate 10 ", 810,910 upside.In this so-called encapsulation, thereon on the side respectively by being electrically connected coil electrode 127b ", 128b " and adjusting terminal L1, L2, can set and keep this induction coefficient when mounted is predetermined value.
At above-mentioned semiconductor device 1 ", in 81,91, preferably, the rolling conductive foil of coil 30 " being to be fixed to substrate 10 ", 810,910 uper side surface.By this mode, for example, compare, owing to kept coil 30 with the coil that forms by plating ", 830,930 more high-purity and resistance can be controlled at littler level; therefore, semiconductor device 1 ", 81,91 induction coefficient maintains predetermined value easily.For example, compare, because the coil 30 of this embodiment ", 830,930 have more high strength and resistance can be controlled at littler level, therefore, semiconductor device 1 " with the coil that forms by plating, 81,91 induction coefficient maintains predetermined value easily.
---other embodiment---
Above embodiment of the present invention is to understand the present invention for convenience, and does not limit its explanation.Not breaking away from its spiritual scope the present invention can make various variations and change and the present invention and comprise its equivalent.
Although this semiconductor device 1 has substrate 10 (Fig. 1) in above embodiment, the present invention does not mean and is limited to this.For example, semiconductor device 1 can not have substrate 10, and conductive path 12a, 12b can directly be embedded in the mould notes resin 50.In this case, on the same surface of mould notes resin 50 1 sides, provide conductive path 12a and conductive path 12b together.Therefore, annotate at mould on the side of resin 50, seal IC chip 20 and the coil 301,302 that is electrically connected to conductive path 12a, 12b respectively each other abreast.
Although in above embodiment coil electrode 127b, 128b and adjustment terminal L1, L2 is adjacent and each interval is insulated from each other, the present invention does not mean and is limited to this, for example, coil electrode 127b, 128b and adjustment terminal L1, L2 can be not nearby.In fact, realize being electrically connected as long as wait by the line bonding at user side, coil electrode 127b, 128b and adjustment terminal L1, L2 just can have the space distance of being longer than or being shorter than above-mentioned embodiment situation, and can have another conductive path etc. in the interval betwixt.
Although with the part of coil 701,702 (Fig. 4) as second coil 801,802 (Fig. 5), the present invention does not mean and is limited to this in above embodiment.For example coil pattern can be pre-formed on printed circuit board 500.

Claims (18)

1, a kind of semiconductor device comprises;
Semiconductor chip;
First coil, it is electrically connected to semiconductor chip;
First electrode, it is electrically connected to first coil; With
Second electrode, it is electrically connected to first electrode and at second coil of the outside of this semiconductor device, with the inductance that obtains to be made up of first coil and second coil.
2, a kind of semiconductor device comprises:
Substrate;
Semiconductor chip, it is arranged on substrate one side;
First coil, it is formed on the substrate opposite side and is electrically connected to semiconductor chip by spiral-shaped;
First electrode, it is formed on the substrate opposite side and is electrically connected to first coil; With
Second electrode, it is formed on the opposite side of substrate and is electrically connected to first electrode and at second coil of the outside of this semiconductor device, with the inductance that obtains to be made up of first coil and second coil.
3, semiconductor device as claimed in claim 2 also comprises:
Conductive pattern, its be formed on the described side of substrate on the surface of semiconductor chip, be used to stablize the induction coefficient characteristic of first coil.
4, semiconductor device as claimed in claim 3, wherein semiconductor chip is fastened on the conductive pattern by insulating binder.
5, semiconductor device as claimed in claim 3, wherein conductive pattern comprises the conductor of a plurality of isolation of the reservation shape that is spaced apart from each other with predetermined gap.
6, semiconductor device as claimed in claim 5, wherein conductive pattern comprises the conductor of a plurality of isolation that rectangle is arranged, so that described predetermined gap extends linearly and intersects each other into the angle.
7, semiconductor device as claimed in claim 6, wherein semiconductor chip is a rectangle, and
The wherein said a plurality of predetermined gaps that intersect linearly are arranged to respect to semiconductor chip outward flange definition predetermined angle.
8, semiconductor device as claimed in claim 2 also comprises:
Through hole, it extends between side of substrate and opposite side and is electrically connected the semiconductor chip and first electrode; With
Insulating resin, a described side of its covered substrate.
9, semiconductor device as claimed in claim 2, wherein first coil is the rolling conductive foil that is fastened to the substrate opposite side.
10, a kind of semiconductor device comprises:
Substrate;
Semiconductor chip, it is arranged on substrate one side;
First coil, it is formed on substrate one side surface of semiconductor chip by spiral-shaped, and first coil is electrically connected to semiconductor chip;
First electrode, it is formed on the substrate opposite side surface and is electrically connected to first coil; With
Second electrode, it is formed on the opposite side surface of substrate and is electrically connected to first electrode and at second coil of the outside of this semiconductor device, with the inductance that obtains to be made up of first coil and second coil.
11, as the semiconductor device of claim 10, also comprise:
Conductive pattern, it is formed on the surface with the first coil opposing substrates opposite side, is used to stablize the induction coefficient characteristic of first coil.
12, as the semiconductor device of claim 10, wherein semiconductor chip is fastened on the substrate by insulating binder.
13, as the semiconductor device of claim 11, also comprise:
A plurality of electrodes, it is formed on the surface of substrate opposite side, and being used to keep conductive pattern is identical voltage.
14, as the semiconductor device of claim 13, wherein a plurality of electrode groundings.
15, as the semiconductor device of claim 10,
Wherein first coil form by tertiary coil and the 4th coil and
Wherein with respect to the border that will be divided into two towards the substrate surface of semiconductor chip, tertiary coil and the 4th coil have the line symmetric shape.
16, as the semiconductor device of claim 11, also comprise:
The additional conductive pattern, it is inserted between the semiconductor chip and insulating binder on substrate one side, is used to stablize the induction coefficient characteristic of first coil.
17, as the semiconductor device of claim 11, also comprise:
Through hole, it extends between side of substrate and opposite side and is electrically connected first coil and first electrode; With
Insulating resin, a described side of its covered substrate.
18, as the semiconductor device of claim 11, wherein first coil is the rolling conductive foil that is fastened to a described side surface of substrate.
CNB2006101214094A 2005-01-24 2006-01-24 Semiconductor device Expired - Fee Related CN100530620C (en)

Applications Claiming Priority (3)

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TWI515843B (en) * 2013-12-16 2016-01-01 南茂科技股份有限公司 Chip package structure

Citations (4)

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Publication number Priority date Publication date Assignee Title
CN1163511A (en) * 1996-01-22 1997-10-29 艾利森电话股份有限公司 Balance integrated semiconductor device worked with parallel resonant circuit
CN1239607A (en) * 1996-12-18 1999-12-22 爱华株式会社 Radio receiver, radio receiving method, and audio transmitter
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6388636B1 (en) * 2000-02-24 2002-05-14 The Goodyear Tire & Rubber Company Circuit module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1163511A (en) * 1996-01-22 1997-10-29 艾利森电话股份有限公司 Balance integrated semiconductor device worked with parallel resonant circuit
CN1239607A (en) * 1996-12-18 1999-12-22 爱华株式会社 Radio receiver, radio receiving method, and audio transmitter
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6388636B1 (en) * 2000-02-24 2002-05-14 The Goodyear Tire & Rubber Company Circuit module

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