CN100524521C - Method and integrated circuit for operating fixed hydrocarbon memory device - Google Patents
Method and integrated circuit for operating fixed hydrocarbon memory device Download PDFInfo
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- CN100524521C CN100524521C CNB200510077895XA CN200510077895A CN100524521C CN 100524521 C CN100524521 C CN 100524521C CN B200510077895X A CNB200510077895X A CN B200510077895XA CN 200510077895 A CN200510077895 A CN 200510077895A CN 100524521 C CN100524521 C CN 100524521C
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
- G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
Abstract
A method for operating an integrated circuit memory device includes applying a verify procedure in which the page of data and one or more bits from a set of replacement cells are matched with a pattern in parallel to indicate a verify result, where the page of data is ''unrepaired'' and may include one or more bits from defective bit lines. While matching to indicate a verify result, the one or more bits from defective bit lines in the page are masked. Flash memory and other memory devices implement the method.
Description
Related application
The application requires the U.S. Provisional Application of application on June 14th, 2004: No.60/579,359 benefit of priority.
Technical field
The present invention relates to a kind of storage component part.More specifically, the present invention relates to a kind of non-volatile memory device with a paging read operation.
Background technology
Non-volatile memory device generally comprises memory array, and it comprises memory cell, though with electric power when its device removes, still can keep data.Non-volatile memory device has the numerous species type.Wherein one type comprises so-called " ROM (read-only memory) ", mask-type ROM for example, by means of by the channel part that impurity is poured into MOS transistor, with data storing in memory cell.Be stored in the data in mask-type MOS device and other non-volatile ROM device, can not directly change.The non-volatile memory device of another kind of type comprises can electrically wipe and the memory cell (for example flash memory) of programmable.Be stored in flash cell and other non-volatile can electrically wipe and the memory cell of programmable in data, can use the electronic program and the program of wiping directly to change.Representational flash memory technology comprises: floating grid formula memory cell and charge trap formula memory cell, for example SONOS, NROM, PHINE and fellow thereof.
In flash memory, many kinds are arranged in order to the sequencing and the biasing procedure of wiping memory cell.The biasing procedure of floating grid formula memory cell and charge trap formula memory cell causes electronics and/or hole to wear tunnel and passes in and out floating type grid or charge trap structure.Concentration of electric charges in floating type grid or charge trap structure can influence the threshold voltage of memory cell.Therefore,, can set the threshold voltage of memory cell by means of by the electric weight in floating type grid of control or the charge trap structure, and storage data.
Based on the memory cell feature, apply voltage, and array in the variation of other parameter, in flash memory, in order to the biasing procedure of sequencing and erase operation, the quantity of electric charge that can cause being stored in each unit is distributed in the array unevenly.Therefore, the applied biasing procedure of many devices comprises a series of sequencing or erasing pulse, has the operation of affirmation between interpulse or each group pulse at each.General affirmation program comprises the driving word line voltage to program validation or erase-verifying level, and it reads level with general standard, and some is different, program to be provided or to wipe the border.Then, from the data of memory cell one-time detection one a bit group or a character, determine the whether successful sequencing or wipe of each unit.If confirm procedure failure, then repeated application retry procedure or erasing pulse is up to reaching a maximum constraints of successfully confirming, or reach number of retries.
At the flash memory of many types, the program of wiping is once carried out relatively large memory cell section.In some device, the program of wiping comprises does a preceding procedure operation to whole section, then whole section is made an erase operation, and then whole section is done so-called soft procedure operation.In some situation, confirm to operate and also after soft routine processes, carry out.Relevant have affirmation wipe and information that procedure operation is relevant can be at U.S. Patent number 6,496, find in 417 and 5,912,845.The affirmation action need of these type of device is confirmed characters all in section with an order.This confirms that operation is quite time-consuming, and occupies the most bulk erase time of device.
Based on to access time faster,, developed and that paging is read and flash memory is read in pulse in conjunction with the demand of the flash memory of large-scale, high density arrays.In general flash memory, read operation word for word unit is carried out, and makes in a special time, for example after address translation, (for example 100ns is to the TAA of 70ms) or behind a chip start signal (TCE), only the character of addressing one 16 bits, detect its content and data output thereof.In the paging mode device, the export structure of array is set so that the not only function of a character of an addressing to be provided, for example at TAA or TCE in the time, and four characters of addressing (64 bit) or more.The data of multiword metapage, and are stored in detecting amplifier or the page buffer from array detection with parallel mode.Be stored in the data in detecting amplifier or the page buffer, can read by pulse mode, or with very short cycle length, read and directly be not subject to the TAA or the TCE time of flash array.
In order further to improve the operating speed of flush memory device, developed a kind ofly except paging is read, also support the paging mode flush memory device of paging programization.For with the paging programization in the array, a page buffer can be written into the data for the treatment of sequencing, by means of by data jump to the bit in the page buffer is latched, and each bit line of Data Control in latching with corresponding bit, and then with this paging programization.The affirmation program of paging mode program is in a parallel work-flow, and the bit that can comprise successful sequencing in the automatic removing page buffer latchs.Be stored in the page buffer data then by turn tuple read, remove all to confirm all bits, to represent a successful paging program operation.With reference to the U.S. Patent number 5,835,414 that Hung invented; And the U.S. Patent number 5,638,326 that Hollmer invented.In the patent of aforementioned Hung, data are detected and store in page buffer, and then (with all be one and all be zero pattern relatively) use a match circuit to judge that its match circuit produces a signal
(ALBRES1), representing that all bits in the page buffer when latch is reset.By means of by the determining step in the deletion affirmation program, need a then demand that reads each tuple that the bit that is stored in the paging mode detecting amplifier or is stored in page buffer latchs, this program can significantly reduce the speed of authentication operation.
Yet along with the increase of memory array size, the defectiveness probability in the array also increases thereupon.A kind of redundancy in order to solve the problem of defectiveness possibility, to develop.According to general redundancy, comprise the detecting amplifier of one group of redundancy in the integrated circuit (IC)-components.When finding a defectiveness unit in main array, the replacement unit in the redundant array can be in order to replace.In the operating period of device, positioning signal and outgoing route can be sent again, replace the unit with automatic access.The background context data please refer to U.S. Patent number 6,065,090 that Deas invents and the U.S. Patent number 6,643,794 that Utsugi invented.Replace newly sending of unit and can confirm that operation produces difficulty paging mode.Particularly, when paging mode detecting amplifier in confirming operation and array or page buffer coupling, the result that will not replace in the unit is delivered to paging mode detecting amplifier or page buffer again, can't obtain correct result.This sends the temporal characteristics or the high-effect unallowable time of device of the detecting operation that can change several nanoseconds again.Another kind method after using an output multiplexer repair data and choosing output, is carried out the affirmation operation of paging mode device in word for word first mode.Replace unit output and can be mapped to output multiplexer more simply, and can not have a strong impact on the time of detecting operation.Yet, in the case, confirm that the determining step of operation can't be indebted to the paging mode operation, reduce the global procedures of this device on the contrary and wipe feature.
Therefore, what need provides a kind of paging mode memory construction, at support program and when wiping program, also can support redundancy and confirm operation at a high speed.
Summary of the invention
The method of operation integrated circuit memory devices described herein, comprise the affirmation program of application, wherein data page and one group are replaced the one or more bits in the unit, a meeting and a pattern PARALLEL MATCHING, to represent that one confirms the result, wherein this data page is " not repairing ", and can include the one or more bits in the defective bit line.With when representing an affirmation result, shield one or more bit of defectiveness bit line in the paging in coupling.Thus, the bit of replacing in the unit need not be delivered to the circuit of operating matching operation.Confirm that therefore operation can be indebted to the advantage that paging mode detects, and improves the global procedures and the erasing speed of its device.
Various embodiments of the present invention be included in sequencing wipe a section of a paging or memory cell or a memory array in use a biasing procedure; Data page in the parallel detection paging, or the section of a plurality of bit lines in the memory array, and one group of one or more bit of replacing in the unit, one or more bit line system in wherein a plurality of bit lines is labeled as defectiveness; And, confirm the result to represent one, and shielding simultaneously is labeled as the data of defective one or more bit line with data page and one or more bit and a pattern PARALLEL MATCHING.In each embodiment of this method, pattern can be changed.For example, all be that one pattern can be applicable to a preceding procedure operation, all be that a pattern of zero can be applicable to an erase operation, and another pattern can be applicable to a procedure operation.
Comprise a flush memory device of future prefaceization at a program of wiping, various embodiments of the present invention provide program and erase operation before the section.In program and the erase operation, a program can be carried out as follows before section:
Each unit in the section of array, and in one group of one or more unit of replacing in the unit, program bias voltage before using is with program pattern before the section program being turned to;
A word line and this group by means of the existing page or leaf in section are replaced in one or more unit of unit, apply a program validation bias voltage, with each page in the sequencing section, and then program pattern before the affirmation section, and if confirm that the result represents to have a coupling that is complementary with preceding program pattern, then proceed to down one page, all pagings in section are by confirming, and if confirm that the result does not represent to have a coupling with existing page or leaf, then retry applies the step of program bias voltage, before descending one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure;
If preceding program changes into merit, then in the unit of the section of array, and in one group of one or more unit of replacing in the unit, apply and wipe bias voltage, so that being turned to one, the section program wipes pattern; And by means of in a word line of the existing page or leaf of one in the section and the one group of one or more unit of replacing the unit, apply an erase-verifying bias voltage, with each page in the sequencing section, and then the affirmation section is wiped pattern, and if the affirmation result represents to have and wipes the coupling that pattern is complementary, then proceed to down one page, all pagings in section are by confirming, and if confirm that the result does not represent to have a coupling with existing page or leaf, then retry applies the step of wiping bias voltage, before descending one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure.
Each embodiment comprises a character programming operations, and according to a selected character of using in a biasing procedure sequencing one paging, and pattern comprises the data for the treatment of sequencing.For bit group or character model programization, program comprises shielding is arranged in selected bits tuple or character paging in addition during mating data.
Various embodiments of the present invention comprise integrated circuit, and it comprises one chip embodiment, and one chip comprises a memory cell array (for example floating dam unit or charge trap unit).The present invention comprises one group and replaces the unit, and it is configured to provide the replacement of defectiveness memory cell in the array.Testing circuit is from array parallel detection one data page, and replaces the unit from one group and detect one or more bit, and its testing circuit is that array and this group are replaced the unit coupling therewith.Match circuit and testing circuit coupling.Match circuit is parallel determines that whether one or more bit that bit replaces the unit in conjunction with this group do not repaired in the paging is complementary with a pattern (all be one or all be zero).When this coupling of operation, the bit line that the defectiveness unit is coupled in match circuit shielding and the array.Various embodiments of the present invention can change be used to wipe, preceding program, and the employed pattern of match circuit of procedure operation.Testing circuit can use the page buffer of testing oneself, page buffer to combine with detecting amplifier or respectively organize the real work of detecting amplifier of parallel arranged, one-time detection one paging.General embodiment also comprise in the array of controls read, program, and the logic of the execution of erase operation.In certain embodiments, program and erase operation before erase operation comprises are as above-mentioned.
At each bit in the paging, each embodiment of match circuit described herein, comprise bit line that expression detected from a corresponding data bit element whether a bit of defective logic, this data bit element of comparison and pattern with the logic that produces a comparative result and if corresponding bit line defectiveness then forces comparative result to represent the logic of a coupling.Each embodiment of match circuit is an interior selected bits tuple or the character of support programization one paging also, and it comprises the logic of forcing the comparative result that is positioned at selected bits tuple or character bit in addition to represent a coupling.
Each embodiment of integrated circuit also comprises an output multiplexer, and itself and testing circuit are coupled, and its output multiplexer is selected character from paging, and replaces from the detected bit of defectiveness bit line with one group of replacement bit of replacing the unit, exports for multiplexer.
Therefore, technology described herein can be used not repair data, and the bit of the replacement unit in array is not replaced in the array in the defectiveness bit line before the bit as yet, does to confirm operation earlier.This technology significantly reduces the required time of erase operation of flash memory integrated circuit, and also helpful to the usefulness of improving integrated circuit memory devices.
Other purpose of the present invention and advantage can be followed accompanying drawing and understand, and details are as follows for the present invention and patent claim.
Description of drawings
Fig. 1 is the calcspar that an integrated circuit comprises the paging match circuit of not repairing paging;
Fig. 2 does not repair the shielding of bit and the circuit diagram of comparator circuit in one memory array;
Fig. 3 is a circuit diagram of replacing a comparator circuit of the replacement bit that detects the unit from one group;
Fig. 4 be according to the circuit of Fig. 2 and Fig. 3 represent a line or (wired.OR) circuit confirm result's circuit diagram for output one:
Fig. 5 is a calcspar of repairing the output multiplexer of character in a paging mode storage component part;
Fig. 6 is that a section of paging mode storage component part is wiped the process flow diagram that the paging matching result is not repaired in its utilization of program;
Fig. 7 is the preceding program of a section of a paging mode storage component part and wipes the process flow diagram that the paging matching result is not repaired in its utilization of program.
The main devices symbol description
9 storage component parts, 10 flash arrays
11 column decoders, 12 Y select demoder
13 detecting amplifiers 14 are not repaired the paging match circuit
15 data multiplexers are replaced the unit for 16 1 groups
18 1 groups of redundancy detection amplifiers of 17 redundant decoders
19 data input/output bus, 20 addressing circuit
21 state machines 22 read/wipe/the program supplying circuit
102 mutual exclusions of 101 multiplexers or door
103,106 Sheffer stroke gates, 104,105 nodes
107 transistors, 110 p type channel transistors
111-117 transistor 118 lines
152 mutual exclusions of 151 multiplexers or door
153 phase inverters, 154 phase inverters
155 rejection gates, 156 n type channel transistors
157 line 160-163 transistors
164 nodes, 165 P transistor npn npns
200-202 multiplexer 203-205 replaces multiplexer
The 206-208 Sheffer stroke gate
Embodiment
Fig. 1-7 describes various embodiments of the present invention in detail.
" bit line " speech at this indication, mean the conductor that the row in array extend, array is an employed array during this row access memory unit, and " data line " speech is often referred to the line of other type of a bit line and load data, for example the line in the output of detecting amplifier, column selection line and data multiplexer.When the use bit line was unstable from the detected data of memory cell, bit line was defective.In the general memory device, comprise the redundant array of replacing the unit, by means of the address is stored on the chip, be defective expression symbol as the bit line of representing institute's identification, so that bit line is labeled as defectiveness.In response to stored address, attempt to use defectiveness bit access memory unit person, can be transferred to redundant array.
Fig. 1 is the simplification calcspar of an one chip, and integrated circuit memory devices 9 is supported memory redundancy and paging mode operation.Storage component part 9 comprises flash array 10, and it comprises memory cell array, forms a plurality of sections usually, and can use a plurality of bit lines and a plurality of word line to come access.Column decoder 11 is in order to the access selected word line.Y selects demoder 12 in order to the selected bit line of access.A plurality of detecting amplifiers 13 or other testing circuit are selected the output and the data line coupling of demoder 12 from Y, and are arranged with the parallel detection data page.In this demonstration example, data page comprises 64 bits, corresponds to four characters, and each character comprises two bit groups, and totally 8 bits are wide.The data that comprise greater number in every page of other embodiment, for example, every page comprises 512 bits or more.Detecting amplifier 13 uses a page buffer or other memory construction, will keep in the data that a read cycle is read.The output of detecting amplifier 13 can be applied to " not repairing " paging match circuit 14, and details are as follows, and be applied to a data multiplexer 15.Data multiplexer 15 is repaired character with one, as output, so that data input/output bus 19 to be provided.
Memory redundancy is held on the storage component part 9 by resource fork, and described resource comprises one group and replaces unit 16, selects its redundant decoder 17 of replacing the unit and one group of redundancy detection amplifier 18 or supply other testing circuit temporary and result that output is detected from selected replacement unit.The output of redundancy detection amplifier 18 can be applied in " not repairing " paging match circuit 14, as detailed below, and is applied in data multiplexer 15.Data multiplexer 15 is replaced from the detected bit of defectiveness bit line to replace the detected bit in unit from one group.
Paging mode reads, wipes, reaches a state machine 21 of procedure operation, is contained in the integrated circuit.For the status of support machine, the Circuits System in the circuit can produce and control and read, wipe, reach the supply circuit 22 of procedure operation.State machine comprises processor, carries out the combination of indication, exclusive logic or a processor and exclusive logic.
Do not repair paging match circuit 14 and be configured to the output of the output of detecting amplifier 13 and redundancy detection amplifier 18 and a pattern (for example all be zero and/or all be one) are made comparisons, and shielding is from the detected data of defectiveness bit line.Using such method is used combining of repair data page or leaf not and the output of replacing the unit, produces one and confirms the result.Confirm that the result can be applied to state machine 21, and in order to control program and erase operation.The not operation of not repairing paging match circuit 14 in the repair data page or leaf can contrast (the available output of the data multiplexer 15 among the embodiment for example) with other match circuit operation after using the replacement unit to repair output data.
The match circuit of a corresponding bit line in Fig. 2 display-memory array.From a corresponding bit line, be denoted as SO[i] data, be applied to the data line output of the detecting amplifier in one group of detecting amplifier, as mutual exclusion or door (exclusive-OR gate)) 102 first input.Pattern data is applied to second input of mutual exclusion or door 102 from the output of multiplexer 101.The input of multiplexer comprises VFYBIT and DATAPGM[i], its VFBIT uses for the affirmation erase operation, and DATAPGM[i] for confirming the procedure operation use.Control signal PGMVFY is in order to control multiplexer 101.With erase operation, at all bits in the paging, VFYBIT is zero.Procedure operation in the past is at all bits in the paging, DATAPGM[i] all be one.With bit or from metaprogram operation, in all selected bits and the character, DATAPGM[i] pattern that is provided equals to treat the data of sequencing.First input as Sheffer stroke gate (NAND-gate) 103 is used in the output of mutual exclusion or door 102.Second input of Sheffer stroke gate 103 is from replacing the node 104 of unit, as detailed below.The output of Sheffer stroke gate 103 is applied as first output of rejection gate (NOR-gate) 105.Second input of rejection gate 105 is from the output of Sheffer stroke gate 106.The input of Sheffer stroke gate 106 comprises address bit PAGEIADDR0 and PAGEIADDR1, in order to be chosen in one of four characters in employed four the character pages or leaves of this embodiment.In another embodiment, output can be selected or select in other paging section boundaries of data in the tuple on the throne border.The output of rejection gate 105 is applied to a matching result of n channel transistor 107 grids.The source ground of transistor 107.The drain electrode of transistor 107 can be received line 118, and provides comparative result to a line or circuit (wired-OR circuit), as described in the 4th figure.Node 104 is driven by p type channel transistor 110 and n type channel transistor 111-117, and both are connected between supply circuit VDD and the ground connection with series system.Transistor 110 has the grid of ground connection, and as the pull-up device (pull-updevice) between node 104 and supply current potential.Transistor 111-117 connects with series system between node 104 and ground connection, and operates with one or seven inputs and the mode of door (AND gate).The input of transistor 111-117 comprises I/O message address IO0-IO3, the I/O message address is selected one of 16 bit lines in a character, be used for replacement, reparation address bit RADo and RAD1, replace, repair the address bit and in four group of 16 bit line of four character pages or leaves, select one to do replacement, reach the redundant bit REDEN that starts.When defectiveness bit line of address coupling, REDEN is produced by address circuit.Therefore, the corresponding SO[i of the signal indication on the node 104] bit line defectiveness whether.When the signal on the line 104 was low, then the output of Sheffer stroke gate 103 can be forced to improve, and the signal on the lock of transistor 107: Da[i] can be forced to reduce, with the output of shielding pattern match circuit.
In paging mode operating period, paging home address bit PAGEIADDR0 and PAGEIADDR1 can be forced to improve, and make the output of Sheffer stroke gate 106 to reduce, and can not shield its result.During the character border, paging home address bit PAGEIADDR0 and PAGEIADDR1 represent a page interior selected character in a procedure operation.At the bit beyond the selected character, the output of Sheffer stroke gate 106 is forced to improve, and causes shielding the output of comparative result.About selected character, the output of Sheffer stroke gate 106 is low.Therefore, paging mode operation and character border or other paging sections, procedure operation all can be used identical match circuit.
One group of match circuit of replacing the corresponding bit line in the unit in Fig. 3 display-memory array.From a corresponding unit of replacing, be labeled as the data of RSO, be the data line output that is applied to the redundancy detection amplifier in one group of redundancy detection amplifier, as first input of mutual exclusion or door 152.Pattern data is applied to second input of mutual exclusion or door 152 from the output of multiplexer 151.The input of multiplexer comprises VFYBIT and DATAPGM[i], its VFYBIT is in order to the affirmation erase operation, and its DATAPGM[i] in order to confirm procedure operation.Control signal.PGMVFY is used for controlling multiplexer 151.With erase operation, at all bits in the paging, VFYBIT is zero.Procedure operation in the past, at all bits in the paging, VFYBIT is one.With bit group or character procedure operation, in all selected bits tuples and the character, DATAPGM[i] pattern that provided, equal in selected bits tuple and character, to treat the data of sequencing.The output of mutual exclusion or door 152 is as the input of phase inverter 153.The output of phase inverter 153 is as first input of rejection gate 155.Second input of rejection gate 155 is the output of phase inverter 154.The input REDEN bit of phase inverter 154.The output of rejection gate 155 is matching result signals, is applied to the grid of n type channel transistor 156.The source ground of transistor 156.The drain electrode of transistor 156 is applied on the line 157, and provides comparative result to line or circuit, as described in the 4th figure.Therefore, the circuit among Fig. 3 provides a comparative result to replacing the unit according to the comparative result of not repairing in the paging that output provided of circuit shown in Figure 2.
One embodiment of Fig. 4 display circuit, the output of the match circuit that its displayed map 2 and Fig. 3 are shown is with a line or mode combination.The match circuit of Fig. 3 provides a pattern matching result DA[i], have in the paging of n+1 bit one, its index is to n from 0.A pattern matching result RDA of bit is replaced in the match circuit output one of Fig. 3.This pattern matching result DA " i ", its index are from 0 to n, and RDA is applied to corresponding n type channel transistor 160-163.The source ground of transistor 160-163.The drain electrode of transistor 160-163 is with a line or mode and node 164 couplings.P transistor npn npn 165 with its grounded-grid and source-coupled current potential thereof pressure and its drain coupled node 164 is as a pull-up device.If any pattern matching result DA[i], its index is from 0 to n, and RDA is high, and then the PASS signal on the line 164 can be dragged down.The PASS signal application is in state machine, and control utilization is confirmed result's program or erase operation.Therefore, the PASS signal, before being repaired as paging in the data that comprise a defectiveness bit line, a paging confirmation signal that is produced.This PASS signal can be used for program and erase operation, reducing required affirmation number of iterations, and accelerates the speed of paging mode operation.
Fig. 5 video data multiplexer circuit is repaired data of not repairing in the page or leaf with the output of replacing the unit, is applicable to the integrated circuit of first figure.For the paging of one 64 bits, the detecting amplifier circuit comprises the output of 64 detecting amplifiers and is being denoted as SO[0] to SO[63] data line on.Four detecting amplifier output＜SO[0 of 16 groups]-SO[3], SO[4]-SO[7] ..., SO[60]-SO[63] be applied to corresponding multiplexer 200,201,202.Multiplexer 200,201,202 is by paging home address bit: PAGEIADDR0 and PAGEIADDR1 are controlled, and select one of four detecting amplifiers outputs, with the replacement multiplexer 203,204,205 that exports a correspondence to.Replacing second input of multiplexer 203,204,205, is the output RSO of a redundancy detection amplifier, in order to replace a bit of defectiveness bit line in the array.Replacing multiplexer 203,204,205 is controlled by the signal of the output of the Sheffer stroke gate 206,207,208 of correspondence.The input of Sheffer stroke gate 206,207,208 comprises redundant bit REDEN of startup and address signal 100-103.Sheffer stroke gate is in 16 replacement multiplexers, can use of replacement bit of RSO to decode.Therefore, the input of Sheffer stroke gate 206 comprises IO0B, IO1B, IO2B, and IO3B, when IO0-IO3 be＜0000 the time, start the selection of RSO by multiplexer 203.Therefore, the input of Sheffer stroke gate 207 comprises IO0B, IO1B, IO2B, reaches IO3B, when IO0-IO3 system＜1000〉time, the selection of RSO started by multiplexer 203.The input of Sheffer stroke gate 208 comprises IO0B, IO1B, IO2B, and IO3B, when IO0-IO3 be＜1111 the time, start the selection of RSO by multiplexer 205, be supplied as DOUT[15].Therefore, do not repair 64 bit page or leaf SO[i] as the input of data multiplexer, and 16 bit characters selected, that repair are output.
Fig. 6 is the process flow diagram of a section erase operation, represents paging mode to confirm the deviation program of operation, is implemented by other logical circuit shown in the shown integrated circuit memory of state machine or Fig. 1.The section erase operation starts from square 600 with a section erasing instruction.Setting a retries count value is zero (square 601).Use being fit to one of memory cell in the array wipes bias voltage and arranges section (square 602) so far.After wipe bias voltage and repair, one confirms that operation starts from page address (square 603) at the beginning.The word line of beginning page address is set in an erase-verifying voltage level, and detects " not repairing " data page.When detecting not the repair data page or leaf, also detect the defectiveness bit line (square 604) of the output of replacing the unit.Then, the result is confirmed in test.In this example, confirm that it all is zero pattern that the result seeks in not repairing paging and replacement unit, and the bit (square 605) of shielding from the detected paging of a defectiveness bit line.If confirm that the result is for being that then algorithm determines whether to have confirmed finally to divide page address (square 606) in section.If confirm finally to divide page address, then to represent among the embodiment at this, algorithm proceeds to a soft procedure operation (square 611).If at square 606, last minute still unconfirmed page address then divides page address to increase progressively (square 607) with a paging size, and algorithm is got back to square 604 to confirm one page down.If detecting the affirmation result in square 605 is that then algorithm branch does not determine whether retries count value equals a maximum retry parameter (square 608).If do not reach maximum retry parameter as yet, then increase progressively this counting (square 609), and algorithm gets back to square 602, the bias voltage of wiping of this section of retry is arranged.If reach maximum retry parameter in square 608, then expression failure (square 610).Therefore, this program provides paging mode to confirm operation, replaces tuple or word for word the carrying out of tuple by turn in the mode of paging size.Significantly accelerate a section and wiped the speed of program.
In certain embodiments, before section is wiped, can carry out a preceding procedure operation earlier.Preceding procedure operation also is indebted to paging mode and confirms operation.Fig. 7 shows a representational preceding procedure operation.Program begins (step 700) after operating in a section erasing instruction before the section.Setting a retries count value is zero (step 701).Using a program bias voltage that is fit to memory cell in the array arranges to section (square 702).After repairing from the program bias voltage, one confirms to operate at the beginning, and page address begins (square 703).The word line of beginning page address is to be set in a program validation voltage level, and detects " not repairing " data page.When detecting not the repair data page or leaf, also detect the defectiveness bit line (square 704) of the output of replacing the unit.Then, the result is confirmed in test.In this example, confirm that the result is not repairing paging and replacing in the unit, searching all is one pattern, shields the bit (square 705) from the detected paging of a defectiveness bit line simultaneously.If confirm that the result is for being that then algorithm determines whether to have confirmed finally to divide page address (square 706) in section.If confirm finally to divide page address, then algorithm proceeds to a section erase operation, shown in the 6th figure (square 711).If at square 706, final minute still unconfirmed page address then divides page address to increase progressively (square 707) with a paging size, and algorithm gets back to square 704, to confirm one page down.If confirm that in square 705 result is that then algorithm branch does not determine whether retries count value equals a maximum retry parameter (square 708).If do not reach maximum retry parameter as yet, then increase progressively this counting (square 709), and algorithm is got back to square 702, the preceding program bias voltage arrangement of this section of retry.If reach maximum retry parameter in square 708, then expression failure (square 710).Therefore, this program provides paging mode to confirm operation, with the mode of paging size replace by turn tuple or word for word tuple carry out.This confirms program page by page, use not repair data page or leaf, has significantly accelerated program before the section and has wiped the speed of program.
The invention provides a flash memory, it has the erase operation time that shortens.Among the embodiment described herein, a flash memory comprises nonvolatile storage location, and with the arrayed of a plurality of sections, each section support is read simultaneously, and confirms according to repair data page or leaf not.Above-mentioned paging comprises 64 bits.As above-mentioned, other embodiment comprise the paging of more or less bit, do parallel detection, and comprise a not only character.
Compare with the mode of word for word unit's affirmation, program validation, erase-verifying and soft program validation were the original required time of 1/N before the paging of flash memory was confirmed to shorten, and wherein N is the counting of character in the paging.Therefore total erasing time greatly improves, especially for large-scale minute page operations.One simplifies potential the saving time that computing shows that paging mode affirmation described here is provided.Generally speaking, the erasing time=preceding program time+preceding program acknowledging time+erasing time+erase-verifying time+soft program time+retry time.In some situation, also can need the soft program validation time.
Lifting an example that room for improvement still arranged, suppose the mode that has now, is that the retry of program before the retry of soft program, 10ms of the wiping of preceding program, 150ms, 192ms with 110ms, 10ms is wiped and made dispositions.The character pattern erase-verifying time, a character can spend 200ns.Suppose to wipe a section, the 32k character is arranged in the section.
If do not have retry operation to produce in each stage, then total acknowledging time can be 13.2ms (each section has the preceding program validation of 6.5ms, the erase-verifying of 6.5ms), is total up to 2.7% (110+150+192+13.2) in whole erasing time.If chip is supported the preceding program and the erase feature of many sections at one time, then acknowledging time may be more of a specified duration, suppose to make 4 sections simultaneously, then confirm to send out 5% (the affirmation time of 4*13.2=52.8ms, the total erasing time of 110+150+192+52.8=1080.8) of expense T.T..But if carry out retry, then can need extra program validation and erase-verifying program, and processing needs the extra time.
Nowadays, described hereinly do not repair paging and confirm that its erasing time is shorter.Confirm that function occupies less ratio in whole flow process.In the example of Fig. 1, it supports the affirmation of four characters simultaneously, supposes above-mentioned time parameter, and a section confirms that operation only needs affirmation time of one of four minutes, or 3.3ms, if there is not retry operation to take place, only takies about 0.6% of the erasing time.When retry takes place, also can improve efficient.
In above-mentioned calculating, for there not being the erase operation of retry, efficient has tangible improvement.In retry period, improvement doubles.Supporting one to suspend in the paging mode or pulse mode flush memory device of reopening function, doubling that paging mode is confirmed and can be had a significant effect because confirm the chance of operation.For example, in the application of some flash memory, a client can wipe stage issue pause instruction one, with other block reading of data from flash chip.After pause function was finished, issue one instruction that restarts was to continue erase feature.Generally speaking, in order to support this function, the internal state machine restarts to wipe (if at preceding program halt, then restart in preceding program, if suspend in the stage of wiping, then restart in the erase-verifying stage) at the stage of recognition.In the case, have the efficient that the multi session of a large amount of time-outs/reopening instruction is wiped, may be significantly improved.For example, 1000 time-out/reopening instructions can be issued during one 4 sections are wiped processing, cause 1000 extra affirmation operations.In these situations, paging mode affirmation operation described herein can be saved a lot of times.
Though example embodiment of the present invention is described at this companion's accompanying drawing, what need know is, the present invention is not limited to these demonstration example accurately, and many other modification and retouching when can realizing by those of ordinary skills, and do not depart from scope of the present invention and spirit.
Claims (28)
1, a kind of integrated circuit comprises:
Memory cell array comprises a plurality of bit lines and a plurality of word line:
Replace the unit, be configured to the replacement that defectiveness memory cell in the described array is provided for one group;
Testing circuit, parallel detection one data page from this array, wherein one page comprises a plurality of bits, and this testing circuit is replaced the one or more bits of detection the unit from this group; And
Match circuit, with this testing circuit coupling, this match circuit determines that these one or more bits and a pattern that this data page and this group are replaced in the unit are complementary, this match circuit comprises a shielding and a comparator circuit, in order to the data in the shielding defectiveness bit line.
2, circuit according to claim 1, wherein, this testing circuit comprises a page buffer, is arranged with this data page of parallel detection from described a plurality of bit lines.
3, circuit according to claim 1, wherein, this testing circuit comprises one group of detecting amplifier, is arranged with this data page of parallel detection from these a plurality of bit lines.
4, circuit according to claim 1, wherein, employed this pattern is changeable in this match circuit.
5, circuit according to claim 1, wherein, this match circuit comprises and is used for this pattern all is set at one and all be set at zero circuit with program before confirming and erase operation.
6, circuit according to claim 1, wherein, this pattern comprises the data for the treatment of sequencing, and match circuit comprise the procedure operation that is used for carrying out a paging section with shielding at the circuit of the bit in this paging section at this data page not during the program validation.
7, circuit according to claim 1, wherein this match circuit comprises a corresponding group of shielding and comparator circuit, this shielding and comparator circuit and the coupling of data line separately, this shielding and comparator circuit comprise respectively:
Be illustrated in this array whether defective logical circuit of a corresponding bit line;
Bit in this data page is compared to produce the logical circuit of a comparative result with the bit in this pattern; And
If during this correspondence bit line defectiveness, this comparative result is a coupling, and force the logical circuit of this comparative result of expression.
8, circuit according to claim 1, wherein this match circuit comprises a corresponding group of shielding and comparator circuit, this shielding and comparator circuit and the coupling of data line separately, this shielding and comparator circuit comprise respectively:
Be illustrated in whether a corresponding bit line is defective logical circuit in this array;
Bit in this data page is compared to produce the logical circuit of a comparative result with a bit of this pattern; And
If during this correspondence bit line defectiveness, this comparative result is a coupling, and forces this comparative result of expression, and in this page during the procedure operation of a selected paging section, if this correspondence bit is not then represented the logical circuit of a coupling in this selected paging section.
9, circuit according to claim 1, wherein this match circuit be with this array in one group of data line coupling in the data page, and this match circuit comprises correspondence one set of shield and the comparator circuit of the corresponding data line that is coupled, this shielding and comparator circuit have the output of arranging with a line or mode, to export a matching result.
10, circuit according to claim 1, it comprises the logical circuit of carrying out a section procedure operation, and it comprises:
In the unit of a section of this array and should group replace in one or more unit in unit, apply the program bias voltage, so that this section program is turned to a program pattern; And
A word line and this group by means of the existing page or leaf in this section are replaced in this one or more unit of unit, apply one and confirm bias voltage, with each page in this section of sequencing, and then confirm this section program pattern, and if this match circuit represents to have a coupling that is complementary with this program pattern, then proceed to down one page, all pagings in section are by confirming, and if this match circuit is not represented and should be had a coupling by existing page or leaf, then retry applies this step of program bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure.
11, circuit according to claim 1, it comprises the logical circuit of carrying out a section erase operation, and this logical circuit comprises:
In the unit of the section in this array and in one or more unit in this group replacement unit, apply and wipe bias voltage, wipe pattern so that this section program is turned to one;
A word line and this group by means of the existing page or leaf in this section are replaced in this one or more unit of unit, apply one and confirm bias voltage, with each page in this section of sequencing, and then confirm that this section wipes pattern, and if this match circuit is represented to have with this and is wiped the coupling that pattern is complementary, then proceed to down one page, all pagings in this section are by confirming, and if this match circuit is not represented and should be had a coupling by existing page or leaf, then retry applies this step of wiping bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure.
12, circuit according to claim 1, it comprises the logical circuit of carrying out a section erase operation, and this logical circuit comprises:
In the unit of the section in this array and should group replace in one or more unit in the unit, program bias voltage before applying is with program pattern before this section program being turned to;
A word line and this group by means of the existing page or leaf in this section are replaced in this one or more unit of unit, apply one and confirm bias voltage, with each page in this section of sequencing, and then confirm program pattern before this section, and if this match circuit is represented to have and is somebody's turn to do the coupling that preceding program pattern is complementary, then proceed to one page, all pagings in this section are by confirming, and if this match circuit is not represented and should be had a coupling by existing page or leaf, then retry applies this step of program bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure;
If preceding program changes into merit, then in the unit of a section of this array, and should group replace in one or more unit in unit group, apply and wipe bias voltage, so that being turned to one, this section program wipes pattern; And
A word line and this group by means of the existing page or leaf in this section are replaced in this one or more unit of unit, apply one and confirm bias voltage, with each page in this section of sequencing, and then confirm that this section wipes pattern, and if this match circuit is represented to have with this and is wiped the coupling that pattern is complementary, then proceed to one page, all pagings in this section are by confirming, and if this match circuit is not represented and should be had a coupling by existing page or leaf, then retry applies this step of wiping bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure.
13, a kind of method of operating non-volatile memory device comprises:
Apply in the section of the memory cell of a biasing procedure in the memory array;
Data page in this section on a plurality of bit lines of parallel detection in this memory array and one group are replaced the one or more bits in the unit, wherein the one or more bit lines in these a plurality of bit lines be labeled as defective;
This data page and this one or more bit and a pattern are made PARALLEL MATCHING, confirm the result to represent one, shielding simultaneously is labeled as the data of defective one or more bit lines.
14, method according to claim 13, it is included in and uses one first pattern to make an erase operation in this coupling step, and uses one second pattern and do a procedure operation in this coupling step, and wherein this first pattern is different from this second pattern.
15, method according to claim 13, its be included in this coupling step use be all a pattern of zero be used for an erase operation and a procedure operation one of them, and use is that a pattern of one is used for wherein another of this erase operation and this procedure operation all in this coupling step.
16, method according to claim 13, wherein this biasing procedure comprises the operation with the paging section sequencing in the paging, and this pattern comprises the data of desiring sequencing, and this biasing procedure comprises shielding be positioned at data beyond this paging section in this paging during this coupling.
17, method according to claim 13, it comprises carries out a section procedure operation, this operation comprises: the program of applying is biased in the unit of the section in this array and this group is replaced in one or more unit of unit, so that this section program is turned to a program pattern; By means of in the word line of an existing page or leaf in this section and in this one or more unit of this group replacement unit, apply one and confirm bias voltage, with each page in this section of sequencing, and then confirm this section program pattern, and if this affirmation result represents to have a coupling that is complementary with this program pattern, then proceed to one page, all pagings in this section are by confirming, and if this affirmation result does not represent and should have a coupling by existing page or leaf, then retry applies this step of program bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure.
18, method according to claim 13, it comprises carries out a section erase operation, and this erase operation comprises:
Apply in one or more unit that reaches in the unit of wiping a section that is biased into this array in this group replacement unit group, wipe pattern so that this section program is turned to one;
By means of in the word line of the existing page or leaf in this section and in this one or more unit of this group replacement unit, apply one and confirm bias voltage, with each page in this section of sequencing, and then confirm that this section wipes pattern, and if this affirmation result represents to have with this and wipes the coupling that pattern is complementary, then proceed to one page, all pagings in this section are by confirming, and if this affirmation result does not represent and should have a coupling by existing page or leaf, then retry applies this step of wiping bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure.
19, method according to claim 13, it comprises carries out a section erase operation, and this erase operation comprises:
Before applying program be biased in the unit in the section in this array and should group replacement unit in one or more unit in, this section program is turned to a preceding program pattern;
By means of in the word line of the existing page or leaf in this section and in this one or more unit of this group replacement unit, apply a program bias voltage, with each page in this section of sequencing, and then confirm program pattern before this section, and if this affirmation result represents to have and is somebody's turn to do the coupling that preceding program pattern is complementary, then proceed to one page, all pagings in this section are by confirming, and if this affirmation result does not represent and should have a coupling by existing page or leaf, then retry applies this step of program bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure;
If preceding program changes into merit, then in the unit of this section in this array, and should group replace in one or more unit in unit, apply and wipe bias voltage, so that being turned to one, this section program wipes pattern; And
By means of in the word line of the existing page or leaf in this section and in this one or more unit of this group replacement unit, apply an erase-verifying bias voltage, with each page in this section of sequencing, and then confirm that this section wipes pattern, and if this affirmation result represents to have with this and wipes the coupling that pattern is complementary, then proceed to one page, all pagings in this section are by confirming, and if this affirmation result does not represent and should have a coupling by existing page or leaf, then retry applies this step of wiping bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure.
20, a kind of integrated circuit, it comprises:
Nonvolatile charging storing memory cell array, it comprises a plurality of bit lines and a plurality of word line;
Replace the unit, be configured to the replacement that defective memory cell in this array is provided for one group;
The circuit of representing defectiveness bit line in this array;
Testing circuit is used for from this array parallel detection one data page, and wherein one page comprises a plurality of bits, and replaces the one or more bits of detection the unit from this group;
Match circuit, with this testing circuit coupling, parallel these one or more bits and the pattern of determining that this data page and this group are replaced in the unit of this match circuit is complementary, and this match circuit comprises a shielding and a comparator circuit, in order to shield defective bit line; And
Output multiplexer, with the coupling of this match circuit, this output multiplexer is selected character from this page or leaf, and will replace with the replacement bit confession that this group replaces in unit from the bit the detected character of defectiveness bit line and export.
21, circuit according to claim 20, wherein this testing circuit comprises a page buffer, is arranged with this data page of parallel detection from these a plurality of bit lines.
22, circuit according to claim 20, wherein this testing circuit comprises one group of detecting amplifier, is arranged with this data page of parallel detection from these a plurality of bit lines.
23, circuit according to claim 20, wherein this match circuit comprises this pattern set and all is one and all is zero circuit with program before confirming and erase operation.
24, circuit according to claim 20, wherein this pattern comprises the data for the treatment of sequencing, and match circuit comprises the circuit that can operate with the procedure operation of carrying out a paging section, with shielding during the program validation at this page bit in this paging section not.
25, circuit according to claim 20, wherein this match circuit comprises a corresponding group of shielding and comparator circuit, this shielding comparator circuit and the coupling of data line separately, this shielding and comparator circuit comprise respectively:
Represent whether a corresponding bit line is defective logical circuit in this array;
One bit of the bit in this data page and this pattern is made comparisons to produce the logical circuit of a comparative result; And
If during this correspondence bit line defectiveness, this comparative result is a coupling, then force the logical circuit of this comparative result of expression.
26, circuit according to claim 20, wherein this match circuit comprises a corresponding group of shielding and comparator circuit, this shielding and comparator circuit and the coupling of data line separately, this shielding and comparator circuit comprise respectively:
Represent whether a corresponding bit line is defective logical circuit in this array;
One bit of the bit in this data page and this pattern is made comparisons to produce the logical circuit of a comparative result; And
If during this correspondence bit line defectiveness, this comparative result is a coupling, then force this comparative result of expression, and during a procedure operation of the selected paging section of this page, if this correspondence bit does not then force this comparative result to represent the logical circuit of a coupling in this selected paging section.
27, circuit according to claim 20, wherein one group of data line coupling of the data page in this match circuit and this array, and this match circuit comprises a corresponding group of shielding and comparator circuit, this shielding and comparator circuit and the coupling of data line separately, this shielding and comparator circuit have the output of arranging with a line or mode, to export a matching result.
28, circuit according to claim 20, it comprises the logical circuit of carrying out a section erase operation, and this logical circuit comprises:
In the unit of the section in this array and in one or more unit in this group replacement unit, program bias voltage before applying is with program pattern before this section program being turned to;
By means of in the word line of the existing page or leaf in this section and in this one or more unit of this group replacement unit, apply one and confirm bias voltage, with each page in this section of sequencing, and then confirm program pattern before this section, and if this match circuit is represented to have and is somebody's turn to do the coupling that preceding program pattern is complementary, then proceed to one page, all pagings in this section are by confirming, and if this match circuit is not represented and should be had a coupling by existing page or leaf, then retry applies this step of program bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure;
If preceding program success then in the unit of the section in this array, reaches in one or more unit in this group replacement unit, apply and wipe bias voltage, be to wipe pattern with this section of sequencing; And
By means of in the word line of the existing page or leaf in this section and in this one or more unit of this group replacement unit, apply one and confirm bias voltage, with each page in this section of sequencing, and then confirm that this section wipes pattern, and if this match circuit is represented to have with this and is wiped the coupling that pattern is complementary, then proceed to one page, all pagings in this section are by confirming, and if this match circuit is not represented and should be had a coupling by existing page or leaf, then retry applies this step of wiping bias voltage, before carrying out this time one page, expression has a coupling, or up to a determined maximum number of retries that reaches the expression failure.
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-
2005
- 2005-06-01 US US11/141,953 patent/US7151694B2/en active Active
- 2005-06-10 TW TW094119365A patent/TWI270886B/en active
- 2005-06-13 CN CNB200510077895XA patent/CN100524521C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20050276129A1 (en) | 2005-12-15 |
| TW200605082A (en) | 2006-02-01 |
| TWI270886B (en) | 2007-01-11 |
| US7151694B2 (en) | 2006-12-19 |
| CN1734675A (en) | 2006-02-15 |
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