CN100514596C - Manufacturing method and structure of metal interconnector - Google Patents
Manufacturing method and structure of metal interconnector Download PDFInfo
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- CN100514596C CN100514596C CNB2006100051884A CN200610005188A CN100514596C CN 100514596 C CN100514596 C CN 100514596C CN B2006100051884 A CNB2006100051884 A CN B2006100051884A CN 200610005188 A CN200610005188 A CN 200610005188A CN 100514596 C CN100514596 C CN 100514596C
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Abstract
The invention relates to an inter-wire technology in metal and its structure, which provides a substrate with the first conductor. Firstly, it forms the first dielectric layer and the first pattern hard mask on the substrate. Then it etches the first hard mask to form the first shedding and the second conductor, and forms the second dielectric layer and the second hard mask on the firs hard mask. Finally, it takes the second hard mask as the etching mask and takes the first hard mask as the etching stop layer to form the second shedding and the third conductor.
Description
Technical field
The present invention relates to a kind of metal interconnecting technology and structure, relate in particular to a kind of metal interconnecting technology and structure of utilizing hard mask as etching mask and etching stopping layer.
Background technology
Along with the live width of integrated circuit is constantly dwindled, the microminiaturization of semiconductor element has entered into nano-scale, and the interval between the bigger expression element of the density of the integrated level of one chip that is the semiconductor element on it is also just little, and this makes that the making of contact hole and metal interconnecting is more and more difficult.
Please refer to Fig. 1 to Figure 11.Fig. 1 to Figure 11 is the method schematic diagram that prior art is made contact hole and metal interconnecting.As shown in Figure 1, semi-conductive substrate 10 at first is provided, and be formed with at least one metal-oxide semiconductor (MOS) (MOS) transistor unit 20 on the Semiconductor substrate 10, it includes regions and source 12 and is located in the Semiconductor substrate 10, one grid structure 14 is located on the Semiconductor substrate 10, and a clearance wall 16 is located at the sidewall on every side of grid structure 14.MOS transistor element 20 is also with shallow-channel insulation zone 24 electrical isolation simultaneously.In addition, on MOS transistor element 20 and Semiconductor substrate 10 surfaces, be coated with a contact etch stop layer (contact etch stop layer, CESL) 32, on contact etch stop layer 32, then be coated with one deck first dielectric layer 34.Then, above first dielectric layer 34, form an anti-reflecting layer 36 and a photoresist layer 40 in regular turn, utilize exposure and developing process again, in photoresist layer 40, form required opening 42, to define the position of contact hole respectively in regions and source 12 and grid structure 14 tops.
As shown in Figure 2, then utilize photoresist layer 40 as etching mask carrying out anisotropic etching process, coming the etching anti-reflecting layer 36 and first dielectric layer 34 via each opening 42, and stop at contact etch stop layer 32 surfaces, to form opening 44.Subsequently, as shown in Figure 3, utilize again photoresist layer 40 and anti-reflecting layer 36 as etching mask to carry out etch process, with the contact etch stop layer 32 of etching openings 44 bottoms, form contact hole 46.At last, as shown in Figure 4, remaining photoresist layer 40 in first dielectric layer, 34 tops and anti-reflecting layer 36 are removed.
As shown in Figure 5, for increasing the adhesive force between the metal and first dielectric layer 34, and prevent follow-up metal filled time institute issuable spike (spike) problem and the electromigration phenomenons such as (electromigration) of in contact hole 46, carrying out simultaneously, therefore need deposition one diffusion barrier (diffusion barrier) layer 47 earlier, titanium nitride (titanium nitride for example, TiN)/titanium (titanium, Ti) complex metal layer, cover on the grid structure 14 and regions and source 12 of each contact hole 46 sidewall surfaces and bottom, and then deposits tungsten (tungsten, W) etc. metal 48 fills up each contact hole 46 and covers diffused barrier layer 47 surfaces, as shown in Figure 6.Subsequently more as shown in Figure 7, (chemical mechanicalpolishing, CMP) technology go up unnecessary metal 48 to first dielectric layer, 34 surfaces and remove, to form required contact plunger (contact plug) 49 to carry out first chemico-mechanical polishing.
As shown in Figure 8, then on first dielectric layer 34 and contact plunger 49, pile up an etching stopping layer 50, one second dielectric layer 52 and a patterning photoresist layer 54 in regular turn, and utilize patterning photoresist layer 54 to come second dielectric layer 52 and etching stopping layer 50 of etching part as etching mask, to form irrigation canals and ditches 56, as shown in Figure 9.Carry out the process for copper of a standard afterwards again, cover on second dielectric layer 52 and each contact plunger 49 of each irrigation canals and ditches 56 sidewall surfaces and bottom with diffused barrier layer (not shown) and a crystal seed layer (seed layer) (not shown) that in each irrigation canals and ditches 56, deposits titanium nitride (TiN)/titanium (Ti) in regular turn, re-plating forms copper metal 58, as shown in figure 10.Carry out second chemico-mechanical polishing at last, unnecessary copper metal 58 is gone up on second dielectric layer, 52 surfaces removed, promptly form the plain conductor 60 that is electrically connected each contact plunger 49 respectively, as shown in figure 11.
As mentioned above, present semi-conductive contact etch technology all only uses the photoresist layer pattern as etching mask, but along with semiconductor element to the etching of contact hole after critical dimension (After-Etch-Inspection Critical Dimension, AEI CD) demand is more and more little, and the some optical confinement of photoetching process on the 193nm photoresist is more and more many, therefore in the contact hole technology of 65 nanometers of present standard, photoetching process must reduce the contact hole that photoresist thickness to 2800 dust just can be produced 65 nanometers, and in the contact hole technology of 45 nanometers, below the more necessary reduction photoresist of photoetching process thickness to 2200 dust.Yet the photoresist layer that thickness is thin excessively but can produce the shielding deficiency and cause problems such as boundary defect in etch process, so etch process can't only use the photoresist layer pattern as etching mask, and the necessary technology of using hard mask.But 45 nanometer technologies but can't use the general hard mask of polysilicon commonly used, because it can cause the undergoing phase transition of metal silicides such as nickle silicide (silicide) of element surface.
In addition, above-mentioned prior art also has a shortcoming when making metal interconnecting, need first deposition etch to stop layer before forming irrigation canals and ditches exactly, if use hard mask process proposed by the invention, can omit deposition etch and stop this step of layer.
Summary of the invention
One of purpose of the present invention is to propose a kind of metal interconnecting technology and structure of utilizing hard mask as etching mask and etching stopping layer, to overcome prior art problems.
According to the present invention, the invention provides a method and a structure of making metal interconnecting.Said method and structure comprise at least: a substrate that is provided with at least one first electric conductor is provided, and on this substrate and this first electric conductor, form one first dielectric layer and one first hard mask in regular turn, in order to define at least one first aperture position, and utilize this first hard mask to come this first dielectric layer of etching as etching mask, in this first dielectric layer, to form this first opening.Then in this first opening, form one second electric conductor, and be electrically connected this first electric conductor, and on this first hard mask and this second electric conductor, form one second dielectric layer, one second hard mask in regular turn, in order to define at least one second aperture position.Utilize this second hard mask as etching mask and utilize this first hard mask and this second dielectric layer of etching is come as etching stopping layer in this second electric conductor surface, in this second dielectric layer, to form this second opening, and in this second opening, form one the 3rd electric conductor, and be electrically connected this second electric conductor.
Since the present invention be earlier with the design transfer of patterning photoresist layer to hard mask layer, and then utilize hard mask to come etching first dielectric layer as etching mask, form contact hole, so critical dimension (AEI CD) can be less than the back critical dimension (ADI CD) of developing after the etching.And hard mask of the present invention also has the functions such as etching stopping layer of the irrigation canals and ditches that stop layer and follow-up metal interconnecting technology of CMP (Chemical Mechanical Polishing) process of etching mask, the contact plunger of contact hole.In addition, the present invention utilizes the carborundum (SiC) or the carbonitride of silicium (SiCN) of low temperature preparation to be used as hard mask, so the nickle silicide (NiSi) that can effectively avoid being located at grid structure and regions and source surface produces phase change.
In order to make those skilled in the art can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and explanation usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 to Figure 11 makes the method schematic diagram of a metal interconnecting structure for prior art;
Figure 12 to Figure 20 is for making the method schematic diagram of a metal interconnecting structure among the present invention.
The main element symbol description
10 Semiconductor substrate, 12 regions and source
14 grid structures, 16 clearance walls
20 MOS transistor elements, 24 shallow-channel insulation zones
24 shallow-channel insulations zone, 32 contact etch stop layers
34 first dielectric layers, 36 anti-reflecting layers
40 photoresist layers, 42 opening
44 openings, 46 contact holes
47 diffused barrier layers, 48 metals
49 contact plungers, 50 etching stopping layers
52 second dielectric layers, 54 patterning photoresist layers
56 irrigation canals and ditches, 58 bronze medal metals
60 plain conductors, 62 Semiconductor substrate
64 regions and source, 66 grid structures
68 clearance walls, 70 metal silicides
72 MOS transistor elements, 74 shallow-channel insulation zones
76 contact etch stop layers, 78 first dielectric layers
80 hard mask layers, 81 first hard mask
82 first anti-reflecting layers, 84 patterning photoresist layers
Critical dimension after 86 openings 88 develop
94 diffused barrier layers, 98 the first metal layers
100 contact plungers, 102 second dielectric layers
104 second anti-reflecting layers, 106 second hard mask
108 openings, 110 irrigation canals and ditches
112 second metal levels, 114 plain conductors
Embodiment
Please refer to Figure 12 to Figure 20.Figure 12 to Figure 20 makes the method schematic diagram of a metal interconnecting for one embodiment of the present invention.As shown in figure 12, semi-conductive substrate 62 at first is provided, for example semiconductor wafer (wafer) or silicon-coated insulated substrate (SOI) etc., and be formed with at least one MOS transistor element 72 on the Semiconductor substrate 62, it includes regions and source 64 and is located in the Semiconductor substrate 62, one grid structure 66 is located on the Semiconductor substrate 62, and a clearance wall 68 is located at the surrounding wall of grid structure 66.The grid structure 66 of MOS transistor element 72 also comprises layer of metal silicide (silicide) 70 with the surface of regions and source 64 simultaneously, its material can be utilizes the formed nickle silicide of autoregistration silication technique for metal (salicide) (NiSi) etc., and MOS transistor element 72 is also with shallow-channel insulation zone 74 electrical isolation.In addition, on MOS transistor element 72 and Semiconductor substrate 62 surfaces, be coated with a contact etch stop layer 76 in regular turn, on contact etch stop layer 76, then be coated with one deck first dielectric layer 78.
Aforesaid first dielectric layer 78 should be considered its etching selectivity with contact etch stop layer 76 in the selection of material.Generally speaking, the material that constitutes first dielectric layer 78 can comprise the doping silica layer of TEOS silica layer, undoped silicon oxygen layer or boron phosphorus silicon oxide layer, fluorine silica layer, phosphorus silica layer or boron silica layer etc., it also can utilize at least once various spin coating (spin coating) or technology such as chemical vapor deposition (CVD), for example plasma enhanced chemical vapor deposition technologies such as (PECVD) is formed, and contact etch stop layer 76 then can be the material that the heavily stressed materials of tool such as silicon nitride layer or other and first dielectric layer 78 have high etching selectivity.
Then, above first dielectric layer 78, form a hard mask layer 80, one first anti-reflecting layer 82 and a patterning photoresist layer 84 in regular turn, and patterning photoresist layer 84 comprises a plurality of openings 86, correspond respectively to grid structure 66 and regions and source 64, use each required contact hole of definition.Wherein, in a preferred embodiment of the invention, the material of hard mask layer 80 be select for use can low temperature the carborundum (SiC) of preparation or carbonitride of silicium (SiCN) or the like comprise silicon and carbon or nitrogen compound, because when selecting the material of hard mask layer 80, its film reaction of formation temperature must be less than 400 ℃, produce phase change with the nickle silicide of avoiding being located at grid structure 66 and regions and source 64 surfaces (NiSi), first anti-reflecting layer 82 then can be nitrogen-oxygen-silicon compound (SiON) etc.
Utilize patterning photoresist layer 84 to carry out an anisotropic etching process subsequently as etching mask, via opening 86 etchings first anti-reflecting layer 82 and hard mask layer 80, with with the design transfer of patterning photoresist layer 84 to hard mask layer 80, form first hard mask 81, as shown in figure 13, wherein it should be noted that, under the control and adjustment of normal etching parameter, critical dimension after the development of patterning photoresist layer 84 of the present invention (ADI CD) 88 is slightly larger than critical dimension (AEI CD) 90 after the etching of first hard mask 81, and can satisfy the semiconductor technology below 45 nanometers.
As shown in figure 14, after removing patterning photoresist layer 84 and anti-reflecting layer 82, the present invention utilizes first hard mask 81 to come etching first dielectric layer 78 and contact etch stop layer 76 as etching mask, in first dielectric layer 78 and contact etch stop layer 76, to form opening as contact hole 92, and after forming, contact hole 92 can carry out a cleaning procedure in addition, wherein cleaning procedure can be a wet-cleaned technology or a dry type cleaning, and utilize original position (in-situ) or ex situ (ex-situ) mode to carry out, when removing etching first dielectric layer 78 in the inwall of contact hole 92 residual macromolecule accessory substance.On the inwall of the surface of first hard mask 81 and contact hole 92, form a diffused barrier layer 94 subsequently.Wherein diffused barrier layer 94 is titanium nitride (titanium nitride, TiN)/titanium (titanium, Ti) or tantalum nitride (tantalum nitride, TaN)/tantalum (tantalum, Ta) complex metal layer, in order to the problems such as destruction element characteristic that diffusion caused of avoiding metallic atom, and increase the adhesive force of the metal and first dielectric layer 78 simultaneously.It should be noted that in addition, for guaranteeing that grid structure 66 is good or keep the cleanliness factor of contact hole 92 inwalls with the conduction of regions and source 64, after forming contact hole 92, also can carry out at least one process of surface treatment, for example utilize a doping process to reduce the resistance value of grid structure 66 and regions and source 64, be beneficial to the making of follow-up contact plunger.
As shown in figure 15, follow deposits tungsten (tungsten, W) etc. first metal level 98 fills up contact hole 92, and be covered on the diffused barrier layer 94, with electric connection grid electrode structure 66 and regions and source 64, and then utilize first hard mask 81 to be used as to stop layer, the first metal layer 98 and diffused barrier layer 94 are carried out first CMP (Chemical Mechanical Polishing) process, in first dielectric layer 78, to finish the technology of each contact plunger 100, as shown in figure 16.
Subsequently as shown in figure 17, form one second dielectric layer 102, one second anti-reflecting layer 104 and one second hard mask 106 in first hard mask 81 in regular turn with each contact plunger 100 top, and second hard mask 106 comprises a plurality of openings 108, and correspond respectively to each contact plunger 100 of electric connection grid electrode structure 66 and regions and source 64, the position of using the required irrigation canals and ditches 110 of definition.And then utilize second hard mask 106 as etching mask and utilize first hard mask 81 and the surface of contact plunger 100 to come etching second anti-reflecting layer 104 and second dielectric layer 102 as etching stopping layer, in second anti-reflecting layer 104 and second dielectric layer 102, to form corresponding irrigation canals and ditches 110, remove second hard mask 106 and second anti-reflecting layer 104 afterwards, as shown in figure 18.Wherein, the material of second dielectric layer 102 can comprise the doping silica layer of TEOS silica layer, undoped silicon oxygen layer or boron phosphorus silicon oxide layer, fluorine silica layer, phosphorus silica layer or boron silica layer etc., it also can utilize at least once various spin coating or technology such as chemical vapor deposition (CVD), for example the depositing operation of plasma enhanced chemical vapor deposition etc. is formed, and second hard mask 106 then is a photo anti-corrosion agent material.
As shown in figure 19, then carry out the process for copper of a standard or the depositing operation of other low resistance electric conductors again.For example cover on second dielectric layer 102 and each contact plunger 100 of each irrigation canals and ditches 110 sidewall surfaces and bottom prior to diffused barrier layer (not shown) and a crystal seed layer (seed layer) (not shown) that deposits titanium nitride (TiN)/titanium (Ti) or tantalum nitride (TaN)/tantalum (Ta) in each irrigation canals and ditches 110 in regular turn, re-plating copper fills up irrigation canals and ditches 110 to form second metal level 112, this is well known to those skilled in the art, and does not add to give unnecessary details at this.Utilize second dielectric layer 102 to be used as at last again and stop layer, second metal level 112 and diffused barrier layer (not shown) are carried out second CMP (Chemical Mechanical Polishing) process, to finish required plain conductor 114 and to be electrically connected each contact plunger 100 respectively, as shown in figure 20.
In sum, the present invention also discloses a kind of metal interconnecting structure simultaneously.As shown in figure 20, metal interconnecting structure of the present invention is to be positioned on the semi-conductive substrate 62, and be provided with at least one first electric conductor in the Semiconductor substrate 62, for example comprise grid 66, the MOS transistor element 72 of regions and source 64 and clearance wall 68, and metal interconnecting structure of the present invention comprises that one is positioned on the Semiconductor substrate 62 and covers first dielectric layer 78 of first electric conductor, one is positioned at first hard mask 81 on first dielectric layer 78, one is arranged in first hard mask 81 and first dielectric layer 78 and is electrically connected the contact plunger 100 of first electric conductor, one is arranged at second dielectric layer 102 on the contact plunger 100 and first hard mask 81, and one is arranged in second dielectric layer 102 and is positioned on first hard mask 81 and is electrically connected the plain conductor 114 of contact plunger 100.The material that wherein constitutes each thin layer and each electric conductor has been exposed among the embodiment of Figure 12 to Figure 20, in this also not narration in detail.
Because the present invention is that sharp patterning photoresist layer 84 comes etch hard mask layer 80 as etching mask earlier, with with the design transfer of patterning photoresist layer 84 to hard mask layer 80, form first hard mask 81, and then utilize first hard mask 81 to come etching first dielectric layer 78 as etching mask, to form required contact hole 92.Thus, just can control the critical dimension of pattern on first hard mask 81, make that critical dimension (AEI CD) is less than the back critical dimension (ADI CD) of developing after the etching with the etching formula.Simultaneously, first hard mask 81 of the present invention still is not used for being used as the etching mask of contact hole 92, and be used for being used as contact plunger 100 CMP (Chemical Mechanical Polishing) process stop layer, but also can be used as the etching stopping layer of irrigation canals and ditches 110 in the follow-up metal interconnecting technology, save the step that needs additional deposition one etching stopping layer in the prior art.In addition, because the following arts demand of 65 nanometers uses nickle silicide (NiSi) as the metal silicide 70 of grid structure 66 with regions and source 64 surfaces, so in the present invention, the material of hard mask layer 80 be adopt can the low temperature preparation carborundum (SiC) or carbonitride of silicium (SiCN), its film reaction of formation temperature must produce phase change with the nickle silicide of avoiding being located at grid structure 66 and regions and source 64 surfaces (NiSi) less than 400 ℃.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (22)
1. a metal interconnecting technology comprises:
Provide a substrate, and this substrate is provided with at least one first electric conductor;
In forming one first dielectric layer on this substrate and covering on this first electric conductor;
On this first dielectric layer, form one first hard mask, in order to define at least one first aperture position;
Utilize this first hard mask to come this first dielectric layer of etching, in this first dielectric layer, to form this first opening as etching mask;
In this first opening, form one second electric conductor, and be electrically connected this first electric conductor;
On this first hard mask and this second electric conductor, form one second dielectric layer;
On this second dielectric layer, form one second hard mask, in order to define at least one second aperture position;
Utilize this second hard mask as etching mask and utilize this first hard mask and this second dielectric layer of etching is come as etching stopping layer in this second electric conductor surface, in this second dielectric layer, to form this second opening; And
In this second opening, form one the 3rd electric conductor, and be electrically connected this second electric conductor,
Wherein this first opening of this second aperture efficiency is big.
2. metal interconnecting technology as claimed in claim 1, wherein this first electric conductor comprises grid, source electrode, drain electrode or ion doped region.
3. metal interconnecting technology as claimed in claim 2, wherein this first opening is a contact hole, and this second electric conductor is a contact plunger.
4. metal interconnecting technology as claimed in claim 3, wherein this substrate also is formed with a contact etch stop layer, is located between this substrate and this first dielectric layer and covers this first electric conductor.
5. metal interconnecting technology as claimed in claim 1, the method that wherein forms this first hard mask comprises in addition:
On this first dielectric layer, form a mask layer, an anti-reflecting layer and a patterning photoresist layer in regular turn;
Utilize this patterning photoresist layer to come this anti-reflecting layer of etching and this mask layer as etching mask, with the design transfer of this patterning photoresist layer to this mask layer, form this first hard mask; And
Remove this patterning photoresist layer and this anti-reflecting layer.
6. metal interconnecting technology as claimed in claim 5, wherein after the development of this patterning photoresist layer critical dimension greater than the etching of this first hard mask after critical dimension.
7. metal interconnecting technology as claimed in claim 5, wherein this first electric conductor surface comprises a metal silicide layer, and the reaction of formation temperature of this mask layer is less than 400 degree Celsius.
8. metal interconnecting technology as claimed in claim 7, wherein this mask layer is made of silicon and carbon compound or silicon and nitrogen compound.
9. metal interconnecting technology as claimed in claim 1, the method that wherein forms this second electric conductor in this first opening comprises in addition:
Forming a first metal layer fills up this first opening and is covered on this first hard mask; And
Utilize this first hard mask to be used as and stop layer, this first metal layer is carried out one first CMP (Chemical Mechanical Polishing) process.
10. metal interconnecting technology as claimed in claim 1, wherein this second opening comprises interlayer hole, lead irrigation canals and ditches, singly inlays opening or dual damascene opening.
11. metal interconnecting technology as claimed in claim 10, wherein the 3rd electric conductor comprises interlayer connector or plain conductor.
12. metal interconnecting technology as claimed in claim 10, the method that wherein forms the 3rd electric conductor in this second opening comprises in addition:
Form one second metal level fill up this second opening and be covered in this second electric conductor with the part this first hard mask on; And
Utilize this second dielectric layer to be used as and stop layer, this second metal level is carried out one second CMP (Chemical Mechanical Polishing) process.
13. metal interconnecting technology as claimed in claim 12, wherein this second metal level comprises copper.
14. metal interconnecting technology as claimed in claim 1, wherein this second patterning hard mask layer is a patterning photoresist layer.
15. metal interconnecting technology as claimed in claim 14 wherein also is formed with an anti-reflecting layer between this second patterning hard mask layer and this second dielectric layer.
16. a metal interconnecting structure, this metal interconnecting structure are to be positioned on the substrate, and this substrate is provided with at least one first electric conductor, this metal interconnecting structure comprises:
One first dielectric layer is positioned on this substrate and covers this first electric conductor, and wherein this first dielectric layer has one first opening;
One first hard mask is positioned on this first dielectric layer;
One second electric conductor is arranged in this first opening of this first hard mask and this first dielectric layer and is electrically connected this first electric conductor;
One second dielectric layer is arranged on this second electric conductor and this first hard mask, and wherein this second dielectric layer has one second opening, and this first opening of this second aperture efficiency is big; And
One the 3rd electric conductor is arranged in this second opening of this second dielectric layer and is positioned on this first hard mask, and is electrically connected this second electric conductor.
17. metal interconnecting structure as claimed in claim 16, wherein this first electric conductor comprises grid, source electrode, drain electrode or ion doped region.
18. metal interconnecting structure as claimed in claim 17, wherein this second electric conductor is a contact plunger.
19. metal interconnecting structure as claimed in claim 18, wherein this substrate also comprises a contact etch stop layer, is located between this substrate and this first dielectric layer and covers this first electric conductor.
20. metal interconnecting structure as claimed in claim 16, wherein this first electric conductor surface also comprises a metal silicide layer.
21. metal interconnecting structure as claimed in claim 20, wherein this patterning hard mask layer comprises silicon and carbon compound or silicon and nitrogen compound.
22. metal interconnecting structure as claimed in claim 16, wherein the 3rd electric conductor comprises interlayer connector or plain conductor.
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| CNB2006100051884A CN100514596C (en) | 2006-01-13 | 2006-01-13 | Manufacturing method and structure of metal interconnector |
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| CNB2006100051884A CN100514596C (en) | 2006-01-13 | 2006-01-13 | Manufacturing method and structure of metal interconnector |
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| CN100514596C true CN100514596C (en) | 2009-07-15 |
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| KR100948078B1 (en) * | 2008-05-21 | 2010-03-16 | 주식회사 하이닉스반도체 | Method for manufcturing semiconductor device |
| US8035165B2 (en) * | 2008-08-26 | 2011-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a first contact structure in a gate last process |
| US20100252930A1 (en) * | 2009-04-01 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Improving Performance of Etch Stop Layer |
| US8617986B2 (en) * | 2009-11-09 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the integrated circuits |
| CN111554659B (en) * | 2013-03-29 | 2022-05-24 | 联华电子股份有限公司 | Plug structure and manufacturing process thereof |
| CN104347485B (en) * | 2013-08-06 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN103700648B (en) * | 2013-12-18 | 2016-09-07 | 无锡中微晶园电子有限公司 | Metal interconnection structure and preparation method for high temperature circuit |
| JP6450296B2 (en) * | 2015-10-05 | 2019-01-09 | 浜松ホトニクス株式会社 | Wiring structure and manufacturing method of wiring structure |
| CN111092047B (en) * | 2018-10-23 | 2022-09-27 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| US10943829B2 (en) * | 2018-10-23 | 2021-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Slot contacts and method forming same |
| TWI707385B (en) * | 2019-10-15 | 2020-10-11 | 力晶積成電子製造股份有限公司 | Method of manufacturing semiconductor structure |
| CN111146181B (en) * | 2019-11-26 | 2022-03-04 | 上海集成电路研发中心有限公司 | Semiconductor structure and manufacturing method |
| CN113539943B (en) * | 2020-04-16 | 2023-10-13 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN113284808B (en) * | 2021-07-22 | 2021-10-15 | 江苏茂硕新材料科技有限公司 | Preparation method of semiconductor structure |
| CN114758986B (en) * | 2022-06-14 | 2022-09-16 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor device |
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