CN100501970C - 前金属介电层的有限热预算形成 - Google Patents

前金属介电层的有限热预算形成 Download PDF

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CN100501970C
CN100501970C CNB2005800076974A CN200580007697A CN100501970C CN 100501970 C CN100501970 C CN 100501970C CN B2005800076974 A CNB2005800076974 A CN B2005800076974A CN 200580007697 A CN200580007697 A CN 200580007697A CN 100501970 C CN100501970 C CN 100501970C
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phosphorous
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郑源
尚卡·文卡塔拉曼
卡里·钦
商旺
凯文·米凯尔·马凯
尼汀·K·英格尔
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Abstract

本发明提供一种填充由基板上邻近凸起特征所限定的间隙的方法，其包括提供含硅工艺气体流进入装有该基板的处理室，提供氧化工艺气体流进入该处理室，以及提供含磷工艺气体流进入该处理室。该方法还包括通过使该含硅工艺气体、该含磷工艺气体以及该氧化工艺气体之间发生反应沉积掺杂磷的硅氧化薄膜的第一部分作为该间隙中的大致均匀层。沉积该均匀层包括随着时间改变该(含硅工艺气体加含磷工艺气体)：(氧化工艺气体)的比例，并在沉积均匀层期间，使该基板的温度维持在500℃以下。该方法还包括沉积该掺杂磷的硅氧化薄膜的第二部分作为块层。沉积该薄膜的第二部分包括在沉积该块层期间使该(含硅工艺气体)：(氧化工艺气体)的比例基本上维持不变，并使改基板的温度维持在约500℃以下。

Description

前金属介电层的有限热预算形成
相关申请的交叉引用
本发明为Nitin K.Ingle等人在2002年9月19日递交的在审美国专利申请第10/247,672号，发明名称为“METHOD USING TEOS RAMP—UP DURINGTEOS/OZONE CVD FOR IMPROVED GAP FILL”的部分继续申请，并要求享有该在审申请的权益，在此引用其全部内容作为参考。
技术领域
集成电路的制造工序通常包括多轮构图工艺。该构图工艺可限定一导体层，诸如构图的金属或多晶硅层，或可限定多个绝缘结构，诸如沟槽。在许多情况中该沟槽中填充有绝缘或介电材料。该绝缘材料具有多种功能。例如，在某些应用中，该绝缘材料用于将IC的一个区域与另一区域电性绝缘，并电性地钝化该沟槽表面。该绝缘材料一般也可作为要在半导体结构构造的下一层的基底。
随着半导体设计的进步，半导体器件的特征尺寸已显著降低。许多电路现在所具有的特征，诸如线路或沟槽，已小于一微米宽。虽然特征尺寸的降低可容许更高的器件密度、每一晶圆上更多的晶片、更复杂的电路、较低的工作能耗和较低成本及其他优点，但是较小的几何结构也会产生新的问题，或再次出现曾经对于较大几何结构已经解决的问题。
因亚微米器件而面临的一种制造挑战是以无孔洞的方式完全填充窄沟道的能力。为在沟槽中填以硅氧化物(silicon oxide)，首先将硅氧化物层沉积在构图的基板上。该硅氧化物层一般覆盖场区以及沟槽的壁和底部。如果该沟槽宽且浅，则相对容易完全填充该沟槽。当沟槽变窄且深宽比(沟槽高度对宽度的比值)增加时，沟槽开口便很容易夹断(“pinch off”)。
沟槽夹断时将会在沟槽内形成孔洞。因夹断而形成的孔洞是不尽人意的，因为孔洞会降低每一晶圆上良好晶片的产率和器件的可靠性。在某些条件下，在回流过程中可填充孔洞，例如沉积的硅氧化物被掺杂且在高温下粘性流动时。然而，随着沟槽变得更窄，孔洞可能无法在回流过程中被填充。此外，多种应用类型都需要沉积未掺杂的硅氧化物，这即使在高温下也难以进行回流。
一种解决此问题的可能方案是在高温下对该氧化层退火。虽然此方案在过去很成功，然而在特定情况中却不再适用。用于高端半导体设计的新材料，诸如镍硅化物，降低了热预算，因而使某些退火的温度/持续范围无法进行。
因此，极需一种以无孔洞方式向窄间隙填充介电材料的方法，也需要该方法不会超过热预算。
发明内容
本发明的实施例因此提供了一种填充由基板上邻近凸起的特征限定的间隙的方法。该方法包括向装有基板的处理室提供含硅的工艺气体流，并向该处理室提供氧化工艺气体流，以及向该处理室提供含磷的工艺气体流。该方法还包括通过使该含硅工艺气体、该含磷工艺气体以及该氧化工艺气体间发生的反应沉积掺杂P(磷)的硅氧化物层的第一部分，而在该间隙中形成大致均匀层。沉积该均匀层包括随着时间改变(含硅的工艺气体加含磷的工艺气体)：(氧化工艺气体)的比例，并在沉积均匀层的期间使基板的温度保持在大约500°C以下。该方法还包括沉积掺杂P(磷)的硅氧化层的第二部分作为块层。沉积该薄膜的第二部分包括在沉积块层的期间使(含硅工艺气体加含磷工艺气体)与(氧化工艺气体)之比基本保持不变，并使基板温度保持在约500°C以下。在某些实施例中，该方法包括在基板上掺杂P(磷)的硅氧化层上方构图金属线，并在块层沉积后的即时点到在基板上构图金属线的即时点间使基板温度维持在掺杂P(磷)的硅氧化层的回流温度以下。
在另一实施例中，填充由相邻突出特征限定的间隙的方法包括向装有基板的处理室提供含硅的工艺气体流，并向该处理室提供氧化的工艺气体。该方法还包括通过使含硅的工艺气体和氧化的工艺气体之间反应沉积氧化硅层的第一部分而在间隙中形成大致均匀层。沉积该均匀层包括随着时间改变(含硅工艺气体)：(氧化工艺气体)之比。该方法包括在沉积均匀层期间使该基板材料保持温度在500°C以下。该方法还包括沉积硅氧化层作为块层。沉积该薄膜的第二部分包括在沉积块层期间使(含硅工艺气体)：(氧化工艺气体)之比基板保持不变，并使基板温度保持在500°C以下。该方法还包括沉积包含掺杂P(磷)的硅氧化薄膜的覆盖层，同时在沉积该覆盖层期间使基板温度保持在500°C以下。
在另一实施例中，提供一种处理半导体基板的方法。该方法包括向装有基板的处理室提供含硅工艺气体，并向该处理室提供氧化工艺气体。该方法还包括使含硅工艺气体和氧化工艺气体反应在基板上形成硅氧化层。该方法还包括随着时间改变进入处理室的(含硅气体)：(氧化气体)的比例，以改变硅氧化物在基板上的沉积速率。在工艺期间，该基板的温度保持在或低于500°C的硅氧化层的回流温度。
在某些实施例中，该硅氧化层可为前金属介电层。该基板可包括镍硅化物。该方法可包括在一段时间中向处理室提供含磷工艺气体流。并至少在一段时间中提供部分含硅工艺气体流。该含硅工艺气体可包含TEOS且该含磷工艺气体可包含磷酸三乙酯(TEPo)。
在某些实施例中，该方法包括之后接着向处理室提供含磷工艺气体流。该方法还可包括在向该处理室提供含磷工艺气体的同时，将处理室压力范围由约200托调整到约760托。该方法还可包括，在向该处理室提供含磷工艺气体的同时，由该含磷的工艺气体形成等离子体。该等离子体的密度可高于约1011ions/cm3。
在又一实施例中，处理半导体基板的方法包括向处理室提供含硅工艺气体流，并向该处理室提供氧化工艺气体，以及向该处理室提供含磷工艺气体流。该方法还包括使含硅工艺气体、氧化工艺气体以及含磷工艺气体间反应在基板上形成磷掺杂的硅氧化层。该方法还包括随时间改变向该处理室通入的(含硅气体)：(氧化气体)：(含磷气体)的比例，以改变在基板上沉积硅氧化物的速率。在该工艺期间，基板温度维持在或低于500°C。
在某些实施例中，掺杂磷的硅氧化层包含前金属介电层。该基板可包括镍硅化物。该含硅工艺气体可包括TEOS，且该含磷工艺气体可包括TEPo。
在又一实施例中，该方法包括之后接着向处理室提供含磷工艺气体流。该方法还可包括在向该处理室提供含磷工艺气体的同时，将处理室压力范围由约200托调整到约760托。该方法还可包括，在向该处理室提供含磷工艺气体的同时，由含磷的工艺气体形成等离子体。该等离子体的密度可高于约1011ions/cm3。
附图说明
可以参照说明书的剩余部分和附图更进一步理解本发明的目的和优点，其中在多个附图中用相同的标记表示相似的部件。
图1示出了采用传统沉积工艺用氧化物填充沟槽的简化截面图；
图2示出了根据本发明实施例中氧化物填充的沟槽的简化截面图；
图3示出了根据本发明实施例的第一沉积工艺；
图4示出了根据本发明实施例的第二沉积工艺；
图5A示出了根据本发明实施例的CVD设备的简化示意图；
图5B示出了CVD系统的用户界面的简化示意图，该系统与多处理室系统的沉积室相关；
图5C示出了与沉积室相关的气体面板和供应线的简化示意图；以及
图6示出了根据本发明实施例的部分集成电路的简化截面图。
具体实施方式
本发明的实施例提供与硅氧化物的化学气相沉积相关的方法、设备及装置，特别适合用于形成前金属介电(PMD)层。在一实施例中，采用一种工艺在形成一未掺杂的硅氧化物(有时称为未掺杂的硅酸盐玻璃，“USG”)均匀层之后形成一掺杂磷的硅氧化物(有时称为掺杂磷的硅酸盐玻璃，“PSG”)覆盖层。在第一化学气相沉积阶段期间，通入含硅气体和氧化气体同时改变两者的比例，使形成的硅氧化物具有高的均匀特性和良好的填充间隙特性。在随后的CVD阶段接着形成该PSG。在其它实施例中，通过改变(含硅工艺气体)：(含磷工艺气体)：(氧化工艺气体)的比例而形成PSG均匀层。在一些实施例中，可不包括PSG覆盖层。然而在这两个实施例中，这些层不需要退火工艺，因此可避免超过热预算的风险。本发明的各方面可参照传统工艺的限制而更好地理解。
I.引言
图1示出了利用传统工艺沉积的硅氧化物102填充沟槽100示例的简化截面图。图1示出了沟槽100的凸起边缘上氧化物沉积速率的增加导致沟槽夹断，并在特征形状内形成不必要的空洞或小孔缺陷104。孔洞104会不利地影响半导体器件的操作，其取决于氧化物填充的沟槽的一致介电强度。
氧化物填充的沟槽100可形成为PMD结构的一部分。传统上，在次大气化学气相沉积(SACVD)中形成的掺杂硼和磷的硅酸盐玻璃(BPSG)已用于PMD。然而，这些薄膜一般需要高温退火，使氧化物超过玻璃的相变温度并使之回流，因此在大多数情况下可移除孔洞。使用诸如镍硅化物的现今材料会与高温退火工艺不相容，因为其包含在集成电路中会要求其上制造电路的基板不经受高于500°C的温度。
用图2与图1对照，其示出了利用根据本发明实施例的工艺形成的具有氧化层202的沟槽结构200的简化截面图。在某些实施例中，氧化物填充的沟槽为PMD结构的一部分。该氧化层可包含均匀层204和覆盖层206。该均匀层204可包含未掺杂氧化物或掺杂磷的氧化物。在某些实施例中，该均匀层204可以通过改变(含硅工艺气体)：(氧化工艺气体)的比例形成，在下文将有更详细的描述。在一些实施例中，该均匀层通过改变(含硅工艺气体)：(含磷工艺气体)：(氧化工艺气体)的比例形成。该覆盖层206可包括PSG以作为吸附层。该PSG可在SACVD PSG工艺、等离子体增强CVD(PECVD)PSG工艺、高密度CVD(HDCVD)PSG工艺或者相似的工艺中形成，这将在以下描述。在与PMD相关的具体实施例中，该均匀层204包含掺杂磷的氧化物，且不包含该覆盖层。
图2的氧化物填充的沟槽200不包含利用传统工艺形成的类似特征相关的孔洞或者脆弱缝隙。此外，该氧化物填充的沟槽200的形成未超过热预算。
II.示例性沉积工艺
参照图3简要描述了本发明的实施例，说明了根据本发明实施例的第一沉积工艺300。该工艺300可用来沉积前金属介电层或其它层。该工艺可在CVD处理室中进行，其中的一个示例将在下文描述。该工艺300包含均匀层沉积302和覆盖层沉积304。在某些实施例中，在方块305处在覆盖层上构图金属线。
在一特定实施例中，含硅工艺气体包含四乙氧基硅烷(TEOS)；然而，其它含硅工艺气体，诸如SiH4、S2H6、S3H8等也可使用。同样在一特定实施例中，该氧化工艺气体包含臭氧(O3)，然而氧化气体诸如O2、H2O、H2O2可替代使用。此外，本发明的实施例描述利用未掺杂的硅酸盐玻璃(USG)进行间隙填充，但是在其它实施方式中所述膜也可以被掺杂，以下将参照图4进行说明。
均匀层沉积302可根据先前结合的美国专利申请第10/247,672号中所详细描述的工艺执行。该工艺包括通入含硅工艺气体306和氧化工艺气体308。改变该(含硅气体)：(含氧化物气体)的比例310，从而改变均匀层的沉积速率和该均匀层可能的组成。例如，在工艺起始时，该混合物中含硅气体的浓度可能很小，然后随着薄膜厚度的增加而增加。在该示例中，均匀层沉积302可包含在混合物中含硅气体浓度小的阶段沉积均匀层，然后在混合物中含硅气体浓度较高的阶段沉积块层。
调整基板的温度312，在某些情况包括程度以及持续时间，从而不超过热预算。在均匀层沉积302、覆盖层沉积304和/或构图金属线305期间，调整该温度312。在某些实施例中，其包含在处理基板期间，使温度维持在500°C以下。在某些实施例中，这包含不对基板的任何层进行退火处理。
覆盖层沉积304可在按照同样方式(in situ)进行。例如，如果均匀层沉积302在CVD处理室中进行，则覆盖层沉积304可以之后在同一处理室中进行。覆盖层304或者可通过在多处理室系统中的另一处理室中或在不同处理室系统中形成覆盖层的方式而不按照上述方式(ex situ)进行。覆盖层沉积302包含通入含磷气体314。在某些实施例中，含磷气体包含磷酸三乙酯(triethylphosphate，TEPo)或PH3。覆盖层沉积304还可包括以与上述用于均匀层沉积302相同的方式通入含硅工艺气体和氧化工艺气体。
覆盖层沉积304还可包括调整该沉积环境的压力316，和/或在该环境中形成等离子体318。在一些实施例中，该等离子体环境为高密度等离子体环境，其定义为离子密度高于1011ions/cm3。在覆盖层沉积期间，某些实施例中磷浓度的重量百分比可在约7％到约9％之间，而在其它实施例中，重量百分比可在约3.5％到4％之间。其它实施例包含的磷浓度重量比约在1％到10％之间。如上所述，覆盖层沉积可包括调整该基板的温度320。
图4示出了根据本发明实施例的第二沉积工艺400。该工艺例如可用于在基板上沉积PSG PMD层。该工艺包括均匀层沉积402并可包括覆盖层沉积404。该工艺还可包括构图金属线405。
均匀层沉积402包括提供含硅工艺气体406、氧化工艺气体408以及含磷工艺气体410。该含硅工艺气体可包含四乙氧基硅烷(TEOS)或其它含硅气体，诸如SiH4、S2H6、S3H8等。该氧化工艺气体可包含臭氧(O3)、O2、H2O、H2O2或类似物。在特定实施例中，该含磷气体包含TEPo。虽然此实施例关于沉积掺杂磷的均匀层，但也可使用其它掺杂物。例如，可用SiF4气流氟化该薄膜、PH3气流可用来磷化该薄膜、B2H6气流可用来硼化该薄膜、N2气流可用来氮化该薄膜等。
如以上关于均匀层沉积302更详细的描述，可以改变该三种气体的比例412以调整沉积速率，例如，通过在工艺开始时使氧化工艺气体维持在较高的浓度，并随着薄膜厚度的增加而降低氧化工艺气体的浓度。其可通过降低氧化工艺气体的流速和/或增加其它气体的流速实现。该含硅气体的浓度和/或掺杂气体可类似地进行调整。
也可以调整温度414，包括程度及持续时间以使之不超过热预算。如上所述，调整温度414可在均匀层沉积402、覆盖层沉积404和/或构图金属线405期间进行。在某些实施例中，这包含在处理基板整个过程中使温度维持在约500°C以下。在某些实施例中，这包含不对该基板任一层作退火处理。如需要，覆盖层沉积404可如前文所述的图3的覆盖层沉积304进行处理，其包括提供含磷气体416、调整压力418，在某些实施例中形成等离子体420，以及调整温度422。
该沉积步骤302、304、402、404可包含SACVD工艺。在该工艺中，虽然可以调节温度曲线(profile)以维持在热预算内，然而应当注意该间隙填充工艺倾向于在高温下较为成功。如上文所述及在先前结合的美国专利申请第10/247,672号中更详细的描述，以较低浓度的含硅工艺气体开始，通过改变(含硅工艺气体)：(氧化气体)比例的方式而较成功地填充高深宽比的窄间隙。该工艺可进一步辅以将气体均匀分布到该基板的方式。随着混合物中含硅工艺气体浓度的增加，该气体可经分布更靠近该基板表面。用于实施其的技术和设备，在2002年1月25日递交的在审美国专利申请第10/057,280号，发明名称为“GAS DISTRIBUTION SHOWERHEAD”中，及/或在2003年9月29日递交的在审美国专利申请第10/674,569号，发明名称为“GAS DISTRIBUTIONSHOWERHEAD”中有详细的描述，在此引用这两篇文献的全部内容作为参考。改变工艺气体的比例及在距晶圆的不同位置处分布气体的两种方式相结合，可得到更好的间隙填充效果，且在大多数情况下，不需要退火。
前文描述工艺的替代实施例可包括更多或较少的操作。此外，替代实施例中的操作不一定需按所示的顺序实施，这对于本领域的技术人员可参照本文描述明显可见。
III.示例性沉积系统
在描述了根据本发明实施例的所述方法之后，现在参照图5A，其示出了根据本发明实施例的CVD系统510的简化图。该系统适合用于进行热、SACVD工艺以及其它工艺，诸如回流、植入、净化、蚀刻和吸附工艺。多步骤工艺也可在单一基板或晶圆上执行，而无需将基板从处理室移出。该系统的主要部件包括从气体输送系统589接收工艺气体和其它气体的真空处理室515、真空系统588、远端微波等离子体系统555以及控制系统553。为便于理解本发明，这些和其它部件在下文将详细描述。
该CVD设备510包括外围部件512，用以包围具有气体反应区516的真空处理室515。气体分配版520设置于该气体反应区516上方以将反应气体和其它气体，诸如洁净气体，经过该气体分配板520中的穿孔分布到置于垂直可移动的加热器525(也称为晶圆支撑底座)的晶圆上(未示出)。该加热器525可在较低位置和工艺位置之间移动，所述较低位置处例如晶圆可装载或卸载的位置，所述工艺位置为由虚线513表示的接近气体分配版520的位置，或者可以为其它目的诸如用于蚀刻或洁净工艺而移动到其它位置。中心板(未示出)包括传感器，用来提供晶圆位置的信息。
在某些实施例中，该气体分配板520可为先前结合的美国专利申请第10/057,280或10/674,659号所述之一种。这些板改善了基板上气体分布的均匀性，且在沉积工艺中改变气体浓度的比例时特别有帮助。在一些实例中，该板与可垂直移动的加热器525(或移动式的晶圆支撑底座)结合操作，以在沿一个方向的比例明显偏差时(例如当含硅气体的浓度与含氧化物气体相比较小时)，将该沉积气体远离基板释放，并在浓度改变时(例如当混合物中的含硅气体浓度较高时)，将该沉积气体接近该基板释放。在其它实例中，设计气体分配板的气孔以提供更均匀的气体混合物。
加热器525包括封闭于陶瓷中的电阻加热元件(未示出)。该陶瓷保护加热元件不受潜在的腐蚀性处理室环境影响，并允许该加热器可达温度约为800°C。在一示例性实施例中，加热器525的所有暴露于真空处理室515中的表面均由陶瓷材料制成，诸如铝氧化物(三氧化二铝Al2O3或氧化铝)或铝氮化物。
反应性及载送气体由供应线543供应给气体混合盒内(也称为气体混合区)527，在该处它们将较好地进行混合并输送到气体分配板520。该气体混合盒527优选地为与工艺气体供应线和洁净/蚀刻空气导管547连接的双输入混合区。阀528用于操作以容许或阻止气体或等离子体从气体导管547进入该气体混合区527。该气体导管547接收来自集成的远端微波等离子体系统555的气体，其具有接收进入气体的入口557。在沉积处理期间，供应给该板520的气体排向晶圆表面(如箭头521所示)，在该处一般以层流方式在基板表面径向均匀分布。
洁净气体可从该板520和/或入口处或管子(未示出)经过外围组件512的底部壁送入到真空处理室515。该洁净气体从入口处经过该加热器525向上流至环形抽吸通道540。抽气系统接着将气体抽入(如箭头522所示)该环形抽吸通道540，并通过抽气线560进入真空系统588，该真空系统包括真空泵(未示出)。抽出气体和残留微粒以节流阀系统563控制的速率经过该抽气线560从环形抽吸通道540引出。
远端微波等离子体系统555可产生等离子体用于选定的应用，例如处理室洁净或蚀刻由晶圆工艺产生的自然氧化层或残留物。在远端等离子体系统555中，经由输入线557供应的前驱物形成的等离子体类经由导管547传送，通过该板520分配到真空处理室515。用于洁净应用的前体气体可包括氟、氯及其它反应元素。该远端微波等离子系统555也适于通过选择适当的用于该远程微波等离子体系统555中沉积前体气体而沉积等离子体增强型CVD薄膜。
该系统控制器553控制该沉积系统的活动及操作参数。该处理器550执行系统控制软件，诸如存储于与该处理器550相连的存储器570中的计算机程序。优选地，该存储器570可为硬盘驱动器，然而该存储器570也可为其它类型的存储器，诸如只读存储器或闪存。除了硬盘驱动器(例如，存储器570)外，在优选的实施例中该CVD设备510包括软盘驱动器和卡片架(未示出)。
该处理器550根据系统控制软件程序运行，以根据本文所述方法操作该装置。例如，指令组可指定时序、气体混合物、处理室压力、处理室温度、微波功率级、基座位置和特定工艺的其它参数。其它计算机程序诸如存储在其它存储器上的其它计算机程序，例如存储在软盘或者插入在磁盘驱动器或其它适当驱动器的其它计算机程序产品等，也可用来操作处理器550，以将该CVD系统510配置于不同设备中。
该处理器550具有卡片架(未示出)，其包含单片机、模拟和数字输入/输出板、界面板和步进电机控制器板。该CVD系统510的各种部件符合VersaModular European(VME)标准，其定义板、卡片架以及连接器尺寸和类型。该VME标准还定义具有16位数据总线和24位地址总线的总线结构。
图5B为与该CVD设备处理室530相关的用户界面的简化图。该CVD设备510包括多处理室系统的一个处理室。晶圆可从一个处理室传送到另一处理室用于额外处理。在某些情况中，该晶圆在真空下或所选的气体条件下进行传送。用户和处理器间的界面经由CRT显示器573a和光笔573b连接。主机单元575提供电源、配管及CVD设备510的其它支持功能。与描述的实施例CVD设备相容的示例性主机单元目前可从位于Calrfornia，Santa Clara的APPLIEDMATERIALS公司售出的RRECISION 5000TM、the CENTURA5200TM及PRODUCER SETM系统购买得到。
在某些实施例中使用两个显示器573a，其中一个安装于洁净室壁571以给操作者使用，而另一个位于壁572后以给维修技术员使用。两个显示器573a同时显示相同的信息，但是仅有一个光笔573b能操作。该光笔573b用笔尖上的光传感器探测由CRT显示器发出的光线。为选择特定显示屏或功能，操作者触摸该显示屏的指定区域，并按下笔573b上的按钮。该触摸区域改变其亮色，或者显示新的菜单或显示屏，以确定该光笔及显示屏之间的通讯。当然，除光笔573b以外，也可使用其他装置诸如键盘、鼠标或其它指示或通信装置以允许用户与处理器通信。
图5C示出了与位于洁净室中的气体供应面板580相关的CVD设备510的一实施例的一般概要图。如上所述，该CVD系统510包括具有加热器525的处理室515、具有从入口管543及导管547输入的气体混合盒527以及具有输入线557的远端微波等离子体系统555。如上所述，该气体混合盒527用于混合以及经由该入口管543将沉积气体和洁净气体或其它气体注入到工艺处理室515。
该远端微波等离子体系统555集成地位于并安装在处理室515下方，其中导管547沿着该处理室515向上到位于该处理室515上方的闸式阀528及气体混合盒527。微波产生器511和臭氧产生器551位于洁净室的远处。该气体供应面板580的供应线583和585提供反应气体给该气体供应线543。该气体供应面板580包括气体或液体源590的线路，以提供用于所选应用的工艺气体。该气体供应面板580具有混合系统593，以在进入该气体混合盒527之前混合所选气体。在某些实施例中，气体混合系统593包括液体注入系统，用以蒸发反应性液体诸如四乙氧基硅烷(“TEOS”)、硼酸三酯(“TEB”)及磷酸三乙酯(“TEPO”)。来自液体的蒸汽通常与载送气体诸如氦气结合。用于工艺气体的供应线可包括(i)关闭阀585，可用来自动或手动关闭进入线路585或线路577的工艺气流，以及(ii)液体流量计(FLM)501或其它类型的控制器，其测量通过供应线的气体或液体流。
作为一示例，包含作为硅源的TEOS的混合物可与沉积工艺中的气体混合系统593使用，以形成硅氧化物薄膜。该TEPO为液体源，其可通过传统的锅炉型或扩散器型热箱蒸发。然而，优选的液体注入系统可更好地控制引入该气体混合系统的反应性液体的体积。该液体在传送至加热气体输送线585进入气体混合室和处理室之前一般以致密喷雾或薄雾注入载送气流。一个或多个源，诸如氧气(O2)或臭氧(O3)经由另一气体输送线583流入处理室，以与来自靠近或位于该处理室中的加热气体输送线585的反应性气体混合。当然，可以认为也可使用其它掺杂物、硅和氧气源。
IV.示例性半导体结构
图6示出了根据本发明实施例的集成电路700的简化截面图。如图7所示，该集成电路700包括NMOS和PMOS晶体管703和706，其由氧化物填充的绝缘结构720分离且彼此绝缘。或者，场氧化物绝缘体也可用于绝缘器件，或者可使用组合的绝缘技术。各晶体管703和706包括源区712、栅区715及漏区718。
前金属介电(PMD)层721将晶体管703和706与金属层740隔开，由接触体724形成金属层740和晶体管间的连接。该前金属介电层721可包含单层或多层。该金属层740为包括该集成电路700中的四种金属层740、742、744和746中的一种。各金属层由金属层间介电层727、728和729与邻近金属层分隔。邻近金属层经由通孔726在所选的开口处连接。平坦化的钝化层730沉积在金属层746上。
根据本发明实施例沉积的硅氧化层可用于形成集成电路700中所示的一层或多层介电层。例如，硅氧化层可用于形成沟槽绝缘结构720。根据本发明沉积的硅氧化层还可用于形成PMD层721，或连接结构下方的较高层的金属层间介电层727—729。
根据本发明实施例沉积的硅氧化层可用于镶嵌层中，其包含在某些集成电路中。在镶嵌层中，覆盖层沉积在基板上，并选择性地蚀刻直至基板，接着以金属填充并回蚀或抛光以形成金属接触层724。在金属层沉积后，执行第二覆盖层沉积并选择性地蚀刻。该蚀刻区域接着用金属填充并回蚀或抛光形成通孔726。
应当理解该简化的集成电路700仅为示例性说明。本领域的普通技术人员可实施本发明方法制造其它集成电路，诸如微处理器、专用集成电路(ASIC)、存储器等。
显然在不脱离本发明的精神下，本领域的普通技术人员可以对以上所述的各种实施例进行各种修改、使用替代的结构及等同物。例如，虽然本发明的实施例的描述与沉积PMD层相关，然而其它实施例也可与沉积其它层相关。另外，对许多已熟知的工艺和元件没有进行描述以避免不必要地妨碍理解本发明。因此，以上描述不应视为对本发明范围的限制，其将在以下权利要求书中限定。

Claims (28)

1.一种填充由基板上邻近凸起特征所限定的间隙的方法，其包含：
提供含硅的工艺气体流进入装有所述基板的处理室；
提供氧化工艺气体流进入所述处理室；
提供含磷的工艺气体流进入所述处理室；
通过使所述含硅的工艺气体、所述含磷的工艺气体及所述氧化工艺气体之间发生反应而沉积掺杂磷的硅氧化物薄膜的第一部分，以在间隙中形成大致均匀层，其中沉积所述均匀层包括随着时间改变所述含硅工艺气体加含磷工艺气体；氧化工艺气体的比例，并在沉积所述均匀层期间将所述基板的温度维持在500℃以下；以及
之后，沉积掺杂磷的硅氧化物层的第二部分作为块层，其中沉积所述薄膜第二部分包括在沉积所述块层期间使所述含硅工艺气体加含磷的工艺气体：氧化工艺气体的比例维持不变，并使所述基板的温度维持在500℃以下。
2.根据权利要求1所述的方法，还包括：
之后，在所述基板上的所述掺杂磷的硅氧化物薄膜上构图金属线；以及
从在沉积所述块层的即时点到在所述基板上构图金属线后的即时点之间，使所述基板的温度维持在所述掺杂磷的硅氧化物薄膜的回流温度以下。
3.根据权利要求2所述的方法，其特征在于，从在沉积所述块层的即时点到在所述基板上构图金属线的即时点之间使所述基板的温度维持在所述掺杂磷的硅氧化物层的回流温度以下的步骤包含不对所述基板的任一部分进行退火处理。
4.根据权利要求1所述的方法，其特征在于，所述基板包括镍硅化物连接器，且所述掺杂磷的硅氧化物薄膜包含前金属介电层。
5.一种填充由基板上邻近凸起特征限定的间隙的方法，包括：
提供含硅工艺气体流进入装有所述基板的处理室；
提供氧化工艺气体流进入所述处理室；
通过使所述含硅工艺气体和氧化工艺气体之间发生反应而沉积硅氧化物薄膜的第一部分，以在所述间隙中形成大致均匀层，其中沉积所述均匀层包括随着时间改变所述含硅工艺气体：氧化工艺气体的比例，并在沉积所述均匀层期间，使所述基板的温度维持在500℃以下；
之后，沉积所述硅氧化物薄膜的第二部分作为块层，其中沉积所述薄膜的第二部分包括在沉积所述块层期间使所述含硅工艺气体：氧化工艺气体的比例维持不变，并使所述基板的温度维持在500℃以下；以及
之后，沉积包含掺杂磷的硅氧化物薄膜的覆盖层，同时在沉积所述覆盖层期间使所述基板温度维持在500℃以下。
6.根据权利要求5所述的方法，还包括：
之后，在所述基板上的所述掺杂磷的硅氧化物薄膜上构图金属线；以及
从在沉积所述块层的即时点到在所述基板上构图金属线的即时点之间，使所述基板的温度维持在所述硅氧化物薄膜或所述掺杂磷的硅氧化物薄膜的回流温度以下。
7.根据权利要求6所述的方法，其特征在于，从在沉积所述块层的即时点到在所述基板上构图金属线的即时点之间使所述基板温度维持在硅氧化物层薄膜或所述掺杂磷的硅氧化物薄膜的回流温度以下的步骤包括不对所述基板的任一部分进行退火处理。
8.一种处理半导体基板的方法，包括：
提供含硅工艺气体流进入装有所述基板的处理室；
提供氧化工艺气体流进入所述处理室；
使含所述含硅工艺气体和所述氧化工艺气体发生反应以在所述基板上形成硅氧化物层；
随着时间改变所述流入所述处理室的含硅气体：氧化气体的比例，以改变所述基板上沉积所述硅氧化物的速率；以及
在处理所述半导体基板期间使所述基板温度维持在或低于所述硅氧化物层的回流温度。
9.根据权利要求8所述的方法，其特征在于，在处理所述半导体基板期间使所述基板温度维持在或低于所述硅氧化物层的回流温度的步骤包括不对基板进行退火处理。
10.根据权利要求8所述的方法，其特征在于，所述硅氧化物层包括前金属介电层。
11.根据权利要求8所述的方法，其特征在于，所述基板包括邻近表面之间的间隙，且其中所述硅氧化物沉积在所述间隙中。
12.根据权利要求8所述的方法，其特征在于，所述基板包括镍硅化物。
13.根据权利要求8所述的方法，还包括在一段时间内提供含磷气体流进入所述处理室，其中在所述时间段内至少部分提供所述含硅工艺气体流。
14.根据权利要求13所述的方法，其特征在于，所述含硅工艺气体包含四乙氧基硅烷，且其中所述含磷工艺气体包含磷酸三乙酯。
15.根据权利要求13所述的方法，其特征在于：
之后提供含磷工艺气体流进入所述处理室。
16.根据权利要求5所述的方法，还包含，在提供所述含磷工艺气体流进入所述处理室的同时，将所述处理室的压力调节200托到760托之间。
17.根据权利要求15所述的方法，还包含，在提供含磷工艺气体流进入所述处理室的同时，由所述含磷工艺气体形成等离子体。
18.根据权利要求17所述的方法，其特征在于，所述等离子体的密度大于1011ions/cm3。
19.一种处理半导体基板的方法，包含：
提供含硅工艺气体流进入装有所述基板的处理室；
提供氧化工艺气体流进入所述处理室；
提供含磷工艺气体流进入所述处理室；
使所述含硅工艺气体、氧化工艺气体及含磷气体之间发生反应以在基板上形成掺杂磷的硅氧化物；以及
随着时间改变进入所述处理室的所述含硅气体：氧化气体：含磷气体的比例以改变基板上所述硅氧化物的沉积速率。
20.根据权利要求19所述的方法，进一步包含使基板的温度维持在或低于掺杂磷的硅氧化物的回流温度。
21.根据权利要求19所述的方法，其特征在于，所述基板包含邻近表面之间的间隙，且其中所述硅氧化物沉积在所述间隙中。
22.根据权利要求19所述的方法，其特征在于，所述掺杂磷的硅氧化层包含前金属介电层。
23.根据权利要求19所述的方法，其特征在于，所述基板包含镍硅化物。
24.根据权利要求19所述的方法，其特征在于，所述含硅工艺气体包含四乙氧基硅烷，且其中含磷工艺气体包含磷酸三乙酯。
25.根据权利要求24所述的方法，进一步包含：
之后提供含磷工艺气体流进入所述处理室。
26.根据权利要求25所述的方法，进一步包含，在提供所述含磷工艺气体进入所述处理室的同时，将所述处理室的压力调节在200托到760托之间。
27.根据权利要求25所述的方法，进一步包含，在提供所述含磷工艺气体进入所述处理室的同时，由含磷工艺气体形成等离子体。
28.根据权利要求27所述的方法，其特征在于，所述等离子体的密度大于1011ions/cm3。
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