CN100498891C - Pixel structure, display panel, display device, and its drive method - Google Patents

Pixel structure, display panel, display device, and its drive method Download PDF

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Publication number
CN100498891C
CN100498891C CNB2006100077032A CN200610007703A CN100498891C CN 100498891 C CN100498891 C CN 100498891C CN B2006100077032 A CNB2006100077032 A CN B2006100077032A CN 200610007703 A CN200610007703 A CN 200610007703A CN 100498891 C CN100498891 C CN 100498891C
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electrode
transistor
row
couples
storage capacitors
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CN1808537A (en
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叶宗林
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AU Optronics Corp
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AU Optronics Corp
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Abstract

Disclosed is a display panel comprising a first column electrode, a second column electrode, a first row electrode, a first transistor and a second transistor, the second column electrode is parallel to the first column electrode, the first row electrode is perpendicular to the first and second column electrodes, the grid electrode of the first transistor is coupled to the first column electrode, the grid electrode of the second transistor is coupled to the second column electrode, its drain is coupled to the first row electrode, and its source is coupled to the drain of the first transistor.

Description

Dot structure, display panel and display device and its driving method
Technical field
The invention relates to a kind of display panel, particularly relevant for a kind of display panel with most pixel cells.
Background technology
Fig. 1 shows the synoptic diagram of known display panel.As shown in the figure, display panel 10 has gate electrode G 1-G n, source electrode S 1-S m, and pixel cell P 11-P MnGate electrode that each group is staggered and source electrode can be with controlling a pixel cell.For example, gate electrode G 1With source electrode S 1Can be used for controlling pixel cell P 11
Pixel cell P 11-P MnEquivalent electrical circuit comprise that mainly control data enters the transistor T of usefulness 11-T Mn, storage capacitors Ccs 11-Ccs Mn, and liquid crystal capacitance Clc 11-Clc MnBy gate electrode G 1-G nOn sweep signal, just can conducting or close the same all crystals pipe that lists, use control source electrode S 1-S mOn vision signal whether can enter into corresponding display unit.
Display panel with 1024X768 is an example.Because each pixel cell has R, B, three pixels of G, so need 1024 * 3 column electrodes altogether, can control all pixel cells.
The resolution of the picture that the quantity of the display unit of panel and panel are presented has the relation of direct ratio.When the resolution of the picture that panel presented heals when high, then the quantity of the display unit of panel also must increase, and then increases the quantity of source electrode.
Panel 10 has many source electrode drivers (not icon).Each source electrode driver is in order to the source electrode of control equal number.Therefore, when the quantity of source electrode increases, not only make the aperture opening ratio (aperture ratio) of display panel reduce, also make the quantity of source electrode driver relatively improve, and then improve the manufacturing cost of panel and the volume of panel, and significantly reduce the spendable space of panel.
Summary of the invention
The invention provides a kind of display panel, comprise first, second row electrode, first column electrode and first, second transistor.The secondary series electrode is parallel to the first row electrode.Vertical first and second row electrode of first column electrode.The grid of the first transistor couples the first row electrode.The grid of transistor seconds couples the secondary series electrode, and its drain electrode couples first column electrode, and its source electrode couples the drain electrode of the first transistor.
The present invention provides a kind of display device in addition, comprises row driver element, row driver element and display panel.The row driver element is in order to provide first and second column signal.The row driver element is in order to provide the first row signal.Display panel comprises first, second row electrode, first column electrode and first, second transistor.The first row electrode receives first column signal.The secondary series electrode is parallel to the first row electrode, and receives the secondary series signal.Vertical first and second row electrode of first column electrode, and receive the first row signal.The grid of the first transistor couples the first row electrode.The grid of transistor seconds couples the secondary series electrode, and its drain electrode couples first column electrode, and its source electrode couples the drain electrode of the first transistor.
The present invention also provides a kind of dot structure, comprises first, second and third row electrode, first column electrode and the first, second, third and the 4th transistor at least.First, second and third row electrode is parallel to each other.Vertical first and second row electrode of first column electrode.First control end that the first transistor has first, second end and couples the first row electrode.Transistor seconds has the 3rd end and couples first end and second control end that first column electrode, the 4th end couple the first transistor and couple the secondary series electrode.The 3rd transistor has the one the 5th, the 6th end and one the 3rd control end couples the secondary series electrode.The 4th transistor has that one the 7th end couples first column electrode, the 8th end couples the 3rd transistorized five terminal and one the 4th control end couples the 3rd row electrode.
When a period 1, activate first and second row electrode simultaneously, and first and second transistor is given in the transmission of first data signal by first column electrode; When a second round, only activate the secondary series electrode then, and transistor seconds is given in the transmission of second data signal by first column electrode; Then, when a period 3, activate second and third row electrode simultaneously, and by first column electrode the 3rd data signal is transmitted and to give second, third and the 4th transistor; Then, when a period 4, only activate the 3rd row electrode, and the 4th transistor is given in the transmission of one the 4th data signal by first column electrode; Then, when a period 5, only activate the secondary series electrode, and transistor seconds is given in the transmission of the 5th data signal by first column electrode.
Description of drawings
Fig. 1 shows the synoptic diagram of known panel.
Fig. 2 is first embodiment of display device of the present invention.
Fig. 3 is second embodiment of display device of the present invention.
Fig. 4 is the 3rd embodiment of display device of the present invention.
Fig. 5 is the 4th embodiment of display device of the present invention.
Fig. 6 is the 5th embodiment of display device of the present invention.
Fig. 7 is the 6th embodiment of display device of the present invention.
Fig. 8 is the 7th embodiment of display device of the present invention.
Fig. 9 is the 8th embodiment of display device of the present invention.
Figure 10 is the pixel cell synoptic diagram of the utilization first embodiment of the present invention.
Figure 11 is the control timing figure of pixel cell of the present invention.
Symbol description:
10,26: display panel; G0-Gn: gate electrode;
S1-Sm: source electrode; 22: the row driver element;
24: the row driver element; Com1, com2: common electrode;
P11-Pmn, 32,34,42,44,52,54,62,64,72,74,82,84,92,94,102-108,112-118: pixel cell;
T11-Tmn, 322,342,422,442,522,542,622,642,722,742,822,842,922,942: transistor;
Ccs11-Ccsmn, 324,344,424,444,524,544,624,644,724,744,824,844,924,944: storage capacitors;
Clc11-Clcmn, 326,346,426,446,526,546,626,646,726,746,826,846,926,946: liquid crystal capacitance.
Embodiment
For purpose of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Fig. 2 is first embodiment of display device of the present invention.Display device comprises, row driver element 22, row driver element 24 and display panel 26.Row driver element 22 provides capable signal (for example, data-signal).Row driver element 24 provides column signal (for example, sweep signal).Display panel 26 comprises gate electrode (row electrode) G 0-G n, receive row signal, source electrode (column electrode) S 1-S M-1, receive column signal and pixel cell P 11-P Mn
In this embodiment, be to remove even line electrode.Be coupled to transistor in the adjacent unit pixel with originally being coupled to transistor in the pixel cell of even line electrode.In addition, the transistorized grid of the pixel cell of shared same source electrode need be coupled to different gate electrodes.
For convenience of description, below only with pixel cell P 11, P 21Be example, coupling mode of the present invention is described.Pixel cell P 11Has transistor T 11, storage capacitors Ccs 11, liquid crystal capacitance Clc 11Pixel cell P 21Has transistor T 21, storage capacitors Ccs 21, liquid crystal capacitance Clc 21
Because transistorized source electrode and drain electrode are to determine according to sense of current, thus below will represent transistorized two ends respectively with " source/drain electrode " and " leakage/source electrode ".
Transistor T 11Source/drain electrode couple source electrode S 1, its grid couples gate electrode G 1Storage capacitors Ccs 11Be coupled to transistor T 11Leakage/source electrode and common electrode com 1Between, and liquid crystal capacitance Clc 11Be coupled to transistor T 11Leakage/source electrode and common electrode com 2Between, common electrode com wherein 1Current potential be different from common electrode com 2Current potential.
Transistor T 21Source/drain electrode couple transistor T 11Leakage/source electrode, its grid couples gate electrode G 0Storage capacitors Ccs 21Be coupled to transistor T 21Leakage/source electrode and common electrode com 1Between, and liquid crystal capacitance Clc 21Be coupled to transistor T 21Leakage/source electrode and common electrode com 2Between.
Fig. 3 is second embodiment of display device of the present invention.For convenience of description, Fig. 3 display pixel cells 32,34 only.Source/the drain electrode of transistor 322 couples source electrode S 1, its grid couples gate electrode G 0Source/the drain electrode of transistor 342 couples the leakage/source electrode of transistor 322, and its grid couples gate electrode G 1Storage capacitors 324 is coupled to the leakage/source electrode and the common electrode com of transistor 322 1Between, liquid crystal capacitance 326 is coupled to the leakage/source electrode and the common electrode com of transistor 322 2Between.Storage capacitors 344 is coupled to the leakage/source electrode and the common electrode com of transistor 342 1Between.Liquid crystal capacitance 346 is coupled to the leakage/source electrode and the common electrode com of transistor 342 2Between.
Fig. 4 is the 3rd embodiment of display device of the present invention.For convenience of description, Fig. 4 display pixel cells 42,44 only.Source/the drain electrode of transistor 442 couples source electrode S 2, its grid couples gate electrode G 1Source/the drain electrode of transistor 422 couples the leakage/source electrode of transistor 442, and its grid couples gate electrode G 0Storage capacitors 424 is coupled to the leakage/source electrode and the common electrode com of transistor 422 1Between.Liquid crystal capacitance 426 is coupled to the leakage/source electrode and the common electrode com of transistor 422 2Between.Storage capacitors 444 and liquid crystal capacitance 446 are coupled between the leakage/source electrode and common electrode of transistor 442.
Fig. 5 is the 4th embodiment of display device of the present invention.For convenience of description, Fig. 5 display pixel cells 52,54 only.Source/the drain electrode of transistor 542 couples source electrode S 2, its grid couples gate electrode G 0Source/the drain electrode of transistor 522 couples the leakage/source electrode of transistor 542, and its grid couples gate electrode G 1Storage capacitors 524 is coupled to the leakage/source electrode and the common electrode com of transistor 522 1Between.Liquid crystal capacitance 526 is coupled to the leakage/source electrode and the common electrode com of transistor 522 2Between.Storage capacitors 544 is coupled to the leakage/source electrode and the common electrode com of transistor 542 1Between.Liquid crystal capacitance 546 is coupled to the leakage/source electrode and the common electrode com of transistor 542 2Between.
Fig. 6 is the 5th embodiment of display device of the present invention.For convenience of description, Fig. 6 display pixel cells 62,64 only.Source/the drain electrode of transistor 622 couples source electrode S 1, its grid couples gate electrode G 1Source/the drain electrode of transistor 642 couples the leakage/source electrode of transistor 622, and its grid couples common electrode com 1 Storage capacitors 624 is coupled to the leakage/source electrode and the common electrode com of transistor 622 1Between.Liquid crystal capacitance 626 is coupled to the leakage/source electrode and the common electrode com of transistor 622 2Between.Storage capacitors 644 is coupled to the leakage/source electrode and the common electrode com of transistor 642 1Between.Liquid crystal capacitance 646 is coupled to the leakage/source electrode and the common electrode com of transistor 642 2Between.
Fig. 7 is the 6th embodiment of display device of the present invention.For convenience of description, Fig. 7 display pixel cells 72,74 only.Source/the drain electrode of transistor 722 couples source electrode S 1, its grid couples common electrode com 1Source/the drain electrode of transistor 742 couples the leakage/source electrode of transistor 722, and its grid couples gate electrode G 1Storage capacitors 724 is coupled to the leakage/source electrode and the common electrode com of transistor 722 1Between.Liquid crystal capacitance 726 is coupled to the leakage/source electrode and the common electrode com of transistor 722 2Between.Storage capacitors 744 is coupled to the leakage/source electrode and the common electrode com of transistor 742 1Between.Liquid crystal capacitance 746 is coupled to the leakage/source electrode and the common electrode com of transistor 742 2Between.
Fig. 8 is the 7th embodiment of display device of the present invention.For convenience of description, Fig. 8 display pixel cells 82,84 only.Source/the drain electrode of transistor 842 couples source electrode S 2, its grid couples gate electrode G 1Source/the drain electrode of transistor 822 couples the leakage/source electrode of transistor 842, and its grid couples common electrode com 1 Storage capacitors 824 is coupled to the leakage/source electrode and the common electrode com of transistor 822 1Between.Liquid crystal capacitance 826 is coupled to the leakage/source electrode and the common electrode com of transistor 822 2Between.Storage capacitors 844 is coupled to the leakage/source electrode and the common electrode com of transistor 842 1Between.Liquid crystal capacitance 846 is coupled to the leakage/source electrode and the common electrode com of transistor 842 2Between.
Fig. 9 is the 8th embodiment of display device of the present invention.For convenience of description, Fig. 9 display pixel cells 92,94 only.Source/the drain electrode of transistor 942 couples source electrode S 2, its grid couples common electrode com 1Source/the drain electrode of transistor 922 couples the leakage/source electrode of transistor 942, and its grid couples gate electrode G 1Storage capacitors 924 is coupled to the leakage/source electrode and the common electrode com of transistor 922 1Between.Liquid crystal capacitance 926 is coupled to the leakage/source electrode and the common electrode com of transistor 922 2Between.Storage capacitors 944 is coupled to the leakage/source electrode and the common electrode com of transistor 942 1Between.Liquid crystal capacitance 946 is coupled to the leakage/source electrode and the common electrode com of transistor 942 2Between.
To be example below, the control mode of pixel cell of the present invention will be described with pixel cell shown in Figure 10.Figure 11 is the control timing figure of pixel cell of the present invention.
When time T 1, activate gate electrode G 0, G 1, and by source electrode S 1To storage capacitors in the pixel cell 102,104 and liquid crystal capacitance charging, and by source electrode S 3To storage capacitors in the pixel cell 106,108 and liquid crystal capacitance charging.
When time T 2, only activate gate electrode G 1, and by source electrode S 1To storage capacitors in the pixel cell 102 and liquid crystal capacitance charging, and by source electrode S 3To storage capacitors in the pixel cell 106 and liquid crystal capacitance charging.
When time T 3, activate gate electrode G 1, G 2, and by source electrode S 1To storage capacitors in the pixel cell 102,112,114 and liquid crystal capacitance charging, and by source electrode S 3To storage capacitors in the pixel cell 106,116,118 and liquid crystal capacitance charging.
When time T 4, only activate gate electrode G 2, and by source electrode S 1To storage capacitors in the pixel cell 112 and liquid crystal capacitance charging, and by source electrode S 3To storage capacitors in the pixel cell 116 and liquid crystal capacitance charging.
When time T 5, only activate gate electrode G 1, and by source electrode S 1To storage capacitors in the pixel cell 102 and liquid crystal capacitance charging, and by source electrode S 3To storage capacitors in the pixel cell 106 and liquid crystal capacitance charging.
By above-mentioned control mode, just can make storage capacitors and liquid crystal capacitance in pixel cell 102-108, the 112-118 store corresponding electric charge.Because above-mentioned control mode is in order to control three gate electrode G 0-G 3So, only need carry out above-mentioned control mode to each group respectively with per three gate electrodes as a group, just can charge to storage capacitors in all pixel cells and liquid crystal capacitance.
In sum, because the present invention can save the source electrode of half, so can improve the aperture opening ratio of display panel, reduce the quantity of row driver, and can increase the spendable space of display panel.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is looked being as the criterion that claim defines.

Claims (43)

1. display panel comprises at least:
One first row electrode;
One secondary series electrode is parallel to this first row electrode;
One first column electrode, vertically this first and second row electrode;
One the first transistor, one first control end that has a first transistor source electrode, the first transistor drain electrode and couple this first row electrode; And
One transistor seconds, have a transistor seconds source electrode, transistor seconds drain electrode and one second control end, this second control end couples this secondary series electrode, and this transistor seconds source electrode couples this first column electrode, and this transistor seconds drain electrode couples this first transistor source electrode.
2. display panel as claimed in claim 1, wherein this first row electrode and secondary series electrode are respectively a first grid electrode and second grid electrode.
3. display panel as claimed in claim 2 also comprises:
One first storage capacitors is coupled between this first transistor drain electrode and one the 3rd row electrode; And
One second storage capacitors couples between this transistor seconds drain electrode and the 3rd row electrode.
4. display panel as claimed in claim 3, wherein the 3rd row electrode is one first common electrode.
5. display panel as claimed in claim 4 also comprises:
One the 4th row electrode is parallel to this first row electrode;
One the 3rd transistor has one the 3rd transistor source, the 3rd transistor drain and one the 3rd control end and couples this secondary series electrode; And
One the 4th transistor, have one the 4th transistor source, the 4th transistor drain and one the 4th control end, the 4th control end couples the 4th row electrode, and the 4th transistor source couples this first column electrode, and the 4th transistor drain couples the 3rd transistor source.
6. display panel as claimed in claim 5 also comprises:
One the 3rd storage capacitors is coupled between the 3rd transistor drain and one the 5th row electrode; And
One the 4th storage capacitors couples between the 4th transistor drain and the 5th row electrode.
7. display panel as claimed in claim 6, wherein the 5th row electrode is one second common electrode, the level of this second common electrode equals the level of this first common electrode.
8. display panel as claimed in claim 1, wherein this first and second row electrode is respectively one first common electrode and a gate electrode.
9. display panel as claimed in claim 8 also comprises:
One first storage capacitors is coupled between this first transistor drain electrode and this first row electrode; And
One second storage capacitors couples between this transistor seconds drain electrode and this first row electrode.
10. display panel as claimed in claim 1, wherein this first column electrode is the one source pole electrode.
11. a display device comprises at least:
One row driver element is in order to provide first and second column signal;
Delegation's driver element is in order to provide one first row signal; And
One display panel comprises:
One first row electrode receives this first column signal;
One secondary series electrode is parallel to this first row electrode, and receives this secondary series signal;
One first column electrode, vertically this first row electrode and secondary series electrode, and receive this first row signal;
One the first transistor has a first transistor source electrode, the first transistor drain electrode and one first control end and couples this first row electrode; And
One transistor seconds, have a transistor seconds source electrode, transistor seconds drain electrode and one second control end, this second control end couples this secondary series electrode, and this transistor seconds source electrode couples this first column electrode, and this transistor seconds drain electrode couples this first transistor source electrode.
12. display device as claimed in claim 11, wherein this display panel also comprises:
One first storage capacitors is coupled between this first transistor drain electrode and this first row electrode; And
One second storage capacitors couples between this transistor seconds drain electrode and this first row electrode.
13. display device as claimed in claim 11, wherein this row driver element is the one source pole driver.
14. display device as claimed in claim 11, wherein this row driver element is a gate drivers.
15. display device as claimed in claim 14, wherein this display panel also comprises:
One first storage capacitors is coupled between this first transistor drain electrode and one the 3rd row electrode; And
One second storage capacitors couples between this transistor seconds drain electrode and the 3rd row electrode.
16. display device as claimed in claim 15, wherein the 3rd row electrode is one first common electrode.
17. display device as claimed in claim 16, wherein this display panel also comprises:
One the 4th row electrode is parallel to this first row electrode;
One the 3rd transistor has one the 3rd transistor source, the 3rd transistor drain and one the 3rd control end and couples this secondary series electrode; And
One the 4th transistor, have one the 4th transistor source, the 4th transistor drain and one the 4th control end, the 4th control end couples the 4th row electrode, and the 4th transistor source couples this first column electrode, and the 4th transistor drain couples the 3rd transistor source.
18. display device as claimed in claim 17, wherein this display panel also comprises:
One the 3rd storage capacitors is coupled between the 3rd transistor drain and one the 5th row electrode; And
One the 4th storage capacitors couples between the 4th transistor drain and the 5th row electrode.
19. display device as claimed in claim 18, wherein the 5th row electrode is one second common electrode, and the level of this second common electrode equals the level of this first common electrode.
20. a driving method, in order to drive in display device as claimed in claim 21, this driving method comprises the following steps:
Activate this first and second row electrode simultaneously, in order to this first and second storage capacitors is charged;
Activate this secondary series electrode, in order to this second storage capacitors is charged;
Activate this secondary series electrode and the 4th row electrode simultaneously, in order to this second storage capacitors, the 3rd storage capacitors and the 4th storage capacitors are charged;
Activate the 4th row electrode, in order to the 4th storage capacitors is charged; And
Activate this secondary series electrode, in order to this second storage capacitors is charged.
21. a dot structure comprises at least:
One first row electrode;
One secondary series electrode is parallel to this first row electrode;
One the 3rd row electrode is parallel to this first row electrode;
One first column electrode, vertically this first and second row electrode;
One the first transistor, one first control end that has one first end, second end and couple this first row electrode; And
One transistor seconds has one the 3rd end, the 4th end and one second control end, and this second control end couples this secondary series electrode, and the 3rd end couples this first column electrode, and the 4th end couples this first end;
One the 3rd transistor has a five terminal, the 6th end and one the 3rd control end and couples this secondary series electrode; And
One the 4th transistor has one the 7th end, the 8th end and one the 4th control end, and the 4th control end couples the 3rd row electrode, and the 7th end couples this first column electrode, and the 8th end couples this five terminal;
Wherein, when a period 1, activate this first and second row electrode simultaneously, and this first transistor and transistor seconds are given in the transmission of one first data signal by this first column electrode; When a second round, only activate this secondary series electrode then, and this transistor seconds is given in the transmission of one second data signal by this first column electrode; Then, when a period 3, activate this secondary series electrode and the 3rd row electrode simultaneously, and this transistor seconds, the 3rd transistor and the 4th transistor are given in the transmission of one the 3rd data signal by this first column electrode; Then, when a period 4, only activate the 3rd row electrode, and the 4th transistor is given in the transmission of one the 4th data signal by this first column electrode; Then, when a period 5, only activate this secondary series electrode, and this transistor seconds is given in the transmission of one the 5th data signal by this first column electrode.
22. dot structure as claimed in claim 21 also comprises:
One first storage capacitors is coupled between this second end and one the 4th row electrode; And
One second storage capacitors couples between the 4th end and the 4th row electrode.
23. dot structure as claimed in claim 22 also comprises:
One the 3rd storage capacitors is coupled between the 6th end and one the 5th row electrode; And
One the 4th storage capacitors couples between the 8th end and the 5th row electrode.
24. dot structure as claimed in claim 23, wherein when this period 1, this first storage capacitors and second storage capacitors are charged according to this first data signal, when this second round, this second storage capacitors is charged according to this second data signal, when this period 3, this second storage capacitors, the 3rd storage capacitors and the 4th storage capacitors are charged according to the 3rd data signal, when this period 4, the 4th storage capacitors is charged according to the 4th data signal, when this period 5, this second storage capacitors is charged according to the 5th data signal.
25. a display panel comprises at least:
One first row electrode;
One secondary series electrode is parallel to this first row electrode;
One first column electrode, vertically this first and second row electrode;
One the first transistor, one first control end that has a first transistor source electrode, the first transistor drain electrode and couple this first row electrode; And
One transistor seconds, have a transistor seconds source electrode, transistor seconds drain electrode and one second control end, this second control end couples this secondary series electrode, and this transistor seconds drain electrode couples this first column electrode, and this transistor seconds source electrode couples this first transistor drain electrode.
26. display panel as claimed in claim 25, wherein this first row electrode and secondary series electrode are respectively a first grid electrode and second grid electrode.
27. display panel as claimed in claim 26 also comprises:
One first storage capacitors is coupled between this first transistor source electrode and one the 3rd row electrode; And
One second storage capacitors couples between this transistor seconds source electrode and the 3rd row electrode.
28. display panel as claimed in claim 27, wherein the 3rd row electrode is one first common electrode.
29. display panel as claimed in claim 28 also comprises:
One the 4th row electrode is parallel to this first row electrode;
One the 3rd transistor has one the 3rd transistor source, the 3rd transistor drain and one the 3rd control end and couples this secondary series electrode; And
One the 4th transistor, have one the 4th transistor source, the 4th transistor drain and one the 4th control end, the 4th control end couples the 4th row electrode, and the 4th transistor drain couples this first column electrode, and the 4th transistor source couples the 3rd transistor drain.
30. display panel as claimed in claim 29 also comprises:
One the 3rd storage capacitors is coupled between the 3rd transistor source and one the 5th row electrode; And
One the 4th storage capacitors couples between the 4th transistor source and the 5th row electrode.
31. display panel as claimed in claim 30, wherein the 5th row electrode is one second common electrode, and the level of this second common electrode equals the level of this first common electrode.
32. display panel as claimed in claim 25, wherein this first and second row electrode is respectively one first common electrode and a gate electrode.
33. display panel as claimed in claim 32 also comprises:
One first storage capacitors is coupled between this first transistor source electrode and this first row electrode; And
One second storage capacitors couples between this transistor seconds source electrode and this first row electrode.
34. display panel as claimed in claim 25, wherein this first column electrode is the one source pole electrode.
35. a display device comprises at least:
One row driver element is in order to provide first and second column signal;
Delegation's driver element is in order to provide one first row signal; And
One display panel comprises:
One first row electrode receives this first column signal;
One secondary series electrode is parallel to this first row electrode, and receives this secondary series signal;
One first column electrode, vertically this first row electrode and secondary series electrode, and receive this first row signal;
One the first transistor has a first transistor source electrode, the first transistor drain electrode and one first control end and couples this first row electrode; And
One transistor seconds, have a transistor seconds source electrode, transistor seconds drain electrode and one second control end, this second control end couples this secondary series electrode, and this transistor seconds drain electrode couples this first column electrode, and this transistor seconds source electrode couples this first transistor drain electrode.
36. display device as claimed in claim 35, wherein this display panel also comprises:
One first storage capacitors is coupled between this first transistor source electrode and this first row electrode; And
One second storage capacitors couples between this transistor seconds source electrode and this first row electrode.
37. display device as claimed in claim 35, wherein this row driver element is the one source pole driver.
38. display device as claimed in claim 35, wherein this row driver element is a gate drivers.
39. display device as claimed in claim 38, wherein this display panel also comprises:
One first storage capacitors is coupled between this first transistor source electrode and one the 3rd row electrode; And
One second storage capacitors couples between this transistor seconds source electrode and the 3rd row electrode.
40. display device as claimed in claim 39, wherein the 3rd row electrode is one first common electrode.
41. display device as claimed in claim 40, wherein this display panel also comprises:
One the 4th row electrode is parallel to this first row electrode;
One the 3rd transistor has one the 3rd transistor source, the 3rd transistor drain and one the 3rd control end and couples this secondary series electrode; And
One the 4th transistor, have one the 4th transistor source, the 4th transistor drain and one the 4th control end, the 4th control end couples the 4th row electrode, and the 4th transistor drain couples this first column electrode, and the 4th transistor source couples the 3rd transistor drain.
42. display device as claimed in claim 41, wherein this display panel also comprises:
One the 3rd storage capacitors is coupled between the 3rd transistor source and one the 5th row electrode; And
One the 4th storage capacitors couples between the 4th transistor source and the 5th row electrode.
43. display device as claimed in claim 42, wherein the 5th row electrode is one second common electrode, and the level of this second common electrode equals the level of this first common electrode.
CNB2006100077032A 2006-02-14 2006-02-14 Pixel structure, display panel, display device, and its drive method Expired - Fee Related CN100498891C (en)

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Application Number Priority Date Filing Date Title
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CN100498891C true CN100498891C (en) 2009-06-10

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