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Publication numberCN100495703 C
Publication typeGrant
Application numberCN 200410010418
Publication date3 Jun 2009
Filing date8 Nov 2004
Priority date6 Nov 2003
Also published asCN1624916A, DE602004014331D1, EP1530226A2, EP1530226A3, EP1530226B1, US7807337, US20050116317, US20080102409
Publication number200410010418.7, CN 100495703 C, CN 100495703C, CN 200410010418, CN-C-100495703, CN100495703 C, CN100495703C, CN200410010418, CN200410010418.7
Inventors孙洪成, 李义亨, 李孝钟, 河商录, 金一龙, 金二权
Applicant三星电子株式会社
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Inductor for a system-on-a-chip and method for manufacturing the same
CN 100495703 C
Abstract  translated from Chinese
本发明公开了一种用于芯片上系统的电感器及制造该电感器的方法。 The present invention discloses an inductor and a method for manufacturing the same system on a chip inductor. 该电感器包括通过连接多个导电图案形成导线,其中该导电图案从在下布线上形成的籽层生长。 The inductor comprises a wire formed by connecting a plurality of conductive patterns, wherein the seed layer is formed from the conductive pattern on the lower wiring growth. 该方法包括使用电解镀层工艺或非电镀层工艺从籽层生长多个相邻的导电图案,直到它们彼此连接。 The method comprises using an electrolytic plating process or the plating process a plurality of adjacent conductive patterns grown from the seed layer until they are connected to each other. 该方法还能够将导线的高度和宽度调节到所需值。 The method is also able to adjust the height and width of the wire to the desired value.
Claims(10)  translated from Chinese
1. 一种电感器,包括:一基板,包括一导电结构;一模层,形成在所述基板上,其中所述模层包括具有内表面的孔阵列;一第一籽层,形成在所述孔阵列的所述内表面上和在所述模层上;一帽盖层,形成在所述第一籽层上;一第二籽层,形成在位于所述孔阵列中的所述帽盖层的部分上;以及一导线,形成在所述第二籽层上,其中所述导线电连接到所述导电结构上并由多个连接的从所述第二籽层生长的导电图案而形成。 An inductor, comprising: a substrate comprising a conductive structure; a mold layer formed on the substrate, wherein the mold layer comprises hole arrays having inner surfaces; a first seed layer, formed on the a second seed layer of the cap, the hole formed in said array; the array of said apertures and on the inner surface of said upper mold layer; a cap layer formed on the first seed layer a cap portion; and a conductor formed on the second seed layer, wherein said conductor is electrically connected to the conductive structure by a plurality of the second seed layer is grown from the conductive pattern and connected form.
2. 如权利要求1所述的电感器,其中进一步包括:一防扩散层,形成在所述第一籽层和包括所述导电结构的所述基板之间以及所述第一籽层和所述模层之间。 2. The inductor according to claim 1, further comprising: a diffusion preventing layer formed between the seed layer and the first conductive structure comprises the substrate and the seed layer and the first said mold layer.
3. 如权利要求1所述的电感器,其中所述第一籽层包括选自铜、柏、 钯、镍、银、金及其合金所构成的组中的一成分。 Inductor according to claim, wherein the first seed layer is selected from the group comprising copper, cypress, palladium, nickel, silver, gold and alloys composed of a component.
4. 如权利要求1所述的电感器,其中所述帽盖层包括铝。 4. The inductor according to claim 1, wherein the capping layer comprises aluminum.
5. 如权利要求4所述的电感器,其中所述帽盖层具有大约100到500 埃的一厚度。 5. The inductor according to claim 4, wherein the capping layer has a thickness of about 100-500 angstroms.
6. 如权利要求1所述的电感器,其中所述第二籽层包括选自铜、钼、 钯、镍、银、金及其合金所构成的组中的一成分。 6. The inductor according to claim 1, wherein said second seed layer selected from the group comprising copper, molybdenum, palladium, nickel, silver, gold and alloys composed of a component.
7. 如权利要求1所述的电感器,其中进一步包括: 一保护层,形成在所述导线上。 7. The inductor according to claim 1, further comprising: a protective layer formed on the wire.
8. 如权利要求1所述的电感器,其中所述导线具有一圓形上部。 8. The inductor according to claim 1, wherein said wire has a circular upper portion.
9. 一种制造电感器的方法,包括以下步骤:在包括一导电结构的一基板上形成一模层,其中所述模层包括具有内表面的孔阵列;在所述孔阵列的内表面上和在所述模层上形成一防扩散层;在所述防扩散层上形成一第一籽层;在所述第一籽层上形成一帽盖层;在位于孔阵列中的所述帽盖层的部分上形成一第二籽层图案; 从所述第二籽层图案形成导电图案以填充孔阵列;通过在所述模层上生长导电图案并连接所述导电图案而在所述模层上形成一导线;以及在所述导线上形成一保护层。 9. A method of manufacturing an inductor, comprising the steps of: forming a mold layer on a substrate comprising a conductive structure, wherein the mold layer comprises an inner surface having an array of apertures; on the inner surface of the hole array and formed on the mold of a diffusion barrier layer; a first seed layer is formed on the diffusion preventing layer; forming a cap layer on the first seed layer; the cap located hole array forming a cap layer on a second portion of the seed layer pattern; conductive pattern is formed to fill the hole arrays from the second seed layer pattern; by growing the conductive patterns on the mold layer and connecting the conductive pattern in the mold forming a conductor layer; and a protective layer formed on the wire.
10.如权利要求9所述的方法,其中形成所述第二籽层图案的步骤包括: 在所述帽盖层上形成一第二籽层;以及除去位于所述模层上的所述第二籽层的部分。 10. The method of claim 9, wherein said step of forming a second seed layer patterns comprises: a second seed layer on the capping layer; and removing the first layer is on the mold Part two seed layer.
Description  translated from Chinese

用于芯片上系统的电感器及其制造方法 System and method for manufacturing the inductor chip for

技术领域 Technical Field

本发明一般涉及一种电感器及制造该电感器的方法。 The present invention relates generally to a method for producing the inductor and the inductor. 更具体地,本发明 More particularly, the present invention

涉及一种用于芯片上系统(system-on-a-chip,SOC )的射频(RF )器件的电感器以及制造该电感器的方法。 Relates (RF) inductor device and a method of on-chip system (system-on-a-chip, SOC) for the manufacture of the RF inductor.

要求享受于2003年11月6日提交的韩国专利申请No. 2003 - 78195的优先权,该专利申请的全部公开内容在此引用作参考。 Claims the benefit of Korean Patent on November 6, 2003 filed No. 2003 - 78195 of priority, the entire disclosure of this patent application is hereby incorporated by reference.

背景技术 Background

SOC包括与系统所有元件一起集成的单个微芯片。 SOC includes integrated system with all components single microchip. 该系统的元件一般包括独立工作的半导体器件或电路。 Elements of the system generally includes a semiconductor device or circuit work independently. 例如,用于无线通讯的SOC —般包括微处理器、数字信号处理器(DSP)、随机存储器(RAM)器件和只读存储器(ROM)。 For example, SOC for wireless communications - typically includes a microprocessor, a digital signal processor (DSP), a random access memory (RAM) devices and Read Only Memory (ROM). 通常,SOC元件集成在大规模集成(LSI)电路或集成电路(IC)上。 Typically, SOC components into large-scale integration (LSI) circuit or integrated circuit (IC) on.

在用于RF通讯的SOC中,半导体器件和RF电路通常集成在单个芯片上。 In the SOC for RF communications, the semiconductor devices and RF circuits typically integrated on a single chip. 在集成电路形成在半导体基板上之后,电感器一般形成在SOC的集成电路上。 After the integrated circuit formed on a semiconductor substrate, the inductor is generally formed on an integrated circuit SOC. 具有螺旋或螺线管结构的薄膜型电感器通常使用在SOC中,因为它易于与集成电路结合。 Having a helical structure of a thin film or a solenoid type inductors typically used in the SOC, because it is easy to combine with the integrated circuit. 另外,薄膜型电感器用于各种器件,例如电压控制振荡器(VCO)、滤波器或逆变器。 In addition, the thin film inductor for various devices, e.g., a voltage controlled oscillator (VCO), a filter or inverter.

传统的薄膜型电感器被公开在各种国家专利出版物中,例如包括韩国专利申请公开No. 2003 - 20603,韩国专利No. 348250和日本专利申请公开No. 1998 -241983。 Traditional film type inductor are disclosed in various national patent publications, for example, the Korean Patent Application Publication No. 2003 - 20603, Korean Patent No. 348250 and Japanese Patent Application Publication No. 1998 -241983.

图1A到IC是示出在上面提到的韩国专利申请公开中公开的制造常规电感器的方法的横截面图。 1A to IC is a cross sectional view of the above-mentioned Korean Patent Application Publication discloses a conventional manufacturing method of the inductor.

参考图1A,软磁薄膜15形成在基板10上,该基板形成在硅晶片上。 1A, a soft magnetic thin film 15 formed on the substrate 10, the substrate is formed on a silicon wafer. 软磁薄膜15具有包括氮化铁钽(FeTaN)层和钛(Ti)层的双层结构。 Soft magnetic thin film 15 has a two-layer structure including iron, tantalum nitride (FeTaN) layer and a titanium (Ti) layer.

氧化硅绝缘膜20形成在软it薄膜15上,用于电镀工艺的籽层(seediayer) 25形成在绝缘膜20上。 A silicon oxide insulating film 20 is formed on the flexible film 15 it, the seed layer (seediayer) 25 for the plating process is formed on the insulating film 20. 籽层25具有包括铜(Cu)层和铬(Cr)层的双层结构。 Seed layer 25 having a two-layer structure including copper (Cu) layer and a chromium (Cr) layer.

光敏膜30沉积在籽层25上,然后掩模35形成在光敏膜30上。 The photosensitive film 30 is deposited on the seed layer 25, a mask 35 is then formed on the photosensitive film 30. 通过掩模35的图案将光敏膜30曝光。 Through a mask pattern 35 exposing the photosensitive film 30. 掩模35的图案限定了具有线圈结构的电感器。 35 defines the mask pattern having an inductor coil structure.

参考图1B,通过对光敏膜30的曝光部分显影,穿过光敏膜30形成多个孔。 1B, the photosensitive film 30 by developing the exposed portion, the photosensitive film 30 is formed through the plurality of holes. 这些孔使位于光敏膜30下面的籽层25暴露出。 These holes so that the seed layer is a photosensitive film 30 is exposed below 25. 电感器的线圈40从籽层25形成以填充这些孔。 The inductor coil 40 is formed to fill these holes 25 from the seed layer. 线圏40通过使用包含铜的镀液的电镀工艺形成。 Juan line 40 is formed by using a copper plating solution containing a plating process.

参考图1C,除去光敏膜30并使用湿蚀刻工艺蚀刻掉线圈40的环之间暴露出的籽层25的部分以在绝缘膜20上完成线圈40。 With reference to Figure 1C, the photosensitive film 30 is removed using a wet etch process and etching away the seed layer coil portion 25 is exposed between the ring 40 to complete the coil 20 on the insulating film 40. 使用环氧树脂粘结膜45将线圈40贴附到上部磁膜50上,以在基板10上形成电感器。 An epoxy resin adhesive film 45 is attached to the upper coil 40 on the magnetic film 50, to form the inductor on the substrate 10.

在上述制造常规电感器的方法中,线圏40从籽层25填充光敏膜30中的孔的生长速率随孔尺寸的增加而显著下降。 In the method of manufacturing the conventional inductor, the line rings of 40 from the growth rate of the seed layer 25 is filled with the light sensitive film 30 holes with increasing pore size decreased significantly. 随电感器宽度和高度的增加, 线圈生长速率相应减慢,因此电感器及相关RF器件的制造时间和成本提高。 With the increase of the width and height of the inductor, coils corresponding growth rate slows, so manufacturing time and cost inductors and related RF devices increase. 然而,电感器具有足够的宽度和高度以确保电感器的所需电特性是重要的。 However, the inductor has a sufficient width and height to ensure the desired electrical characteristics of the inductor is important.

发明内容 DISCLOSURE

本发明提供了一种根据简化工艺制造的用于SOC的电感器。 The present invention provides a simplified manufacturing process of an inductor for the SOC. 本发明也提供了一种使用简化的工艺制造用于SOC的电感器的低成本方法。 The present invention also provides a low cost method of using a simplified manufacturing process for the SOC of inductor.

根据本发明的一个方案, 一种电感器,包括形成在基板上的籽层和形成在籽层上的导线。 According to one aspect of the present invention, an inductor, comprising forming a seed layer on a substrate and forming a conductor on the seed layer. 导线通过连接多个从籽层生长的导电图案形成。 Wires formed from the seed layer is grown by connecting a plurality of conductive patterns. 优选在基板和籽层之间形成防扩散层,并优选在导线上形成保护层。 Preferably between the substrate and the seed layer anti-diffusion layer, and a protective layer is preferably formed on the wire. 另外,优选采用各自的导电图案填充包括孔阵列的模层。 In addition, each of the conductive pattern is preferably used to fill the mold layer comprises an array of holes.

根据本发明的另一个方案, 一种电感器,.包括:包含导电结构的基板、 形成在基板上的籽层、形成在籽层上的模层以及形成在籽层上的导线。 According to another aspect of the present invention, an inductor, comprising: a substrate comprising a conductive structure, forming a seed layer on the substrate, the seed layer is formed on the mold layer and forming a conductor on the seed layer. 模层包括暴露出籽层的孔阵列,导线电连接到导电结构。 The mold layer includes hole arrays exposing the seed layer, electrically connected to the conductive wire structure. 通过连接多个从籽层生长的导电图案而形成导线。 By connecting a plurality of layers grown from the seed of the conductive pattern formed wire. 优选在导线上形成保护层。 The protective layer is preferably formed on the wire.

根据本发明的又一个方案, 一种电感器,包括:包含导电结构的基板、 包含具有形成在基板上的内表面上的孔阵列的模层、在孔阵内表面上形成的籽层以及在籽层形成的导线。 According to another aspect of the present invention, an inductor, comprising: a substrate comprising a conductive structure, comprising an array of mold layer having an aperture formed on the inner surface on the substrate, the seed layer is formed on the inner bore surface of the array and in Wire seed layer. 导线电连接到导电结构并通过连接多个从籽层生长的导电图案而形成。 Leads electrically connected to the conductive structure and is formed by connecting a plurality of growth from the seed layer conductive pattern. 根据本发明的又一个方案, 一种电感器,包括:包含导电结构的基板、 According to another aspect of the present invention, an inductor, comprising: a substrate comprising a conductive structure,

包含具有在基板上形成的内表面的孔阵列的模层、在孔阵列内表面上和在模层上形成的第一籽层、在第一籽层上形成的帽盖层、在位于孔阵列中的部分帽盖层上形成的第二籽层以及在第二籽层形成的导线。 The mold layer comprising hole arrays having inner surfaces formed on the substrate, an array of apertures in the upper surface of the first seed layer is formed on the mold layer, a first capping layer on the seed layer, the hole pattern located The second seed layer formed on the part of the capping layer and the lead in the second seed layer. 导线电连接到导电结构并通过连接多个从第二籽层生长的导电图案而形成。 Leads electrically connected to the conductive structure and is formed by connecting a plurality of the second seed layer is grown from the conductive pattern.

根据本发明的又一个方案,提供一种制造电感器的方法。 According to another aspect of the present invention, there is provided a method of manufacturing an inductor. 该方法包括在籽层上形成模层,其中模层包括暴露出籽层的孔阵列。 The method comprises forming a mold layer on a seed layer, wherein the mold layer comprises hole arrays exposing the seed layer. 该方法进一步包括从籽层在模层上形成导电图案以填充孔阵列。 The method further comprises a conductive pattern to fill the array of holes from the seed layer is formed on the mold layer. 该方法进一步包括通过在模层上生长导电图案并连接导电图案而在模层上形成导线。 The method further comprises growing the conductive patterns and connected by a conductive pattern formed on the mold layer conductor layer on the mold. 优选该方法进一步包括在对莫层上形成防反射层并在导线上形成保护层。 Preferably, the method further comprises the Mo layer is formed on the anti-reflective layer and a protective layer formed on the wire.

根据本发明的又一个方案,提供一种制造电感器的方法。 According to another aspect of the present invention, there is provided a method of manufacturing an inductor. 该方法包括在包括导电结构的基板上形成包括具有内表面的孔阵列的模层并且在孔阵列的内表面上和在模层上形成防扩散层。 The method includes forming includes an array of holes having an inner surface of the mold layer on a substrate includes a conductive structure and the diffusion preventing layer on the inner surface of the hole pattern formed on the mold layer. 该方法进一步包括在位于孔阵列中的部分防扩散层上形成籽层图案,并从籽层图案形成导电图案以填充孔阵列。 The method further comprises forming seed layer patterns on a portion located in the aperture array diffusion preventing layer, and the conductive pattern to fill the hole arrays formed from the seed layer pattern. 该方法还进一步包括通过在模层上生长导电图案和通过连接导电图案而在模层上形成导线并在导线上形成保护层。 The method further comprises growing the conductive pattern through the upper mold layer and by connecting the conductive pattern formed on the mold layer and the conductor layer is formed on the protective conductor.

仍然根据本发明的另一个方案,提供一种制造电感器的方法。 According to still another aspect of the present invention, there is provided a method of manufacturing an inductor. 该方法包 The method pack

括在包括导电结构的基板上形成包括孔阵列的模层并且在孔阵列的内表面上和在模层上形成防扩散层。 Comprising a substrate including the conductive structure is formed on the mold layer comprises hole arrays and on the inner surface of the hole arrays and on the mold layer diffusion preventing layer. 该方法进一步包括在防扩散层上形成第一籽层,并在第一籽层上形成帽盖层,并在位于孔阵列中的部分帽盖层上形成第二籽层。 The method further includes forming a first seed layer on the anti-diffusion layer and a cap layer formed on the first seed layer, and the second seed layer is formed on a bore array portion of the cap seal. 该方法还进一步包括从第二籽层图案形成导电图案以填充孔阵,在模层上生长导电图案并连接导电图案,由此在模层上形成导线,并在导线上形成保护层。 The method further comprises forming conductive patterns from the second seed layer patterns to fill the hole arrays, growing the conductive patterns on the mold layer and connecting the conductive pattern, thereby forming a conductor layer on the mold, and the protective layer is formed on the conductor.

根据本发明,通过使用电解工艺或非电镀层工艺,可以以相对低的成本很容易地制造包括螺旋导线的电感器。 According to the present invention, by using an electrolytic plating process or processes, it can be relatively low cost easily manufactured including wire spiral inductors. 通过使用电解工艺或非电镀层工艺 By using an electrolytic plating process or processes

(elec加less plating process),调节导电图案的生长速率,将导线的宽度和高度调节到所需值。 (Elec plus less plating process), the growth rate adjusting conductive pattern, the width and height of the wires is adjusted to the desired value. 与传统的电感器的高度相比,导线的所需高度经常相对的高。 Compared with the conventional inductor height, the desired height of the wire is often relatively high. 调节导线的高度使得由本发明形成的电感器具有在基板上的相对高的螺旋结构。 Adjust the height of the wire so that the inductor formed by the present invention has a relatively high helix structure on the substrate.

与形成电感器有关的制造时间和成本由于显著的裕度而潜在地降低,因为不需要用于将电感器与形成在基板上的下布线结构电连接的额外工艺。 Forming inductor manufacturing time and costs associated due to the significant margin and potentially reduced because the inductor is not required for additional process structure formed in the electric wiring on the substrate under the connection. 因此,优选电感器直接形成在常规基板上而没有任何另外的工艺,由此使用传统的制造电感器的制造装置,易于以低成本在基板上形成具有相对高的螺旋结构的电感器。 Therefore, preferably the inductor is formed directly on a conventional substrate without any additional process, thereby using the conventional manufacturing apparatus for manufacturing an inductor, readily formed at low cost with a relatively high spiral structure on the substrate inductor.

附图说明 Brief Description

附图示出本发明几个选择的实施例。 The drawings illustrate embodiments of the present invention, several selected. 在图中: In the drawings:

图1A到图1C是示出制造常规电感器的方法的横截面图; 1A to FIG. 1C is a cross-sectional view illustrating a conventional method of manufacturing the inductor;

图2是示出根据本发明一个方案形成的典型电感器的平面图; 2 is a diagram showing a typical inductor formed in accordance with one aspect of the present invention, a plan view;

图3A到图3E是沿图2的I到I,线切割的图2中所示的电感器的横截面 3A to 3E of Figure 2 along I to I, line cutting of the inductor shown in FIG. 2 in cross-section

图; Figure;

图3A到图3E示出图2中所示电感器的制造方法; 图4A是进一步示出图3B所示的掩模元件的平面图; 图4B是进一步示出用于形成根据本发明的一个方案的导电图案的掩模的平面图; 3A to 3E show a method of manufacturing the inductor shown in Figure 2 a; FIG. 4A is a plan view of Figure 3B further illustrates the mask element shown; Fig. 4B is a diagram showing a further embodiment of the present invention is formed according to the a plan view of a conductive pattern on the mask;

图5A是示出图3C中的导电图案的横截面的电子显^敖图; 图5B是示出图3E中电感器平面图的电子显微图; 图6是示出根据本发明的另一个方案的典型电感器的横截面图; 图7A到图7E是示出图6中典型电感器的制造方法的横截面图; 图8是示出图7C中的导电图案的横截面的电子显微图; 图9A到图9E是示出根据本发明的另一个方案的电感器的制造方法的横截面图; 5A is a diagram electron ^ Ao Fig. 3C shows a cross-section of the conductive pattern; Fig. 5B is a diagram showing a plan view of the inductor electron micrograph Figure 3E; Fig. 6 is a diagram showing another embodiment of the present invention electron micrograph of a cross-sectional view of FIG. 8 is a diagram illustrating the conductive pattern 7C; cross-sectional diagram of a typical inductor; FIG. 7A to FIG. 7E is a cross-sectional view diagram illustrating a typical method of manufacturing the inductor of 6 ; 9A to 9E is a cross-sectional view showing a manufacturing method of the inductor to another aspect of the present invention;

图IOA和图IOB是示出图9D中的导电图案的横截面的电子显微图; Figure IOA and IOB is an electron micrograph shown in FIG. 9D cross-section of the conductive pattern;

图11是示出仍根据本发明的另一个方案的典型电感器的平面图; Figure 11 shows a plan view of a typical still inductor according to another aspect of the present invention;

图12是沿II到II,线切割的图11中所示的电感器部分的横截面图;以 Figure 12 along II to II, part cross-sectional view of the inductor shown in FIG cutting line 11; to

及, And,

图13A到图13D是示出图12中电感器的制造方法的横截面图。 13A to 13D is a cross-sectional view of the manufacturing method of the inductor 12. 具体实施方式 DETAILED DESCRIPTION

现在参考附图更详尽地描述本发明,在附图中示出了本发明的几个实施例。 Several are now described in more detail with reference to the accompanying drawings of the present invention, it is shown in the drawings embodiments of the present invention. 在图中,为了清楚起见,层和区的厚度被放大,且全文中相同的附图标记表示相同的元件。 In the drawings, for clarity, the thickness of layers and regions are exaggerated, and the text in the same reference numerals denote the same elements. 可以理解当元件如层、区和基板被称作在另一元件"上"或"之上"时,该层即可直接在另一元件之上,也可具有插入元件。 You can understand when an element such as layer, region and the substrate is referred to as being "on" another element or "above", the layer can be directly on top of another element may have inserted elements.

图2是示出根据本发明的一个方面的电感器的平面图。 Figure 2 is a plan view showing an inductor aspect of the present invention. 在图2中,电感 In Figure 2, the inductor

器200包括螺旋导线190。 200 includes a helix 190. 螺旋导线190电连接到作为在基板上形成的下布线元件一部分形成的触头160。 Spiral electrical conductor 190 is connected to the contact portion 160 is formed as a lower wiring element formed on the substrate. 所以,螺旋导线190位于包括触头160的下布线之上并以螺旋结构形成。 So, the helix 190 is located above the contact includes a lower wiring 160 and form a spiral structure. 导线190优选通过连接从籽层(未示出)生长出的多个导电图案而形成。 Preferably connected by wires 190 from the seed layer (not shown) is grown to form a plurality of conductive patterns.

电感器200 —般包括在基板上形成的籽层。 Inductor 200 - as including seed layer formed on the substrate. 包括绝缘隔层或导电层的多层结构通常形成在基板和籽层之间。 Or a conductive layer including an insulating barrier multilayer structure is typically formed between the substrate and the seed layer.

图3A到图3E为沿图2中从I到I,延伸的线截取的横截面图。 Figure 3A to 3E is taken along from I 2 to I, extending cross-sectional view taken on the line. 图3A到图3E示出图2电感器的制造方法。 Figures 3A to 3E illustrates a method of manufacturing an inductor of FIG.

参考图3A,绝缘层150形成在包括下导电结构的基板(未示出)上。 3A, the insulating layer 150 is formed on a substrate including a lower conductive structure (not shown). 通过使用光刻工艺部分蚀刻绝缘层150,穿过绝缘层150形成开口155。 Partially etched by a photolithography process using the insulating layer 150, an opening 150 is formed through the insulating layer 155. 下导电结构一般包括字线、位线、导电图案和焊盘(pad)。 A lower conductive structure generally includes a word line, bit line, the conductive pattern and pads (pad). 开口155暴露出电连接到下导电结构的下布线(未示出)的一部分。 Exposing a portion of the opening 155 is electrically connected to the lower wiring (not shown) of the lower conductive structure.

导电层形成在绝缘层150上以填充开口155。 Conductive layer 150 is formed on the insulating layer 155 to fill the opening. 导电层通常使用如金属或掺杂的多晶硅的导电材料形成。 The conductive layer is typically used such as a metal or doped polysilicon is formed of a conductive material. 通过化学机械抛光(CMP)工艺、内蚀刻工艺(etch back process )、 CMP工艺和内蚀刻工艺的组合、或者光刻工艺来部分地去除导电层,直到暴露出绝缘层150。 By chemical mechanical polishing (CMP) process, the etching process (etch back process), a combination of a CMP process and the etching process, or photolithography process to partially removing the conductive layer until the insulating layer 150 is exposed. 作为部分去除导电层的结果,电连接到下布线的触头160形成在开口155中。 As a result of the removal of part of the conductive layer, a wiring electrically connected to the lower contact 160 is formed in the opening 155. 包括触头160的下布线电连接到位于基板上的下导电结构。 Including lower wiring electrical contact 160 is connected to a conductive structure located on the lower substrate.

防扩散层165形成在触头160和绝缘层150上。 Diffusion preventing layer 165 is formed on the contact 160 and the insulating layer 150. 防扩散层165通常具有单层结构和多层结构。 Diffusion preventing layer 165 typically has a single layer structure and a multilayer structure. 单层结构通常使用钽(Ta)、氮化钽(TaN)、氮化铝钽(TaAlN)、硅化钽(TaSi2)、钛(Ti)、氮化钛(TiN)、氮化硅钛(TiSiN) 或氮化鴒(WN)。 Layer structure typically use a tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum silicide (TaSi2), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN) or nitride ling (WN). 多层结构通常使用包括由钽(Ta)、氮化钽(TaN)、氮化铝钽(TaAlN )、硅化钽(TaSi2 )、钛(Ti )、氮化钛(TiN )、氮化硅钛(TiSiN) 和氮化钨(WN)构成的一组之中的的至少两种元素的混合物。 Typically comprises the use of a multilayer structure of tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum silicide (TaSi2), titanium (Ti), titanium nitride (TiN), titanium nitride ( mixture TiSiN) and tungsten nitride (WN) among a group of at least two elements constituted. 防扩散层165 通常具有50到1000埃的厚度。 Diffusion preventing layer 165 typically has a thickness of 50-1000 angstroms. 防扩散层165防止包含在导电图案185 (参见图3C)中的铜扩散到下部结构。 Diffusion preventing layer 165 prevents the conductive pattern included in 185 (see Fig. 3C) in the diffusion of copper into the substructure.

籽层170形成在防扩散层165上。 Seed layer 170 is formed on the diffusion preventing layer 165. 籽层170通常由化学汽相沉积(CVD) 工艺或如溅射工艺或真空蒸发工艺的物理汽相沉积(PVD)工艺形成。 Seed layer 170 is usually formed by a chemical vapor deposition (CVD) process or a physical vapor deposition such as sputtering or vacuum evaporation process (PVD) process. 籽层170优选由PVD工艺形成,并具有大约100到5000埃的厚度。 Seed layer 170 is preferably formed of a PVD process, and having a thickness of about 100 to 5000 Angstroms. 作为选择,籽层170使用导电材料形成,该导电材料基本上防止了诸如氧化膜或氮化膜 Alternatively, the seed layer 170 is formed using a conductive material, the conductive material is substantially prevented such as an oxide film or nitride film

的表面绝缘膜的形成。 Formed surface of the insulating film. 例如,籽层170使用铂(Pt)、钇(Pd)、镍(Ni)、 银(Ag)、金(Au)或其合金形成。 For example, the seed layer 170 using platinum (Pt), yttrium (Pd), a nickel (Ni), silver (Ag), gold (Au) or an alloy thereof.

光刻胶膜涂在籽层170上。 Photoresist film is coated on the seed layer 170. 通过具有如图3B所示的多个孔的掩模220 将光刻胶膜曝光。 Through a mask 220 having a plurality of holes as shown in Fig. 3B will be exposed photoresist film. 光刻胶膜用作模层(mold layer)来形成导线190,如图3D所示。 The photoresist layer film is used as the mold (mold layer) formed conductor 190, shown in Figure 3D. 光刻胶膜通常具有大约500到30000埃的厚度以充分长出导电图案185 (参见图3C)。 The photoresist film typically has a thickness of about 500 to 30,000 angstroms to grow sufficiently conductive pattern 185 (see FIG. 3C).

图4A是进一步示出图3B中的掩模220的平面图。 4A is further illustrated in the plan view of FIG. 3B mask 220.

参考图3B和4A,掩模220包括图案215,该图案具有以螺旋形设置的多个孔阵列,以形成具有导线190的电感器200。 With reference to FIG. 3B and 4A, the mask 220 includes a pattern 215, the pattern array having a plurality of apertures arranged in a spiral to form a wire 190 having an inductor 200. 当使用掩模220对光刻胶膜曝光时,光刻胶膜按照掩模220的螺旋形形成多个孔阵列。 When using a mask 220 exposing the photoresist film, the photoresist film 220 in accordance with a mask to form a plurality of helical array of holes. 在曝光的光刻胶膜显影之后,包括多个按照掩模220的螺旋形设置的沟道(trench)或孔阵列180的光刻胶图案175形成在籽层170上。 After the exposed photoresist film is developed, the photoresist pattern 180 includes a plurality of mask 220 in accordance with a spiral channel settings (trench) or array of holes 175 are formed on the seed layer 170.

虽然图4示出形成在掩模220中的一对螺旋形孔阵,但是孔阵的数量和尺寸是可以变化的,它根据电感器200的尺寸和结构变化。 Although Figure 4 shows a mask 220 is formed in a pair of spiral-shaped hole array, but the number and size of the hole arrays may be varied, it changes in size and structure of the inductor 200.

图4B是显示用于形成根据本发明的一个具体实施例的导线的掩模230 的平面图。 4B is a mask for forming the wire 230 in accordance with an example of a plan view of a specific embodiment of the present invention.

参考图4B,掩模230包括具有多个根据电感器结构螺旋设置的沟道的图案225。 4B, the mask 230 includes a plurality of spiral inductor structure in accordance with the channel pattern 225 disposed. 沟道的尺寸和数量根据电感器的尺寸和结构变化。 Size and number of channels varies depending on the size and structure of the inductor.

现在参考图3B,使用掩模220对光刻胶膜曝光和显影,结果,具有孔阵列180的光刻胶图案175形成在籽层170上。 Referring now to Figure 3B, using the mask 220 exposing and developing the photoresist film, the result, a resist pattern 180 having an array of apertures 175 are formed on the seed layer 170. 沟道或孔阵列180部分地暴露出籽层170。 Channel or hole pattern 180 is partially exposed seed layer 170. 沟道或孔阵180优选具有大约500到30000埃的深度。 Channel or aperture arrays 180 preferably has a depth of about 500 to 30,000 angstroms.

根据本发明的一个方面,防反射层(ARL)形成在光刻胶膜上以保证光刻工艺的工艺裕度(process margin)。 According to one aspect of the invention, an anti-reflection layer (ARL) is formed on the photoresist film lithography process to ensure a process margin (process margin). 通过使用ARL作为蚀刻掩模对光刻胶膜构图,然后在籽层170上形成光刻胶图案175。 ARL by using the photoresist film as an etching mask patterned photoresist pattern 175 is then formed on the seed layer 170. ARL—般具有大约50到1000 埃的厚度。 ARL- generally have a thickness of about 50 to 1000 Angstroms.

在本发明的另一个方面中,考虑到连续的蚀刻工艺,在籽层170上形成蚀刻阻止层。 In another aspect of the present invention, in view of the continuous etch process, the etch stop layer 170 is formed on the seed layer. 然后在蚀刻阻止层上形成光刻胶图案175。 Photoresist pattern 175 is then formed on the etching stop layer. 蚀刻阻止层通常使用氮化物,例如氮化硅,形成。 An etching stop layer is generally used a nitride, such as silicon nitride, is formed.

参考图3C,通过电解镀层工艺(electrolytic plating process)从籽层170 将多个导电图案185形成在光刻胶图案175上,以填充沟道或孔阵列180。 3C, the through electroless plating process (electrolytic plating process) from the seed layer 170. The plurality of conductive patterns 185 are formed on the photoresist pattern 175, to fill the trench or hole arrays 180. 通常采用大约20到40mA/cm2的电流密度并使用包括硫酸铜(CuS04 )溶液、 硫酸(H2S04)溶液以及包括氯离子(CI—)的溶液的镀液进行电解镀层工艺。 Usually about 20 to 40mA / cm2 current density and electrolytic copper sulfate plating process comprising (CuS04) solution of sulfuric acid (H2S04) and a solution comprising chloride ions (CI-) bath was carried out. 导电图案185按照图3C中箭头所示的方向从籽层170生长,使得在光刻胶图案175上形成导电图案185的上部。 Conductive patterns 185 in the direction shown by the arrow in FIG. 3C grown from the seed layer 170, so that the upper conductive pattern 185 is formed on the photoresist pattern 175. 当导电图案185从籽层170在孔阵列180中生长时,在相对于基板的垂直方向上在孔阵列180中的生长加快,而沿相对于基板的水平方向在孔阵列180中的生长受到限。 When the conductive pattern 185 seed layer 170 grown from an array of apertures 180 in the vertical direction with respect to the growth of the hole array substrate 180 is accelerated, and along the horizontal direction of the substrate relative to the growth of the hole 180 in the array is limited . 一旦导电图案185 充满孔阵列180,则导电图案185的上部在光刻胶图案175上形成凸起。 Once the conductive pattern 185 full array of holes 180, 185 of the upper conductive pattern on the photoresist pattern 175 forming a projection.

参考图3D,用于形成图3C的导电图案185的电解镀层工艺被延续以在光刻胶图案175上形成导线190。 With reference to FIG. 3D, the conductive pattern 185 of FIG. 3C electrolytic plating process is used to form a continuation of the photoresist pattern 175 is formed on the conductor 190. 换句话说,在光刻胶图案175上导电图案185垂直和水平生长,直到导电图案185彼此连接,由此在光刻胶图案175 上形成导线190。 In other words, the resist pattern 175 on the conductive pattern 185 vertical and horizontal growth, until the conductive pattern 185 connected to each other, thereby forming a wire 190 on the photoresist pattern 175. 当由延续电解镀层工艺形成导线190时,导线l卯的上部通常具有蘑菇状。 When forming the continuation of the electroless plating process wire 190, upper wires l d generally have a mushroom shape.

现在给出用于形成导线190的工艺4既要,它包括一些额外的细节。 4 will now be given not only to the process for forming the wire 190, which includes some additional details. 导电图案185从籽层170垂直生长。 The conductive pattern 185 grows from the seed layer 170 vertically. 接下来,导电图案185在光刻胶图案175上水平和垂直生长,如图3C和图3D所示。 Next, the conductive pattern 185 on the photoresist pattern 175 in the horizontal and vertical growth, 3C and 3D shown in Fig. 然后根据它们的垂直和水平生长, 邻近的导电图案185在光刻胶图案175上彼此连接,导致导线190的形成。 Then according to their vertical and horizontal growth, the adjacent conductive pattern 185 on the photoresist pattern 175 is connected to each other, resulting in the formation of the conductor 190. 通过调节导电图案185的垂直和水平生长,将导线l卯的宽度和厚度调整到所需值。 By adjusting the conductive pattern 185 vertical and horizontal growth, will adjust the width and thickness of the wire l d to the desired value. 为了获得此结果, 一旦它们已经充满孔阵列180时,延续执行电解镀层工艺以进一步使导电图案185生长。 To achieve this result, once they have been filled with an array of holes 180, and continued to perform electroless plating process to further the growth of the conductive pattern 185. 进一步的生长使得邻近的导电图案185彼此连接,由此在光刻胶图案175上形成导线l卯。 Further growth so that adjacent conductive pattern 185 connected to each other, thereby forming a wire l sockets on the photoresist pattern 175. 为了使导线l卯形成具有所需的宽度和厚度,在充满孔阵列180后对导电图案185的生长进行有利地调节。 In order to lead l d formed with the desired width and thickness, hole after a full array of conductive pattern 185 180 growth were favorably adjusted. 导线190优选具有约1000到100000埃的厚度。 Wire 190 preferably has a thickness of about 1000 to 100,000 Angstroms. 通常导线190 在光刻胶图案175上具有足够的厚度,因为导电图案185的水平生长在孔阵列180是受限制的。 Wire 190 typically has a sufficient thickness on the photoresist pattern 175 because the horizontal growth of the conductive patterns 185 in the hole arrays 180 is limited.

参考图3E,除了位于导线190下面的一部分光刻胶图案175,光刻胶图案175被部分去除。 With reference to FIG. 3E, in addition to the wire 190 is located below a portion of the photoresist pattern 175, a resist pattern 175 is partially removed. 当光刻胶图案175被部分去除时,籽层170被部分暴露出。 When the photoresist pattern 175 is partially removed, the seed layer 170 is partially exposed. 部分除去暴露出的籽层170和防扩散层165以完成成具有螺旋结构的导线190。 Seed layer 170 is partially removed layer 165 exposed and non-proliferation in order to complete a wire having a spiral structure 190. 通过湿蚀刻工艺,部分除去光刻胶图案175、籽层170和防扩散层165。 By wet etching process, partial removal of the resist pattern 175, the seed layer 170 and the diffusion preventing layer 165. 使用有机剥离剂(stripper )、包括浓度相当高的臭氧(03)的溶液、或包括二氧化碳(C02)的标准清洁(SC)溶液进行湿蚀刻工艺。 An organic release agent (stripper), including a relatively high concentration of ozone (03) a solution, or a standard cleaning (SC) including carbon dioxide (C02) was subjected to wet etching process. 作为选择, 光刻胶图案175可以通过抛光工艺或剥离(stripping)工艺部分去除。 Alternatively, the photoresist pattern 175 may (stripping) process is partially removed by polishing process or peeling. 在本发明的一个实施例中,可以使用氟化氢(HF)溶液和过氧化氢(H202)溶液的混合物或氟化氬(HF)溶液和硝酸(HN03)溶液的混合物部分去除籽层170和防扩散层165。 In one embodiment of the present invention may be used hydrogen fluoride (HF) portion of the solution and the mixture of hydrogen peroxide (H202) solution or a mixture of argon fluoride (HF) solution and nitric acid (HN03) solution is to remove the seed layer 170 and the non-proliferation layer 165. 当在光刻胶图案175上形成ARL时,同时去除ARL 和光刻胶图案175。 When the photoresist pattern is formed on the ARL 175 ARL and simultaneously remove the photoresist pattern 175.

形成保护层195以包围导线190,由此完成电感器200,其优选包括多个导线190。 The protective layer 195 is formed to surround the conductor 190, thereby completing the inductor 200, which preferably includes a plurality of wires 190. 电感器200具有由多个导线190形成的螺旋结构。 Inductor 200 has a spiral structure formed by a plurality of wires 190. 一般使用碳化硅(SiC)或氮化硅(SiN)形成保护层195。 Typically silicon carbide (SiC) or silicon nitride (SiN) protective layer 195 is formed. 作为选择,保护层195具有包括碳化硅、氮化硅和碳氧化硅的至少两层膜的多层结构。 Alternatively, the protective layer 195 has a multilayer structure comprising silicon carbide, silicon nitride, silicon oxide and carbon at least two films. 保护层195优选具有约100到1000埃的厚度。 The protective layer 195 preferably has a thickness of about 100-1000 . 保护层195形成在防扩散层165的剩余部分的侧壁上、籽层170的剩余部分的侧壁上、光刻胶图案175的剩余部分的侧壁上,以及形成在螺旋结构的导线190上。 The protective layer 195 is formed on the remaining portion of the sidewall of the diffusion preventing layer 165, the sidewalls of the remaining portion of the seed layer 170, the remaining portion of the side wall of the photoresist pattern 175, is formed on the conductor 190 and the helical structure .

图5A是显示图3C中的导电图案的横截面的电子显微照片;图5B是显示图3E中电感器平面图的电子显微照片; 5A is a cross-sectional electron micrograph displayed in Figure 3C conductive pattern; FIG. 5B is a diagram showing a plan view of the inductor. 3E electron micrograph;

参考图5A和图5B,通过上述电解镀层工艺导电图案185垂直和水平生长,以在光刻胶图案175上形成包括螺旋导线190的电感器200。 5A and 5B, the electroless plating process by the above-described conductive patterns 185 grow vertically and horizontally, to form a helix 190 comprising inductor 200 on the photoresist pattern 175. 每个导电图案185具有蘑菇状的上部。 Each conductive pattern 185 having a mushroom-shaped upper portion.

图6是显示根据本发明的一个方面的电感器的横截面图。 Figure 6 is a cross-sectional view of the inductor of an aspect of the present invention. 根据该方面, 导线的制造方法包括与参考图3A到图3D描述的工艺相同的工艺。 According to this aspect, a method of manufacturing wire includes reference to Figures 3A to 3D of the same process described in the process.

参考图6描述电感器300的制造方法。 Manufacturing method described with reference to FIG. 6 of the inductor 300. 在具有绝缘层250的基板上制造电感器300,如以上所述那样该绝缘层具有穿过它的触头260。 Producing an inductor on a substrate 300 having an insulating layer 250, as described above, as the insulating layer having a contact 260 therethrough. 完全除去用于形成导线290的光刻胶图案,部分除去籽层270和防扩散层265。 Completely remove the wire used to form a resist pattern 290, partially removing the seed layer 270 and the diffusion preventing layer 265. 于是暴露出导线290的下部。 So the lower wire 290 is exposed.

保护层295形成在绝缘层250上、暴露出的籽层270和防扩散层265上、 以及导线290上。 The protective layer 295 is formed on the insulating layer 250, the seed layer 270 and the diffusion preventing layer 265 is exposed, and the wire 290. 保护层295通常具有由碳化硅、碳氧化硅或氮化硅构成的单层结构,或具有从碳化硅、碳氧化硅或氮化硅构成的组中选择的若干层的多层结构。 The protective layer 295 typically has a single layer structure made of silicon carbide, silicon oxycarbide or silicon nitride, or with a group from silicon carbide, silicon oxycarbide or silicon nitride multilayer structure of a plurality of selected layers. 从导线290的上部到绝缘层265形成保护层295,借此完全包围导线2卯。 265 to form a protective layer 295 from the upper wire 290 to the insulating layer, thereby completely surrounding the wire 2 d.

图7A到图7E是显示图6中电感器的制造方法的横截面图。 7A to FIG. 7E is a cross-sectional view of the manufacturing method of the inductor in FIG. 6. 在图7A到图7E中,未示出包括具有字线、位线和焊盘的下导电结构的基板。 In Figures 7A-7E, the substrate is not shown comprises a word line, bit line and the lower conductive pad structure.

参考图7A,绝缘层350形成在基板上。 With reference to FIG. 7A, the insulating layer 350 is formed on the substrate. 部分蚀刻绝缘层350以形成暴露出电连接到下导电结构的下布线的开口355。 Partially etched to form an insulating layer 350 is electrically connected to the lower wiring exposed at the opening of the conductive structure 355. 在绝缘层350上形成导电层以填充开口355。 Forming a conductive layer on the insulating layer 350 to fill the opening 355. 导电层可以使用金属或掺杂的多晶硅形成。 The conductive layer may be metal or doped polysilicon. 然后通过CMP工艺、内蚀刻工艺或CMP工艺和内蚀刻工艺的组合部分去除导电层。 Then by a CMP process, etching process or the combining section CMP process and an etching process to remove the conductive layer. 部分去除导电层直到暴露出绝缘层350。 Removing the exposed portion of the conductive layer until the insulating layer 350. 于是, 在开口355中形成电连接到下布线的触头360。 Thus, the wiring electrically connected to the lower contact 360 is formed in the opening 355. 包括触头360的下布线电连接到在基板上形成的下导电结构。 Including lower wiring electrical contact 360 is connected to the lower conductive structure on a substrate.

在绝缘层350和触头360上形成模层365。 Formed on the insulating layer 350 and the contact layer 365 360 die. 模层365可以使用氧化物或光刻胶形成。 Mold layer 365 may be formed using an oxide or a photoresist. 部分烛刻模层365以形成多个暴露出如上所述的触头360的沟道或孔阵列370。 Part candle engraving layer 365 to form a channel or hole arrays exposed as described above, a plurality of contacts 370 360. 模层365通常具有约500到30000埃的厚度,从而容易形成导线400 (参见图7D)并使下导电结构与导线400充分绝缘。 The mold layer 365 typically has a thickness of about 500 to 30,000 Angstroms, thereby easily forming a conductor 400 (see FIG. 7D) and the lower conductive structure 400 sufficiently insulated wires.

当使用氧化物形成模层365时,在模层365上另外形成光刻胶膜。 When using an oxide layer 365 is formed mold when the mold layer 365 additionally form a photoresist film. 使用如图4A或图4B所示的掩模将光刻胶膜曝光,以形成包括多个孔阵列或沟道的光刻月交图案。 Use the mask shown in Fig. 4A or 4B, the resist film is exposed to form an array comprising a plurality of holes or channels photolithography month cross pattern. 在光刻胶膜上另外形成约50到IOOO埃厚的ARL后,在模层365上形成光刻胶图案。 After the photoresist film is formed separately from about 50 to IOOO thick ARL, the mold layer 365 to form a photoresist pattern. 接着,使用光刻胶图案作为掩模蚀刻模层365, 由此形成具有深度为500到1000埃并穿过模层365的沟道或孔阵列370。 Next, using the resist pattern as a mask mold layer 365 is etched, thereby forming a depth of 500 to 1,000 angstroms and a channel through the mold layer 365, or an array of apertures 370.

当使用光刻胶形成模层365时,优选使用图4A或图4B中的掩模直接曝光模层365,从而形成穿过模层365的沟道或孔阵列370,其中沟道或孔阵列370具有内表面。 When using the photoresist layer 365 during molding, preferably using a mask in FIG. 4B or FIG. 4A directly exposing the mold layer 365, thereby forming a mold layer 365 through the channel or hole arrays 370, wherein the channel or hole arrays 370 It has an inner surface.

参考图7B,防扩散层375形成在模层365上、触头360上以及沟道或孔阵列370的内表面上。 Reference 7B, the diffusion preventing layer 375 is formed on the mold layer 365, the upper contact 360 and the inner surface of the channel or the array of holes 370. 防扩散层375具有约50到1000埃的厚度。 Diffusion preventing layer 375 having a thickness of about 50 to 1000 Angstroms. 防扩散层375通常具有单层结构或多层结构。 Diffusion preventing layer 375 typically has a single layer structure or a multilayer structure. 单层结构通常包括钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化鴒、氮化硅钛或其合金。 Single-layer structure typically includes tantalum, tantalum nitride, tantalum aluminum nitride, silicon nitride, tantalum, tantalum silicide, titanium, titanium nitride, ling, silicon nitride, titanium or alloys thereof. 多层结构通常包括由钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、 Multi-layer structure typically includes tantalum, tantalum nitride, tantalum aluminum nitride, silicon nitride, tantalum, tantalum silicide, titanium, titanium nitride,

通过CVD工艺或如溅射工艺或真空蒸发工艺的PVD工艺,第一籽层380 形成在防扩散层375上。 By CVD process or PVD process such as sputtering process or vacuum evaporation process, the first seed layer 380 is formed on the diffusion preventing layer 375. 第一籽层380具有大约100到5000埃的厚度。 The first seed layer 380 having a thickness of about 100 to 5000 Angstroms. 第一籽层380优选使用铜、钼、把、镍、银、金或其合金形成。 The first seed layer 380 is preferably copper, molybdenum, the nickel, silver, gold or an alloy thereof.

使用如铝的金属在第一籽层380上形成帽盖层385。 Using a metal such as aluminum capping layer 385 is formed on the first seed layer 380. 帽盖层385具有约IOO到500埃的厚度。 Cap layer has a thickness of about 385 to 500 angstroms IOO. 当除去在模层365上的部分籽层3卯时,作为帽盖层385中金属氧化的结果,在帽盖层385上形成金属氧化膜。 When removing the mold layer 365 part 3 seed layer Mao Shi, as a result of a metal oxide cap layer 385, and a cap layer 385 on the metal oxide film. 即,除了形成在孔阵列370中的帽盖层385的其它部分,帽盖层385的上部转换成金属氧化物绝缘膜,使得帽盖层385可以选择性地限制导电图案395的生长。 That is, in addition to an array of apertures formed in the other portion 370 of the cap layer 385, an upper cap layer 385 is converted into a metal oxide insulating film, so that the capping layer 385 may selectively limit the growth of the conductive pattern 395. (参见图7C)。 (See Fig. 7C). 所以,导电图案395可以在孔阵列370中快速生长,而导电图案395 可以在帽盖层385的金属氧化膜上緩慢生长。 Therefore, the conductive patterns 395 may rapidly grow in the hole arrays 370, the conductive patterns 395 may slowly grow on the metal oxide film cap layer 385. 使用铜、柏、钇、镍、银、金或其合金在帽盖层385上形成第二籽层3卯。 The second seed layer 3 is formed on the cap layer 385 d copper, cypress, yttrium, nickel, silver, gold or its alloys.

参考图7C,为了进行选择性的电解镀层工艺,通过CMP工艺、内蚀刻工艺或CMP工艺和内蚀刻工艺的组合除去一部分位于模层365上的第二籽层390。 With reference to FIG. 7C, in order to perform selective electroless plating process, by a CMP process, a combination of internal and etching process or CMP process in the etching process of removing a portion of the mold layer located on the second seed layer 365 390. 结果,第二籽层图案393形成在孔阵列370的内表面上。 As a result, the second seed layer pattern 393 is formed on the inner surface of the bore 370 of the array. 在孔阵列370的内表面上依次形成防扩散层375、第一籽层380、帽盖层385和第二籽层图案393,而在模层365上不形成第二籽层图案393。 On the inner surface of the aperture array 370 are sequentially formed diffusion preventing layer 375, a first seed layer 380, cap layer 385 and the second seed layer patterns 393, and the upper mold 365 without forming the second seed layer patterns 393 layers.

通过使用选择性电解镀层工艺,导电图案395从第二籽层图案393选择性地并垂直地生长,以填充孔阵列370。 By using a selective electroless plating process, the conductive pattern 395 and grow vertically from the second seed layer pattern 393 selectively to fill the hole arrays 370. 使用约20到40mA/cn^的电流密度和使用包括石克酸铜溶液、硫酸溶液以及包含氯离子的电镀溶液进行电解镀层工艺。 Use about 20 to 40mA / cn ^ current density and electrolytic plating process includes stone g acid copper solution, sulfuric acid solution and plating solution containing chloride ions were. 如上所述,由于导电图案395的水平生长被限制在孔阵列370中,所以导电图案395在孔阵列370中从第二籽层图案393垂直生长。 As described above, the level of growth of the conductive pattern 395 is limited to an array of apertures 370, 395 in the hole so that the conductive pattern array 370 vertical growth from the second seed layer pattern 393. 当连续地进行选择性的电解镀层工艺时,填充孔阵列370的导电图案395在模层365上水平地和垂直地生长。 When the continuous selective electroless plating process, filling the hole arrays 370 395 conductive pattern on the mold layer 365 grow horizontally and vertically. 包含金属氧化膜的帽盖层385限制在孔阵列370中的导电图案395的水平生长。 Cap layer 385 comprises a metal oxide film is limited to an array of apertures 370 in the conductive pattern 395 horizontal growth. 然而,因为由于帽盖层385在孔阵列370的上部形成瓶颈结构,所以在用导电图案395充满孔阵列370之后,导电图案395 水平和垂直生长。 However, because due to the capping layer 385 in the upper portion 370 of the aperture array forming a bottleneck structure, after the conductive pattern 395 is filled with an array of apertures 370, the conductive patterns 395 grow horizontally and vertically. 充满孔阵列370的导电图案395在如箭头所指示的水平和垂直方向上连续地生长,使得相邻的导电图案395彼此连接,形成具有所需宽度和高度的导线400。 Full aperture array 370 conductive pattern 395 in the horizontal and vertical directions as indicated by arrows grow continuously, so that adjacent conductive patterns 395 connected to each other to form a wire 400 having a desired width and height.

图8是示出图7C中的导电图案的横截面的电子显微图。 Figure 8 is an electron micrograph shown in Fig. 7C cross-section of the conductive pattern.

如图7C和图8所示,虽然导电图案395的水平生长在孔阵列370中受到限制,但在充满孔阵列370之后导电图案395仍然在垂直和水平方向都生长。 Fig. 7C and 8, although the horizontal growth of the conductive patterns 395 is limited in the hole arrays 370, but after full aperture array 370 conductive pattern 395 is still in the vertical and horizontal directions are grown. 结果,相邻的导电图案395彼此连接,从而形成导线400。 As a result, adjacent conductive patterns 395 connected to each other, thereby forming a wire 400.

参考图7D,具有所需宽度和高度的导线400通过连接相邻的导电图案395自第二籽层图案393形成在模层365上。 With reference to FIG. 7D, having a desired width and height of the wire 400 by connecting adjacent conductive patterns 395 from the second seed layer pattern 393 is formed on the mold layer 365. 导电图案395通过连续进行电解镀层工艺被连接。 The conductive pattern 395 is connected by a continuous electrolytic plating process. 在导电图案395充满孔阵列370后,可以有利地调节导电图案395的生长速率,以形成具有大约1000到100000埃高度的导线400。 After the conductive pattern 395 filled with an array of apertures 370 may be advantageously adjusted growth rate of the conductive pattern 395 to form a wire having a height of about 400 angstroms 1000-100000.

参考图7E,除了被导线400覆盖的部分,部分地除去帽盖层385、第一籽层380和防扩散层375。 With reference to FIG. 7E, in addition to part of the wire 400 is covered partially removed cap layer 385, a first seed layer 380 and the diffusion preventing layer 375. 形成保护层405以覆盖导线400,由此形成具有包括多个导线400的螺旋结构的电感器430。 The protective layer 405 is formed to cover the conductor 400, thereby forming an inductor having a spiral structure comprising a plurality of conductors 400 430. 可以使用氟化氢溶液和过氧化氢溶液的混合物或氟化氢溶液和硝酸溶液的混合物部分地去除帽盖层385、 第一籽层380和防扩散层375。 You can use the hydrogen fluoride solution and hydrogen peroxide solution or a mixture solution of hydrogen fluoride and nitric acid solution was partially removed cap layer 385, a first seed layer 380 and the diffusion preventing layer 375.

在本发明的一个实施例中,在去除模层365后,在导线400上形成保护层405。 In one embodiment of the present invention, after removing the mold layer 365, the wire 400 forming the protective layer 405. 当使用光刻胶形成模层365时,优选使用有机去除剂、包含相当高浓度的臭氧的溶液、或包含二氧化碳的SC溶液除去模层365。 When using the photoresist layer 365 during molding, preferably a solution comprising carbon dioxide SC removed the mold layer 365 is removed using an organic agent, containing relatively high concentrations of ozone solution, or. 当使用氧化物形成模层365时,优选通过使用硫酸溶液的湿蚀刻工艺或如活性离子蚀刻工艺或等离子体蚀刻工艺的干蚀刻工艺除去模层365。 When the mold is formed using an oxide layer 365, it is preferable to use a wet etching process through a sulfuric acid solution, or as a dry etching process or a reactive ion etching process of removing plasma etching process mold layer 365.

参考图7E,优选使用碳化硅或氮化硅形成保护层405。 With reference to Figure 7E, the protective layer 405 is preferably formed using silicon carbide or silicon nitride. 保护层405具有约100到1000埃的厚度。 The protective layer 405 has a thickness of about 100-1000 . 保护层405覆盖暴露出的导线400下面的帽盖层385、第一籽层380和防扩散层375的侧壁。 A protective layer covering the exposed wire 405 400 below the cap layer 385, a first seed layer 380 and the sidewall diffusion barrier 375.

在本发明的一个实施例中,保护层405具有包括由碳化硅、氮化硅和碳氧化硅构成的组中的至少一种成分的多层结构。 In one embodiment of the present invention, the protective layer 405 having a multilayer structure comprising the group consisting of silicon carbide, silicon nitride and silicon oxycarbide constitutes at least one component.

图9A到图9E是示出根据本发明的一个方案的电感器的制造方法的横截面图。 9A to 9E is a cross-sectional view illustrating a method of manufacturing an inductor of the present invention.

参考图9A,绝缘层450形成在包括下导电结构的基板上。 With reference to Figure 9A, the insulating layer 450 is formed on a substrate including a lower conductive structure. 绝缘层450 优选使用氧化物或氮化物形成。 Insulating layer 450 is preferably formed using oxide or nitride. 通过光刻工艺部分蚀刻绝缘层450,然后穿过绝缘层450形成开口455。 Partially etched through a photolithography process the insulating layer 450, and then through the insulating layer 450 is formed an opening 455. 下导电结构一般包括字线(word line )、位线(bit line)和焊盘。 A lower conductive structure generally includes a word line (word line), a bit line (bit line) and the pad. 开口455暴露出电连接到下导电结构的下布线。 455 exposed electrical wiring connected to the lower opening of the lower conductive structure.

金属或掺杂多晶硅的导电层形成在绝缘层450上以填充开口455。 Metal or doped polysilicon conductive layer 450 is formed on the insulating layer 455 to fill the opening. 通过CMP工艺、内蚀刻工艺、CMP工艺和内蚀刻工艺的组合来部分去除导电层, 从而在开口455中形成触头460。 By a CMP process, a combination of the etching process, CMP process and the etching process to the conductive layer is partially removed, so that the opening 455 in the contact 460 is formed. 触头460电连接到下布线。 Contact 460 is electrically connected to the lower wiring. 因此,包括触头460的下布线电连接到下导电结构。 Therefore, under the electrical wiring includes a contact 460 is connected to the lower conductive structure.

具有约500到30000埃厚度的模层465形成在绝缘层450和触头460上。 Of about 500 to 30,000 angstroms thickness of the mold layer 465 is formed on the insulating layer 450 and the contact 460. 可以使用氧化物或光刻胶形成模层465。 You can use an oxide or a photoresist layer 465 is formed mold. 部分蚀刻模层465以形成暴露出如上所述的触头460的多个沟道或孔阵列470。 Partially etched mold layer 465 to form a plurality of channels or hole pattern described above expose contacts 470 460. 沟道或孔阵列470具有1000 到30000埃的深度。 Channel or hole pattern 470 has a depth of 1000-30000 Angstroms.

当使用氧化物形成模层465时,在模层465上另外形成光刻胶膜。 When using an oxide layer 465 is formed mold when the mold layer 465 additionally form a photoresist film. 使用如图4A和图4B所示的一种掩模将光刻胶膜曝光,以形成包括多个孔阵列或沟道的光刻胶图案。 Use of a mask as shown in FIG. 4A and 4B exposing the resist film to form a resist pattern comprising an array of a plurality of holes or channels. 在光刻胶膜上通常也形成约50到IOOO埃厚的ARL, 然后在模层465上形成光刻胶图案。 The photoresist film is formed usually from about 50 to IOOO thick ARL, a resist pattern is then formed on the mold layer 465. 接着,使用光刻胶图案作为蚀刻掩模蚀刻模层465,由此形成穿过模层465的沟道或孔阵列470。 Next, using the photoresist pattern as an etch mask layer 465 is etched mold, thereby forming a mold layer 465 through the channel or hole arrays 470. 当使用光刻胶形成模层465时,优选使用图4A或图4B中的一种掩模直接曝光模层465而不形成另外的光刻胶膜,由此形成穿过模层465的沟道或孔阵列470,其中沟道或孔阵列470具有内表面。 When using the photoresist layer 465 during molding, preferably using a mask in FIG. 4A or FIG. 4B directly exposing the mold layer 465 is formed without additional photoresist film, thereby forming a channel through the mold layer 465 or an array of apertures 470, wherein the channel or hole arrays 470 having an inner surface. 优选在模层465上形成另外的ARL以保证光刻工艺的工艺裕度。 ARL is preferably formed another layer in the mold 465 to ensure that the process margin by a photolithography process.

参考图9B,具有约50到1000埃厚度的防扩散层475形成在模层465上、 触头460上以及孔阵列470的内表面上。 9B, the having about 50 to 1000 Angstroms of diffusion preventing layer 475 is formed on the mold layer 465, the upper contact 460 and the inner surface of the hole array 470. 防扩散层475通常具有单层结构或多层结构。 Diffusion preventing layer 475 typically has a single layer structure or a multilayer structure. 单层结构通常包括钽、氮化钽、氮化铝钽、氮化珪钽、硅化钽、 钛、氮化钛、氮化钨、氮化硅钛或其合金。 Single-layer structure typically includes tantalum, tantalum nitride, aluminum nitride, tantalum, tantalum nitride, Gui, tantalum silicide, titanium, titanium nitride, tungsten nitride, silicon nitride, titanium or alloys thereof. 多层结构通常包括由钽、氮化钽、 氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化鴒、氮化硅钛以及其合金构成的组的至少两种成分。 The group consisting of a multilayer structure typically includes tantalum, tantalum nitride, tantalum aluminum nitride, silicon nitride, tantalum, tantalum silicide, titanium, titanium nitride, ling, silicon nitride, titanium, and alloys composed of at least two components .

通过CVD工艺或如賊射工艺或真空蒸发工艺的PVD工艺,具有大约100 到5000埃的厚度的籽层480形成在防扩散层475上。 By a CVD process or as a thief shot process or vacuum evaporation process PVD process, with a thickness of the seed layer is about 100-5000 angstroms 480 formed on the diffusion preventing layer 475. 籽层480优选使用铜、 鉑、钯、镍、银、金或其合金形成。 Seed layer 480 is preferably formed using copper, platinum, palladium, nickel, silver, gold or an alloy thereof.

参考图9C,在触头460上和在位于孔阵列470内表面的防扩散层475上形成籽层图案483以实现选择性非电镀层工艺。 With reference to FIG. 9C, on the contact form seed layer patterns 460 and 483 in order to achieve a non-selective plating process an array of apertures 470 located on the inner surface of the diffusion preventing layer 475. 通过使用CMP工艺、内蚀刻工艺或CMP工艺和内蚀刻工艺的组合部分除去籽层480直到暴露出防扩散层475来形成籽层图案483。 By using the CMP process, a combination of part or CMP process in the etching process and the etching process within the seed layer 480 is removed until the diffusion preventing layer 475 is exposed to form the seed layer pattern 483. 结果,防扩散层475和籽层图案483被定位在孔阵列470的内表面上,而只有防扩散层475位于模层465上。 As a result, the diffusion preventing layer 475 and patterned seed layer 483 is positioned on the inner surface of the aperture array 470, and only the diffusion preventing layer 475 is located on the mold layer 465.

参考图9D,使用选择性非电镀层工艺,从籽层图案483形成导电图案485,以填充孔阵列470。 With reference to FIG. 9D, the use of selective non-plating process, the seed layer pattern 483 is formed from a conductive pattern 485 to fill the hole arrays 470. 使用包含如甲醛或联氨的还原剂的硫酸铜溶液进行非电镀层工艺。 Copper sulfate solution containing formaldehyde or hydrazine as a reducing agent of the non-plating processes. 如上所述,因为在孔阵列470中导电图案485的水平生长受到限制,导电图案485在孔阵列470中从籽层图案483垂直生长。 As described above, since the horizontal holes 470 in the array of conductive pattern of growth restriction 485, the conductive pattern array of holes 470, 485 in the growth from the seed layer pattern 483 vertical. 当继续进行非电镀层工艺时,导电图案485充满孔阵列470,然后在模层465上水平和垂直生长。 When a non-plating process to continue, the conductive pattern 485 full array of holes 470 and the horizontal and vertical growth in the mold layer 465. 充满孔阵列470的导电图案485在如箭头所示的水平和垂直方向上继续生长,由此相邻的导电图案485彼此连接,形成具有所需宽度和高度的导线490。 Full aperture array 485 conductive pattern 470 in the horizontal and vertical directions as indicated by arrows continue to grow, whereby adjacent conductive pattern 485 connected to each other to form a wire having a desired width and height of 490.

图IOA和图10B是示出图9D中的导电图案485的横截面的电子显微图。 Figure IOA and 10B are diagrams showing the conductive pattern 9D electron micrograph of a cross-section of 485. 参考图9D、图IOA和图10B,随着非电镀层工艺的进行,导电图案485 从籽层图案483垂直生长以填充孔阵列470。 With reference to FIG. 9D, FIG IOA and 10B, the non-plating layer as the process, the conductive pattern 485 from the seed layer patterns 483 are vertically grown to fill an array of 470 holes. 然后,导电图案485在模层465 上垂直和水平生长。 Then, the conductive pattern 485 in the mold layer 465 in the vertical and horizontal growth. 在本实施例中,导电图案485由非电镀层工艺形成,使得导电图案485具有相对密集的结构。 In the present embodiment, the conductive pattern 485 is formed of a non-plating process, so that the conductive pattern 485 has a relatively dense structure. 参考图9E,继续进行非电镀层工艺以连接从籽层图案483生长的邻近的导电图案485。 With reference to FIG. 9E, proceed with a non-plating process to connect grown from the seed layer pattern 483 adjacent conductive pattern 485. 在模层465上导电图案485在垂直和水平方向连续生长,结果邻近的导电图案485在模层465上彼此连接。 In the mold layer 465 on the conductive patterns 485 continuously grow in horizontal and vertical directions, the results of the adjacent conductive pattern 485 connected to each other in the mold layer 465. 如图9D、 10A和10B所示, 在导电图案485从籽层图案483以垂直方向生长后,它们在模层465上在垂直和水平方向上生长。 As shown in Figure 9D, 10A and 10B, after the conductive pattern 485 from the seed layer pattern 483 to grow vertically, they grow in the vertical and horizontal directions in the mold layer 465. 导线4卯通过连接导电图案485形成。 Mao connection wire 4 is formed by a conductive pattern 485. 通常在导电图案485充满孔阵列470后调节导电图案485的生长速率,以形成所需宽度和高度的导线490。 Usually in the conductive pattern 485 full array of holes 470 after adjusting the growth rate of the conductive pattern 485 to form the desired width and height of the wire 490.

参考图9E,具有约100到1000埃的厚度的保护层495形成在模层465 上以覆盖导线490。 With reference to FIG. 9E, a protective layer thickness of about 100-1000 495 is formed on the mold layer 465 to cover the wire 490. 可以使用碳化硅或氮化硅形成保护层495。 Silicon carbide or silicon nitride may be used to form a protective layer 495.

除去位于模层465上的部分保护层495以完成覆盖导线490的保护层495。 Removing the mold layer located on the portion of the protective layer 465 495 490 to complete the protective layer covering the wire 495. 结果,在基板上形成了具有螺旋导线490的电感器500。 As a result, formed on a substrate having a spiral inductor conductor 490 500.

在本发明的一个实施例中,在除去模层465后,形成保护层495以覆盖导线490。 In one embodiment of the present invention, after removing the mold layer 465 to form a protective layer 495 to cover the wire 490. 由于未除去位于导线490之下的防扩散层475,所以防扩散层475 的侧壁也被保护层495覆盖。 Because not remove the wire 490 is located below the diffusion preventing layer 475, so the sidewall diffusion barrier 475 is also covered with a protective layer 495.

图11是示出根据本发明一个实施例的电感器的平面图,图12是沿从I1 到II,延伸的线切割的图11中电感器部分的横截面图。 Figure 11 is a plan view illustrating an inductor embodiment of the present invention, FIG. 12 is a direction from the I1 to II, Fig extending cutting line cross-sectional view of part of the inductor 11.

参考图11和图12,电感器600包括直接连接到下布线560的螺旋导线590,该下布线560包括用于电信号输入输出的焊盘570。 With reference to FIG. 11 and FIG. 12, an inductor 600 includes a lower wiring 560 is directly connected to the coil wire 590, the lower wiring 560 including pads 570 for input and output of electrical signals. 换句话说,在电感器600中,螺旋导线590直接连接到下布线560的端部(焊盘570 )而没有另外的电触头将它连接到下布线560。 In other words, the inductor 600, spiral wire 590 is directly connected to the lower end portion of the wiring 560 (pad 570) without additional electrical contacts to connect it to the lower wiring 560. 另外的电触头的省略有助于更简单、 更低成本的制造工艺,因为它省去了触头形成工艺。 Additional electrical contacts omitted contribute to a more simple, lower cost manufacturing process, because it eliminates the need for the contact formation process.

穿过下布线560的一部分而形成开口515,在下布线560中螺旋导线590 是从开口515通过,以便防止螺旋导线590连接到下布线560。 Wiring portion 560 is formed through the lower opening 515, the lower wiring helix 590 from opening 515 through 560 in order to prevent the spiral wire 590 connected to the lower wiring 560. 螺旋导线590 直接连接到下布线560的端部(焊盘570 ),而因为开口515是穿过部分下布线560形成的,所以螺旋导线590不与下布线560接触。 Helix 590 is directly connected to the lower end portion of the wiring 560 (pad 570), and since the opening 515 is formed through the portion of the lower wiring 560, so that the helix 590 is not in contact with the lower wires 560.

图13A到图13D是示出图12中电感器的制造方法的横截面图。 13A to 13D is a cross-sectional view of the manufacturing method of the inductor 12.

参考图13A,绝缘层550形成在包括下导电结构的基板上。 With reference to FIG. 13A, the insulating layer 550 is formed on a substrate including a lower conductive structure. 通常使用氧化物或氮化物形成绝缘层550。 Typically formed using oxide or nitride insulating layer 550.

使用金属或掺杂的多晶硅在绝缘层550上形成导电层,以在绝缘层550 上形成下布线560。 Metal or doped polysilicon conductive layer is formed on the insulating layer 550 to the insulating layer 550 is formed on the lower wiring 560. 如图ll所示,对导电层构图以形成下布线560,其电连接到下导电结构。 As shown in Fig ll, of the conductive layer is patterned to form a lower wiring 560 electrically connected to the lower conductive structure. 同时穿过下布线560的一部分形成具有预定宽度的开口515 ,在下布线560中螺旋导线590 (参见图13C)是从开口515通过。 While passing through the lower wiring portion 560 has an opening 515 having a predetermined width, lower wiring 560 helix 590 (see FIG. 13C) is from the opening 515 through. 优选开口515具有稍微大于螺旋导线590的宽度的宽度。 Opening 515 preferably has a width slightly larger than the width of the helix 590.

参考图13B,具有约500到30000埃的厚度的模层565形成在下布线560 上以填充开口515。 With reference to FIG. 13B, having a thickness of about 500 to 30,000 angstroms mold layer 565 is formed on the lower wiring 560 to fill the opening 515. 模层565可以使用氧化物或光刻胶形成。 Mold layer 565 may be formed using an oxide or a photoresist. 部分蚀刻模层565以形成多个通过开口515同时暴露出下布线560的端部(即焊盘)和绝缘层550的一部分的孔。 Partially etched mold layer 565 to form a part of the plurality of end holes through the opening 515 at the same time exposing the wiring 560 (ie land) and the insulating layer 550. 通过模层565形成的每个孔具有约500到30000埃的深度。 Each hole is formed through the mold layer 565 has a depth of about 500 to 30,000 angstroms. 如上所述,当使用氧化物形成模层565时,在模层565上另外形成光刻胶膜。 As described above, when the mold is formed using an oxide layer 565, the upper mold layer 565 additionally form a photoresist film. 使用基本和图4A或4B相同的掩模使光刻胶膜曝光,以形成包括多个孔的光刻胶图案。 Use basic and 4A or 4B same mask exposing the photoresist film to form a photoresist pattern comprising a plurality of apertures. 具有大约50到1000埃厚度的ARL通常另外形成在光刻胶膜上。 ARL having a thickness of about 50 to 1000 typically additionally formed on the photoresist film. 然后使用光刻胶图案作为蚀刻掩模来蚀刻模层565,从而形成穿过模层565的孔。 Then using the photoresist pattern as an etching mask to etch mold layer 565, thereby forming holes through the mold layer 565. 当使用光刻胶形成模层565时,可以使用基本和图4A 或图4B相同的掩模对模层565直接曝光,而不用形成另外的光刻胶膜,由此形成穿过模层565的孔,其中该孔具有内表面。 When the mold layer 565 is formed using a photoresist, and 4A may be used substantially the same or 4B, a mask layer 565 directly exposed to the mold, without forming an additional photoresist film, whereby the layer 565 is formed through the mold hole, wherein the bore has an inner surface. 可以在模层565上直接形成另外的ARL以保证光刻工艺的工艺裕度。 Another may be directly formed on the mold layer 565 ARL to ensure the process margin of the photolithography process.

具有大约50到1000埃厚度的防扩散层575形成在下布线560的暴露出的端部上、绝缘层550的暴露出的端部上、孔的内表面上和模层565上。 The end of the anti-diffusion layer has a thickness of about 50-1000 575 560 formed on the lower wiring exposed on the ends of the insulating layer 550 is exposed on the inner surface of the hole and the mold layer 565. 防扩散层575通常具有单层结构或多层结构。 Diffusion preventing layer 575 typically has a single layer structure or a multilayer structure. 单层结构通常包括钽、氮化钽、 氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化鴒、氮化硅钛或其合金。 Single-layer structure typically includes tantalum, tantalum nitride, tantalum aluminum nitride, silicon nitride, tantalum, tantalum silicide, titanium, titanium nitride, ling, silicon nitride, titanium or alloys thereof. 多层结构通常包括由钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化 Multi-layer structure typically includes tantalum, tantalum nitride, tantalum aluminum nitride, silicon nitride, tantalum, tantalum silicide, titanium nitride

通过CVD工艺或PVD工艺,在防扩散层575上形成具有大约100到5000 埃厚度的籽层。 By CVD process or PVD process, the diffusion preventing layer 575 in seed layer has a thickness of about 100-5000 is formed. 籽层优选使用铜、柏、4巴、镍、银、金或其合金形成。 Seed layer is preferably formed using copper, cypress, 4 bar, nickel, silver, gold or alloys thereof.

为了实现选择性电解镀层工艺或非电镀层工艺,在孔的内表面和下布线560的端部上通过除去位于模层565上的部分籽层而形成籽层图案580。 In order to achieve a selective electroless plating process or plating process, on the inner surface of the hole 560 and the lower end portion of the wiring portion located on the seed layer removing the mold layer 565 is formed on the seed layer 580 by patterning. 可以通过使用CMP工艺、内蚀刻工艺或CMP工艺和内蚀刻工艺的组合形成籽层图案580。 By using a CMP process, etching process, or a combination of the CMP process and the etch process of forming the seed layer pattern 580. 在此不蚀刻位于模层565上的防扩散层575。 This is not etched in the diffusion preventing layer 575 is located on the mold layer 565. 所以,籽层图案580和防扩散层575位于孔的内表面上,而只有防扩散层575位于模层565 上。 So, on the inner surface of the hole 575 located patterned seed layer and the diffusion preventing layer 580, and only the diffusion preventing layer 575 is located on the mold layer 565.

通过选择性电解或非电镀层工艺,从籽层图案580形成导电图案585以填充孔。 Or by selective electroless plating process, seed layer pattern 580 is formed from the conductive pattern 585 to fill the hole. 优选釆用大约20到40mA/cm2的电流密度,并使用包括硫酸铜溶液、 硫酸溶液以及包括氯离子的溶液的镀层溶液进行电解镀层工艺。 Preferably from about 20 to preclude the use of 40mA / cm2 current density, and the use of a solution comprising copper sulfate, sulfuric acid solution and the coating solution comprises a solution of chloride electrolysis plating process. 优选使用包含如曱醛或联氨的还原剂的硫酸铜溶液进行选择性非电镀层工艺。 Preferably containing an aldehyde or reducing agent such as hydrazine 曱 of copper sulfate solution for selective non-plating processes.

因为可以限制导电图案585在孔中的水平生长,导电图案585在孔中从籽层图案580垂直生长。 Since the conductive pattern 585 can restrict the level of growth in the holes, the conductive patterns 585 in the hole pattern vertical growth from the seed layer 580. 当继续进行选择性电解镀层工艺或非电镀层工艺直到导电图案585充满孔时,然后继续进行以使导电图案585在模层565上水平和垂直生长。 While continuing to selectively electroless plating process or plating process until the hole is filled when the conductive pattern 585, and then proceed to the conductive pattern 585 on the mold layer 565 horizontal and vertical growth. 导电图案585在如箭头所示的水平和垂直方向继续生长,由此相邻的导电图案585彼此连接。 Conductive patterns 585 in horizontal and vertical directions as indicated by the arrows continue to grow, whereby adjacent conductive pattern 585 connected to each other.

导电图案585电连接到下布线560的端部,而由于开口515导电图案585 与下布线560的另一部分分开。 Conductive pattern 585 is electrically connected to the lower end portion of the wiring 560, and the conductive pattern 585 since the opening 515 and lower portion 560 separated from the other wiring. 即除了下布线560的端部,导电图案585与下布线560电绝缘。 That is in addition to the end of the lower wiring 560, the conductive pattern 585 electrically insulated from the lower wiring 560. 结果,通过省去了另外的涉及将导电图案图585电连接到下布线560的触头形成工艺而可以使电感器600 (参见图13C)的制造方法简化并以低成本进行。 As a result, by eliminating the need for further relates to a conductive pattern 585 connected to the lower view of the electrical wiring 560 can contact formation process and the inductor 600 (see FIG. 13C) to simplify the manufacturing method and at low cost.

参考图13C,随着选择性电解或非电镀层工艺的进行,在导电图案585 从籽层图案580垂直生长充满孔之后,导电图案585在模层565上垂直和水平生长。 With reference to FIG. 13C, as the selective electrolytic plating process or after the conductive pattern 585 from the seed layer patterns 580 are vertically grown filled hole, the conductive patterns 585 on the mold layer 565 in vertical and horizontal growth. 结果,通过连接导电图案585从籽层图案580在模层565上形成具有所需宽度和高度的导线590。 As a result, by connecting the conductive pattern 585 is formed from the seed layer pattern 580 wire 590 having a desired width and height in the mold layer 565. 当导电图案585由非电镀层工艺形成时,导电图案585可以具有相对密集的结构。 When the conductive pattern 585 is formed by electroless plating layer technology, conductive pattern 585 may have a relatively dense structure. 具体而言,导电图案585在垂直和水平方向在模层565上连续生长,使得相邻的导电图案585在模层565上彼此连接。 Specifically, the conductive pattern 585 in the vertical and horizontal direction of the continuous layer 565 is grown on the die, so that adjacent conductive patterns 585 on the mold layer 565 connected to each other. 在导电图案585从籽层图案580垂直生长后,它们在模层565垂直和水平生长。 After the conductive pattern 585 vertical growth from the seed layer pattern 580, the mold layer 565 are grown in vertical and horizontal. 通过导电图案585的水平和垂直生长形成导线590。 Growth is formed by a conductive pattern wire 590 horizontal and 585 vertical. 优选在导电图案585孔后对导电图案585的生长速率进行调节以使导线590在模层565 上形成具有所需的宽度和高度。 Preferably after the conductive pattern 585 holes on the growth rate of the conductive pattern 585 is adjusted so that the wire 590 is formed with the desired width and height in the mold layer 565.

现在参考图13D,在去除位于模层565上的部分防扩散层575后,在模层565上形成具有约100到1000埃的厚度的保护层595,以覆盖导线590。 Referring now to Figure 13D, after removing the portion located on the diffusion preventing layer 575 on the mold layer 565, is formed on the mold layer 565 protective layer 595 having a thickness of about 100 to 1000 Angstroms, so as to cover the wires 590. 使用碳化硅、氮化硅形成保护层595。 Silicon carbide, silicon nitride protection layer 595. 所以,在基板上形成具有多个螺旋导线590的电感器600。 Therefore, the conductor 590 is formed on a substrate 600 having a plurality of spiral inductors. 在本发明的一个实施例中,在去除模层565后,形成保护层595以完全覆盖导线590。 In one embodiment of the present invention, after removal of the mold layer 565, protective layer 595 is formed to completely cover the wires 590.

总之,根据本发明,包括螺旋导线的电感器可以通过使用电解工艺或非电镀层工艺以相对低的成本而易于制造。 In short, according to the present invention, including the helix inductor by using an electrolytic plating process or process at a relatively low cost and easy to manufacture.

电感器优选包括具有所需宽度和高度的导线,这通过使用电解镀层工艺或非电镀层工艺来调节导电图案的生长速率获得。 Inductor preferably includes a desired width and height of the wire, which is adjusted growth rate of the conductive pattern obtained by electrolytic plating process or plating process.

因为导线的所需高度通常大于常规电感器,电感器可具有以基板上大的高度为特征的螺旋结构。 Because the desired height is generally greater than conventional wire inductor, the inductor may have to a large height on a substrate characterized helical structure.

因为省去了将电感器电连接到形成在基板上的下布线所通常要求的另外的工艺,因此形成电感器所需的制造时间和成本可以被大大降低。 Because omitted electrically connected to the inductor formed on the substrate additional process of the lower wiring normally required, thereby forming inductor manufacturing time and cost required can be greatly reduced. 可直接在常规的基板上形成电感器而无需任何另外的工艺,由此具有大高度的电感器可以使用制造电感器的常规装置以低成本而易于形成。 It may be formed directly on a conventional substrate without any additional inductors process, whereby the height of the conventional apparatus large inductors can be used to manufacture an inductor having a low cost and easily formed.

在附图和相应的文字描述中所公开的优选实施例是讲授的例子。 In the drawings and accompanying text description of the preferred embodiments disclosed it is taught by example. 本领域的技术人员可以理解,在不脱离本发明的范围的情况下可以对典型实施例在形式和细节上进行各种变化。 Those skilled in the art can appreciate that exemplary embodiments of various changes in form and detail without departing from the scope of the present invention the situation. 本发明的范围由所附的权利要求书限定。 The scope of the invention claimed by the appended claims.

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Classifications
International ClassificationH01L27/00, H01L27/04, H01L23/522, H01L27/08, H01F41/04, H01F17/00, H01L21/02
Cooperative ClassificationH01L2924/0002, H01L28/10, H01F41/041, H01L23/5227, H01L27/08, H01F2017/0046
European ClassificationH01L28/10, H01L27/08, H01L23/522L
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