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Publication numberCN100474581 C
Publication typeGrant
Application numberCN 03156270
Publication date1 Apr 2009
Filing date2 Sep 2003
Priority date2 Sep 2003
Also published asCN1591862A
Publication number03156270.1, CN 03156270, CN 100474581 C, CN 100474581C, CN-C-100474581, CN03156270, CN03156270.1, CN100474581 C, CN100474581C
Inventors洪志斌
Applicant日月光半导体制造股份有限公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Bridging multi-chip packaging structure
CN 100474581 C
Abstract  translated from Chinese
一种桥接型式的多芯片封装构造主要包括一载板、一第一芯片、一第二芯片及至少一导电凸块。 One kind of bridge type multi-chip package structure includes a carrier plate, a first chip, a second chip and at least one conductive bump. 该载板具有一上表面及对应的一下表面,多个载板接点,位在载板的上表面。 The carrier plate has an upper surface and a lower surface corresponding to a plurality of carrier board contacts, located in the upper surface of the carrier board. 第一芯片具有一第一主动表面,该第一芯片还具有至少一第一接点,配置在第一芯片的第一主动表面上。 A first chip having a first active surface, said first chip further having at least one first contact, a first active surface disposed on the first chip. 同样地,第二芯片具有一第二主动表面,该第二芯片还具有至少一第二接点,配置在第二芯片的第二主动表面上。 Likewise, the second chip having a second active surface, the second chip further having at least one second contact disposed on the second active surface of the second chip. 第一芯片的第一侧壁紧邻第二芯片的第二侧壁,且第一芯片的第一主动表面与第二芯片的第二主动表面为共平面的配置。 A first side wall adjacent to the second side wall of the first chip of the second chip, and a first active chip second active surface a first planar surface and the second configuration is common chip. 导电凸块在第一芯片的第一主动表面上及第二芯片的第二主动表面上延伸,使第一芯片的第一接点与第二芯片的第二接点电性连接。 And a second conductive bump on the active surface of the second chip extends on a first active surface of the first chip, the first joint connects the first chip and the second chip second contact electrically.
Claims(31)  translated from Chinese
1. 一种桥接形式的多芯片封装构造,其特征在于,包含:一载板,该载板具有一上表面及一下表面;一第一芯片,其具有一第一主动表面、一第一背面及一第一侧壁,该第一主动表面具有至少一第一接点且该第一侧壁连接该第一主动表面与该第一背面,该第一芯片以该第一背面面向该封装载板的上表面配置,并与该载板电性连接;一第二芯片,其具有一第二主动表面、一第二背面及一第二侧壁,该第二主动表面具有至少一第二接点且该第二侧壁连接该第二主动表面与该第二背面,该第二芯片以该第二背面面向该封装载板的上表面配置,并与该载板电性连接;及至少一第一导电凸块,该导电凸块依附在该第一芯片的第一主动表面上及第二芯片的第二主动表面上延伸,使该第一芯片与该第二芯片电性连接。 A bridged form of a multi-chip package structure, characterized by comprising: a carrier plate, the carrier plate having an upper surface and a lower surface; a first chip having a first active surface, a first back and a first side wall, the first active surface having at least a first contact and the first side wall connecting the first active surface and the first back, the first chip in the back of the first face of the package carrier The upper surface configuration, and is connected electrically with the carrier plate; a second chip having a second active surface, a back surface and a second sidewall of the second, the second active surface having at least a second contact and The second side wall connected to the second active surface and the second back, the second chip to the back surface of the upwardly facing surface of the second package substrate configuration, and connected electrically with the carrier; and at least one first conductive bumps, the conductive bumps attached to and extending on a second surface of the second chip is active on the first active surface of the first chip, so that the first chip to the second chip is connected electrically.
2. 如权利要求l所述的桥接形式的多芯片封装构造,其中更包含一封装材料,其包覆该第一芯片、该第二芯片、该载板的上表面及该第一导电凸块。 2. The bridge as claimed in claim l in the form of a multi-chip package configuration, which further includes a packaging material, which covers the first chip, the second chip, the upper surface of the carrier board and the first conductive bump .
3. 如权利要求l所述的桥接形式的多芯片封装构造,其中更包含多个导电组件,该导电组件设置在该载板的下表面。 L bridge form according to claim multi-chip package structure, which further includes a plurality of conductive elements, the conductive elements disposed on the lower surface of the carrier plate.
4. 如权利要求3所述的桥接形式的多芯片封装构造,其中所述导电组件为焊球。 4. A multi-chip package structure forms a bridge as claimed in claim 3, wherein said conductive component of the solder balls.
5. 如权利要求l所述的桥接形式的多芯片封装构造,其中所述第一芯片具有的第一接点至少部分位于该第一芯片的边缘上。 5. A bridge according to claim l in the form of a multi-chip package structure, wherein the first chip having at least a first contact portion located on the edge of the first chip.
6. 如权利要求l所述的桥接形式的多芯片封装构造,其中所述第二芯片具有的第二接点至少部分位于该第二芯片的边缘上。 L bridge form according to claim 6. The multi-chip package structure, wherein the second chip having a second contact point is at least partially located on the edge of the second chip.
7. 如权利要求l所述的桥接形式的多芯片封装构造,其中所述第一导电凸块为锡铅合金。 7. A bridge according to claim l in the form of a multi-chip package structure, wherein said first conductive bump of tin-lead alloy.
8. 如权利要求l所述的桥接形式的多芯片封装构造,其中所述第一导电凸块无铅导电材料。 L bridge form according to claim 8. A multi-chip package structure, wherein said first conductive bump lead-free conductive material.
9. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第一芯片的第一接点紧靠在该第二芯片的第二接点的旁边。 9. A multi-chip package structure as a bridge form according to claim 1, wherein the first chip in the first contact against a second side of the second chip contacts.
10. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第一导电凸块为导电胶。 10. The multi-chip package structure forms a bridge as claimed in claim 1, wherein said first conductive bump to conductive paste.
11. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第二芯片的第二侧壁紧邻于所述第一芯片的第一侧壁。 11. The multi-chip package structure forms a bridge as claimed in claim 1, wherein the second side wall adjacent said second chip to the first side wall of the first chip.
12. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第二芯片具有的第二接点紧邻于所述第一芯片具有的第一接点配置。 12. The multi-chip package structure forms a bridge as claimed in claim 1, wherein the second chip having a second contact adjacent to the first chip having a first contact configuration.
13. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第二芯片的主动表面与所述第一芯片的主动表面为共平面的配置。 13. The multi-chip package structure forms a bridge as claimed in claim 1, wherein the active surface of the second chip with the active surface of the first chip is coplanar configuration.
14. 如权利要求1所述的桥接形式的多芯片封装构造,更包含多条导电线,其中第一芯片通过所述导电线与该载板电性连接。 14. A multi-chip package structure as claimed in claim 1 in the form of bridges claims, further comprising a plurality of conductive lines, wherein the first chip through the conductive wire is connected electrically with the carrier plate.
15. 如权利要求1所述的桥接形式的多芯片封装构造,还包含多条导电线,其中第二芯片通过所述导电线与该载板电性连接。 15. The multi-chip package structure bridging form of claim 1, further comprising a plurality of conductive lines, wherein the second chip via the conductive wire is connected electrically to the carrier plate.
16. 如权利要求13所述的桥接形式的多芯片封装构造,其中所述第一芯片的第一侧壁及所述第二芯片的第二侧壁间设置一填充体,该填充体具有一上表面,该上表面同时与第一芯片的主动表面与第二芯片的主动表面为共平面。 16. The multi-chip package structure bridging form of claim 13, wherein a first sidewall between said first chip and said second chip of a second side wall provided with a filler, the filler having a On the surface, the upper surface simultaneously with the active surface active surface of the first chip and the second chip is coplanar.
17. 如权利要求1所述的桥接形式的多芯片封装构造,其中该载板还具有一开口,所述第一芯片及所述第二芯片容置于该开口中。 17. The multi-chip package structure forms a bridge as claimed in claim 1, wherein the carrier plate further having an opening, said first chip and said second chip received in the opening.
18. 如权利要求17所述的桥接形式的多芯片封装构造,其中还包含一散热片,所述散热片设置于该载板的下表面。 18. The multi-chip package structure bridging form of claim 17, further comprising a heat sink, the heat sink disposed on a lower surface of the carrier plate.
19. 如权利要求18所述的桥接形式的多芯片封装构造,其中还包含多个焊球,所述焊球设置于该载板的上表面。 19. The multi-chip package structure bridging form of claim 18, further comprising a plurality of solder balls, the solder balls provided on the surface of the carrier board.
20. 如权利要求17所述的桥接形式的多芯片封装构造,其中所述开口内部具有一周壁,该第一芯片及该第二芯片还分别具有第三侧壁及一第四侧壁,且该第三侧壁及第四侧壁分别紧邻该周壁。 20. The multi-chip package structure bridging form of claim 17, wherein the internal opening having a peripheral wall, the first chip and the second chip further respectively have third sidewall and a fourth sidewall, and The third and fourth sides were close to the sidewall of the peripheral wall.
21. 如权利要求17所述的桥接形式的多芯片封装构造,其中所述第二芯片的主动表面、所述第一芯片的主动表面及所述载板的上表面为共平面的配置。 21. The multi-chip package structure bridging form of claim 17, wherein the active surface of the second chip, the active surface of the first chip and the upper surface of the carrier plate is coplanar configuration.
22. 如权利要求20所述的桥接形式的多芯片封装构造,其中还包含一散热片,该散热片设置于该载板的下表面。 22. The multi-chip package structure bridging form of claim 20, further comprising a heat sink, the heat sink disposed on a lower surface of the carrier plate.
23. 如权利要求21所述的桥接形式的多芯片封装构造,其中还包含一散热片,该散热片设置于该载板的下表面。 23. The multi-chip package structure bridging form of claim 21, further comprising a heat sink, the heat sink disposed on a lower surface of the carrier plate.
24. 如权利要求22所述的桥接形式的多芯片封装构造,其中还包含多个焊球,所述焊球设置在该载板的上表面。 24. The multi-chip package structure bridging form of claim 22, further comprising a plurality of solder balls, the solder balls provided on the surface of the carrier board.
25. 如权利要求23所述的桥接形式的多芯片封装构造,其中还包含多个焊球,所述焊球设置在该载板的上表面。 25. The multi-chip package structure bridging form of claim 23, further comprising a plurality of solder balls, the solder balls provided on the surface of the carrier board.
26. 如权利要求17所述的桥接形式的多芯片封装构造,还包含多条导电线,其中第一芯片通过所述导电线与该载板电性连接。 26. The structure of the bridge in the form of multi-chip package according to claim 17, further comprising a plurality of conductive lines, wherein the first chip through the conductive wire is connected electrically with the carrier plate.
27. 如权利要求17所述的桥接形式的多芯片封装构造,还包含多条导电线,其中第二芯片通过所述导电线与该载板电性连接。 27. The multi-chip package in the form of a bridge structure according to claim 17, further comprising a plurality of conductive lines, wherein the second chip via the conductive wire is connected electrically to the carrier plate.
28. 如权利要求20所述的桥接形式的多芯片封装构造,还包含至少一第二导电凸块,其中第一芯片通过所述第二导电凸块与该载板电性连接。 28. The multi-chip package structure bridging form of claim 20, further comprising at least one second conductive bump, wherein the first chip is connected through the second conductive bumps electrically with the carrier plate.
29. 如权利要求20所述的桥接形式的多芯片封装构造,还包含至少一第二导电凸块,其中第二芯片通过所述第二导电凸块与该载板电性连接。 29. The multi-chip package structure bridging form of claim 20, further comprising at least one second conductive bumps, wherein the second chip is connected through the second conductive bumps electrically with the carrier plate.
30. 如权利要求21所述的桥接形式的多芯片封装构造,还包含至少一第二导电凸块,其中第一芯片通过所述第二导电凸块与该载板电性连接。 A multi-chip package structure 21 of the bridge 30. The form of claim, further comprising at least one second conductive bump, wherein the first chip is connected through the second conductive bumps electrically with the carrier plate.
31. 如权利要求21所述的桥接形式的多芯片封装构造,还包含至少一第二导电凸块,其中第二芯片通过所述第二导电凸块与该载板电性连接。 A multi-chip package structure 21 of the bridge 31. The form of claim, further comprising at least one second conductive bumps, wherein the second chip is connected through the second conductive bumps electrically with the carrier plate.
Description  translated from Chinese

桥接形式的多芯片封装构造技术领域本发明涉及一种多芯片封装构造,特别涉及一种桥接形式的多芯片封装构造。 TECHNICAL FIELD The multi-chip package structure of the present invention relates to bridged form of a multi-chip package structure, and more particularly to a bridge in the form of a multi-chip package structure. 背景技术近年来,随着电子技术的日新月异,高科技电子产品也相继问世, 因而更人性化、功能性更佳的电子产品不断推陈出新,然而各种产品无不朝向轻、薄、短、小的趋势设计,以提供更便利舒适的使用。 In recent years, as electronic technology advances, high-tech electronic products have also come out, and therefore more humane, better functional electronic product innovation, but a variety of products are all facing the light, thin, short, small trend designed to provide a more convenient and comfortable to use. 而一个电子产品的完成,电子封装扮演着重要的角色,其芯片间电性连接的方式, 一般常见的有两种,第一种为引线键合(wire-bonding)的方式、第二种为倒装芯片(flip chip)的方式。 The completion of an electronic products, electronic packaging plays an important role in the way electrical connection between its chips, in general there are two common, the first one for wire bonding (wire-bonding) approach, the second is flip-chip (flip chip) approach. 就引线键合的方式而言,其利用一引线键合机台将其引线键合头先移动至芯片的接点上,并利用尖端放电的方式将导电线的端点熔化而成为球型的样式,如此便可以将导电线打到芯片的接点上,然后便移动引线键合头到另一芯片的接点上,而在移动的过程中,引线键合头亦会放出导电线,最后再利用超音波熔接的方式将导电线打到另一芯片的接点上。 Wire bonding on the way, its use of a wire bonding machine to wire bonding head first to move contacts on the chip, and use sophisticated way discharge end of the conductive wire to melt and become the style of ball, so they can hit the conductive wire contacts the chip, and then they move on the wire bonding head to another chip contacts, and in the process of moving, wire-bonding head will release conductive wire, and finally the use of ultrasound welding way contacts the conductive wire hit another chip. 接下来,将介绍一种已知利用引线键合方式的多芯片封装结构。 Next, we introduce a known wire bonding method utilizing multi-chip package structure. 请参照图1,其图示已知利用引线键合方式的多芯片封装结构的剖面示意图。 Please refer to FIG. 1, which illustrates the use of a cross-sectional schematic view of a known multi-chip package structure of wire bonding. 该封装结构包括一载板10、 一第一芯片12、 一第二芯片14、多条导电线160、 162、 164、 一封装材料18及多个焊球19。 The package structure comprises a carrier plate 10, a first chip 12, a second chip 14, a plurality of conductive wires 160, 162, 164, a packaging material 18 and a plurality of solder balls 19. 载板10具有一上表面102及对应的下表面104,而载板IO具有多个载板接点106 及第一芯片座105与第二芯片座109,载板接点106及第一芯片座105 与第二芯片座109位在载板10的上表面102上,并且载板接点106环绕在第一芯片座105与第二芯片座109的周围,而载板接点107位在载板10的下表面104上。 Carrier plate 10 has a lower surface 104 and an upper surface 102 corresponding, and carrier plate has a plurality of carrier contacts IO 106 and the first chip 105 and second chip carrier seat 109, 106 and the contact carrier plate 105 and the first chip carrier The second chip seat 109 on the upper surface 102 of the carrier board 10 and the contact carrier plate 106 surrounds the first chip 105 and second chip carrier seat 109, while the lower surface of the contact carrier 10 of 107 in the carrier plate 104. 第一芯片12具有一主动表面122及对应的第一背面124,而第一芯片12还具有多个第一芯片接点126,位在第一芯片12的主动表面122上。 The first chip 12 has an active surface 122 and back surface 124 corresponding to the first, and the first chip 12 further has a plurality of first chip contacts 126, 122 positioned on the active surface 12 of the first chip. 第一芯片12以其第一背面124并通过一黏着材料(未标示于图中)贴附到载板10的芯片座108上,而利用引线键合的方式使第一芯片12与载板10电性连接,其中导电线160的一端接合到第一芯片接点126上,而导电线160的另一端接合到载板接点106上。 The first chip 12 with its first back 124 and through an adhesive material (not shown in the figure) is attached to the chip carrier 10 of 108 seats, and the use of wire bonding manner of the first chip 12 and the carrier plate 10 electrically connected, wherein one end of the conductive wire 160 is bonded to the first chip contacts 126, 160 while the other end of the conductive wire is bonded to the carrier plate 106 contacts. 同样地,第二芯片14具有一第二主动表面142及对应的第二背面144,而第二芯片14还具有多个第二芯片接点146,位在第二芯片14的第二主动表面142上。 Likewise, the second chip 14 has a second back surface 142 and a second active surface 144 corresponding to the second chip 14 also has a plurality of second contacts 146 chips, a second position in the second chip 14 on the active surface 142 . 第二芯片14以其第二背面144并通过一黏着材料(未标示于图中)贴附到载板10的芯片座109上,而利用引线键合的方式使第二芯片14与载板10电性连接,其中导电线162 的一端接合到第二芯片接点146上,而导电线162的另一端接合到载板接点108上。 The second chip 14 on the back for its second 144 by an adhesive material (not shown in the figure) is attached to the chip carrier 10 of 109 seats, and the use of wire bonding a way that the second chip 14 and the carrier plate 10 electrically connected, wherein one end of the conductive wire 162 is joined to the second chip contacts 146, 162 while the other end of the conductive wire is bonded to the carrier plate 108 contacts. 此外,第一芯片12与第二芯片14通过导电线164电性导通。 In addition, the first chip 12 and second chip 14 through the conductive wire 164 electrically conductive. 另外,封装材料18包覆第一芯片12、第二芯片14、载板10 的上表面102及导电线160、 162及164。 In addition, the packaging material 18 covering the first chip 12, the second chip 14, the carrier plate 10 on the surface of the conductive line 102 and 160, 162 and 164. 在上述的封装结构中,第一芯片12通过导线164与第二芯片14 电性连接,然而由于导线164的截面积甚小并且长度甚长,因此特性阻抗匹配不良,使得讯号会被快速地衰减,并且在高频电路运作时, 会有电感电容寄生效应(Parasitics)的发生,以致产生讯号反射的情形。 In the above package structure, the first chip 12 via wire 164 connected to the second chip 14 electrically, but due to the cross-sectional area of the wire 164 is very small and the length very long, and therefore undesirable characteristic impedance, so that the signal will be quickly damped and a circuit operating at high frequencies, the parasitic inductance and capacitance will have the effect (Parasitics) occurs, thus resulting in the case of the reflected signal. 此外,由于导线164与第一芯片接点传输路径的面积甚小,不利于电压及电流提供,导致电源及接地的效果变差。 In addition, since the area of the contact wire 164 and the transmission path of the first chip is very small, is not conducive to providing the voltage and current, power and ground leads to less effective. 有鉴于此,为避免前述多芯片封装构造的缺点,以提升多芯片封装构造的芯片效能,实为一重要的课题。 In view of this, in order to avoid the aforementioned disadvantages of multi-chip package structure, in order to enhance the effectiveness of the chip multi-chip package structure, in fact, an important issue. 发明内容有鉴于上述课题,本发明的目的提供一种多芯片封装结构,以桥接型式的导电材料取代导电线,如此可縮短芯片间电性连接的距离, 使得多芯片封装结构的电性效能可以提高。 SUMMARY OF THE INVENTION In view of the above problems, an object of the invention to provide a multi-chip package structure, a conductive material bridging substituent type conductive wire, thus shortening the distance between the chips can be electrically connected, so that the electrical multi-chip package structure can Effectiveness increase.

由此,为了达成上述目的,本发明提出一种芯片封装结构,至少包括一载板、 一第一芯片、 一第二芯片及至少一导电凸块及多个焊球。 Thus, in order to achieve the above object, the present invention provides a chip package structure, comprising at least one carrier plate, a first chip, a second chip and at least one conductive bump and a plurality of solder balls. 载板具有一上表面及对应的下表面,载板还具至少一载板接点,均位在载板的上表面。 Carrier plate has an upper surface and a lower surface of the corresponding carrying plate also has at least one carrier board contacts are positioned on the surface of the carrier board. 第一芯片具有一第一主动表面,第一芯片还具有至少一第一芯片接点,配置在第一芯片的第一主动表面上。 A first chip having a first active surface, at least one first chip further having a first chip contacts disposed on a first surface of the first active chip. 同样地,第二芯片具有一第二主动表面,第二芯片还具有至少一第二芯片接点, 配置在第二芯片的第二主动表面上。 Likewise, the second chip having a second active surface, the second chip further has at least one second chip contacts disposed on the second active surface of the second chip. 其中,第一芯片及第二芯片以引线键合方式配置于载板上,并与载板电性连接。 Wherein the first chip and the second chip in wire bonding configuration to the carrier board and electrically connected to the carrier board. 此外,第一芯片的至少一第一侧壁紧邻第二芯片的第二侧壁,并且第一芯片的第一主动表面与第二芯片的第二主动表面为共平面的配置。 In addition, at least a first side wall adjacent to the second side wall of the first chip of the second chip, and the second active surface a first active surface of the first chip and the second chip is coplanar configuration. 导电凸块在第一芯片的第一主动表面上及第二芯片的第二表面上延伸,使第一芯片的第一接点与第二芯片的第二接点电性连接。 And a second conductive bump on the surface of the second chip, extending in a first active surface of the first chip, the first contact point and the second connection of the first chip-chip second contact electrically. 承上所述,其中芯片封装结构还包括一封装材料,包覆第一芯片及第二芯片、载板的上表面及导电凸块。 Said bearing, wherein the chip package structure further includes a packaging material, covering the first chip and the second chip, the upper surface and the carrier plate conductive bump. 第一芯片接点及第二芯片接点分别位在第一芯片及第二芯片的边缘上,且紧邻配置。 The first chip contact and a second chip contacts are positioned on the edge of the first chip and the second chip, and close to the configuration. 此外,导电凸块可以是锡铅合金、无铅导电材料或导电胶。 In addition, the conductive bumps can be tin-lead alloy, lead-free conductive material or conductive adhesive. 综上所述,本发明的多芯片封装结构,由于芯片间的接点可以透过导电凸块电性连接,因此芯片接点间的传导路径甚短,且传导路径的径宽甚大,故可以降低传导阻抗,而减缓讯号的衰减,并且可以适于在高频电路的运作,而减少电感电容寄生效应的发生。 In summary, the multi-chip package structure of the present invention, since the contacts between the chips can be connected through the electrically conductive bump, and therefore the conduction path between the chip contacts is very short, and the width of the conduction path of very large diameter, it is possible to reduce the conduction impedance, and the slowing of the signal attenuation, and can be adapted to the operation of high-frequency circuit, and reduce the occurrence of parasitic inductance and capacitance effects. 另外,由于导电凸块与芯片接点接触的面积甚大,且载板接点可以直接与芯片接点接触,故可以避免发生如引线键合结构的阻抗不匹配的现象,并且会有甚佳的电源及接地效果。 Further, since the area of contact with the conductive bumps of the chip contacts is very large, and the carrier may be in direct contact with the contact plate contacts the chip, so as to avoid the wire bonding structure of the impedance mismatch occurs, there will be very good and the power and ground effect. 以下将参照相关附图,说明依本发明较佳实施例的桥接形式的多芯片封装构造。 Below with reference to the relevant drawings, an example of a bridge in the form of a multi-chip package structure under this preferred embodiment of the invention. 附图说明 Brief Description

图l为一示意图,显示已知多芯片封装构造。 Figure l is a schematic view showing a multi-chip package structure is known. 图2为一示意图,显示本发明第一较佳实施例中的桥接形式的多芯片封装结构。 Figure 2 is a schematic view showing a first preferred embodiment of the present invention in the form of a bridge structure of multi-chip package. 图3为一示意图,显示本发明第二较佳实施例中的桥接形式的多芯片封装结构。 Figure 3 is a schematic view showing a second preferred embodiment of the present invention in the form of a bridge structure of multi-chip package. 图4为一示意图,显示本发明第三较佳实施例中的桥接形式的多芯片封装结构。 Figure 4 is a schematic view showing a third preferred embodiment of the present invention in the form of a bridge structure of multi-chip package. 图5为一示意图,显示本发明第四较佳实施例中的桥接形式的多芯片封装结构。 Figure 5 is a schematic view showing a fourth preferred embodiment of the present invention in the form of a bridge structure of multi-chip package. 图6为一示意图,显示本发明第五较佳实施例中的桥接形式的多芯片封装结构。 Figure 6 is a schematic view showing a fifth preferred embodiment of the present invention in the form of a multi-chip package bridged structure. 图7至图9为一示意图,显示本发明第四较佳实施例的一种桥接形式的多芯片封装结构制程的剖面示意图。 Figures 7 to 9 is a schematic cross-sectional schematic view of a bridge in the form of a fourth preferred embodiment of the present invention, a multi-chip package structure of the display process. 图中符号说明 10 载板102 载板上表面104 载板下表面105 第一芯片座106、 108 载板接点107 导电组件(焊球)109 第二芯片座12 第一芯片122 第一主动面124 第一背面126 第一芯片接点14 第—心片142 第二主动表面144 第二背面146 第二芯片接点160、 162、 164 导电线18 封胶体20 载板201 开口202 载板上表面203 周壁204 载板下表面206、 208 载板接点207 导电组件(焊球)21 散热片22 第一心片221 第一侧壁222 第一主动面223 第三侧壁224 第一背面226、 228 第一芯片接点24 第一心片241 第二側壁242 第二主动表面243 第四侧壁244 第二背面246、 248 第二芯片接点254 屏蔽层256 开口258 焊料259 导电凸块260、 262 导电线264 导电凸块268 导电凸块28 封胶体29 填充体292 填充体上表面具体实施方式图2揭示一种本发明第一较佳实施例的桥接形式的多芯片封装构造,其主要包括一载板20、 一第一芯片22、 一第二芯片24及一导电凸块264。 Symbols described in Figure 10 carrier board 102 carrier board surface 104 of the first chip carrier board seat surface 105 106 108 107 conductive component carrier board contacts (bumps) 109 second chip carrier 12 of the first chip 122 of the first active surface 124 The first contacts the back 14 of the first chip 126 - 142 Tablet second active surface 144 contacts the second back side 146 of the second chip 160, 162, 164 of the conductive wire 18 colloidal carrier board 20 202 201 open surface wall 204 carrier board 203 weeks Under the surface of the carrier board 206 208 207 conductive component carrier board contacts (bumps) 21 fin 22 of the first core sheet 221 of the first sidewall of the first active surface 223 222 224 first back third side 226, 228 of the first chip contact 24 of the first core sheet 241 second active surface of the second side wall 242 243 244 second back fourth side 246, 248 of the second chip 254 contacts the shield opening 258 256 259 conductive solder bumps 260, 262 of the conductive wire 264 conductive bump Block 268 colloidal conductive bumps 28 on the surface 29 filled DETAILED DESCRIPTION Figure 2 discloses a bridging member 292 filling a first preferred form of embodiment of the present invention, a multi-chip package structure, which includes a carrier plate 20, a The first chip 22, a chip 24 and a second conductive bump 264. 该载板20具有一上表面202及对应的一下表面204,多个载板接点206、 208,均位在载板20的上表面。 The carrier plate 20 has an upper surface 202 and lower surface 204 corresponding to the plurality of carrier contacts 206, 208 are positioned on the surface 20 of the carrier plate. 第一芯片22具有一第一主动表面222,该第一芯片22还具有至少一第一接点226,配置在第一芯片22的第一主动表面222上。 The first chip 22 has a first active surface 222, the first chip 22 also has at least a first contact 226, arranged on a first active surface 222 of the first chip 22. 同样地,第二芯片24具有一第二主动表面242,该第二芯片24还具有至少一第二接点246,配置在第二芯片24的第二主动表面242上。 Likewise, the second chip 24 has a second active surface 242, the second chip 24 also has at least a second contact 246, arranged on a second active surface 242 of the second chip 24. 其中,第一芯片22以其背面(第一背面224)并通过一黏着材料(如银胶)设置于载板20上;同样地,第二芯片24以其背面(第二背面224)并通过一黏着材料(如银胶)设置于载板20上。 Wherein, the first chip 22 with its back surface (back surface 224 first) by an adhesive material (e.g., silver paste) disposed on the carrier plate 20; in the same manner, the second chip 24 with its back surface (second back surface 224) and by an adhesive material (such as silver paste) is provided on the carrier plate 20. 导电线260电性连接第一芯片22的第一接点226与载板20的载板接点206,而导电线262电性连接第二芯片24的第二接点246 与载板20的载板接点208。 260 is electrically connected to the conductive wire 22 of the first chip 226 and the first contact carrier plate carrier plate 20 of the contact 206, and the conductive line 262 is electrically connected to the second contact 24 of the second chip 246 and the carrier plate 20 of the contact carrier plate 208 . 此外,第一芯片22的第一侧壁221紧邻第二芯片24的第二侧壁241 ,且第一芯片22的第一主动表面222与第二芯片24的第二主动表面242为共平面的配置,再者,第一芯片接点226及第二芯片接点246 分别位在第一芯片22及第二芯片24的边缘上,且紧邻配置。 In addition, the first 22 chips of the first side wall 221 of the second chip 24 adjacent to the second side wall 241, and the first active surface 22 of the first chip 222 and the second active surface 24 of the second chip 242 is coplanar configuration, and further, the first chip 226 and second chip contacts 246 contacts were positioned on the edge of the first chip 22 and second chip 24, and close to the configuration. 导电凸块264在第一芯片22的第一主动表面222上及第二芯片24的第二主动表面242上延伸,使第一芯片22的第一接点228与第二芯片24的第二接点248电性连接。 Conductive bump 264 and the second active surface of the second extension 24 of the chip 242 on the first active surface 222 of the first chip 22, the first chip 22 of the first contacts 228 and second contacts 248 of the second chip 24 electrically connected. 承上所述,该多芯片封装结构还包括一封装材料280,包覆第一芯片22及第二芯片24、载板20的上表面202及导电凸块264。 Cheng said that the multi-chip package structure further includes a packaging material 280, covering the first chip 22 and second chip 24, the upper surface of the carrier board 20 264 202 and the conductive bump. 此外,上述的导电凸块264可以是锡铅合金、无铅导电材料或导电胶。 Further, the conductive bumps 264 can be tin-lead alloy, lead-free conductive material or conductive adhesive. 如图3所示,本发明的第二较佳实施例的桥接形式的多芯片封装 As illustrated, the bridge forms a second preferred embodiment of the present invention, a multi-chip package 3

构造,当第一芯片22的第一侧边221与第二芯片24的第二侧边241 间具有一较大的空隙时,可先设置一填充体29,如不导电胶体。 Configuration, when the first side 221 of the first chip 22 and the second side edge 24 of the second chip 241 having a large gap, may be provided with a filler 29, such as a non-conductive colloid. 该填充体29的上表面与第一芯片22的第一主动表面222及第二芯片24的第二主动表面242共平面。 The second active surface 29 of the upper surface of the first active surface of the filling body 22 of the first chip 222 and second chip 24 of 242 co-planar. 接着,可以利用网板印刷的方式,形成一焊料到第一芯片接点226、第二芯片接点246及填充体的上表面292上, 其中焊料由一助焊剂(未绘示)及多个金属粒子(未绘示)所构成,金属粒子均匀地混合在助焊剂中。 Subsequently, screen printing can be used a way to form a solder joint 226 to the first chip, the second chip 292 contacts the upper surface 246 and filler, wherein the solder flux by a (not shown) and a plurality of metal particles ( not shown) of the composition, the metal particles are uniformly mixed in flux. 之后,便进行回焊的制程,使得金属粒子可以熔融聚合而固化形成导电凸块264到第一芯片接点226及第二芯片接点246上。 After that, it was back to the welding process, so that the metal particles may melt polymerization and cured to form a conductive bump on chip contacts 264 to the first 226 and second 246 chip contacts. 其中第一芯片接点226及第二芯片接点246可通过导电凸块264相互电性连接,而导电凸块264比如是锡铅合金或是无铅导电材料。 Wherein the first chip and the second chip 226 contacts the contact 246 through the conductive bumps 264 may be electrically connected to each other, and the conductive bumps 264 such as a tin-lead alloy or lead-free conductive material. 接着,请参照图4,为本发明的第三较佳实施例的桥接形式的多芯片封装构造。 Next, refer to FIG. 4, the bridge forms a third preferred embodiment of the present invention, a multi-chip package construction. 其中,载板20具有一开口201,第一芯片22及第二芯片24容置于该开口201中,而封胶体28包覆该载板20上表面202的部分、第一芯片22、第二芯片24及导电凸块264,并且使第一芯片22 及第二芯片24的背面外露的,以通过此进一步縮小整体封装构造的厚度。 Among them, the carrier plate 20 has an opening 201, the first chip 22 and second chip 24 is received in the opening 201, and the package material 28 coated on the surface of the carrier board 20 part 202, the first chip 22, the second chip 24 and the conductive bump 264, and the backside of the first chip 22 and second chip 24 are exposed to through this whole package to further reduce the thickness of the structure. 再者,承上所述,如图5所示,亦可设置一散热片21于载板20 下表面204,而第一芯片22及第二芯片24设置在散热片21上,如此更可提升封装体的散热效能,此为本发明的第四较佳实施例的桥接形式的多芯片封装构造。 Further, on the bearing, shown in Figure 5, the fins 21 may also be provided with a carrier plate 20 to lower surface 204, and the first chip 22 and second chip 24 is disposed on the heat sink 21, so more can improve the thermal performance of the package, the bridge forms a fourth preferred embodiment of the present invention, a multi-chip package structure. 承上所述,请参照图6,为本发明的第五较佳实施例的桥接形式的多芯片封装构造。 Cheng said, refer to Figure 6, the present invention in the form of a bridge fifth preferred embodiment of a multi-chip package structure. 载板20亦具有一开口201,第一芯片22及第二芯片24同时容置于该开口201中,而该开口201的大小恰可容置第一芯片22及第二芯片24。 Carrier plate 20 also has an opening 201, the first chip 22 and second chip 24 simultaneously received in the opening 201, and the size of the opening 201 can be accommodated just the first chip 22 and second chip 24. 其中,第一芯片22具有一第三侧边223,第二芯片24具有一第四侧边243,开口20内具有一周壁203,该第一芯片22及第二芯片24的侧壁紧邻开口的周壁203,且第一芯片22的第一 Wherein, the first chip 22 has a third side 223, a second chip 24 has a fourth side 243, the opening 20 has a peripheral wall 203, the side walls 22 of the first chip and the second chip 24 immediately adjacent the opening the peripheral wall 203, and the first 22 of the first chip

主动表面222、第二芯片24的第二主动表面242与载板20的上表面202共平面配置。 Active surface 222, on the surface of the second active surface 24 of the second chip 242 and the carrier plate 20 202 co-planar configuration. 接着,形成一第二导电凸块266以电性连接第一芯片22与载板20。 Then, forming a second conductive bump 266 electrically connected to the first chip 22 and the carrier plate 20. 同样地,另形成一第三导电凸块268以电性连接第二芯片24与载板20。 Similarly, the other forming a third conductive bump 268 electrically connected to the second chip 24 and the carrier plate 20. 不论是上述何种实施例,皆可于载板的上表面或下表面另植接多个焊球于其上,用以与外界电性导通的接点。 No matter what the above embodiment, the upper surface of the carrier board Jieke or lower surface of another plant connected to a plurality of solder balls thereon for contacts with the outside electrically conductive. 在上述的封装结构中,由于芯片接点间可以透过导电凸块电性连接,因此芯片接点间及芯片与载板接点间的传导路径甚短,且传导路径的径宽甚大,故可以降低传导阻抗,而减缓讯号的衰减,并且可以适于在高频电路的运作,而减少电感电容寄生效应(Parasitics)的发生。 In the package configuration, since the contact between the chip through the conductive bumps can be electrically connected, so the contact between the chip and the chip carrier conduction path between the contact plate is very short, and the diameter of the conductive path width is very large, it is possible to reduce conduction impedance, and the slowing of the signal attenuation, and can be adapted to the operation of high-frequency circuit, and to reduce inductance and capacitance parasitics (Parasitics) occurs. 此外,由于导电凸块与载板接点或芯片接点接触的面积甚大,且载板接点可以直接与芯片接点接触,因此其接触阻抗甚小,故可以避免发生阻抗不匹配的现象,以致产生讯号反射的情形。 In addition, since the area of contact with the conductive bump chip carrier contact or contacts is very large, and the carrier board contacts in direct contact with the chip contacts, so the contact resistance is very small, so avoid the impedance mismatch occurs, thus resulting in signal reflection situation. 另外,由于本发明可以改善芯片封装结构中如上所述的电性效能,因此会有甚佳的电源及接地的效果。 In addition, since the present invention can improve the electrical efficiency of the chip package structure as described above, so there will be very good power and ground effects. 在上述实施例中,以网板印刷的方式形成焊料于芯片接点上及载板点上,然而本发明形成焊料的方式并非仅限于此,请参照图7至图9, 亦可以先形成一屏蔽层(mask layer)254到第一芯片22的第一主动表面222、第二芯片24的第二主动表面242及载板20的上表面202上,当屏蔽层254为感光材质时,如光阻,便可以直接透过曝光的步骤而直接形成开口256,以暴露出第一芯片接点226、第二芯片接点246及载板接点208;当屏蔽层254为非感光材质时,便可以透过微影蚀刻等步骤而形成开口256,以暴露出第一芯片接点226、第二芯片接点246及载板接点208。 In the above example, to screen printing solder is formed on the chip contact and carrier point, however, the present invention is not limited to the formation of solder, refer to Figure 7-9, also can be formed a shield layer (mask layer) 254 to a first active surface 222 of the first chip 22, the upper surface 202 of the second active surface 24 of the second chip 242 and the carrier plate 20, when the shield layer 254 as a photosensitive material, such as photoresist , you can directly through the steps directly exposed to form an opening 256 to expose the first chip contacts 226, second chip contacts 246 and 208 carrier board contacts; when the shield layer 254 is non-photosensitive material, they can pass through the micro- Movies etching step to form an opening 256 to expose the first chip contacts 226, contacts 246 and the second chip carrier board contacts 208. 接着,便可以利用印刷的方式,形成一焊料258到屏蔽层254的开口256中,形成如图8所示的样式,其中焊料258由一助焊剂(未绘示)及多个金属粒子(未绘示)所构成,金属粒子均匀地混合在助焊剂中。 Then, they can take advantage of the printing method to form a solder layer 258 to the shield 254 aperture 256, the pattern is formed as shown in FIG. 8, which consists of a solder flux 258 (not shown) and a plurality of metal particles (not drawn shown) of the composition, the metal particles are uniformly mixed in flux. 之后,便进行回焊的制程,使得金属粒子可以熔融聚合而 After that, it was back to the welding process, so that the metal particles may melt polymerization

固化形成导电凸块259到第一芯片接点226、第二芯片接点246及载板接点208,如图9所示,其中第一芯片接点226可以通过导电凸块259 与第二芯片接点246电性连接。 Cured to form the conductive bumps 259 to the first chip contacts 226, second contacts 246 and the chip carrier board contacts 208, shown in Figure 9, wherein the first chip 226 via the contacts 259 and conductive bumps 246 electrically contacts the second chip connection. 同样地,第一芯片接点226可以通过导电凸块259与载板接点208电性连接。 Similarly, the first chip 208 contacts the contact 226 may electrically connected via the conductive bumps 259 and the carrier plate. 接着,便将屏蔽层254去除。 Then, they put the shield 254 removed. 其接下来的制程,如第一较佳实施例所述,在此便不再赘述。 Its next process, as in the first preferred embodiment described herein will not repeat them. 需说明的是,图4、 5、 6、 7、 8及9中各组件的参考符号与图3中的各组件的参考符号相对应。 It should be noted that FIG. 4, 5, 6, 7, 8 and 9, the components of the reference symbols and reference symbols in FIG. 3 correspond to each component. 于本实施例的详细说明中所提出的具体的实施例仅为了易于说明本发明的技术内容,而并非将本发明狭义地限制于该实施例,因此, 在不超出本发明的精神及以下申请专利范围的情况,可作种种变化实施。 Specific examples in the detailed description of the embodiments set forth only for ease of illustration teachings of the present invention, and the invention is not narrowly limited to this embodiment, therefore, the spirit and the following applications without departing from the invention The patentable scope of the case, can be used to implement various changes.

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