CN100464319C - Device and method for implementing communication between processes - Google Patents
Device and method for implementing communication between processes Download PDFInfo
- Publication number
- CN100464319C CN100464319C CNB2006100864818A CN200610086481A CN100464319C CN 100464319 C CN100464319 C CN 100464319C CN B2006100864818 A CNB2006100864818 A CN B2006100864818A CN 200610086481 A CN200610086481 A CN 200610086481A CN 100464319 C CN100464319 C CN 100464319C
- Authority
- CN
- China
- Prior art keywords
- interrupt
- communication unit
- register
- signal
- place
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
A method for carrying out communication between processors includes setting multiprocessor communication unit in multiprocessor system, calling said multiprocessor communication unit by each processor through control bus in order to carry out communication between processors through said multiprocessor communication unit. The device used for realizing said method is also disclosed.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of apparatus and method that realize communication between processes.
Background technology
ARM (a kind of brief instruction set computer processor) be use in the present embedded system a kind of very widely main flow RISC (brief instruction set computer) processor, nearly all in the world semiconductor factory commercial city produces the general-purpose chip based on the ARM architecture.ARM has huge market in fields such as wireless device, networking products, consumer electronics, automotive electronics, mass memory unit, imaging system and safety products.
ARM has very big advantage on operating system, and DSP (digital signal processor) has very big advantage on all kinds of mathematical algorithms of calculating, therefore, present many embedded systems have all adopted the framework of ARM+DSP, realize the application of aspects such as communication, medium by the framework of this ARM+DSP.
Communication scheme in the prior art between a kind of ARM and the DSP is: proposed a kind of multi-functional combined portable digital audio-frequency player in the prior art, it belongs to a kind of consumer electronics and computer peripheral equipment product.This digital audio-frequency player has multiple digital audio decoding and digital recording functions such as MP3, possess simultaneously that PC external sound card, mobile storage, language are re-reading, function such as electronic watch and perpetual calendar, support audios such as mega bass and surround sound, its firmware can be upgraded.
Above-mentioned digital audio-frequency player adopts the ARM+DSP dual-core architecture, and the decoding of the various compacted voice files of ARM kernel processes realizes mobile storage and external sound card function, supports multi-lingual demonstration; The DSP kernel carries out the processing of various audios; Adopt the power supply of class D power amplifier and usb bus.The main application of above-mentioned digital audio-frequency player is: external sound card of PC and loudspeaker, digital music is play, voice recording, mobile storage, FM radio, language playback device, electronic watch, electronic calendar and power amplifier etc.
The shortcoming of the means of communication in the above-mentioned prior art between ARM and the DSP is: in the dual-core architecture audio process of the ARM+DSP in this scheme, ARM and DSP communication mechanism between the two is fairly simple, can only be based on waiting for that interactive mode be inquired about, simple communication such as synchronous, be unfavorable for that system carries out computing faster, finishes more complicated function.
If promote the functional level of total system, must be on ARM the operation system, all kinds of audio algorithm of operation on DSP, so must synthetic operation between ARM and the DSP, simple rely on above-mentioned based on the inquiry of waiting for interactive mode, simple communication mechanism such as synchronous, will spend considerable resource between ARM and the DSP and remove to monitor or wait for the other side's behavior and state, the travelling speed of total system can not obtain the performance of high level ground.Simultaneously, the system of no good communication mechanism generally is difficult to support function or business such as real time operating system, file system, big data quantity computing between ARM and the DSP, is easy to cause the function singleness of system, and is even unstable.
Summary of the invention
In view of above-mentioned existing in prior technology problem, the purpose of this invention is to provide a kind of apparatus and method that realize communication between processes, thereby can realize carrying out fast between the processor, communication timely.
The objective of the invention is to be achieved through the following technical solutions:
A kind of device of realizing communication between processes, this device comprises multiprocessor communication unit and control bus, each processor is visited described multiprocessor communication unit by described control bus, and carries out communication between each processor by described multiprocessor communication unit
Described multiprocessor communication unit specifically comprises: read-write controller, code translator and interrupt register module, wherein:
Read-write controller: the address signal that the receiving end/sending end processor passes over by control bus, control signal, write enable signal and read enable signal according to this control signal generation, the enable signal of writing that produces is passed to code translator with the address signal of reading enable signal and receive;
Code translator: the address signal that read-write controller is passed over, write enable signal and read enable signal and decipher, the address signal after decoding is handled, write enable signal and read enable signal and pass to the interrupt register module;
Interrupt register module: comprise a plurality of interrupt registers, the address signal that passes over according to code translator, write enable signal, in corresponding interrupt register, writing effective value, and exporting corresponding interrupt control signal to the receiving end processor; Or the address signal that passes over according to code translator, read enable signal, from corresponding interrupt register, read effective value and output.
Described multiprocessor communication unit also comprises:
Impact damper: address signal and control signal that the receiving end/sending end processor passes over by control bus, this address signal and control signal are postponed to handle, address signal and control signal after handling are passed to read-write controller.
Described multiprocessor communication unit also comprises:
Mistake discrimination module: when the signal on the control bus meets the condition of makeing mistakes of control bus agreement, transmit wrong control signal, read-write controller is not produced effectively write enable signal and read enable signal to read-write controller.
Described interrupt register module specifically comprises:
Interrupt source register: comprise the figure place of setting, all corresponding interruption of each figure place is write enable signal according to what code translator passed over, is writing corresponding effective value on corresponding figure place;
Interrupt status register: comprise the figure place of setting,, on corresponding figure place, write corresponding effective value, export corresponding interrupt control signal to the receiving end processor according to the combination of the value of each in the interrupt source register; Or read enable signal according to what code translator passed over, from corresponding interrupt source register, read effective value and output.
Described interrupt register module also comprises:
OIER: comprise the figure place of setting, all corresponding interruption of each figure place is write enable signal according to what code translator passed over, is writing corresponding effective value on corresponding figure place; And in the OIER in value of each and the interrupt source register value of each make up, obtain the value of corresponding figure place in the interrupt status register.
Described interrupt register module also comprises:
Interrupt clear register: comprise the figure place of setting, all corresponding interruption of each figure place, according to the value that writes on the corresponding positions, it is invalid that the value of the corresponding positions of described interrupt source register is set to.
Described processor is: central processor CPU or microprocessor MPU or microcontroller MCU or RISC processor ARM or data signal processor DSP.
Described control bus is: Advanced High-performance Bus AHB or Advanced Peripheral Bus APB or AS bus ASB or level extensive interface AXI of elder generation or chip internal interconnect bus Wishbone.
A kind of method that realizes communication between processes, the multiprocessor communication unit is set in multicomputer system, each processor is visited this multiprocessor communication unit by control bus, carries out communication between each processor by this multiprocessor communication unit, and described method specifically comprises:
A, transmitting terminal processor are visited described multiprocessor communication unit by control bus, write effective value on the corresponding positions of the interrupt source register in described multiprocessor communication unit, perhaps, write effective value on the corresponding positions of OIER in described multiprocessor communication unit and interrupt source register; Interrupt status register in the multiprocessor communication unit obtains the value of corresponding figure place according to the effective value of said write;
B, described multiprocessor communication unit produce the interrupt control signal according to the value of corresponding figure place in the described interrupt status register, send this interrupt control signal to the receiving end processor; The receiving end processor obtains the effective value information that described transmitting terminal processor writes according to this interrupt control signal.
Described steps A specifically comprises:
A1, transmitting terminal processor are visited described multiprocessor communication unit by control bus, send address signal, control signal to described multiprocessor communication unit;
A2, according to described address signal, control signal, write effective value on the corresponding positions of the respective interrupt source-register in described multiprocessor communication unit, interrupt status register in the multiprocessor communication unit makes up the value of each in the interrupt source register, obtains the value of corresponding figure place;
Perhaps,
According to described address signal, control signal, write effective value on the respective interrupt enable register in described multiprocessor communication unit and the corresponding positions of interrupt source register, interrupt status register in the multiprocessor communication unit makes up the value of each in OIER and the interrupt source register, obtains the value of corresponding figure place.
The receiving end processor obtains the effective value information that described transmitting terminal processor writes according to this interrupt control signal and specifically comprises among the described step B:
After B1, receiving end processor receive described interrupt control signal, visit described multiprocessor communication unit, send address signal and control signal to described multiprocessor communication unit by control bus;
B2, multiprocessor communication unit are according to described address signal and control signal, read effective value on the interrupt source register corresponding positions of portion within it, perhaps, read effective value on the corresponding positions of the interrupt source register of portion, OIER within it, and the effective value information of reading is exported to described receiving end processor.
Described step B also comprises:
In the time will removing described interrupt control signal, the corresponding positions in the interrupt clear register in described multiprocessor communication unit writes effective value, and it is invalid that the corresponding positions of the described interrupt source register of this interrupt clear register is set to.
Also comprise:
Take place at the same time under the situation of a plurality of interruptions or a plurality of interrupt nestings, described multiprocessor communication unit carries out prioritization by software to these a plurality of interruptions, the interruption that preferential answering priority is high.
As seen from the above technical solution provided by the invention, the present invention compares with prior art by between processor (such as CPU, ARM or DSP) the multiprocessor communication unit being set, and has following advantage:
1, undertaken alternately by interrupt mechanism between the processor (such as CPU, ARM or DSP), real-time is very strong, and when a processor needed another processor to assist, the other side can provide response immediately, has promoted system performance.
2, improved degree of coupling between ARM and the DSP, can make SOC (on the sheet) system of ARM+DSP and so on can satisfy audio frequency, Streaming Media, communication aspect in real time, big data quantity, multiple services demand, can utilize the resource of SOC system better.
3, by the bit wide of expansion interrupt register, ARM and DSP can have a plurality of maskable interrupts source, can satisfy aspect application demands such as most of communications, agreement, algorithm, real-time, interactive.
4, finish operations such as interrupt inquiry, prioritization by software, saved hardware resource.The interruption of ARM and DSP is by array output, and the system break resource that takies has only 2, has reduced the complicated device of system hardware.
5, by the ahb bus interface in the multiprocessor communication unit is inserted the SOC system bus, the present invention goes for the SOC system of many ARM, many DSP, multilayer system bus.
Description of drawings
Fig. 1 is the structural representation of the embodiment of the system that finishes the interruption communication between ARM and the DSP by INT_GEN of the present invention;
Fig. 2 is the interface synoptic diagram of INT_GEN of the present invention;
Fig. 3 is the inner structure synoptic diagram of INT_GEN of the present invention;
Fig. 4 is the processing flow chart of the embodiment of the method that communicates between ARM of the present invention and the DSP.
Embodiment
The invention provides a kind of apparatus and method that realize communication between processes, core of the present invention is: an INT_GEN (multiprocessor communication unit) is set in multicomputer system, each processor is visited this INT_GEN multiprocessor communication unit by control bus, carries out communication by this INT_GEN multiprocessor communication unit.
Describe the present invention below in detail, processor of the present invention can be CPU (central processing unit), MPU (microprocessor), MCU (microcontroller), ARM (RISC processor) or DSP (data signal processor).Be that example illustrates the present invention with ARM and DSP below.
The structural representation of the embodiment of the system that finishes the interruption communication between ARM and the DSP by INT_GEN of the present invention as shown in Figure 1.ARM_AHB (ARM Advanced High-performance Bus) is connected by MUX (multiplexer) with DSP_AHB (DSP_ Advanced High-performance Bus), and MUX is connected with INT_GEN by ahb bus again, and ARM and DSP can select to visit INT_GEN by this MUX.
Above-mentioned ARM, DSP and INT_GEN can also be mounted on same the ahb bus, judge the control of ahb bus between them by the moderator on the ahb bus, and which has access rights to INT_GEN to judge current ARM and DSP.
In actual applications, above-mentioned ahb bus can also adopt APB (Advanced Peripheral Bus), ASB (AS bus), AXI (level extensive interface earlier), Wishbone (chip internal interconnect bus) bus to replace.
Above-mentioned INT_GEN can be integrated in the system controller, perhaps is integrated in the interruptable controller of total system, perhaps is integrated in other modules.
The interface synoptic diagram of above-mentioned INT_GEN as shown in Figure 2.Comprise AHB Slave bus interface, arm_int interface and dsp_int interface.
AHB Slave bus interface signal links to each other with ahb bus, is used for the AHB system bus configuration register of INT_GEN is carried out read and write access.The AHB interface meets the AHB agreement of AMBA (advanced microprocessor bus framework).
The arm_int signal is the ARM look-at-me, is the look-at-me that ahb bus sends to ARM.The dsp_int signal is the DSP look-at-me, is the look-at-me that ahb bus sends to DSP.The interruptable controller (the vectored interrupt controller IP that provides as ARM company) of total system also can be provided these two look-at-mes, is used for further making up with priority with other look-at-mes judging.
The inner structure synoptic diagram of above-mentioned INT_GEN comprises interrupt register module: Buffer (buffer), read-write controller, DEC (demoder) module and mistaken verdict module as shown in Figure 3.
The interrupt register module: comprising 8 registers, is respectively ARM interrupt source register, ARM OIER, ARM interrupt clear register, ARM interrupt status register, DSP interrupt source register, DSP OIER, DSP interrupt clear register, DSP interrupt status register.All registers are 32 bit wides, and each corresponding ARM interrupts in four registers relevant with ARM, and each corresponding DSP interrupts in four registers relevant with DSP, so ARM and DSP can have 32 logic interrupt sources separately respectively.By MUX the value of all 32 positions in the ARM interrupt status register is made up, output arm_int signal makes up the value of all 32 positions in the DSP interrupt status register by MUX, output dsp_int signal.Buffer: receive address signal haddr that DSP or ARM pass over by ahb bus and control signal hsel, htrans, hwrite, hreadyin, make address signal haddr and control signal hsel, htrans, hwrite, hreadyin postpone a bat, address signal haddr and data-signal wrdata are effective in same clock.Address signal haddr and control signal hsel, htrans, hwrite, hreadyin after handling are passed to read-write controller.
Read-write controller: control signal hsel, the htrans, hwrite, the hreadyin that pass over according to Buffer, produce wren (writing enable signal) and rden (reading enable signal), wren and the rden that produces passed to the DEC module with the address signal haddr that receives.
The DEC module: address signal haddr, wren and rden that read-write controller is passed over decipher, and according to the address signal haddr after the decoding 8 interrupt registers in the register module are carried out addressing.When wren is effective, the OIER that obtains through addressing, the relevant position of interrupt source register are write correct wrdata, promptly be set to effectively; When rden is effective, from the relevant position sense data of the interrupt source register that obtains through addressing, and the data of reading to be exported by MUX, these data can be visited by ahb bus in next bat.
The mistake discrimination module: when the AHB interface signal met the condition of makeing mistakes of ahb bus agreement, the mistake discrimination module made the hreadyout on the ahb bus drag down a bat, showed when the forward pass data transmit to make mistakes.And transmit wrong control signal hreadyou to read-write controller, and do not produce effective wren and rden signal from read-write controller, simultaneously hresp is changed to ERROR, keep two to clap.
Based on above-mentioned INT_GEN, the treatment scheme of the embodiment of the method that communicates between a kind of ARM and the DSP comprises the steps: as shown in Figure 4
Step 4-1:DSP or ARM visit INT_GEN transmit address signal and control signal to INT_GEN.
When DSP need be when ARM sends interruption, at first DSP will visit INT_GEN by ahb bus, transmit corresponding address signal and control signal to Buffer, Buffer postpones to handle to this address signal and control signal, and address signal and control signal after handling are passed to read-write controller.Read-write controller produces wren according to the control signal that Buffer passes over, and wren that produces and the address signal that receives are passed to the DEC module.
When ARM need be when DSP sends interruption, at first ARM will visit INT_GEN by ahb bus, transmit corresponding address signal and control signal to Buffer, Buffer postpones to handle to this address signal and control signal, and address signal and control signal after handling are passed to read-write controller.Read-write controller produces wren according to the control signal that Buffer passes over, and wren that produces and the address signal that receives are passed to the DEC module.
Step 4-2: the OIER among the INT_GEN and the corresponding positions of interrupt source register are set to effectively.
When DSP need be when ARM send to interrupt, above-mentioned DEC module is deciphered address signal and the wren that read-write controller passes over, and according to the address signal after the decoding 8 interrupt registers in the register module is carried out addressing.The ARM OIER that obtains through addressing, the corresponding positions of ARM interrupt source register are write correct wrdata, promptly be set to effectively.Because the value of ARM interrupt status register is the combination of ARM interrupt source register and ARM OIER, the result after the combination guarantees that interrupt bit is effective, and therefore, the corresponding positions of ARM interrupt status register also can be effective.
In above-mentioned processing procedure, the DEC module also can a corresponding positions at the ARM interrupt source register write effective value, and the ARM interrupt status register makes up the value of each in this ARM interrupt source register, obtains the value of corresponding figure place.
When ARM need be when DSP send to interrupt, above-mentioned DEC module is deciphered address signal and the wren that read-write controller passes over, and according to the address signal after the decoding 8 interrupt registers in the register module is carried out addressing.The DSP OIER that obtains through addressing, the relevant position of DSP interrupt source register are write correct wrdata, promptly be set to effectively.Because the value of DSP interrupt status register is the combination of DSP interrupt source register and DSP OIER, the result after the combination guarantees that interrupt bit is effective, and therefore, the corresponding positions of DSP interrupt status register also can be effective.
In above-mentioned processing procedure, the DEC module also can a corresponding positions at the DSP interrupt source register write effective value, and the DSP interrupt status register makes up the value of each in this DSP interrupt source register, obtains the value of corresponding figure place.
Step 4-3:INT_GEN sends arm_int signal or dsp_int signal according to the value of all figure places in the interrupt status register, and ARM or DSP inquire about to INT_GEN after receiving this arm_int signal or dsp_int signal, obtain effective value information.
After the corresponding positions at DSP interrupt status register or ARM interrupt status register is set to effectively, INT_GEN just can produce dsp_in signal or tarm_int signal according to the value of all figure places in DSP interrupt status register or the ARM interrupt status register, and sends the arm_int signal or send the dsp_int signal to DSP to ARM.
The arm_int signal is the array output of all 32 positions in the ARM interrupt status register, is the logical OR of 32 positions as if interrupting the effective then arm_int signal of high level, is the logical and of 32 positions if interrupt the effective then arm_int signal of low level.In the time will removing this arm_int, then the corresponding positions in the ARM interrupt clear register writes effective value, and effective value can be a high level, also can be low level.It is invalid that the corresponding positions of the above-mentioned ARM interrupt source register of ARM interrupt clear register is set to, thereby remove the corresponding positions in the ARM interrupt status register.
The dsp_int signal is the array output of all 32 positions in the DSP interrupt status register, effectively then is the logical OR of 32 positions if interrupt high level, effectively then is the logical and of 32 positions if interrupt low level.If remove this dsp_int, then the corresponding positions in the DSP interrupt clear register writes effective value.Effective value can be a high level, also can be low level.It is invalid that the corresponding positions of the above-mentioned DSP interrupt source register of DSP interrupt clear register is set to, thereby remove the corresponding positions in the DSP interrupt status register.
Above-mentioned ARM and DSP have 32 interrupt sources, after ARM or DSP receive above-mentioned arm_int signal or dsp_int signal, need to inquire about to INT_GEN again, obtain the effective value information that DSP or ARM write in interrupt source register, OIER, promptly inquire about effective value information, concrete query script is as follows:
When DSP need be when INT_GEN inquires about effective value, when promptly inquiring about corresponding interrupt event information, at first DSP will visit INT_GEN by ahb bus, transmit corresponding address signal and control signal to Buffer, Buffer postpones to handle to this address signal and control signal, will handle back address signal and control signal and pass to read-write controller.Read-write controller produces rden according to the control signal that Buffer passes over, and rden that produces and the address signal that receives are passed to the DEC module.
The DEC module is deciphered address signal and the rden that read-write controller passes over, and according to the address signal after the decoding 8 interrupt registers in the register module is carried out addressing.From corresponding D SP interrupt source register, read effective value.And the effective value of reading exported to DSP by MUX.Each bit in the DSP interrupt source register is logically all represented an interrupt source, and the effective value of INT_GEN output interrupts dsp_int (as long as these positions have effectively, INT_GEN will produce and interrupt output) for the combination of these bits.
When ARM need be when INT_GEN inquires about effective value, at first ARM will visit INT_GEN by ahb bus, transmit corresponding address signal and control signal to Buffer, Buffer postpones to handle to this address signal and control signal, and address signal and control signal after handling are passed to read-write controller.Read-write controller produces rden according to the control signal that Buffer passes over, and rden that produces and the address signal that receives are passed to the DEC module.
The DEC module is deciphered address signal and the rden that read-write controller passes over, and according to the address signal after the decoding 8 interrupt registers in the register module is carried out addressing.From corresponding ARM interrupt source register, read effective value.And the effective value of reading exported to ARM by MUX.Each bit in the ARM interrupt source register is logically all represented an interrupt source, and the effective value of INT_GEN output interrupts arm_int (as long as these positions have effectively, INT_GEN will produce and interrupt output) for the combination of these bits.
Take place at the same time under the situation of a plurality of interruptions or a plurality of interrupt nestings, described INT_GEN carries out prioritization operation, the interruption that preferential answering priority is high by software to these a plurality of interruptions.
For example, the situation that a plurality of interruptions take place simultaneously is as follows: have the interruption 2 of high priority and the interruption 5 of low priority to interrupt simultaneously, INT_GEN judges the priority of interruption 2 than the height that interrupts 5 by software, and therefore, INT_GEN at first responds and interrupts 2; By the time interrupt having removed and having interrupted 2 after 2 end, then response interrupts 5 again.The treatment mechanism that plural interruption takes place simultaneously is identical with said process, always the high interruption of response priority earlier.
Such as, the situation of a plurality of interrupt nestings is as follows: have the interruption 3 of low priority to interrupt earlier, INT_GEN interrupts 3 by software responses and also removes the interrupt source of interruption 3, the interrupt service routine of outage 3; The interruption 6 of a high priority has taken place again this moment, and therefore, INT_GEN responds at once by software and interrupts 6, the interruption 3 that shielding enters low priority, and the interrupt service routine of outage 6; By the time interrupt 6 operations and finish, the service routine of the interruption 3 of reruning.The treatment mechanism that plural interrupt nesting takes place simultaneously is identical with said process, always the high interruption of response priority earlier.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (13)
1. device of realizing communication between processes, it is characterized in that, this device comprises multiprocessor communication unit and control bus, each processor is visited described multiprocessor communication unit by described control bus, and carry out communication between each processor by described multiprocessor communication unit
Described multiprocessor communication unit specifically comprises: read-write controller, code translator and interrupt register module, wherein:
Read-write controller: the address signal that the receiving end/sending end processor passes over by control bus, control signal, write enable signal and read enable signal according to this control signal generation, the enable signal of writing that produces is passed to code translator with the address signal of reading enable signal and receive;
Code translator: the address signal that read-write controller is passed over, write enable signal and read enable signal and decipher, the address signal after decoding is handled, write enable signal and read enable signal and pass to the interrupt register module;
Interrupt register module: comprise a plurality of interrupt registers, the address signal that passes over according to code translator, write enable signal, in corresponding interrupt register, writing effective value, and exporting corresponding interrupt control signal to the receiving end processor; Or the address signal that passes over according to code translator, read enable signal, from corresponding interrupt register, read effective value and output.
2. device according to claim 1 is characterized in that, described multiprocessor communication unit also comprises:
Impact damper: address signal and control signal that the receiving end/sending end processor passes over by control bus, this address signal and control signal are postponed to handle, address signal and control signal after handling are passed to read-write controller.
3. device according to claim 1 is characterized in that, described multiprocessor communication unit also comprises:
Mistake discrimination module: when the signal on the control bus meets the condition of makeing mistakes of control bus agreement, transmit wrong control signal, read-write controller is not produced effectively write enable signal and read enable signal to read-write controller.
4. according to claim 1 or 2 or 3 described devices, it is characterized in that described interrupt register module specifically comprises:
Interrupt source register: comprise the figure place of setting, all corresponding interruption of each figure place is write enable signal according to what code translator passed over, is writing corresponding effective value on corresponding figure place;
Interrupt status register: comprise the figure place of setting,, on corresponding figure place, write corresponding effective value, export corresponding interrupt control signal to the receiving end processor according to the combination of the value of each in the interrupt source register; Or read enable signal according to what code translator passed over, from corresponding interrupt source register, read effective value and output.
5. according to claim 1 or 2 or 3 described devices, it is characterized in that described interrupt register module also comprises:
Interrupt source register: comprise the figure place of setting, all corresponding interruption of each figure place is write enable signal according to what code translator passed over, is writing corresponding effective value on corresponding figure place;
OIER: comprise the figure place of setting, all corresponding interruption of each figure place is write enable signal according to what code translator passed over, is writing corresponding effective value on corresponding figure place;
Interrupt status register: the figure place that comprises setting, according in the OIER each value and interrupt source register in each value make up, on corresponding figure place, write corresponding effective value, export corresponding interrupt control signal to the receiving end processor; Or read enable signal according to what code translator passed over, from corresponding interrupt source register, read effective value and output.
6. device according to claim 4 is characterized in that, described interrupt register module also comprises:
Interrupt clear register: comprise the figure place of setting, all corresponding interruption of each figure place, according to the value that writes on the corresponding positions, it is invalid that the value of the corresponding positions of described interrupt source register is set to.
7. device according to claim 1 is characterized in that, described processor is: central processor CPU or microprocessor MPU or microcontroller MCU or RISC processor ARM or data signal processor DSP.
8. device according to claim 1 is characterized in that, described control bus is: Advanced High-performance Bus AHB or Advanced Peripheral Bus APB or AS bus ASB or level extensive interface AXI of elder generation or chip internal interconnect bus Wishbone.
9. method that realizes communication between processes, it is characterized in that, the multiprocessor communication unit is set in multicomputer system, each processor is visited this multiprocessor communication unit by control bus, carry out communication between each processor by this multiprocessor communication unit, described method specifically comprises:
A, transmitting terminal processor are visited described multiprocessor communication unit by control bus, write effective value on the corresponding positions of the interrupt source register in described multiprocessor communication unit, perhaps, write effective value on the corresponding positions of OIER in described multiprocessor communication unit and interrupt source register; Interrupt status register in the multiprocessor communication unit obtains the value of corresponding figure place according to the effective value of said write;
B, described multiprocessor communication unit produce the interrupt control signal according to the value of corresponding figure place in the described interrupt status register, send this interrupt control signal to the receiving end processor; The receiving end processor obtains the effective value information that described transmitting terminal processor writes according to this interrupt control signal.
10. method according to claim 9 is characterized in that, described steps A specifically comprises:
A1, transmitting terminal processor are visited described multiprocessor communication unit by control bus, send address signal, control signal to described multiprocessor communication unit;
A2, according to described address signal, control signal, write effective value on the corresponding positions of the respective interrupt source-register in described multiprocessor communication unit, interrupt status register in the multiprocessor communication unit makes up the value of each in the interrupt source register, obtains the value of corresponding figure place;
Perhaps,
According to described address signal, control signal, write effective value on the respective interrupt enable register in described multiprocessor communication unit and the corresponding positions of interrupt source register, interrupt status register in the multiprocessor communication unit makes up the value of each in OIER and the interrupt source register, obtains the value of corresponding figure place.
11., it is characterized in that the receiving end processor obtains the effective value information that described transmitting terminal processor writes according to this interrupt control signal and specifically comprises among the described step B according to claim 9 or 10 described methods:
After B1, receiving end processor receive described interrupt control signal, visit described multiprocessor communication unit, send address signal and control signal to described multiprocessor communication unit by control bus;
B2, multiprocessor communication unit are according to described address signal and control signal, read effective value on the interrupt source register corresponding positions of portion within it, perhaps, read effective value on the corresponding positions of the interrupt source register of portion, OIER within it, and the effective value information of reading is exported to described receiving end processor.
12., it is characterized in that described step B also comprises according to claim 9 or 10 described methods:
In the time will removing described interrupt control signal, the corresponding positions in the interrupt clear register in described multiprocessor communication unit writes effective value, and it is invalid that the corresponding positions of the described interrupt source register of this interrupt clear register is set to.
13. according to claim 9 or 10 described methods, it is characterized in that, also comprise:
Take place at the same time under the situation of a plurality of interruptions or a plurality of interrupt nestings, described multiprocessor communication unit carries out prioritization by software to these a plurality of interruptions, the interruption that preferential answering priority is high.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100864818A CN100464319C (en) | 2006-06-23 | 2006-06-23 | Device and method for implementing communication between processes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100864818A CN100464319C (en) | 2006-06-23 | 2006-06-23 | Device and method for implementing communication between processes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101000593A CN101000593A (en) | 2007-07-18 |
| CN100464319C true CN100464319C (en) | 2009-02-25 |
Family
ID=38692571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100864818A Active CN100464319C (en) | 2006-06-23 | 2006-06-23 | Device and method for implementing communication between processes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100464319C (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110097447A (en) * | 2010-02-25 | 2011-08-31 | 삼성전자주식회사 | System on chip having interrupt proxy and processing method thereof |
| CN101916239B (en) * | 2010-08-27 | 2011-09-28 | 上海交通大学 | Method for enhancing communication speed of on-chip multiprocessor |
| CN102591817B (en) * | 2011-12-30 | 2014-12-31 | 中山大学 | Multi-bus bridge controller and implementing method thereof |
| US9665509B2 (en) * | 2014-08-20 | 2017-05-30 | Xilinx, Inc. | Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system |
| CN104915301B (en) * | 2015-06-01 | 2017-11-10 | 浪潮集团有限公司 | A kind of plug-in RAM Interface data access system based on 8051 single-chip microcomputers |
| CN106326172B (en) * | 2016-08-24 | 2019-03-26 | 浙江大华技术股份有限公司 | A kind of APB bus slave Interface Expanding circuit and its application method |
| CN110321309B (en) * | 2019-05-09 | 2020-03-17 | 核芯互联科技(青岛)有限公司 | Data transmission method and system |
| CN110457243B (en) * | 2019-07-30 | 2021-04-06 | 西安理工大学 | Expandable multi-output interrupt controller |
| CN117034827B (en) * | 2023-10-08 | 2023-12-15 | 华中科技大学 | Multi-path selector, interconnection switch and peripheral interface circuit for eFPGA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1288201A (en) * | 1999-09-09 | 2001-03-21 | 上海贝尔有限公司 | Communication interface of master-slave type processor system |
| US6295571B1 (en) * | 1999-03-19 | 2001-09-25 | Times N Systems, Inc. | Shared memory apparatus and method for multiprocessor systems |
| CN1564134A (en) * | 2004-04-13 | 2005-01-12 | 中兴通讯股份有限公司 | Selection method of multiple processors in communication system |
-
2006
- 2006-06-23 CN CNB2006100864818A patent/CN100464319C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6295571B1 (en) * | 1999-03-19 | 2001-09-25 | Times N Systems, Inc. | Shared memory apparatus and method for multiprocessor systems |
| CN1288201A (en) * | 1999-09-09 | 2001-03-21 | 上海贝尔有限公司 | Communication interface of master-slave type processor system |
| CN1564134A (en) * | 2004-04-13 | 2005-01-12 | 中兴通讯股份有限公司 | Selection method of multiple processors in communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101000593A (en) | 2007-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100464319C (en) | Device and method for implementing communication between processes | |
| CN109271335B (en) | FPGA implementation method for DDR cache of multi-channel data source | |
| CN102866971B (en) | Device, the system and method for transmission data | |
| KR101988260B1 (en) | EMBEDDED MULTIMEDIA CARD(eMMC), AND METHOD FOR OPERATING THE eMMC | |
| US7356637B2 (en) | Virtual IDE storage device with PCI express interface | |
| CN111552657A (en) | PHY recalibration using a message bus interface | |
| US8799532B2 (en) | High speed USB hub with full speed to high speed transaction translator | |
| US7606964B2 (en) | Virtual USB flash memory storage device with PCI express interface, controller and method thereof | |
| JP2003316731A (en) | Data transfer control device, electronic equipment, and data transfer control method | |
| JP2014017006A (en) | Method and apparatus for enabling id based streams over pci express | |
| CN112256601A (en) | Data access control method, embedded storage system and embedded equipment | |
| US20070079015A1 (en) | Methods and arrangements to interface a data storage device | |
| WO2021169474A1 (en) | Method for converting avalon bus into axi4 bus | |
| CN114253889A (en) | Approximate data bus inversion techniques for delay sensitive applications | |
| CN110941582A (en) | USB bus structure of BMC chip and communication method thereof | |
| WO2012081085A1 (en) | Interrupt source management device and interrupt processing system | |
| CN117472815A (en) | Storage module conversion interface under AXI protocol and conversion method thereof | |
| US6424179B1 (en) | Logic unit and integrated circuit for clearing interrupts | |
| US20130080141A1 (en) | Power aware simulation system with embedded multi-core dsp | |
| CN104572515B (en) | Tracking module, method, system and on-chip system chip | |
| JP2004349836A (en) | Electronic apparatus, and method for apparatus and data transfer control | |
| CN106940684B (en) | Method and device for writing data according to bits | |
| KR100737549B1 (en) | An apparatus and method for address bus power control | |
| CN102082798B (en) | SDIO (secure digital input output) interface based multimedia information coprocessing equipment and communication method thereof | |
| CN110489359B (en) | Data transmission control method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |