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Publication numberCN100459099 C
Publication typeGrant
Application numberCN 200610030628
Publication date4 Feb 2009
Filing date31 Aug 2006
Priority date31 Aug 2006
Also published asCN101136356A
Publication number200610030628.1, CN 100459099 C, CN 100459099C, CN 200610030628, CN-C-100459099, CN100459099 C, CN100459099C, CN200610030628, CN200610030628.1
Inventors刘艳吉, 汪钉崇, 王晓艳, 高建峰
Applicant中芯国际集成电路制造(上海)有限公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Copper interconnected fabricating method for semiconductor device and structure thereof
CN 100459099 C
Abstract  translated from Chinese
一种铜互连的半导体器件的制造方法,包括提供带有介质隔离层和铜布线层的半导体衬底,铜布线层镶嵌于介质隔离层中;在铜布线层和介质隔离层表面形成扩散阻挡层,扩散阻挡层为面心立方结构的氮化钽材料;在扩散阻挡层上形成铝垫层。 A method of manufacturing a semiconductor device of a copper interconnect, comprising providing a semiconductor substrate having a copper wiring layer dielectric spacer layer and the copper wiring layer embedded in the dielectric spacer layer; the copper wiring layer and the surface of dielectric spacer layer forming a diffusion barrier layer, the diffusion barrier layer is tantalum nitride material face-centered cubic structure; forming an aluminum pad on the diffusion barrier layer. 相应地,本发明提供一种基于上述方法形成的结构。 Accordingly, the present invention provides a method of forming a structure based on the above method. 本发明通过改变沉积扩散阻挡层的工艺及其形成的结构,把TaN薄膜的晶体结构由体心立方结构改变为面心立方结构,覆盖在Cu布线层上更为致密,尤其对于金属台阶部分的“弱区”,更好地阻挡了铜向Al垫层扩散和电迁移。 The present invention, by changing the structure of the diffusion barrier layer deposition process and the formation of the crystal structure of the TaN film by the body-centered cubic structure was changed to a face-centered cubic structure, covering more dense on the Cu wiring layer, especially for metal step portion "weak areas" to better block the migration of copper diffusion to Al cushion and electricity.
Claims(10)  translated from Chinese
1.一种铜互连的半导体器件的制造方法,包括如下步骤:提供带有介质隔离层和铜布线层的半导体衬底,所述铜布线层镶嵌于介质隔离层中;在所述的铜布线层和介质隔离层表面形成扩散阻挡层;在扩散阻挡层上形成铝垫层,其特征在于,所述的扩散阻挡层为面心立方结构的氮化钽材料。 A method of manufacturing a semiconductor device of a copper interconnect, comprising the steps of: providing a semiconductor substrate with a dielectric spacer layer and the copper wiring layer, the copper wiring layer is embedded in the dielectric spacer layer; in the copper the wiring layer and the dielectric spacer layer formed on the surface diffusion barrier layer; forming the aluminum diffusion barrier layer on the underlayer, characterized in that said diffusion barrier layer is tantalum nitride material face-centered cubic structure.
2. 根据权利要求1所述的铜互连的半导体器件的制造方法,其特征在于:所述的扩散阻挡层采用物理气相沉积或者化学气相沉积或者真空电子束蒸发或者脉冲激光沉积方法形成。 The method of manufacturing a semiconductor device copper interconnect according to claim 1, wherein: said diffusion barrier layer by physical vapor deposition or chemical vapor deposition or electron beam evaporation in vacuo or pulsed laser deposition method.
3. 根据权利要求2所述的铜互连的半导体器件的制造方法,其特征在于:所述的物理气相沉积方法形成扩散阻挡层的沉积功率范围为3000 W至8000 W,形成扩散阻挡层的气氛为氮气,氮气的流量范围为25 sccm至55 sccm。 3. The method of manufacturing a semiconductor device of a copper interconnect according to claim 2, characterized in that: the physical vapor deposition method of forming a diffusion barrier layer deposition power range of 3000 W to 8000 W, forming a diffusion barrier layer an atmosphere of nitrogen, the nitrogen flow range of 25 sccm to 55 sccm.
4. 根据权利要求1或者2或者3所述的半导体器件的制造方法,其特征在于: 所述的扩散阻挡层厚度范围为30nm至100nm。 4. A method of manufacturing a semiconductor device according to 1 or 2, or claim 3, wherein, wherein: the diffusion barrier layer thickness in the range of 30nm to 100nm.
5. 根据权利要求1或者2或者3所述的半导体器件的制造方法,其特征在于: 所述的面心立方结构的氮化钽为单层或者多层结构。 5. A method of manufacturing a semiconductor device according to 1 or 2, or claim 3, wherein, wherein: the tantalum nitride of the face-centered cubic structure is a single-layer or multi-layer structure.
6. —种铜互连的半导体器件的制造方法,包括如下步骤:提供带有介质隔离层和铜布线层的半导体衬底,所述铜布线层镶嵌于介质隔离层中;在所述的铜布线层和介质隔离层表面形成接触膜层;在接触膜层上形成扩散阻挡层;在扩散阻挡层上形成铝垫层,其特征在于,所述的扩散阻挡层为面心立方结构的氮化钽材料。 6. - The method of producing seed copper interconnects of a semiconductor device, comprising the steps of: providing a semiconductor substrate with a dielectric spacer layer and the copper wiring layer, the copper wiring layer is embedded in the dielectric spacer layer; in the copper wiring layer and the dielectric spacer layer formed on the surface in contact layer; a diffusion barrier layer formed on the contact layer; forming an aluminum pad on the diffusion barrier layer, wherein the diffusion barrier layer is a nitride face-centered cubic structure tantalum material.
7. 根据权利要求6所述的半导体器件的制造方法,其特征在于:所述的接触膜层由铂族元素、铁族元素中的任意金属构成。 7. A method of manufacturing a semiconductor device according to claim 6, characterized in that: said film layer contacting the platinum group element, iron group element any metal.
8. —种铜互连的半导体器件结构,包括带有介质隔离层和铜布线层的半导体衬底,所述铜布线层镶嵌于介质隔离层中;位于铜布线层和介质隔离层表面的扩散阻挡层以及位于扩散阻挡层之上的铝垫层,其特征在于所述的扩散阻挡层为面心立方结构的氮化钽。 8. - seed copper interconnection structure of a semiconductor device, comprising a semiconductor substrate with a dielectric spacer layer and the copper wiring layer, the copper wiring layer is embedded in the dielectric spacer layer; and a wiring layer located on the copper layer surface diffusion dielectric spacer and a barrier layer located above the diffusion barrier layer of aluminum cushion, characterized in that the diffusion barrier layer is tantalum nitride face-centered cubic structure.
9. 根据权利要求8所述的铜互连的半导体器件结构,其特征在于,所述的面心立方结构的氮化钽为单层或者多层结构。 9. The semiconductor device structure 8 of the copper interconnect according to claim, characterized in that the tantalum nitride of the face-centered cubic structure is a single-layer or multi-layer structure.
10. —种铜互连的半导体器件结构,包括带有介质隔离层和铜布线层的半导体衬底,所述铜布线层镶嵌于介质隔离层中;位于铜布线层和介质隔离层表面的接触膜层;位于接触膜层之上的扩散阻挡层以及位于扩散阻挡层之上的铝垫层,其特征在于所述的扩散阻挡层为面心立方结构的氮化钽。 10. - Species copper interconnection structure semiconductor device comprising a semiconductor substrate with a dielectric spacer layer and the copper wiring layer, the copper wiring layer is embedded in the dielectric spacer layer; and a wiring layer located on the copper layer surface in contact dielectric spacer film; the contact layer located above the diffusion barrier layer and the diffusion barrier layer is located above the aluminum pad, characterized in that said diffusion barrier layer is tantalum nitride face-centered cubic structure.
Description  translated from Chinese

铜互连的半导体器件的制造方法及其结构 Copper interconnect manufacturing method and structure of a semiconductor device

技术领域 Technical Field

本发明涉及一种半导体器件的制造方法及其结构,特别涉及一种铜互连的半导体器件的制造方法及其结构。 The present invention relates to a method and structure for a semiconductor device, and particularly relates to a method of manufacturing a copper interconnection structure of a semiconductor device.

背景技术 Background

随着集成电路集成度的不断提高,Al作为内连线材料其性能已难以很好满足集成电路的要求。 With the increasing integration density of integrated circuits, Al interconnection material as its performance has been difficult to properly meet the requirements of the integrated circuit. Cu较AI具有低的电阻率和高的抗电迁移能力在深亚微米技术中得到广泛的应用。 Cu than the AI has a low resistivity and high electromigration resistance has been widely used in deep submicron technologies. 然而Cu又是导致器件失效的元凶,这主要因为Cu 是一种重金属,在高温和加电场的情况下,可以在半导体硅片和二氧化硅中快速扩散,引起器件可靠性方面的问题。 However, Cu is the culprit leading to device failure, mainly because Cu is a heavy metal, in the case of elevated temperature and electric field, can spread rapidly in the semiconductor silicon and silicon dioxide, causing the device reliability problems. 所以,在Cu布线层和介质隔离层之间,必须加上防止Cu扩散的扩散阻挡层材料,例如TaN、 TiSiN、 Ta等来实现防止Cu扩散的目的。 Therefore, between the Cu wiring layer and the dielectric spacer layer, it must be added to prevent the diffusion of Cu diffusion barrier material, e.g., TaN, TiSiN, Ta, etc. to achieve the purpose of preventing diffusion of Cu.

同时,随着芯片集成度的提高,互连引线变得更细、更窄、更薄,因此其中的电流密度越来越大。 Meanwhile, with the improvement of chip integration, interconnection leads become finer and more narrow and thinner, and therefore one of the current density increases. 在较高的电流密度作用下,互连引线中的金属原子将会沿着电子运动方向进行迁移,这种现象就是电迁移(EM)。 At higher current density effects, interconnecting lead metal atoms will migrate along the direction of movement of electrons, a phenomenon known as electromigration (EM). 电迁移能《吏IC中的互连引线在工作过程中产生断路或短路,是引起集成电路失效的一种塗要机制。 Electromigration can "Officials IC interconnect lead generation open or short circuit during operation, is applied to cause a mechanism integrated circuit failure. 所以,在Cu布线层和介质隔离层之间加上扩散阻挡层材料还可以阻止Qi发生电迁移,另外可以提高Cu和介质隔离层的粘附性。 Therefore, between the Cu wiring layer and the dielectric spacer layer plus diffusion barrier material can also prevent the occurrence of electromigration Qi, Cu addition can improve the adhesion and dielectric spacer layer.

以往公开的专利或者文献对Cu布线层和介质隔离层之间的扩散阻挡层有很多的公开和报道,如公开号为2004/0152301和2004/0152330以及2005/0023686的美国专利申请通过在Cu布线层和介质隔离层之间添加扩散阻挡层如Ta和TaN、金属氮化物以及WSiN材料来防止Cu向介质隔离层进行扩散, 然而对于Cu向金属八I中的扩散未公开防止措施。 Conventional literature published patent or diffusion barrier layer Cu wiring layer and the dielectric spacer layer between the public and there are a lot of reports, such as Publication No. 2004/0152301 and US Patent Application 2004/0152330 and 2005/0023686 by Cu wiring Add a diffusion layer and a dielectric spacer layer between the barrier layer such as Ta and TaN, a metal nitride and WSiN material to prevent Cu diffusion to the dielectric spacer layer, however, does not disclose the measures to prevent the Cu metal eight I diffusion. 在深亚微米工艺中,在顶层Cu布线层上制作的引出金属垫仍然采用Al,由于Cu会向Al垫层中进行扩散, In deep sub-micron process, the top layer Cu wiring layer leads to the production of metal pads still use Al, Cu will be due to the diffusion of Al cushion,

发生反应生成电阻率较大的CuAl2,因此必须在顶层Cu布线层和金属Al垫层之间引入防扩散层。 React generate resistivity greater CuAl2, therefore non-proliferation must be introduced between the top layer Cu wiring layer and the metal Al cushion.

'l'a是一种很有吸引力的Cu的扩散阻挡层,Ta的氮化物比如TaN是一种Cu和l''离子的有效阻挡层,目前在Cu互连工艺中正得到广泛的应用。 'L'a is an attractive Cu diffusion barrier layer, Ta nitride such as TaN and a Cu l' 'effective barrier ions present in Cu interconnection process is gaining wide range of applications. 但是在通常工艺中,形成的TaN结构比较疏松,防止Cu扩散的能力较弱。 But in the usual process, TaN structure formation is relatively loose, weak ability to prevent Cu diffusion. 下面参照图1至图5举例说明,在90nm逻辑电路中,Cu布线层12形成在半导体衬底11上,接着在Cu布线层12上形成TaN作为防止Cu扩散的扩散阻挡层13, 最后在扩散阻挡层13上形成Al垫层14,整个结构如图1所示,由于扩散阻挡层13的结构比较疏松,尤其是在金属台阶处覆盖性不好,形成"弱区",顶层Cu布线层12中的Cu往往在此"弱区"穿过扩散阻挡层13,到达Al垫层14,同时在顶层Cu中形成的空洞15,扩散出来的Cul6和Al垫层14发生反应,生成电阻率大的CuA! Referring to Figures 1 to 5 illustrate, in the logic circuit 90nm, Cu wiring layer 12 is formed on the semiconductor substrate 11, followed by forming a TaN Cu diffusion preventing diffusion barrier layer 13 on the Cu wiring layer 12, and finally diffusion Al cushion 14 is formed, the entire structure shown in Figure 1, the diffusion barrier structure is relatively loose layer 13, especially at the step coverage of the metal is bad, the formation of "weak zone" on the barrier layer 13, top layer Cu wiring layer 12 The Cu often this "weak zone" through the diffusion barrier layer 13, cushion 14 reaches Al, Cu voids simultaneously formed in the top layer 15, and Al diffusion out Cul6 cushion 14 reacts large resistivity CuA! 2,影响器件性能。 2, the impact device performance.

采用X射线衍射(XRD)确定现有技术制备的扩散阻挡层13的晶体结构, 结果如图5所示,图5所示的横坐标为衍射角2e,单位为度,纵坐标为衍射强度之比1/1()。 X-ray diffraction (XRD) to determine the diffusion barrier layer is prepared in the prior art crystal structure 13, the abscissa in FIG. 5 shows the results, shown in Figure 5 is the diffraction angle 2e, in degrees, ordinate diffraction intensity 1/1 (). 制备的TaN扩散阻挡层13分别在29为37。 TaN diffusion barrier layer 13 is prepared in 29 to 37 respectively. 、 53和68处出现比较强的衍射峰,和标准语相对照,这些峰分别相应于(110)、 (200)和(211) 晶面的衍射,TaN的晶体结构为体心立方(bcc)结构。 , 53 and 68 at the emergence of strong diffraction peaks, and in contrast to the standard language, these peaks corresponding to (110), (200) and diffraction (211) plane of the crystal structure of the body-centered cubic TaN ( bcc) structure.

采用HC1腐蚀部分Al垫层,利用光学显微镜观察剩下的Al垫层,结果如图2所示,在Al垫层表面存在许多黑色沾污21 ,众所周知,Cu不会和HC1 反应,同时采用能语仪(1':DX)测试了这些黑色沾污21的成分,主要为Cu 和O,表明Cu布线层12中的Cu穿过扩散阻挡层13扩散到了Al垫层14中而且部分被氧化,由此可以看出体心立方结构的TaN的防止Cu扩散能力较差。 HC1 etching using the Al pad portion, was observed with an optical microscope, the remaining Al cushion, the results shown in Figure 2, the surface of the Al pad 21 there are many black stain is known, Cu and does HC1 reaction, while the use of energy Language apparatus (1 ': DX) tested the dark stain components 21, mainly Cu and O, shows that the Cu wiring layer 12 through the Cu diffusion barrier layer 13 is diffused into the Al pad portion 14 and is oxidized, It can be seen that the body-centered cubic structure of TaN Cu diffusion preventing capability is poor.

采用离子束聚焦(nB )切片测试了上述结构的顶层Cu布线层12的截面形貌,结果如图3所示,在Cu布线层12中出现空洞,此结果和上面光学显微镜以及KDX的结果相一致,即Cu布线层12中的Cu扩散出去导致在Cu Using focused ion beam (nB) tested the top slice sectional shape above structure Cu wiring layer 12, and the results shown in Figure 3, voids in the Cu wiring layer 12, and the results of the above optical microscope and the results of KDX consistent, i.e., the Cu wiring layer 12 spread out resulting in a Cu Cu

布线中形成空洞15。 Wiring is formed in the cavity 15.

测试了同一晶片上从S31至S45的15个单元的电迁移(EM)特性来分析器件的失效,结果如图4所示,可以看出,单元S31最早在2小时就形成了电阻峰,其余单元在IO小时之前均出现了电阻峰,表明这些单元在测试的IO小时内出现了空洞,造成了器件失效. Testing on the same wafer from S31 to S45 of 15 units of electro-migration (EM) feature to analyze the failure of the device, the results shown in Figure 4, it can be seen as early as two hours S31 unit formed resistance peak, the rest unit IO hours ago both been resistance peak, indicating that these cells appear empty in the test of IO hours, resulting in a device failure.

由上面讨论可知,体心立方结构的TaN扩散阻挡层的防止Cu扩散和电迁移能力较弱。 From the above discussion, it is, TaN body-centered cubic structure to prevent Cu diffusion and electromigration weak diffusion barrier layer. 众所周知,Cu通过阻挡材料的电迁移和扩散主要沿着阻挡材料的晶粒边界出现,因此需要优化阻挡材料,从而最小化晶粒边界区和/或者延长沿晶粒边界的扩散路径。 As we all know, Cu mainly along grain boundaries of the barrier material occurs by electromigration and diffusion barrier material, the barrier material and therefore need to be optimized, thereby minimizing crystal grain boundary region and / or extend the diffusion path along the grain boundaries.

发明内容 DISCLOSURE

本发明解决的问题是半导体器件中的Cu布线层中的Cu向Al垫层中扩散,侵蚀八l垫层,从而导致器件性能失效。 The present invention solves the problem is a semiconductor device Cu wiring layer Cu diffusion to Al cushion erosion eight l cushion, causing device performance failure.

为解决上述问题,本发明提供一种Cu互连的半导体器件的制备方法,包括如下步骤:提供带有介质隔离层和铜布线层的半导体衬底,所述的铜布线层镶嵌于介质隔离层中;在所述的介质隔离层表面和铜布线层上形成扩散阻挡层;在扩散阻挡层上形成铝垫层,所述的扩散阻挡层为面心立方结构的氮化钽材料。 To solve the above problems, the present invention provides a method for preparing a Cu interconnect semiconductor device, comprising the steps of: providing a semiconductor substrate with a dielectric spacer layer and the copper wiring layer, the copper wiring layer is embedded in dielectric spacer layer ; the diffusion barrier layer is formed on the surface of the dielectric spacer layer and copper wiring layer; forming an aluminum pad on the diffusion barrier layer, the diffusion barrier layer is tantalum nitride material face-centered cubic structure.

扩散阻挡层可采用物理气相沉积(PVD)或者化学气相沉积(CVD)或者真空电子束蒸发或者脉沖激光沉积(PLD)方法形成,比较优选的方法为采用物理气相沉积(PVI))的方法。 Diffusion layer may be a physical vapor deposition (PVD) or chemical vapor deposition (CVD) or a vacuum electron beam evaporation or pulsed laser deposition (PLD) method are formed, more preferably, the method using a physical vapor deposition (PVI)) a barrier method.

采用物理气相沉积(PVD )方法形成扩散阻挡层的沉积功率范围为3000 W 至8000 W,气氛为N2, N2的流量范围为25 sccm至55 sccm。 Physical vapor deposition (PVD) method of forming a diffusion barrier layer deposited power range of 3000 W to 8000 W, an atmosphere of N2, N2 flow range of 25 sccm to 55 sccm.

扩散阻挡层厚度范围为30 nm至100 nm。 Diffusion barrier layer thickness in the range of 30 nm to 100 nm.

扩散阻挡层的面心立方晶体结构可以在沉积的时候形成,也可以在沉积之后退火实现。 Face-centered cubic crystal structure of the diffusion barrier layer may be formed when deposited, it can also achieve annealing after deposition.

扩散阻挡层可以由单层或者多层面心立方结构的TaN构成。 Diffusion barrier layer may be formed of TaN single layer or multi-level-centered cubic structure. 相应地,本发明提供一种Cu互连的半导体器件结构,包括带有介质隔离层和铜布线层的半导体衬底,所述的铜布线层镶嵌于介质隔离层中;位于介质隔离层表面和铜布线层之上的扩散阻挡层以及位于扩散阻挡层之上的铝垫层,所述的扩散阻挡层为面心立方结构的氮化钽。 Accordingly, the present invention provides a semiconductor device structure of a Cu interconnection, comprising a semiconductor substrate with a dielectric spacer layer and the copper wiring layer, the copper wiring layer embedded in the dielectric spacer layer; located on the surface of the dielectric spacer layer and copper wiring layer above the diffusion barrier layer and the diffusion barrier layer is located above the aluminum cushion, said tantalum nitride diffusion barrier layer face-centered cubic structure.

本发明还提供一种铜互连的半导体器件的制造方法,包括如下步骤:提供带有介质隔离层和铜布线层的半导体衬底,所述铜布线层镶嵌于介质隔离层中;在所述的铜布线层和介质隔离层表面形成接触膜层;在接触膜层上形成扩散阻挡层;在扩散阻挡层上形成铝垫层,所述的扩散阻挡层为面心立方结构的氮化钽材料。 The present invention also provides a method of manufacturing a semiconductor device of a copper interconnect, comprising the steps of: providing a semiconductor substrate with a dielectric spacer layer and the copper wiring layer, the copper wiring layer is embedded in the dielectric spacer layer; in the copper wiring layer and the dielectric spacer layer formed on the surface in contact layer; a diffusion barrier layer formed on the contact layer; forming an aluminum pad on the diffusion barrier layer, the diffusion barrier layer is tantalum nitride material face-centered cubic structure .

所述的接触膜层由铂族元素、铁族元素中的任意金属构成。 Contacting said film layer by a platinum group element, any element of the iron group metal. 本发明还提供一种铜互连的半导体器件结构,包括带有介质隔离层和铜希线层的半导体衬底,所述铜布线层镶嵌于介质隔离层中;位于铜布线层和介质隔离层表面的接触膜层;位于接触膜层之上的扩散阻挡层以及位于扩散阻挡层之上的铝垫层,所述的扩散阻挡层为面心立方结构的氮化钽。 The present invention further provides a copper interconnection structure of a semiconductor device, comprising a semiconductor substrate with a dielectric spacer layer and the copper wiring layer of the Greek, the copper wiring layer is embedded in the dielectric spacer layer; located on the copper wiring layer and the dielectric spacer layer contacting the surface of the film; the contact layer located above the diffusion barrier layer and the diffusion barrier layer is located above the aluminum cushion, said tantalum nitride diffusion barrier layer is a face-centered cubic structure.

与现有技术相比,本发明具有以下优点:本发明通过改变沉积扩散阻挡层的工艺,改变了扩散阻挡层的晶体结构为面心立方结构,从而最小化扩散阻挡层的晶粒边界区,延长了铜沿晶粒边界的扩散路径,使得覆盖在Cu布线层上的扩散阻挡层更为致密,尤其是可以更好地覆盖金属台阶部分的"弱区", 阻挡了铜向Al垫层尤其是通过金属台阶部分的"弱区"进行扩散和电迁移, 防止Al垫层受到侵蚀。 Compared with the prior art, the invention has the following advantages: the present invention, by changing the diffusion barrier layer deposition process, changing the crystal structure of the diffusion barrier layer has a face-centered cubic structure, thereby minimizing the grain boundary diffusion barrier layer region, extending the diffusion path of copper along the grain boundaries, so as to cover the Cu wiring layer diffusion barrier layer is more dense, in particular, can better cover the stepped portion of the metal "weak zone" barrier to the copper underlayer in particular Al the diffusion and electromigration stepped through the metal part of the "weak area" to prevent Al cushion eroded.

附图说明 Brief Description

图1是现有技术制备的半导体衬底上的Cu布线层和Al垫层的结构剖面 Figure 1 is a cross-section Cu wiring layer on a semiconductor substrate prepared in the prior art and Al cushion

示意图。 FIG.

图2是现有技术制备的扩散阻挡层的XRD结果 Figure 2 is prepared by prior art XRD results diffusion barrier layer

图3是现有技术制备的Al垫层采用:HC1腐蚀后的光学显微照片。 Figure 3 is a prior art Al cushion prepared using: HC1 optical micrograph after etching.

图4是现有技术制备的Cu布线层的截面FIB测试结果。 Figure 4 is a cross-sectional FIB test results prior art Cu wiring layer is prepared.

图5是现有^t术制备的Cu布线层的EM测试结果。 Figure 5 is a prior test results EM ^ t were prepared by the Cu wiring layer.

图6A至图6B是本发明技术制备的扩散阻挡层的第一实施例示意图。 6A-6B is a first embodiment of the present invention prepared a schematic diagram of the diffusion barrier layer.

图7是采用本发明技术制备的扩散阻挡层的XRD结果。 Figure 7 is prepared using XRD results of the present invention the diffusion barrier layer.

图8是本发明的技术制备的Al垫层采用HC1腐蚀后的SEM照片。 Figure 8 is Al cushion technique of the invention was made using HC1 etched SEM photograph.

图9是本发明的技术制备的Cu布线层的截面FIB测试结果。 9 is a sectional FIB test results prepared Cu wiring layer of the present invention.

图10A是本发明的技术制备的Cu布线层的EM测试结杲的TTF对数正态分布曲线。 10A is EM testing technology of the present invention prepared Cu wiring layer junction Gao's TTF lognormal distribution curve.

闺10B是采用本发明的技术制备的Cu布线层的EM测试结果的相对电阻值退化曲线。 Gui 10B is the use of EM test results prepared Cu wiring layer of the present invention, the relative resistance of the degradation curve.

图IIA至图IIB是本发明技术制备的扩散阻挡层的第二实施例示意图。 Figure IIA through IIB is a second embodiment of the present invention prepared a schematic diagram of the diffusion barrier layer. 具体实施方式 DETAILED DESCRIPTION

以下通过依据附图详细地描述具体实施例,上述的目的和本发明的优点将更加清楚: The following description based on the drawings in detail by specific examples, objects and advantages of the invention will become apparent from the above:

本实施例首先给出了铜互连的半导体器件的制造方法,工艺步骤为:提供带有介质隔离层和铜布线层的半导体衬底,所述铜布线层镶嵌于介质隔离层中:在所述的铜布线层和介质隔离层表面形成扩散阻挡层;在扩散阻挡层上形成铝垫层,所述的扩散阻挡层为面心立方结构的氮化钽材料。 Firstly, the embodiment of the present method for producing copper interconnects in a semiconductor device, the process steps of: providing a semiconductor substrate with a dielectric spacer layer and the copper wiring layer, the copper wiring layer is embedded in dielectric spacer layer: in the copper wiring layer and the dielectric spacer layer is formed above the surface of the diffusion barrier layer; forming an aluminum pad on the diffusion barrier layer, the diffusion barrier layer is tantalum nitride material face-centered cubic structure.

图6A至图6B是采用本发明的制备方法在半导体衬底上的顶层Cu和上层Al垫层之间形成扩散阻挡层的第一实施例示意图。 6A to 6B are formed using a first embodiment of the diffusion barrier layer between the top of the production method of the present invention on a semiconductor substrate and an upper Al Cu cushion Fig. 下面结合附图对本发明 The present invention with reference to the following

的具体实施方式做一详细的说明。 Specific embodiments do a detailed explanation. 图6A为在半导体衬底上的Cu布线层以及介质隔离层表面形成扩散阻挡层的结构示意图。 Figure 6A a schematic configuration of a Cu diffusion barrier layer is a wiring layer and a dielectric spacer layer surface is formed on the semiconductor substrate. 半导体衬底61带有介质隔离层62和Cu布线层63, Cu布线层63镶嵌于介质隔离层62中,在Cu布线层63和介质隔离层62表面形成扩散阻挡层64,所述扩散阻挡层64由面心立方结构的TaN构成。 The semiconductor substrate 61 with a dielectric spacer layer 62 and the Cu wiring layer 63, Cu wiring layer 63 embedded in the dielectric spacer layer 62, the surface of the Cu wiring layer 62 dielectric spacer layer 63 and the diffusion barrier layer 64 is formed, the diffusion barrier layer 64 consists of TaN face-centered cubic structure.

所述半导体衬底61为一层或者多层导电层和绝缘层所构成的半导体器件结构的衬底。 The semiconductor device substrate structure 61 of the semiconductor substrate one or more layers of conductive and insulating layers are formed.

所述介质隔离层62可为单层或者多层,由Si02、 USG (未掺杂硅酸盐玻璃)、BPSG(硼磷硅玻璃)、PSG(磷珪破璃)、SiN、 SiON、 SiOF、 A1N、 A1203、 BN、类金刚石、SOG(旋涂玻璃)、FOX(可流动氧化物)、聚合物等组中的至少一种及它们的组合构成。 The dielectric spacer layer 62 may be a single layer or a multi-layer, the Si02, USG (undoped silicate glass), BPSG (borophosphosilicate glass), PSG (phosphorus glass breaking Gui), SiN, SiON, SiOF, A1N, A1203, BN, diamond-like carbon, SOG (spin on glass), FOX (flowable oxide), at least one polymer, and combinations thereof and other groups.

所述Cu布线层63采用公知的光刻和刻蚀4支术形成,Cu布线层63为可为单层或者多层的Cu薄膜组成。 The Cu wiring layer 63 using well-known photolithography and etching technique 4 formed, Cu wiring layer 63 may be a single layer or a multilayer film composed of Cu.

所述扩散阻挡层64可以为单层或者多层,扩散阻挡层64的厚度范围为30至100nm范围。 The diffusion barrier layer 64 may be a single layer or multi-layer, diffusion barrier layer 64 thickness in the range of 30 to 100nm range. 扩散阻挡层64可采用物理气相沉积(PVD )、化学气相沉积(CVI))或者真空蒸发、脉沖激光沉积(PLD)、或者其他现有镀膜方式形成。 The diffusion barrier layer 64 may be a physical vapor deposition (PVD), chemical vapor deposition (CVI)) or vacuum evaporation, pulsed laser deposition (PLD), or other conventional coating is formed. 比较优选的制备方式为物理气相沉积(PVD)方式,选用金属Ta作靶, 沉积功率范围为3000 W至8000 W,沉积的气氛为Ar和N2的混合气体,N2 的流量范围为25 scan至55 sccm,沉积时候衬底温度范围为80至150汇。 More preferably prepared in a manner as physical vapor deposition (PVD) methods, the choice of metal for the Ta target, deposition power in the range of 3000 W to 8000 W, the deposition atmosphere of a mixed gas of Ar and N2, and N2 flow range is 55 to 25 scan sccm, deposition when the substrate temperature range of 80-150 sinks.

扩散阻挡层64的面心立方晶体结构可以在沉积过程中形成,也可以在沉积成其他晶体结构以后比如体心立方结构,采用原位退火或者移置到退火炉中形成面心立方结构。 The diffusion barrier layer of the face-centered cubic crystal structure 64 may be formed during the deposition process can also be deposited into other crystal structure after such a body-centered cubic structure, the use of in situ or relocated into the annealing furnace annealing to form a face-centered cubic structure.

在本发明的一个实施方式中,采用:Ta作靶,利用PVD装置,在L3xl0'2 至1.3x 1(T'Pa气压下,在N2和Ar的气氛下,N2的流量为40sccm,在120 X: 下,以每秒1.5 nm的沉积速率形成T^I薄膜,沉积功率为5500 W,形成的 In one embodiment of the present invention, using: Ta as a target, utilizing PVD apparatus, in L3xl0'2 to 1.3x 1 (T'Pa under pressure, under an atmosphere of N2 and Ar, N2 flow rate was 40sccm, 120 X: under a deposition rate of 1.5 nm per second, forming T ^ I film deposition power of 5500 W, is formed

TaN薄膜的厚度为65 nm, TaN薄膜的晶体结构为面心立方结构。 TaN film thickness of 65 nm, the crystal structure of TaN film is face-centered cubic structure.

在本发明的另一个实施方式中,利用PVD装置,在1.3x 1(^Pa至6.5x 10-2 Pa气压下,在N2和Ar的混合气氛下,N2流量为10 sccm,以每秒1.5 nm 的沉积速率形成TaN薄膜,沉积功率为卯00W,形成的TaN薄膜的厚度为70mn, TaN薄膜的晶体结构为体心立方结构。 In another embodiment of the present invention, the use of PVD apparatus, at 1.3x 1 (^ Pa to 6.5x 10-2 Pa pressure, in a mixed atmosphere of N2 and Ar, N2 flow rate of 10 sccm, 1.5 sec The deposition rate nm formed TaN film deposition power sockets 00W, the thickness of the TaN film is formed 70mn, the crystal structure of TaN film is a body-centered cubic structure.

然后在N2气氛下,利用快速退火炉(RTA),在80 r至450 XD温度下, 退火处理30 s至300 s时间,退火过程的升温速率为10至30 t:/s,降温速率为5至30 "C/s。经过退火后形成的TaN薄膜结构为面心立方结构,此TaN 层作为防Cu扩散的扩散阻挡层64。 And then under N2 atmosphere, the use of rapid annealing furnace (RTA), at a temperature of 80 r to 450 XD, annealing 30 s to 300 s time, the heating rate of the annealing process is 10 to 30 t: / s, the cooling rate of 5 to 30 "C / s. TaN film structure after annealing for a face-centered cubic structure, the diffusion of this TaN layer as an anti-diffusion barrier layer 64 Cu.

参照图6B为在扩散阻挡层64上形成Al垫层65结构示意图。 Referring to FIG. 6B is formed cushion Al diffusion barrier layer 64 65 structure diagram. Al垫层65 可为单层或者多层,Al垫层的厚度范围为9500 A至10500 A, Al垫层的图形采用公知的光刻和刻蚀4支术形成。 Al cushion 65 may be a single layer or multi-layer, Al cushion thickness ranging from 9500 A to 10500 A, Al cushion graphics using well-known photolithography and etching four art form.

在本发明的一个具体实施方式中,采用A1作靶,利用PVD装置,在2.6 xl(T"Pa气压下,在Ar气氛下,在270 X:温度下,以每秒167A的沉积速率形成八l薄膜,沉积功率为22000 W。 In one specific embodiment of the present invention, the use of A1 as a target, utilizing PVD apparatus, in 2.6 xl ("T Pa under pressure, under Ar atmosphere, in a 270 X: a temperature, a deposition rate of 167A is formed of eight per second l film deposition power of 22000 W.

结合图6A至图6B,以及上述的工艺描述,本发明给出一个在Cu布线层和Al垫层之间制备扩散阻挡层的具体实施例,如下: Figure 6A bound to 6B, the description as well as the above-described process, the preparation of the present invention provides a diffusion barrier layer between the Cu wiring layer and the Al underlayer specific examples, as follows:

在半导体衬底61上形成介质隔离层62和Cu布线层63, Cu布线层63 为采用公知的光刻和刻蚀4支术形成,在暴露出的Cu布线层63以及介质隔离层62表面形成扩散阻挡层64,扩散阻挡层64采用物理气相沉积(PVD)方式形成。 Dielectric spacer layer 62 and the Cu wiring layer 63 is formed on the semiconductor substrate 61, Cu wiring layer 63 by a known photolithography and etching technique 4 formed in the Cu wiring layer 63 and the surface of the dielectric spacer layer 62 is formed to expose the diffusion barrier layer 64, the diffusion barrier layer 64 by physical vapor deposition (PVD) is formed. 选用金属Ta作靶形成TaN薄膜,沉积功率为6500 W,沉积的气氛为N2, Nb的流量为30 sccm,沉积时候衬底温度范围为100 。 Use metal Ta as a target formed TaN film deposition power of 6500 W, the deposition atmosphere of N2, Nb flow of 30 sccm, the deposition when the substrate temperature range of 100. C。 C. 采用此工艺形成的TaN扩散阻挡层64的晶体结构为面心立方结构,TaN扩散阻挡层64 的厚度为80 nm。 With this process of forming the crystal structure TaN diffusion barrier layer 64 is face-centered cubic structure, TaN thickness of the diffusion barrier layer 64 is 80 nm.

最后在扩散阻挡层64上形成A1垫层65。 Finally, the diffusion barrier layer 64 on the A1 pad 65 is formed. Al垫层65的厚度为1000nm。 Al underlayer 65 has a thickness of 1000nm.

基于以上工艺实施以后,得到最终的结构为图6B所示。 After the implementation of the above process, to obtain the final structure shown in FIG. 6B. 包括带有介质隔离层62和Cu布线层63的半导体衬底,Cu布线层63镶嵌于介质隔离层62 中,位于Cu布线层63和介质隔离层62表面的扩散阻挡层64以及位于扩散阻挡层64之上的Al垫层65,扩散阻挡层64为面心立方结构的TaN构成。 Includes a semiconductor substrate with a dielectric spacer layer 62 and the Cu wiring layer 63, Cu wiring layer 63 embedded in the dielectric spacer layer 62, the Cu wiring layer 63 located on the surface of dielectric spacer layer 62 and the diffusion barrier layer 64 and the diffusion barrier layer located 64 Al cushion over 65, the diffusion barrier layer 64 is a face-centered cubic structure TaN composition.

采用英国百得(Bcdc )公司的BedeMetrix™ - F型号的X射线衍射仪测试了上述扩散阻挡层64的X射线衍射图傳(XRD ),结果如图7所示,制备的TaN扩散阻挡层64分别在20为35.847 、 41.603 、 60.414。 The British Black & Decker (Bcdc) company BedeMetrix ™ - F models of X-ray diffraction test of the diffusion barrier layer 64 of X-ray diffraction pattern transfer (XRD), the results shown in Figure 7, TaN diffusion barrier layer 64 is prepared respectively, in 20 to 35.847 , 41.603 , 60.414. 和72.222 。 And 72.222. 处出现比较强的衍射峰,这些峰分别相应于(lll)、 (200)、 (220)和(331) 的衍射面上,和标准镨相对照,TaN的晶体结构为面心立方(fcc)结构。 Appear at the relatively strong diffraction peaks, these peaks correspond to (lll), (200), (220) and (331) diffraction plane, and the standard praseodymium contrast, TaN crystal structure of face-centered cubic (fcc) structure.

采用HC1腐蚀上述部分Al垫层之后的形貌采用西努光学仪器有P艮公司的徕卡(Lcica) Inm 300型号光学显微镜进行测试,结果如图8所示,Al垫层65表面比较干净和光滑,没有出现图3中的黑色沾污21,表明没有Cu扩散进入Al垫层65中,表明本发明技术制备的面心立方结构的TaN扩散阻挡层64防止Cu扩散和电迁移能力较好。 HC1 using morphology after etching said part of the Al cushion Xinu optical instrument using a P-Gen's Leica (Lcica) Inm 300 type optical microscope test, the results shown in Figure 8, 65 surface Al cushion relatively clean and smooth , does not appear in Figure 3 black stain 21, showed no Cu diffusion into Al cushion 65, indicating that the face-centered cubic structure of the present invention prepared TaN Cu diffusion barrier layer 64 to prevent the diffusion and electromigration better.

相应地,采用美国费(Fei)公司制备的DB 235型离子束聚焦(FIB )设备测试了Cu布线层63的截面形貌,结果如图9所示,Cu布线层63均匀连续,没有出现图4所示的空洞,表明Cu布线层63没有发生扩散。 Accordingly, the use of US fee (Fei) company prepared DB 235 type ion beam focusing (FIB) equipment to test the cross-sectional shape of the Cu wiring layer 63, the result 9, Cu wiring layer 63 is uniformly continuous figure, does not appear in Fig. 4 empty, indicating that the Cu wiring layer 63 is no diffusion occurs.

同时,采用本发明技术形成的扩散阻挡层64后,测试了Cu布线层63的电迁移特性,在套利特有限公司(Qulitau,Ltd.)的电迁移(EM)系统上进行, 结果如图IOA和IOB所示,图IOA给出完成布线的晶片上不同单元电迁移率的'n下对数正态分布曲线,可以看出这些单元在75小时开始出现失效,曲线比较陡直,表明采用本发明制备的扩散阻挡层64阻挡效果比较好。 At the same time, the use of technology diffusion barrier layer 64 after the formation of the present invention, the test characteristics of Cu electromigration wiring layer 63, on the set of Split Limited (Qulitau, Ltd.) The electro-migration (EM) system, results are shown in IOA and IOB, Figure IOA given on the routed chip 'n lognormal distribution curve under different unit electric mobility, we can see that these units began to fail in 75 hours, relatively steep curve, indicating that the present The prepared barrier diffusion barrier layer 64 is better. 在所有测试的单元中,在】50小时大约测试的单元中一半出现失效,然后在大约180 小时左右,由于Cu自身的电迁移特性,所有单元全部失效。 In all tests the unit, in a cell 50 hours] about half of the test failure occurs, then at around 180 hours, due to the characteristics of Cu electromigration itself, all the units all the failures.

图IOB给出相对阻值退化曲线,可以看出,75小时之前,电阻保持不变, 之后出现由于电迁移出现的空洞导致的电阻增大峰,在大约180小时,电阻的增大出现最高峰。 Figure IOB is given relative degradation resistance curve, it can be seen 75 hours before, the resistance remains unchanged after the emergence electromigration resistance since the voids resulting in an increase in the peak occurring at approximately 180 hours, the resistance increasing peak appears. 这是由于Cu自身的电迁移所致,表明此时由于电迁移出现的空洞体积最大,造成电阻最大。 This is because its own electricity due to the migration of Cu, indicating the volume of the cavity appears at this time due to electromigration maximum, resulting in maximum resistance. 与采用现有技术制备的Cu布线层和扩散阻挡层相比(结果如图5所示),图5中在10小时就出现电阻增大峰,表明在Cu线中出现了空洞造成电阻增大,而改变扩散阻挡层制备工艺后,在Cu 自身的电迁移特性出现以前没有在Cu布线层63中出现空洞,与图7的光学显微镜结果相对应,表明本发明的形成面心立方结构的TaN扩散阻挡层64的阻挡Cu扩散和电迁移能力比较好。 Compared with the prior art using Cu wiring layer and the diffusion barrier layer was prepared (the results shown in Figure 5), Fig. 5 in 10 hours appeared to increase the resistance peak, it indicates a void caused by the increase in the Cu line resistance, And after changing the diffusion barrier layer preparation process, in Cu electromigration characteristics itself does not appear empty before the advent of the Cu wiring layer 63, and an optical microscope results in Fig. 7 corresponds show TaN diffusion form a face-centered cubic structure of the present invention. Cu diffusion barrier and electromigration barrier layer 64 is better.

图1】A至图llB是采用本发明的制备方法在半导体衬底上的顶层Cu和上层Al垫层之间形成扩散阻挡层的第二实施例的示意图。 Figure 1] A through llB the preparation process of the present invention employs a diagram of an embodiment of the second diffusion barrier layer is formed on the semiconductor substrate between the top of the upper Cu and Al cushion. 下面结合附图对本发明的具体实施方式做一详细的说明。 With reference to the following specific embodiments of the present invention is to make a detailed explanation. 图IIA为在半导体衬底上的Cu布线层以及介质隔离层表面形成扩散阻挡层的结构示意图。 Figure IIA diffusion barrier layer is a schematic view of the structure of a Cu wiring layer and the surface of dielectric spacer layer is formed on the semiconductor substrate. 半导体衬底61带有介质隔离层62和Cu布线层63, Cu布线层63镶嵌于介质隔离层62中,在Cu布线层63和介质隔离层62表面形成接触膜层71,在接触膜层71上形成扩散阻挡层72,所述扩散阻挡层64由面心立方结构的TaN构成。 The semiconductor substrate 61 with a dielectric spacer layer 62 and the Cu wiring layer 63, Cu wiring layer 63 is embedded in the dielectric spacer layer 62, the Cu wiring layer 63 and the dielectric isolation layer 62 is formed on the surface in contact layer 71, the contact layer 71 diffusion barrier layer 72 is formed on the diffusion barrier layer 64 consists of a face-centered cubic structure of TaN.

接触膜71由铂族元素、铁族元素中的任意金属构成,以便Cu布线层63 和扩散阻挡层64之间的粘附性更好。 Contact film 71 is a platinum group element, any element of the iron group metal, so that the Cu wiring layer 63 and the diffusion barrier layer 64 between the adhesion better.

扩散阻挡层72采用实施例一中的方法形成,在此不作详迷。 The diffusion barrier layer 72 using the method described in example 1 is formed, which I will not detail fan.

参照图11B为在扩散阻挡层72上形成A1垫层73示意图,A1垫层的图形采用公知的光刻和刻蚀4支术形成。 Referring to FIG. 11B is a diffusion barrier layer 72 in schematic form A1 cushion 73, A1 cushion graphics using well-known photolithography and etching four art form.

基于以上工艺实施以后,得到最终的结构为图11B所示。 After the implementation of the above process, to obtain the final structure shown in FIG. 11B. 包括带有介质隔离层62和Cu布线层63的半导体衬底,Cu布线层63镶嵌于介质隔离层62中,位于Cu布线层63和介质隔离层62表面的接触膜层71;位于接触膜层71之上的扩散阻挡层72以及位于扩散阻挡层72之上的铝垫层73,所述的扩散阻挡层72为面心立方结构的氮化钽构成。 Including a semiconductor substrate with a dielectric spacer layer 62 and the Cu wiring layer 63, Cu wiring layer 63 embedded in the dielectric spacer layer 62, Cu 62 located on the surface of the wiring layer 63 and the dielectric spacer layer contacting layer 71; the contact layer located 71 above the diffusion barrier layer 72 and located above the diffusion barrier layer 72 of aluminum cushion 73, the diffusion barrier layer 72 of tantalum nitride constituting the face-centered cubic structure.

虽然本发明己以较佳实施例披露如上,但本发明并非限定于此。 Although already in the preferred embodiment of the present invention to disclose the above, the present invention is not limited thereto. 任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改, 因此本发明的保护范围应当以权利要求所限定的范围为准。 Any skilled in the art, without departing from the spirit and scope of the present invention, various changes and modifications can be made, and therefore the scope of the invention defined by the claims should be based on the scope of subject.

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Referenced by
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CN101882587B4 May 200928 Mar 2012中芯国际集成电路制造(北京)有限公司Structure for achieving wire bonding and packaging and production method thereof
CN101924095B20 Aug 200911 Jul 2012南亚科技股份有限公司Interconnection structure of semiconductor integrated circuit and method for making the same
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Classifications
International ClassificationH01L23/532, H01L21/768
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