CN100428453C - Interconnect structures incorporating low-k dielectric barrier films - Google Patents
Interconnect structures incorporating low-k dielectric barrier films Download PDFInfo
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- CN100428453C CN100428453C CNB2004800028783A CN200480002878A CN100428453C CN 100428453 C CN100428453 C CN 100428453C CN B2004800028783 A CNB2004800028783 A CN B2004800028783A CN 200480002878 A CN200480002878 A CN 200480002878A CN 100428453 C CN100428453 C CN 100428453C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween where the ceramic diffusion barrier has a composition, SivNwCxOyHz, where 0.1<=v<=0.9, 0<=w<=0.5, 0.01<=x<=0.9, 0<=y<=0.7, 0.01<=z<=0.8 for v+w+x+y+Z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.
Description
Quoting alternately of related application
The present invention requires the rights and interests of No. 60/443,504, the U.S. Provisional Patent Application submitted on January 29th, 2003, in this article with way of reference in conjunction with its full content with open.
Technical field
The dielectric layer that the present invention relates to will have low-k (k≤3.3) and barrier properties is used for the barrier metal diffusion.Or rather, be in metal interconnect structure, to use dielectric barrier layer as integrated circuit and microelectronic component parts.Major advantage of the present invention is the electric capacity that has reduced between conductive metal features such as copper lead-in wire, thereby has promoted the overall performance of chip.
Background technology
The material that metal is played the diffusion barrier effect can be added in the metal interconnect structure as an integrated circuit part.For obtaining positive means, be typical requirement to the diffusion barrier of metal, because low k interlayer dielectric layer does not generally stop the diffusion of metal.The metal diffusion barrier layer material that disposes in interconnection structure can be different, and this often depends on the character and the process thereof of diffusion barrier metal.The barrier layer that is made of metal and dielectric material is usually used in the interconnection structure.
The diffusion impervious layer that is made of metal includes, but are not limited to: tantalum, tungsten, ruthenium, tantalum nitride, titanium nitride TiSiN etc.Diffusion impervious layer Chang Zuowei lining, thereby become the conformal interface of metallic conduction structure.These materials generally use chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputter, thermal evaporation and other relevant methods to make.In order to use these materials as barrier layers, metal barrier must be conformal to the metal lead wire of conduction, can not be as cover layer, otherwise can become conductive channel.
The approach that realizes this barrier layer has a lot.A qualifications on this barrier layer is that it can not be too high to the contribution of conductive metal wire resistivity; Otherwise the increase of metallic conduction structure all-in resistance can cause decreased performance.
The diffusion impervious layer that is made of dielectric material also is used for microelectronic component, and this class dielectric material includes, but are not limited to: silicon nitride, carborundum, and fire sand.These materials use chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD) method to come deposit usually, but and deposit be continuous film.Different with the diffusion impervious layer of metal, but this dielectric layer deposit is a cover layer, and can place between the conductive metal wire.Like this, these dielectric layers just have contribution to the electric capacity between metal lead wire.A restrictive condition to this system is its higher dielectric constant (k=4.5-7.0), and this can make the effective dielectric constant between metal lead wire enlarge markedly, and causes device performance to descend.The thickness that reduces these barrier layers also can reduce effective dielectric constant " k "; Yet bed thickness inadequately can be unreliable, and dielectric constant is also had very big negative effect.Another shortcoming of this system is and its deposition apparatus and technology cost related and complexity.
Also proposed to use the spin coated dielectric material, or other are based on methods making barrier film of solvent, this film and copper have suitable joint portion to assign to stop the diffusion of copper.This system is based on the bound fraction of copper as additive, thereby several potential shortcomings are arranged.Because bound fraction and dielectric matrix do not have covalent bond, bound fraction can be evicted from from matrix by diffusion process, solvent discharge and pyrolysis, thereby has lost the barrier properties to copper.
Summary of the invention
The present invention relates to the interconnection structure of (for example, the k≤3.3) ceramic diffusion barrier layer that has low-k, ceramic diffusion barrier layer is used for the diffusion of barrier metal, and by the method based on solvent, for example, spin coated is made.This invention can be used for including, but are not limited in the microelectronic component of any use metal interconnect structure: high speed microprocessor, application-specific integrated circuit (ASIC) (ASICs) and mnemonic.Compared with prior art, it is superior using the low k ceramic diffusion barrier layer of spin coated, because this can be easy to obtain economically diffusion impervious layer, and can make microelectronic component improve performance by the electric capacity that reduces between conductive metal wire.
This interconnection structure can comprise at least one and be produced on conductive metal features on the substrate, and substrate also comprises at least one insulating barrier that surrounds conductive metal features.This insulating barrier from the bottom surface, above and the side surround at least one conductive metal features.This structure also can comprise the barrier layer of at least one conduction, and this barrier layer is produced at least one interface between insulating barrier and conductive metal features.But the combination of repeat conduction metallicity and insulating barrier and generate the stacked interconnection of multilayer.
Interconnection structure can be one of silicon wafer, ceramic carrier, organic chip seat, glass substrate, gallium arsenide wafer, silicon carbide wafer, gallium wafer or other semiconductor wafers of containing microelectronic component.
In first kind of execution mode of the present invention, a kind of interconnection structure with ceramic diffusion barrier layer has been described.In general, the interconnection structure of being invented comprises:
Be produced at least one conductive metal features on the substrate;
Surround at least one interlayer dielectric layer of at least one conductive metal features; And
Be produced on the ceramic diffusion barrier layer between at least one interlayer dielectric layer and at least one conductive metal features, the component of described ceramic diffusion barrier layer is Si
vN
wC
xO
yH
z, 0.1≤v≤0.9,0≤w≤0.5,0.01≤x≤0.9,0≤y≤0.7,0.01≤z≤0.8 wherein, and v+w+x+y+z=1.
In first example of first kind of execution mode, use method (for example, spin coated) to apply polymer-ceramic (preceramic) precursor based on solvent, to generate ceramic diffusion barrier layer, be also referred to as cap barrier layer film.Remaining interconnection structure can comprise via dielectric layer, line level dielectric, hard mask layer and only lose buried regions.
In second example of first kind of execution mode, apply polymeric precursor with method same as described above and generate cap barrier layer film, and simultaneously as low k cap barrier layer film and through hole dielectric film.The interconnection structure that the method is made has the interlayer dielectric layer of mixing, and its line level dielectric can be any dielectric film, and via layer dielectric layer and ceramic diffusion barrier layer can be combined into one deck.
In the 3rd example of first kind of execution mode, apply polymeric precursor with method same as described above and generate ceramic diffusion barrier layer, and simultaneously as low k ceramic diffusion barrier layer, the interlayer dielectric layer of via layer and the interlayer dielectric layer of trace layer.The interlayer dielectric layer of the interconnection structure that the method is made, the dielectric layer of its via layer and trace layer combines with ceramic diffusion barrier layer, forms a continuous interlayer dielectric layer.
In the 4th example of first kind of execution mode, apply polymeric precursor with method same as described above, on interconnection structure, to generate ceramic diffusion barrier layer, the interlayer dielectric layer of interconnection structure comprises at least two dielectric layers, and wherein the dielectric layer below metal lead wire chemically is being different from other regional dielectric layers.
Ceramic diffusion barrier layer has the low-k less than about 3.3, less than about 2.8, more preferably is about 2.6 preferably.Ceramic diffusion barrier layer also stops the diffusion of metal (being preferably copper), and is stable under about 300 ℃ temperature.Ceramic diffusion barrier layer also can be porous, and this can further reduce dielectric constant " k " to less than about 2.6, is most preferably about 1.6.The available sacrificial section of removing, this part can be a polymer, produces pore.Also available a kind of technology of removing high boiling solvent that comprises produces pore.Pore is of a size of about 0.5-20nm, and its pattern can be the cell of sealing.
In second kind of execution mode of the present invention, a kind of manufacture method of ceramic diffusion barrier layer has been described.In general, the method for being invented may further comprise the steps:
Apply the polymeric precursor coating on substrate, this substrate has a metal area and an insulation layer at least, and wherein the component of polymeric precursor is Si
vN
wC
xO
yH
z, 0.1≤v≤0.8,0≤w≤0.8,0.05≤x≤0.8,0≤y≤0.3,0.05≤z≤0.8 wherein, and v+w+x+y+z=1; And
Polymeric precursor is changed into the ceramic diffusion barrier layer that stops metal diffusing.
The component of used polymeric precursor also can be Si in second kind of execution mode
vN
wC
xO
yH
z, 0.1＜v＜0.8,0＜w＜0.8,0.05＜x＜0.8,0＜y＜0.3,0.05＜z＜0.8 wherein, and v+w+x+y+z=1.
More specifically, earlier polymeric precursor is dissolved in the suitable solvent, spin coated is on interconnection structure again, and this interconnection structure has the metal that exposes and the upper space of dielectric material, to form ceramic diffusion barrier layer.But elevated temperature for example, rises to about 400 ℃ by about 200 ℃, ceramic diffusion barrier layer is annealed remove residual solvent, and make material crosslinked.Useful common process generates ceramic diffusion barrier layer and makes interconnection structure, makes it to have the barrier film of low k, and metal lead wire and interlayer dielectric layer are separated.
After the coating, change the polymeric precursor film into ceramic diffusion barrier layer by using a kind of technology or any suitable process combination, these technologies comprise: hot curing, electron irradiation, ion exposure, ultraviolet and/or radiation of visible light etc.During this technology, the polymeric precursor crosslinkable becomes hard insoluble matter and generates ceramic diffusion barrier layer.The dielectric constant of gained ceramic diffusion barrier layer is less than about 3.3, and it is heat-staple, has low-leakage current, high breakdown field values, and stop metal (being preferably copper) diffusion.For the system that is generated by siliceous polymeric precursor, the component of ceramic diffusion barrier layer is Si
vN
wC
xO
yH
z, 0.1≤v≤0.9,0≤w≤0.5,0.01≤x≤0.9,0≤y≤0.7,0.01≤z≤0.8 wherein, and v+w+x+y+z=1.The component of ceramic diffusion barrier layer also can be Si
vN
wC
xO
yH
z, 0.1＜v＜0.9,0＜w＜0.5,0.01＜x＜0.9,0＜y＜0.7,0.01＜z＜0.8 wherein, and v+w+x+y+z=1.
In the third execution mode of the present invention, the component of the ceramic diffusion barrier layer of making has been described.Polymeric precursor is the molecule that a kind of usefulness generates ceramic diffusion barrier layer, makes ceramic diffusion barrier layer have low-k (k≤3.3), stops metal diffusing and be heat-staple under about 300 ℃ temperature.Polymeric precursor can have any chain structure (comprising wire, network-like, chain, complicated and confused shape), and can comprise one or more monomer units with any sequence arrangement (irregular, that replace, block, taper or the like).Polymeric precursor also can be the physical mixture of two or more component of polymer.
The optional own silicon of polymeric precursor comprises as the system of part frame construction: polysilazane, Polycarbosilane, poly-silicon silazane (polysilasilazane), polysilane, poly-silicon-carbon silane (polysilacarbosilane), poly-epoxy silazane, polycarbosilazanes and poly-silicon carbonyl silazane (polysilacarbosilazane).The chain framework of polymeric precursor also can be connected with suspension functional group and include, but are not limited to: hydrogenation base (hydrido), vinyl, pi-allyl, alkoxyl and groups.Polymeric precursor also can include the carbon skeleton structure and hang the system of functional group, hangs functional group and comprises Si and N at least, also C, O and H can be arranged.Such examples of materials is poly-silicyl carbonyl imidodicarbonic diamide [poly (silylcarbodiimide)].In general, can to make the component of ceramic diffusion barrier layer be Si to these siliceous polymeric precursor
vN
wC
xO
yH
z, 0.1≤v≤0.9,0≤w≤0.5,0.01≤x≤0.9,0≤y≤0.7,0.01≤z≤0.8 wherein, and v+w+x+y+z=1.It is Si that siliceous polymeric precursor also can make the component of ceramic diffusion barrier layer
vN
wC
xO
yH
z, 0.1＜v＜0.9,0＜w＜0.5,0.01＜x＜0.9,0＜y＜0.7,0.01＜z＜0.8 wherein, and v+w+x+y+z=1.
Description of drawings
Fig. 1 is the profile of a kind of semiconductor device of the present invention.
Fig. 2 is the profile of the another kind of semiconductor device of the present invention.
Fig. 3 makes the general technology flow process of ceramic diffusion barrier layer for the present invention.
Fig. 4 (a) and 4 (b) are the electrology characteristic example of ceramic diffusion barrier layer of the present invention.
Embodiment
Discuss structure, method and the component that relates to ceramic diffusion barrier layer of the present invention in more detail now with reference to accompanying drawing.Notice that in the accompanying drawings, same and corresponding part is to represent with same reference number.
According to the present invention, the interconnection structure that provides contains metal and dielectric material portion, and ceramic diffusion barrier layer wherein is to be made by the dielectric material of the low-k (k＜3.3) of barrier metal diffusion.Ceramic diffusion barrier layer is generated by polymeric precursor, and polymeric precursor is deposited on the interconnection structure to be made by the technology based on solvent, and these technologies include, but are not limited to: spin coated, scanning coating, spraying, drip and be coated with, use scraping blade etc.The thickness of film can be about 5-1000nm.Suitable solvent comprises those general in any coating solvents, include, but are not limited to: 1-Methoxy-2-propyl acetate (propylene glycol methyl ether acetate) (PGMEA), propylene glycol monomethyl ether (propylene glycol methyl ether) (PGME), toluene, dimethylbenzene, mesitylene, butyrolactone, ketone, cyclohexanone, hexanone, heptanone and ethyl lactate.
Available any appropriate process of knowing is cleaned interconnection structure before the deposit polymeric precursor.This cleaning can be wet-cleaned, comprises being exposed in acid, alkali and the organic solvent.This cleaning also can comprise the dry corrosion process of knowing.
Change the polymeric precursor film into ceramic diffusion barrier layer with a kind of technology or any suitable process combination then, these technologies include, but are not limited to: hot curing, electron irradiation, ion exposure, ultraviolet and/or radiation of visible light.Thermal annealing can and carry out in the inert atmosphere under surpassing about 400 ℃ temperature.During this period, the polymeric precursor crosslinkable becomes hard insoluble matter and generates cap barrier layer film, and its dielectric constant can be less than about 3.3.In addition, ceramic diffusion barrier layer typically is heat-staple, has low-leakage current, high breakdown field values, and stop metal (being preferably copper) to diffuse through this film.
Referring to Fig. 1, there is shown an example of interconnection structure 40 in first kind of execution mode, this interconnection structure comprises a plurality of aspects 1000, wherein each aspect all can comprise via layer 1100 and trace layer 1200.This interconnection structure contains the conductive metal features 33 of laterally passing through this structure, and can the interface be arranged with the lining metal that contains the barrier layer (lining metal containing barrier) 34.This conductive metal features 33 is all surrounded by dielectric layer with the lining metal 34 that contains the lining barrier layer.Dielectric layer in the via layer 1100 comprises via layer dielectric layer 32 and ceramic diffusion barrier layer 36.Dielectric layer in the trace layer 1200 comprises line level dielectric 31 and optionally hard mask dielectric 41.Between via layer dielectric layer 32 and line level dielectric 31, also dielectric etch stop layer 37 can be set alternatively.Line level dielectric 31 can comprise hard mask dielectric 41, and its component is different from remaining line level dielectric 31.
This interconnection structure can be made by a plurality of operations, comprises the combination of using photoetching, chemico-mechanical polishing (CMP), reactive ion etching, thermal annealing, wet-chemical cleaning, using coating process deposition film, usefulness chemical vapor deposition method deposition film and these technologies based on solvent.
Ceramic diffusion barrier layer 36 is to be generated by the polymeric precursor that applies on interconnection structure, and available any coating scheme based on solvent applies polymeric precursor, and this includes, but are not limited to: spin coated, scanning coating, drip and be coated with, spray and make up.By using a kind of technology or any suitable process combination to change polymeric precursor into ceramic diffusion barrier layer 36, these technologies comprise: hot curing, electron irradiation, ion exposure, ultraviolet and/or radiation of visible light etc. then.During this technology, the polymeric precursor crosslinkable becomes hard insoluble matter.The ceramic diffusion barrier layer 36 of gained has low-k (k＜3.3), stops metal (being preferably copper) diffusion, and is heat-staple under about 300 ℃ temperature.
Polymeric precursor can have any chain structure (comprising wire, network-like, chain, complicated and confused shape), and can comprise with any sequence arrangement (homopolymers, irregular copolymer, replace, block copolymer, mixing taper, polymer etc.) one or more monomer units.Polymeric precursor also can be the mixture of two or more component of polymer.The molecular weight of polymeric precursor is about 500-1000000.
Polymeric precursor can be selected from the system of silicon as the part framework and comprise: polysilazane, Polycarbosilane, poly-silicon silazane (polysilasilazane), polysilane, poly-silicon-carbon silane (polysilacarbosilane), poly-epoxy silazane, polycarbosilazanes, poly-silicyl carbonyl imidodicarbonic diamide (polysilylcarbodiimide) and poly-silicon carbonyl silazane (polysilacarbosilazane).The composition that some polysiloxanes or polysilsesquioxane (polysilsesquioxane) also can be arranged in the structure of polymeric precursor.Polymeric precursor also can be polyureas methyl ethylene silazane (polyureamethylvinylsilazane) or polyureas methyl ethylene silazane (KiON).Also can be connected with the functional group of suspension on the chain framework of polymeric precursor, comprise hydride (hydrido), vinyl, pi-allyl, alkoxyl, silicyl and groups.Polymeric precursor also can include the carbon skeleton structure and hang the system of functional group, hangs functional group and comprises Si and N at least, also C, O and H can be arranged.Such examples of materials is poly-silicyl carbonyl imidodicarbonic diamide.
Also can be connected with the suspension functional group with the metal affinity on the chain framework of polymeric precursor, comprise: amine, acid amides, acid imide, thioesters, thioether, urea, urethane, nitrile, isocyanates, mercaptan, sulfone, phosphine, phosphine oxide, phosphono imines, BTA, pyridine, imidazoles, acid imide, oxazole, benzoxazole, thiazole, pyrazoles, triazole, thiophene, oxadiazole, thiazine, thiazole, quinoxaline (quionoxaline), benzimidazole, hydroxyindole and indoline.In general, the component of these siliceous polymeric precursor can be Si
vN
wC
xO
yH
z, 0.1≤v≤0.8,0≤w≤0.8,0.05≤x≤0.8,0≤y≤0.3,0.05≤z≤0.8 wherein, and v+w+x+y+z=1.The component of siliceous polymeric precursor also can be Si
vN
wC
xO
yH
z, 0.1＜v＜0.8,0＜w＜0.8,0.05＜x＜0.8,0＜y＜0.3,0.05＜z＜0.8 wherein, and v+w+x+y+z=1.
For the system that is generated by siliceous polymeric precursor, the component of ceramic diffusion barrier layer can be Si
vN
wC
xO
yH
z, 0.1≤v≤0.9,0≤w≤0.5,0.01≤x≤0.9,0≤y≤0.7,0.01≤z≤0.8 wherein, and v+w+x+y+z=1.The component of ceramic diffusion barrier layer also can be Si
vN
wC
xO
yH
z, 0.1＜v＜0.9,0＜w＜0.5,0.01＜x＜0.9,0＜y＜0.7,0.01＜z＜0.8 wherein, and v+w+x+y+z=1.The example of a kind of preferred ingredient of this ceramic diffusion barrier layer is Si
0.16N
0.17C
0.17H
0.5
Line level dielectric and via layer dielectric layer all are to have low-k (k＜3) and be higher than heat-staple dielectric material under about 300 ℃ temperature.The preferred material of line level dielectric 32 and via layer dielectric layer 31 is: polysiloxanes, polysilsesquioxane, poly (arylene ether) (polyarylene), poly-(arlydene ether) [poly (arylene ether)] and the component that generates with chemical vapor deposition method are Si
vN
wC
xO
yH
zDielectric material, 0.05≤v≤0.8,0≤w≤0.9,0.05≤x≤0.8,0≤y≤0.8,0.05≤z≤0.8 wherein, and v+w+x+y+z=1.The component of dielectric material also can be Si
vN
wC
xO
yH
z, 0.05＜v＜0.8,0＜w＜0.9,0.05＜x＜0.8,0＜y＜0.8,0.05＜z＜0.8 wherein, and v+w+x+y+z=1.Alternatively, dielectric material also can be air or inert gas.This advanced low-k materials also can be porous.In one embodiment, line level dielectric has first component, and the via layer dielectric layer has second component, and wherein first component is different with second component.
Alternatively, also can use hard mask dielectric 41.The thickness of hard mask dielectric can be about 5-100nm.The preferred material of hard mask dielectric is: the component of polysiloxanes, polysilsesquioxane or the deposit of CVD method is Si
vN
wC
xO
yH
zDielectric material, 0.05≤v≤0.8,0≤w≤0.9,0.05≤x≤0.8,0≤y≤0.8,0.05≤z≤0.8 wherein, and v+w+x+y+z=1.The component of dielectric material also can be Si
vN
wC
xO
yH
z, 0.05＜v＜0.8,0＜w＜0.9,0.05＜x＜0.8,0＜y＜0.8,0.05＜z＜0.8 wherein, and v+w+x+y+z=1.
Alternatively, dielectric etch stop layer 37 also can place between via layer dielectric layer 32 and the line level dielectric 31.The thickness of dielectric etch stop layer can be about 5-100nm.The preferred material of dielectric etch stop layer is: the component of polysiloxanes, polysilsesquioxane or the deposit of CVD method is Si
vN
wC
xO
yH
zDielectric material, 0.05≤v≤0.8,0≤w≤0.9,0.05≤x≤0.8,0≤y≤0.8,0.05≤z≤0.8 wherein, and v+w+x+y+z=1.Si
vN
wC
xO
yH
z, 0.05＜v＜0.8,0＜w＜0.9,0.05＜x＜0.8,0＜y＜0.8,0.05＜z＜0.8 wherein, and v+w+x+y+z=1 also can be the component of gate dielectric layer and line level dielectric.
The preferred material of conductive metal features is copper, gold, silver, aluminium and alloy thereof.The upper surface of conductive metal features can have a plurality of layers to reduce electromigration, and its material comprises cobalt, tungsten and phosphorus.Also but some is used for weakening the oxidation of metal to the upper surface of conductive metal features, and its material comprises: BTA, amine, acid amides, acid imide, thioesters, thioether, urea, urethane, nitrile, isocyanates, mercaptan phosphine, sulfone, phosphine, phosphine oxide, phosphono imines, pyridine, imidazoles, acid imide, oxazole, benzoxazole, thiazole, pyrazoles, triazole, thiophene, oxadiazole, thiazine, thiazole, quinoxaline, benzimidazole, hydroxyindole and indoline.The lining metal preferred material that contains the barrier layer is tantalum, tantalum nitride, tungsten, titanium, titanium nitride, ruthenium, TiSiN and combination thereof.
Referring to Fig. 2, there is shown another example of interconnection structure 40 in first kind of execution mode, this interconnection structure comprises a plurality of aspects 1000, wherein each aspect all can comprise via layer 1100 and trace layer 1200.This interconnection structure contains the conductive metal features 33 of laterally passing through this structure, and can the interface be arranged with the lining metal 34 that contains the barrier layer.This conductive metal features 33 is all surrounded by dielectric layer with the lining metal 34 that contains the barrier layer.Dielectric layer in the trace layer 1200 comprises line level dielectric 43 and optionally hard mask dielectric.Dielectric layer in the via layer 1100 is included in via layer dielectric layer 42 below the conductive metal wire, does not have line level dielectric 43 and ceramic diffusion barrier layer 36 in the metal lead wire zone on via layer.Alternatively, dielectric etch stop layer 37 can place between via layer dielectric layer 42 and the line level dielectric 43.
Referring to Fig. 3, this figure represents to make the general technology flow process of ceramic diffusion barrier layer.In step 1, use any general coating solvent to prepare the solution that contains polymeric precursor, these solvents include, but are not limited to: 1-Methoxy-2-propyl acetate (PGMEA), propylene glycol monomethyl ether (PGME), toluene, dimethylbenzene, methyl phenyl ethers anisole, mesitylene, butyrolactone, ketone, cyclohexanone, hexanone, ethyl lactate and heptanone.
In containing the solution of polymeric precursor, also can be total to molten optional anti-striped agent to obtain the film of high uniformity.The content of anti-striped agent can be less than containing 1% of polymeric precursor solution.
Also can be total to molten optional adhesion promoter in containing the solution of polymeric precursor, adhesion promoter can be separated out during applying polymeric precursor to the membrane interface place.Adhesion promoter can be less than and contain 2% of polymeric precursor solution.
In optional step 2, can before the deposit polymeric precursor, clean interconnection structure.Available wet-cleaned comprises interconnection structure is exposed in acid, alkali and/or the organic solvent.This cleaning step also can comprise any dry corrosion process of knowing.In optional step 3, adhesion promoter can be imposed on substrate surface (for example, on the interconnection structure).A kind of component of preferred adhesion promoter is Si
xL
yR
z, wherein L is selected from hydroxyl, methoxyl group, ethyoxyl, acetoxyl group, alkoxyl, carboxyl, amine, halogen, and R then is selected from hydrogenation base (hydrido), methyl, ethyl, vinyl and phenyl (any alkyl or aromatic radical).Adhesion promoter also can be hexamethyldisiloxane (hexamethyldisilazane), vinyltriacetoxy silane (vinyltriacetoxysilane), aminopropyl trimethoxysilane (aminopropyltrimethoxysilane), vinyltrimethoxy silane (vinyltrimethoxysilane) or its combination.
In step 4, to the substrate coating polymeric precursor that will use, use process based on solvent, comprising: spin coated, scanning coating, spraying, drip and be coated with, use scraping blade or its combination.The thickness of polymeric precursor can be 5-1000nm.In step 5, adhesion promoter can impose on the upper surface of polymeric precursor film.Preferred adhesion promoter comprise above-mentioned those.
In step 6, use a kind of technology or any suitable process integration to change polymeric precursor into ceramic diffusion barrier layer, these technologies comprise: hot curing, electron irradiation, ion exposure, ultraviolet and/or radiation of visible light etc.When thermal annealing, can surpass under about 400 ℃ temperature and comprise nitrogen, form and anneal in the inert atmosphere of gas and argon.During this period, polymeric precursor is cross-linked into hard insoluble matter.If use optionally molten adhesion promoter altogether, in this transition process adhesion promoter can separate out to film at the interface.In optional step 7, adhesion promoter can be applied to the upper surface of ceramic diffusion barrier layer.Preferred adhesion promoter comprise above-mentioned those.
The solution that contains polymeric precursor also can comprise the part that some produce pore, comprise sacrificial polymeric material, during polymeric precursor changed ceramic diffusion barrier layer into, this part material degeneration was low-molecular-weight accessory substance and/or high boiling solvent and discharge from film.This sacrificial polymeric material is selected from poly-(styrene), poly-(ester), poly-(methacrylate), poly-(acrylate), poly-(ethylene glycol), poly-(acid amides) and poly-(norborene).
Ceramic diffusion barrier layer preferably has dielectric constant less than about 3.3, and is thermally-stabilised, has low-leakage current, high breakdown field values, and stops metal (being preferably copper) to spread by rete.Referring to Fig. 4 (a) and 4 (b), verified the suitable breakdown characteristics and the leakage current characteristic of the film of making by the polysilazane polymeric precursor, the low percentage of observing when field intensity is lower than 7MV/cm punctures (Fig. 4 (a)), and all has less than 10 under room temperature and 150 ℃
-7A/cm
2Leakage current (Fig. 4 (b)).
Though we represent according to our invention and described several execution modes, person skilled in the art obviously can understand, and making many changes is acceptables.Therefore, shown in we are reluctant to be limited to and described details, but desire to make all changes and revise all within the scope of the appended claims.
Claims (20)
1. an interconnection structure comprises:
Be produced at least one conductive metal features on the substrate;
Surround at least one interlayer dielectric layer of described at least one metallicity; And
Ceramic diffusion barrier layer between described at least one interlayer dielectric layer and at least one conductive metal features, the component of described ceramic diffusion barrier layer are Si
vN
wC
xO
yH
z, 0.1≤v≤0.9,0＜w≤0.5,0.01≤x≤0.9,0≤y≤0.7,0.01≤z≤0.8 wherein, and v+w+x+y+z=1.
2. interconnection structure as claimed in claim 1, the dielectric constant of wherein said ceramic diffusion barrier layer is less than 3.3.
3. interconnection structure as claimed in claim 1, wherein said interlayer dielectric layer comprises line level dielectric.
4. interconnection structure as claimed in claim 1, wherein said interlayer dielectric layer comprise line level dielectric and via layer dielectric layer.
5. interconnection structure as claimed in claim 1, wherein said at least one interlayer dielectric layer also comprise the via layer dielectric layer of the line level dielectric and second component of first component, and wherein said first component is different with described second component.
6. structure as claimed in claim 1, the component of wherein said at least one interlayer dielectric layer comprises air or inert gas.
7. interconnection structure as claimed in claim 1, the component of wherein said at least one interlayer dielectric layer comprises Si
vN
wC
xO
yH
z, 0.05≤v≤0.8,0≤w≤0.9,0.05≤x≤0.8,0≤y≤0.8,0.05≤z≤0.8 wherein, and v+w+x+y+z=1.
8. interconnection structure as claimed in claim 1, also comprise the lining metal that contains the barrier layer, the wherein said lining metal that contains the barrier layer forms an interface between described at least one conductive metal features and described at least one interlayer dielectric layer, the wherein said lining metal that contains the barrier layer comprises tantalum, tantalum nitride, tungsten, titanium, titanium nitride, ruthenium, TiSiN or its combination.
9. interconnection structure as claimed in claim 4, wherein said at least one dielectric layer also comprise the dielectric etch stop layer that places between described line level dielectric and the described via layer dielectric layer.
10. interconnection structure as claimed in claim 1, the component of wherein said ceramic diffusion barrier layer are Si
0.16N
0.17C
0.17H
0.5
11. a method of making ceramic diffusion barrier layer comprises:
Apply polymeric precursor on Semiconductor substrate, the component of wherein said polymeric precursor is Si
vN
wC
xO
yH
z, 0.1≤v≤0.8,0≤w≤0.8,0.05≤x≤0.8,0≤y≤0.3,0.05≤z≤0.8 wherein, and v+w+x+y+z=1; And
Change described polymeric precursor into ceramic diffusion barrier layer, described ceramic diffusion barrier layer stops the diffusion of metal.
12. as the method for claim 11, wherein said polymeric precursor comprises polysilazane, Polycarbosilane, poly-silicon silazane, polysilane, poly-silicon-carbon silane, poly-epoxy silazane, polycarbosilazanes, poly-silicyl carbonyl imidodicarbonic diamide or poly-silicon carbonyl silazane.
13. as the method for claim 11, the wherein said step that applies polymeric precursor on Semiconductor substrate comprises that preparation contains the solution of described polymeric precursor and solvent; Use technology to apply described solution then based on solvent.
14. as the method for claim 13, wherein said technology based on solvent comprises spin coated, spraying, scanning coating, drip and be coated with or its combination.
15. as the method for claim 13, wherein said solution also comprises: adhesion promoter, be dissolved in altogether in the described solvent that contains described polymeric precursor, the component of adhesion promoter described herein is Si
xL
yR
z, wherein L is selected from the group that hydroxyl, methoxyl group, ethyoxyl, acetoxyl group, alkoxyl, carboxyl, amine or halogen constitute, and R then is selected from the group that hydrogenation base, methyl, ethyl, vinyl and phenyl constitute.
16. as the method for claim 13, wherein said solvent comprises 1-Methoxy-2-propyl acetate (PGMEA), propylene glycol monomethyl ether (PGME), toluene, dimethylbenzene, methyl phenyl ethers anisole, mesitylene, butyrolactone, cyclohexanone, hexanone, ethyl lactate, heptanone or its combination.
17. as the method for claim 11, the wherein said step that changes described polymeric precursor into ceramic diffusion barrier layer comprises and adopts hot curing, electron irradiation, ion exposure, ultraviolet irradiation, radiation of visible light or its combination.
18. method as claim 13, the sacrificial section that wherein also will produce pore is dissolved in the described solution that contains described polymeric precursor altogether, described sacrificial section is a sacrificial polymer, is selected from polystyrene, polyester, polymethacrylates, polyacrylate, polyethylene glycol, polyamide and polynorbornene one group.
19., wherein be formed in molten anti-striped agent altogether in the described solution that contains described polymeric precursor as the method for claim 13.
20. as the method for claim 11, wherein said Semiconductor substrate comprises at least one metal area and at least one dielectric material district, described ceramic diffusion barrier layer is between described at least one metal area and described at least one dielectric material district.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44350403P | 2003-01-29 | 2003-01-29 | |
| US60/443,504 | 2003-01-29 | ||
| US10/627,794 | 2003-07-25 |
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|---|---|
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
| CN1320953A (en) * | 2000-04-14 | 2001-11-07 | 国际商业机器公司 | Method for forming electroless plated metal lining |
| CN1373512A (en) * | 2001-02-28 | 2002-10-09 | 国际商业机器公司 | Interlink structure with accurate conductor |
-
2004
- 2004-01-26 CN CNB2004800028783A patent/CN100428453C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
| CN1320953A (en) * | 2000-04-14 | 2001-11-07 | 国际商业机器公司 | Method for forming electroless plated metal lining |
| CN1373512A (en) * | 2001-02-28 | 2002-10-09 | 国际商业机器公司 | Interlink structure with accurate conductor |
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|---|---|
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