CN100413056C - 电路装置及其制造方法 - Google Patents
电路装置及其制造方法 Download PDFInfo
- Publication number
- CN100413056C CN100413056C CNB2005100747190A CN200510074719A CN100413056C CN 100413056 C CN100413056 C CN 100413056C CN B2005100747190 A CNB2005100747190 A CN B2005100747190A CN 200510074719 A CN200510074719 A CN 200510074719A CN 100413056 C CN100413056 C CN 100413056C
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- Prior art keywords
- connecting portion
- wiring layer
- insulating barrier
- hole
- circuit arrangement
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Abstract
一种电路装置及其制造方法,用于贯通绝缘层,将层积的多个配线层相互连接。本发明的混合集成电路装置(10)及其制造方法中,介由第一绝缘层(17A)层积第一导电膜(28A),通过构图第一导电膜(28A),形成第一配线层(18A)。其次,介由第二绝缘层(17B)层积第二导电膜(28B)。而且,通过部分地除去所希望位置的第二绝缘层(17B)和第二导电膜(28A),形成将配线层相互间连接的连接部(25)。
Description
技术领域
本发明涉及电路装置及其制造方法,特别是涉及具有介由绝缘层层积的多层配线层的电路装置及其制造方法。
背景技术
参照图16说明现有混合集成电路装置100的结构(例如参照专利文献1)。图16(A)是混合集成电路装置100的立体图,图16(B)是图16(A)的X-X’线剖面图。
现有的混合集成电路装置100具有矩形衬底106和设于衬底106表面的绝缘层107,在该绝缘层107上构图配线层108。另外,在配线层108上固定有电路元件104,电路元件104和配线层108介由金属细线105电连接。和配线层108电连接的引线101被导出到外部。另外,混合集成电路装置100的整体利用密封树脂102密封,利用密封树脂102密封的方法有使用热塑性树脂的注入模模制和使用热硬性树脂的传递模模制。
专利文献1:特开平6-177295号公报
但是,在上述的混合集成电路装置100中,由于形成单层配线,故存在可集成的电路的规模有限的问题。解决该问题的方法之一有形成介由绝缘层层积的多层配线结构的方法。层积的配线层相互间利用贯通绝缘层形成的连接部电连接。另外,考虑到散热性,在该绝缘层中混入有无机填充物。但是,在为提高散热性,而在绝缘层中混入大量无机填充物时,存在难于贯通绝缘层形成连接部的问题。即,难于形成确保散热性的多层配线结构。
发明内容
本发明是鉴于上述问题而开发的,本发明的主要目的在于,提供一种电路装置及其制造方法,使高散热和高密度化同时成立。通过本发明,防止安装的LSI的温度上升,由此,维持驱动能力,并且整体上消减能耗。
本发明的电路装置包括:第一配线层及第二配线层,其夹着绝缘层而层积;第一连接部,其从所述第一配线层连续且部分地突出,并埋入所述绝缘层中;第二连接部,其从所述第二配线层连续且部分地突出,并埋入所述绝缘层中;电路元件,其经由连接机构与所述第二配线层电连接,所述第一连接部和所述第二连接部在所述绝缘层的厚度方向中间部接触。
本发明的电路装置的制造方法包括:在电路衬底表面形成第一配线层的工序;介由含有无机填充物的绝缘层在所述第一配线层上层积第二导电膜的工序;通过除去所希望位置的所述第二导电膜及所述绝缘层形成通孔,在所述通孔下面露出所述第二导电膜的工序;通过在所述通孔形成镀膜,使所述第二导电膜和所述第一配线层导通的工序;通过构图所述第二导电膜,形成第二配线层的工序。
本发明的电路装置的制造方法包括:在电路衬底表面形成具有部分地连续并沿厚度方向突出的第一连接部的第一配线层的工序;夹着含有无机填充物的绝缘层在所述第一配线层上层积第二导电膜的工序;部分地除去对应形成所述第一连接部的区域的所述第二导电膜的工序;除去因埋入所述第一连接部而较薄地形成的区域的所述绝缘层,形成通孔,使所述第一连接部的上面在所述通孔下面露出的工序;在所述通孔形成由镀膜构成的第二连接部,使所述第二导电膜和所述第一配线层导通,并且使所述第一连接部与所述第二连接部接触的部分位于所述绝缘层厚度方向的中间部的工序;通过构图所述第二导电膜,形成第二配线层的工序。
本发明的电路装置的制造方法中,在电路衬底表面形成具有部分地连续并沿厚度方向突出的第一连接部的第一配线层,覆盖所述第一配线层形成绝缘层,除去对应所述第一连接部的位置的所述绝缘层,形成露出所述第一连接部上面的通孔,和所述第一连接部接触,形成埋入所述通孔的第二连接部及和所述第二连接部构成一体的第二配线层,并且使所述第一连接部与所述第二连接部接触的部分位于所述绝缘层厚度方向的中间部,固定和所述第二配线层电连接的半导体元件。
本发明的电路装置至少具有至少表面被绝缘处理的支承衬底和形成于该支承衬底上的半导体元件,其特征在于,在位于所述支承衬底上的第一配线层上夹着绝缘层设有第二配线层,在与所述第一配线层和所述第二配线层的电连接部对应的部分设有和第一配线层一体且部分地朝向上方的第一连接部,设有和所述第二配线层一体且部分地朝向下方的第二连接部,第一连接部和第二连接部的接触部分位于第一连接部的上面和第二连接部的下面之间。
根据本发明的电路装置,在第一配线层设有第一连接部,在第二配线层设有第二连接部。另外,在层积该第一配线层及第二配线层的绝缘层的厚度方向中间部使第一连接部和第二连接部接触。因此,可提高连接部对热应力等外力的可靠性。另外,通过加工铜箔,使第一连接部或第二连接部中任一个和配线层一体形成,可提高连接部的机械强度。
根据本发明的电路装置的制造方法,即使在介由大量混入有无机填充物的绝缘层层积多层配线层的情况下,也可以形成贯通所述绝缘层使配线层相互间导通的连接部。
另外,通过在因埋入第一连接部而较薄地形成的绝缘层上设置通孔,可容易地在所述绝缘层上形成通孔。另外,由于可较浅地形成通孔,故可容易地对该通孔形成镀膜。
在绝缘层上形成通孔后,通过电镀处理,可自位于该通孔上部的周边部的第二导电膜形成镀膜。因此,即使在用于形成镀膜的条件不好的情况下,也可以形成镀膜。
附图说明
图1是说明本发明混合集成电路装置的立体图(A)、剖面图(B)、剖面图(C);
图2是说明本发明混合集成电路装置的剖面图(A),表示比较例的剖面图(B),表示比较例的剖面图(C);
图3是说明本发明混合集成电路装置的立体图;
图4(A)、(B)是说明本发明混合集成电路装置的剖面图;
图5(A)、(B)是说明本发明混合集成电路装置的剖面图;
图6(A)、(B)是说明本发明混合集成电路装置的剖面图;
图7(A)~(C)是说明本发明混合集成电路装置制造方法的剖面图;
图8(A)~(C)是说明本发明混合集成电路装置制造方法的剖面图;
图9(A)~(D)是说明本发明混合集成电路装置制造方法的剖面图;
图10(A)~(D)是说明本发明混合集成电路装置制造方法的剖面图;
图11(A)~(C)是说明本发明混合集成电路装置制造方法的剖面图;
图12(A)、(B)是说明本发明混合集成电路装置制造方法的剖面图;
图13(A)~(C)是说明本发明混合集成电路装置制造方法的剖面图;
图14(A)、(B)是说明本发明混合集成电路装置制造方法的剖面图;;
图15是说明本发明混合集成电路装置制造方法的剖面图;
图16(A)是说明现有混合集成电路装置的立体图,(B)是其剖面图。
符号说明
10混合集成电路装置
11引线
12密封树脂
14电路元件
15金属细线
16电路衬底
17A~17D绝缘层
18A~18D配线层
19焊料
24单元
25A、25B连接部
26焊盘
27热通路
28A、28D导电膜
29A~29E抗蚀剂
30通孔
31模腔
32通孔
33激光
34镀膜
具体实施方式
第一实施方式
在本形态中,作为电路装置之一例,以图1等所示的混合集成电路装置为例进行说明。但是,下述的本形态也可以适用于其它种类的电路装置。另外,下述的实施形态也可以适用于电路衬底及其制造方法。
参照图1说明本发明的混合集成电路装置10的结构。图1(A)是混合集成电路装置10的立体图,图1(B)是图1(A)的X-X’剖面的剖面图。图1(C)是放大连接部25附近的剖面的图。
在混合集成电路装置10中,参照图1(A)及图1(B),在作为支承衬底起作用的电路衬底16表面形成有由配线层18及电路元件14构成的电路。另外,形成于电路衬底16表面的电路利用密封树脂12密封。在电路衬底16的周边部,在最上层的配线层18上固定有引线11,引线11的端部从密封树脂12导出到外部。在此,也可以在最上层之外的层的配线层上固定引线11。在本形态中,配线层18具有多层配线结构,在此实现了由第一配线层18A及第二配线层18B构成的两层配线结构。各配线层18介由绝缘层层积。下面详细说明具有这种概略结构的混合集成电路装置10。
电路衬底16从散热性能而言,最好是由金属或陶瓷等构成的衬底。另外,作为电路衬底16的材料,作为金属可采用Al、Cu或Fe等,作为陶瓷可采用Al2O3、AlN。除此之外,也可以采用机械强度或散热性优良的其它材料作为电路衬底16的材料。
如实现作为本申请要点的接触结构,若忽略散热性,则可采用挠性板、印刷线路板、玻璃环氧树脂衬底等。在本形态中,考虑到散热性,在由铝构成的电路衬底16表面形成绝缘层17,在绝缘层17的表面形成配线层18。另外,在本形态中,电路衬底16的材料也可采用以铜为整体的金属。由于铜是热传导性优良的材料,故可提高装置整体的散热性。另外,在采用Al作为电路衬底16的材料时,也可以在电路衬底16的表面形成氧化膜。
第一绝缘层17A在电路衬底16的表面形成,覆盖电路衬底16的实质上整个区域。第一绝缘层17A可采用填充有填充物的树脂。在此,填充物例如可采用铝化合物、钙化合物、砷化合物、镁化合物或硅化合物。另外,为提高装置整体的散热性,而在第一绝缘层17A上含有比其它绝缘层的量大的填充物,其重量填充率为60%~80%。另外,通过在第一绝缘层17A中混入直径50μm以上的大径填充物,也可以提高散热性。第一绝缘层17A的厚度根据要求的耐压而变化,但优选约50μm~数百μm程度。
第一配线层18A由铜等金属构成,在第一绝缘层17A表面进行构图。该第一配线层18A和上层的第二配线层18B电连接,主要具有进行交又并回绕配置图案的功能。
第二绝缘层17B在电路衬底16表面形成,覆盖第一配线层18A。而且,在第二绝缘层17B上贯通形成电连接第一配线层18A和第二配线层18B的连接部25。因此,第二绝缘层17B为容易形成连接部25,和第一绝缘层17A相比较,也可以混入少量的填充物。这意味着填充物的含有率小。另外,根据相同的理由,第二绝缘层17B中含有的填充物的最大粒径也可以比第一绝缘层17A中含有的填充物的最大粒径小。
第二配线层18B在第二绝缘层17B的表面形成。第二配线层18B形成载置电路元件14的接合区、和电路元件上的电极连接的焊盘、电连接该焊盘的配线部、固定引线11的焊盘等。另外,第二配线层18B和第一配线层18A可平面交叉地形成。因此,即使在半导体元件14A具有多个电极时,利用本申请的多层配线结构也可以交又并自由地进行图案的回绕设置。该第二配线层18B和上述的第一配线层18A介由连接部25在所希望的位置连接。当然,也可以根据半导体元件的电极数、元件的安装密度等,将层数增加到3层、4层、5层或5层以上。
连接部25是贯通第二绝缘层17B,电连接第一配线层18A和第二配线层18B的部位。在本形态中,连接部25由从第一配线层18A连续延伸的第一连接部25A和从第二配线层18B连续延伸的第二连接部25B构成。连接部25的更详细的情况参照图1后述。
电路元件14固定于第二配线层18B上,由电路元件14和配线层18构成规定的电路。电路元件14采用晶体管、二极管、IC或系统LSI等有源元件,或电容、电阻等无源元件。另外,功率类半导体元件等发热量大的元件也可以介由由金属构成的散热片进行固定。在此,由于半导体元件是面朝上型,故介由金属细线15和第二配线层18B电连接,但也可以通过面朝下接合法安装。
在此,系统LSI具有模拟运算电路、数字运算电路或存储部等,是由一个LSI实现系统功能的大规模的元件。因此,和现有的LSI相比,系统LSI伴随大量的发热而动作。
在本实施形态中,可采用称为SIP的系统封装、晶片尺度CSP等作为电路元件14。SIP是层积多个芯片构成的层叠型、是平面配置并模制半导体元件或无源元件构成的平面型。
另外,在半导体元件14A的背面和接地电位连接时,半导体元件14A的背面由焊料或导电膏等固定。另外,在半导体元件14A的背面浮置时,使用绝缘性粘接剂固定半导体元件14A的背面。另外,在半导体元件14A通过面朝下接合法安装时,介由焊锡等构成的补片电极安装。
可采用控制大电流的功率类晶体管、例如功率管理操作系统、GTBT、IGBT、半导体开关元件等作为半导体元件14A。也可以采用功率类IC作为半导体元件14A。
近年来,由于芯片尺寸减小,且薄型、高功能化,故如图1、图6所示,由装置整体或模块整体来看,产生的热量逐年增大。例如,控制电脑的CPU等就是其一例。内装的元件数量大幅增加,但Si芯片本身更薄更小型。因此,每单位面积的热的产生量逐年增加。而且,由于这些IC或晶体管被大量安装,故作为装置整体,产生的热也大幅地增加。
引线11在电路衬底16的周边部固定在第二配线层18B上,例如具有和外部进行输入、输出的作用。在此,在一边上设有多个引线11,但也可以在对向的两个边、四个边配置。引线11和图案的粘接介由焊锡等焊料19构成。
密封树脂12通过使用热硬性树脂的传递模模制或使用热塑性树脂的注入模模制形成。在此,形成密封树脂12,使其密封电路衬底16及形成于其表面的电路,电路衬底16的背面从密封树脂12露出。另外,模制之外的密封方法例如可使用基于罐装进行的密封、基于壳体件进行的密封等众所周知的密封方法。参照图1(B),为使从载置于电路衬底16表面的电路元件14产生的热顺畅地排出到外部,电路衬底16的背面从密封树脂12露出到外部。另外,为提高装置整体的耐湿性,也可以利用密封树脂12密封也含有电路衬底16背面的整体。
参照图1(C)的剖面图详细说明连接部25。该剖面图是放大连接部25及其附近的混合集成电路装置10的剖面图。连接部25是贯通绝缘层17使层积的配线层18相互间导通的部位。另外,也可以使用连接部25作为用于进行配线层18相互间的热接合的热通路。
在本形态中,形成有由第一连接部25A及第二连接部25B构成的连接部25。第一连接部25A是从第一配线部18A连续沿厚度方向突出的部位。在此,第一连接部25A向上方突出,埋入第二绝缘层17B内。第二连接部25B是从第二配线层18B连续沿厚度方向突出的部位,在此,向下方突出,被埋入第二绝缘层17B中。
第一连接部25A是通过蚀刻加工沿厚度方向突出而形成的部位,由镀敷或轧制形成的Cu箔构成。另外,第一连接部25A也可以利用蚀刻加工之外的方法形成。具体地说,通过使电解镀膜或无电解镀膜在第一配线层18A的表面凸状成膜,可形成第一连接部25A。另外,在第一配线层18A的表面设置焊锡等焊料或银膏等导电性材料,也可以形成第一连接部25A。
第二连接部25B是通过电解镀敷或无电解镀敷的镀敷处理形成的部位。关于该第二连接部25B的形成方法,在说明制造方法的实施形态后述。
在本形态中,使上述的第一连接部25A和第二连接部25B接触的位置位于第二绝缘层17B的厚度方向的中间部。在此,中间部是指,第一配线层18A上面的上方,第二配线层18B下面的下方。因此,在纸面上,第一连接部25A和第二连接部25B接触的位置为第二绝缘层17B的厚度方向中央部附近,但该位置可在上述的中间部的范围内变化。在考虑通过镀敷处理形成第二连接部25B时,第一连接部25A和第二连接部25B接触的部分最好在第一配线层上面和第二配线层下面之间比其中间位置更靠上方配置。由此,具有容易形成由镀膜构成的第二连接部25B的优点。即,由后述的制造方法可知,为形成第二连接部而形成通路(via),但由于该通路的深度较浅。另外,通路直径也可以相应其减浅的量减小。另外,也可以相应通路直径减小的量缩小间隔,整体上实现微细图案。
另外,也可以部分较厚地形成第一配线层18A。由此,可使用较厚地形成的第一配线层18A作为功率类的电极或配线。而由较薄地形成的其它区域的第一配线层18A构成微细化的配线。
参照图2的各剖面图说明上述的连接部25的结构的优点。图2(A)表示本形态的连接部25的剖面形状,图2(B)及图2(C)是表示和本形态比较的比较例的剖面图。
参照图2(A)进一步详细说明本形态的连接部25的结构。首先,在最下层设有第一绝缘层17A,在该第一绝缘层17A的表面构图第一配线层18A。然后,介由第二绝缘层17B层积第二配线层18B。另外,第二配线层18B由密封整体的密封树脂12覆盖整个区域。
如上所述,连接部25由第一连接部25A和第二连接部25B构成。而且,两者接触的位置位于第二绝缘层17B的厚度方向的中间部。覆盖第一配线层18A的部分的第二绝缘层17B的厚度(D2)例如为35μm程度。而且,第一连接部25A和第二连接部25B接触的部分、与第二绝缘层17B上面的距离(D1)例如为15μm程度。通过该结构,可提高连接部25相对热应力等外力的可靠性。
另外,D1的长度最好为D2的一半以下。由此,可容易地形成第二连接部25B。即,容易地形成用于形成第二连接部25B的通孔,容易对该通孔内部形成镀膜。
下面说明上述热应力。可以考虑该热应力在各部件的界面变大。具体地说,第一配线层18A、第二绝缘层17B、密封树脂12的热膨胀系数不同。密封树脂12和第二绝缘层17B都是以树脂为主体的材料,但由于混入的无机填充物量不同等原因,热膨胀系数多少不同。由此,根据使用状况下的温度变化,在密封树脂12和第二绝缘层17B的界面、第二绝缘层17B和第一配线层18A的界面产生应力。如果简单地说,则1是现象之一是层和层相互之间产生滑移。因此,根据本形态的结构,通过使第一连接部25A和第二连接部25B接触的部分位于第二绝缘层17B的中间部,可防止上述滑移,可提高连接部25B相对热应力的可靠性。
参照图2(B)说明第一比较例。在此,形成和上层第二配线层18B一体化的连接部25。而且,埋入第二配线层17B的连接部25的前端部与第一配线层18A的表面接触。根据该比较例,连接部25与第一配线层18A和第二绝缘层17B的界面所处的面接触。因此,考虑上述界面产生的热应力对连接部25B接触的部分的影响(例如滑移)大。因此,该第一比较例的结构和本形态的结构相比,相对热应力的可靠性降低。
参照图2(C)说明第二比较例。在该比较例中从下层的第一配线层18A起形成有一体化的连接部25。另外,连接部25的上端与第二配线层18A的下面接触。如上所述,可考虑即使在第二绝缘层17B和密封树脂12的界面也会产生大的热应力。因此,由于上述热应力作用在连接部25和第二配线层18B接触的部分,故两者的连接可靠性降低。通过将上述的第一比较例及第二比较例和本申请比较,可确认本申请的连接部25相对热应力的可靠性高。
参照图3的立体图说明形成于电路衬底16表面的第二配线层18B的具体形状之一例。在同图图示中,省略了密封整体的树脂。
参照同图,第二配线层18B构成安装电路元件14的接合焊盘部分和固定引线11的焊盘26等。另外,在半导体元件14A的周边部形成多个引线接合金属细线15的焊盘。在载置具有多个接合焊盘的半导体元件14A时,在仅由第二配线层18B构成的单层图案中,由于配线密度有限,故有可能不能充分回绕设置。在本形态中,通过在电路衬底16的表面构筑多层配线结构,实现了复杂的图案盘绕设置。
参照图4说明其它形态的混合集成电路装置的结构。图4(A)及图4(B)是其它形态的混合集成电路装置的剖面图。
参照图4(A),在此,贯通第二绝缘层17B形成有热通路27。热通路27是在贯通第二绝缘层17B的孔中填充有金属的部位,作为向外部排热的经路起作用。因此,热通路27也可以不作为电通路起作用。
在此,在安装于热通路上的IC中,在芯片背面浮置的情况下,热通路也浮置时,IC电位会产生变动,故热通路最好固定在接地(ダランド)上。
具体地说,热通路形成与固定半导体元件14的接合面状的第二配线层18B下面接触。因此,即使在从半导体元件14A产生大量的热时,其热也可以介由多个热通路27传递到电路衬底16上。此时的热的经路是:半导体元件14A→第二配线层18B→热通路27→第一绝缘层17A→电路衬底16→外部。在此,热通路27由上述的第一连接部25A和第二连接部25B构成。而且,第一连接部25A和第二连接部25B接触的部分为绝缘层厚度方向的中间部。热通路27作为热的经路起作用,是预测大的热应力作用的部位,故本形态的结构有意义。
参照图4(B),在此,在第一绝缘层17A及第二绝缘层17B两者上设有热通路27。如上所述,含有大量填充物的第一绝缘层17A是散热性优良的绝缘层。因此,如同图所示,通过在第一绝缘层17A上设置热通路27,可进一步提高散热性。设于第一绝缘层17A上的热通路27也最好设于对应伴随发热的半导体元件14A下方的区域。
如上所述,在电路衬底16和第一绝缘层17A之间形成热通路27时,在电路衬底16的背面形成凸状地突出的第一连接部25A。另外,在第一配线层18A的背面设置第二连接部25B。而且,使第一连接部25A和第二连接部25B在第一绝缘层17A的中间部接触。
参照图5说明另一形态的混合集成电路装置的结构。图5(A)及图5(B)是混合集成电路装置的剖面图。
参照图5(A),在此,通过介由绝缘层17层积配线层18,构成四层配线结构。具体地说,在第一绝缘层17A的上面形成第一配线层18A。而且,介由第二绝缘层17B~第四绝缘层17D层积第二配线层18B~第四配线层18D。这样,通过增加配线层18的层数,可提高配线密度。在第二绝缘层17B~第四绝缘层17D上为连接各层相互之间的配线层,而形成有连接部25。
参照图5(B),在此,在载置焊盘数量多的半导体元件14A的区域的电路衬底16表面形成有多层配线结构,在固定电路元件14B的区域的电路衬底16表面形成有单层的配线结构。
如上所述,半导体元件14A是具有数十~数百个电极的元件。因此,为了回绕配置和半导体元件14的电极连接的图案,在半导体元件14A的周边部形成有多层配线结构。具体地说,形成有由第一配线层18A及第二配线层18B构成的多层配线层。
另外,形成多层的部分的第二配线层18B和形成单层的部分的第一配线层18A介由金属细线15电连接。
电路元件14B是例如功率类半导体元件,是伴随大量发热的开关元件。形成由第一配线层18A构成的单层配线结构的部分的电路衬底16比其它区域的散热效果大。因此,如电路元件14B这样发热量大的分立的晶体管适于直接固定在构成单层配线的第一配线层18A上。
参照图6说明再一形态的电路模块41的结构。图6(A)是表示电路模块41结构的剖面图,图6(B)是构成电路模块41局部的第一电路装置37的剖面图。
参照图6(A),在电路衬底16的表面形成有多层的配线结构。在此,构成从第一配线层18A到第四配线层18D的四层配线结构。在最上层的第四配线层18D上安装有多个电路元件。在此,固定两个电路装置。另外,裸的晶体管芯片即第一电路元件29和第二电路元件40安装于最上层的第四配线层18D上。
第一电路装置37是具有一个半导体芯片的电路装置,在支承衬底上形成有多层配线。第一电路装置37的详细结构将参照图6(B)后述。而且,第二电路装置38是内装半导体元件及无源元件而构成系统的SIP(系统封装System in package)。在此图示了平面配置电路元件实现的封装件,但也可以为叠层结构。内装于第一电路装置37或第二电路装置38的电路元件和参照图1说明的电路元件相同,可全部采用有源元件或无源元件。另外,作为直接固定于第四配线层18D的第一电路元件39或第二电路元件40也和参照图1说明的电路元件相同,可全部采用有源元件或无源元件。
参照图6(B)详细说明第一电路装置37。第一电路装置37中,在形成多层的衬底上倒装片安装半导体元件。
在此,利用第一配线层44A~第三配线层44C形成多层配线结构。因此,即使半导体元件43是具有多个焊盘的LSI元件,也可以进行来自该焊盘的配线的盘绕设置。另外,半导体元件43是倒装片安装的LSI元件,介由焊锡等焊料固定在第三配线层44C上。
连接板42的一侧介由粘接剂固定在半导体元件43的背面(纸面中上面)。而且,连接板42的另一侧被固定在配线层44C上。该连接板42作为用于排出从半导体元件43产生的热的经路起作用。因此,从半导体元件43产生的热介由连接板42传递到第三配线层44C上。另外,连接板42连接的第三配线层44C和其下方的第二配线层44B及第一配线层44A利用连接部46连接。因此,利用这些连接部46形成用于沿衬底厚度方向传递热的经路H1。该经路是作为热的经路起作用的部位。另外,在半导体元件43的背面和接地电位连接时,这些经路也具有作为和接地电位连接的经路的功能。
另外,参照图6(A),位于经路H1最下部的第一配线层44A介由焊锡与层积于电路衬底16表面的第四配线层18D连接。而且,在经路H1下方形成有由利用连接部25连接的各配线层构成的经路H2。经路H2是用于将从第一电路装置37产生的热传递到电路衬底16上的经路。通过上述的结构,从内装于第一电路装置37内的半导体元件产生的热介由形成于第一电路装置37内部的第一经路H1、形成于电路衬底16表面的第二经路H2传递到电路衬底16上。并将其热排出到外部。如上所述,电路模块41构成散热性优良的结构。
第二实施形态
在本形态中,作为电路装置之一例,以混合集成电路装置为例进行制造方法的说明。但是,下述的本形态的制造方法也可以适用于其它种类的电路装置的制造方法。
首先,参照图7(A),在电路衬底16的表面涂敷第一绝缘层17A,层积第一导电膜28A。作为电路衬底16,可采用厚度1.5mm左右的金属衬底。另外,作为第一导电膜28A,可采用以铜为主材料的材料、以Fe-Ni或Al为主材料的材料。第一导电箔28A的厚度必须为预定形成的第一配线层18A的厚度和第一连接部25A的高度相加的厚度或其以上。具体地说,第一导电膜28A的厚度例如在20μm~150μm程度的范围。抗蚀剂29A覆盖予定形成第一连接部25A的区域的第一导电膜28A的表面。在利用抗蚀剂29A覆盖的状态下,进行蚀刻。另外,第一绝缘层17A可采用在环氧树脂等绝缘性树脂中混入无机填充物的材料。在此,混入的无机填充物是SiO2、Al2O3、SiC、AlN等。
图7(B)表示进行蚀刻后的状态的剖面。在此,利用抗蚀剂29A覆盖的区域凸状地突出。利用该凸状突出的的部位形成第一连接部25A。而且,在表面露出的状态下,进行蚀刻的区域的第一导电膜28A同样厚度变薄。在本工序结束后,将抗蚀剂29A剥离。在此,第一连接部25A突出的高度调整为数十μm程度。图7(C)表示剥离了抗蚀剂29A的状态的第一连接部25A。
其次,参照图8说明在第一导电膜28A的表面形成第一连接部25A的另一方法。在此,通过在第一导电膜28A的表面选择性地形成镀膜,形成第一连接部25A。
参照图8(A),首先,选择性地在第一导电膜28A的表面形成抗蚀剂29B。具体地说,在除去形成第一连接部25A的予定区域外的区域,形成抗蚀剂29B。
其次,参照图8(B),在从抗蚀剂29B选择地露出的第一导电膜28A的表面使镀膜成长。该镀膜的成膜可采用电解镀敷处理、无电解镀敷处理或将两者组合使用的方法。在本工序结束后,进行抗蚀剂29B的剥离,得到图8(C)所示的凸状的第一连接部25A。
参照图9(A)~图9(C),其次,利用抗蚀剂29C覆盖包括第一连接部25A的上面的第一导电膜28A。另外,在对抗蚀剂29C按照予定形成的第一配线层18A构图后,进行蚀刻,由此,进行第一配线层18A的构图。在第一配线层18A的蚀刻结束后,将抗蚀剂29C剥离。
参照图9(D),其次,介由覆盖第一配线层18A的第二绝缘层17B层积第二导电膜28B。该方法考虑三个以下方法。第一方法是,覆盖第一配线层18A形成第二绝缘层17B,然后,在第二绝缘层17B的表面形成由镀膜构成的第二导电膜28B。第二方法是,在进行第二绝缘层17B的形成后,在第二绝缘层17B的表面压装由轧制铜箔等构成的第二导电膜28B。根据该第二方法,第二绝缘层17B和第二导电膜28B接合的强度提高。第三方法是,层积在背面付着有第二绝缘层17B的第二导电膜28B覆盖第一配线层18A。即使是该第三方法,也可以提高第二绝缘层17B和第二导电膜28B接合的强度。另外,第一连接部25A的侧面构成锥状,由此,具有容易向第二树脂层17B埋入第一连接部25A的优点。
参照图10,其次,部分地除去形成连接部25的位置的第二绝缘层17B及第二导电膜28B,形成通孔32。首先,参照图10A,部分地除去对应形成通孔32的予定区域的第二导电膜28B。具体地说,除形成通孔32的予定区域外,在第二导电膜28B的表面形成抗蚀剂29D,然后,进行蚀刻。由此,部分地除去第二导电膜28B,形成通孔32。另外,通过除去其下方的第二绝缘层17B,加深通孔32。在通孔32的下面露出第一配线层18A的表面。在此,使设于第一配线层18A的第一连接部25A的上面在通孔32的下面露出。
参照图10(B)进一步详细说明通孔32的形成方法。在本形态中,通过埋入第一连接部25A,通孔32下方的第二绝缘层17B变薄。而且,通过使用激光等除去变薄的区域的第二绝缘层17B,在通孔32的下部露出第一连接部25A。在大部分的区域,第二绝缘层17B的厚度T2例如为50μm程度。与此相对,对应通孔32下方的区域的第二绝缘层17B的厚度变薄为例如10μm~25μm程度。
因此,在假定利用激光形成相同长宽比的通孔32时,根据本形态,可形成直径小的通孔32。在所述这样的条件下,由于可以以一半程度形成通孔的直径,故可将通孔32占有的面积缩小到1/4程度。这有利于装置整体的小型化。另外,为确保散热性,在第二绝缘层17B中混入无机填充物,由此,利用激光形成通孔32会多少困难一些。为了在这种情况下形成通孔32,减薄形成通孔32的区域的第二绝缘层17B是有意义的。
图10(C)表示利用上述方法形成通孔32后的剖面。从各通孔32的下面露出第一连接部25A的上面。而且,从利用激光处理形成的通孔32的侧壁露出混入第二绝缘层17B中的填充物。为提高散热性,而在本形态的第二绝缘层17B中混入多种直径的填充物。因此,通孔32的侧壁构成具有凹凸的形状。这些填充物具有代表性的是Al2O3、AlN等。另外,在利用上述激光处理在通孔32的底部残留残渣时,要进行用于清除该残渣的清洗。
第一连接部25A的平面的大小形成得比形成于其上方的通孔32大。换句话说,由于通孔32及第一连接部25A的平面的形状为圆形,故第一连接部25A的直径比通孔32的直径大。列举一例,在通孔32的直径W1为100μm程度时,第一连接部25A的直径W2形成150μm~200μm程度。另外,通孔32的直径W1为30μm~50μm时,第一连接部25A的直径W2调整为50μm~70μm程度。这样,通过增大第一连接部25A的平面大小,使其比通孔32大,即使多少伴随位置偏差而形成通孔32时,也可以使通孔32位于第一连接部25A的上方。因此,可防止上述位置偏差造成的连接可靠性降低。另外,作为第一连接部25A的平面的形状,也可以采用圆形以外的形状。
参照图10(D)说明形成通孔32的其它方法。在上述说明中,在利用第二导电膜28B覆盖第二绝缘层17B后,形成通孔32,但也可以利用其它方法进行通孔32的形成。具体地说,可在覆盖第二导电膜28A之前,除去第二绝缘层17B,使第一连接部25A的上面从通孔32的下部露出。
当图10(A)的通孔实质上为10微米时,二氧化碳激光其波长不会使树脂飞散。虽然可考虑取而代之使用YAG激光,但此时存在使Cu飞散而被去掉的问题。因此,可以不设置第二导电膜28B而直接利用YAG将绝缘树脂飞散去掉,形成通孔32。相对于激光的光点直径,作为可烧蚀的深度比光点直径浅。因此,由于具有第一连接部25A,故可缩小烧蚀的深度,使脉冲数减少。
另外,也可以代替激光各向同性进行湿式蚀刻。此时,众所周知,第一连接部25A的高度,即第二绝缘层17B的厚度影响开口直径。因此,减薄第二绝缘层17B具有可减小开口直径的优点。也可以利用公知的半导体技术的干式蚀刻来实现。此时,由于开口深度浅,故相应可缩短蚀刻时间。
另外,为利用以下工序进行镀敷处理,而进行作为前处理的锌酸盐处理。在此,锌酸盐处理是通过使用含有Zn离子的碱溶液进行无电解镀敷处理,而使镀敷处理容易的处理。
其次参照图11及图12,说明通过在通孔32中形成镀膜,形成第二连接部25B,使第一配线层18A和第二导电膜28B导通的工序。该镀敷的形成可考虑两个方法。第一个方法是在通过无电解镀敷形成镀膜后,通过电解镀敷再次形成镀膜的方法。第二个方法是仅通过电解镀敷处理形成镀膜的方法。
参照图11说明形成镀膜的上述第一方法。首先,参照图11(A),在也含有通孔32侧壁的第二导电膜28B的表面通过进行无电解镀敷处理形成镀膜34。该镀膜34的厚度为3μm~5μm程度即可。
其次,参照图11(B),在镀膜34的上面利用电解镀敷法形成新的镀膜35。具体地说,以形成镀膜34的第二导电膜28B为阴极电极,通过电解镀敷法形成镀膜35。利用上述的无电解镀敷法在通孔32的内壁形成镀膜34。因此,在此形成的镀膜35包括通孔32的内壁也形成同样的厚度。由此,形成由镀膜形成的第二连接部25B。具体的镀膜35的厚度例如为20μm程度。上述的镀膜34及镀膜35的材料可采用和第二导电膜28B相同的材料即铜。另外,也可以采用铜以外的金属作为镀膜34及镀膜35的材料。
参照图11(C),在此,通过进行填充镀敷,利用镀膜35埋入通孔32。通过进行该填充镀敷,可提高第二连接部25B的机械强度。
其次,参照图12说明使用电解镀敷法形成第二连接部25B的方法。
参照图12(A),首先,使含有金属离子的溶液接触通孔32。在此,可采用铜、金、银、钯等作为镀膜的材料。而且,当以第二导电膜28B作为阴极电极流过电流时,金属在作为阴极电极的第二导电膜28B上析出,形成镀膜。在此,由标号36A、36B表示镀膜成长的情况。在电解镀敷法中,在电场强的位置优先形成镀膜。在本形态中,该电场在面向通孔32周边部的部分的第二导电膜28B增强。因此,如该图所示,从面向通孔32周边部的部分的第二导电膜28B优先成长镀膜。在形成的镀膜与第一连接部25A接触的时刻,第一配线层18A和第二导电膜28B导通。然后,同样在通孔32内部形成镀膜。由此,在通孔32的内部形成和第二导电膜28B一体化的第二连接部25B。
其次参照图12(B),说明形成第二连接部25B的其它方法。在此,通过在通孔32的周边部设置遮檐13,容易利用电解镀敷法形成第二连接部25B。在此,遮檐是指,覆盖通孔32周边部由突出的第二导电膜28B构成的部位。遮檐13的具体的制造方法在利用激光形成通孔32时,可通过增大该激光的功率进行。通过增大激光的功率,由激光沿横向进行第二绝缘层17B的除去,除去遮檐13下方区域的树脂。通过利用上述条件进行以第二导电膜28B为阴极电极的电解镀敷处理,从遮檐13的部分优先成长镀膜。通过从遮檐13成长镀膜,与图12(A)的情况相比,可优先向下方成长镀膜。因此,可可靠采用镀膜埋入通孔32。
如上所述,本形态的通孔32的侧壁构成具有凹凸的形状。另外,在通孔32的侧壁露出混入第二绝缘层17B中的无机填充物。由此,难于在通孔32的侧壁形成镀膜。通常,在作为无机物的填充物表面难于附着镀膜,但特别是在AlN在通孔32的侧壁露出时,难于形成镀膜。因此,在本形态中,通过使用上述电解镀敷法的方法形成第二连接部25B。
在本形态中,通过在通孔32中形成镀膜,必然也在第二导电膜28B的表面形成镀膜,其厚度增厚。但是,在本形态中,如上所述,由于在10μm程度的浅的通孔32中形成镀膜,故可减薄形成的镀膜的总厚度。因此,基于附着镀膜的第二导电膜28B的厚度的增加量小,故可使第二导电膜28B保持薄的状态。因此,可微细地形成由第二导电膜28B形成的第二配线层18B。
另外,即使在通过施行填充镀敷,埋入通孔32时,如上所述,由于较浅地形成通孔32,因此,可容易地进行填充镀敷。
参照图13(A),通过形成第二连接部25B,形成由第一连接部25A及第二连接部25B构成的连接部25。另外,参照图13(B),通过进行使用抗蚀剂29E的选择性的蚀刻,形成第二配线层18B。进一步参照图13(C),在此,形成由第一配线层18A、第二配线层18B、第三配线层18C构成的三层的多层配线。此时,在第二配线层18B上,在上面及下面两面形成凸状突出的连接部25。
参照图14(A),其次,介由焊锡或导电膏等将电路元件14固定在第二配线层18B(岛)上。在此,利用面朝下接合法安装有源元件,但也可以根据需要利用面朝下接合法进行。另外,参照图14(B),介由金属细线15进行电路元件14和第二配线层18B的电连接。
在上述工序结束后,进行各单元24的分离。各单元24的分离可通过使用冲压机的冲切、切割、折曲等进行。然后,在各单元24的电路衬底16上固定引线11。
参照图15,其次,进行各电路衬底16的树脂密封。在此,通过使用热硬性树脂的传递模模制进行密封。即,在由上模型30A及下模型30B构成的模型30中收纳电路衬底16,然后,通过将两模型咬合,进行引线11的固定。然后,通过向模腔31中封入密封树脂,进行树脂密封的工序。利用以上的工序制造其结构示于图1的混合集成电路装置。
Claims (15)
1. 一种电路装置,其特征在于,包括:第一配线层及第二配线层,其形成在电路衬底的上面,并且夹着一层绝缘层而层积;第一连接部,其从所述第一配线层延伸而突出,并且埋入所述绝缘层中;第二连接部,其从所述第二配线层延伸而突出,并且埋入所述绝缘层中;电路元件,其经由连接机构与所述第二配线层电连接,所述第一连接部和所述第二连接部在所述绝缘层的厚度方向中间部接触。
2. 如权利要求1所述的电路装置,其特征在于,所述绝缘层由含有填充物的树脂构成。
3. 如权利要求1所述的电路装置,其特征在于,所述第一连接部或所述第二连接部通过蚀刻加工一张铜箔而形成。
4. 如权利要求1所述的电路装置,其特征在于,所述第一连接部或所述第二连接部由镀膜构成。
5. 如权利要求1所述的电路装置,其特征在于,所述第一连接部通过蚀刻加工一张铜箔而形成,所述第二连接部由镀膜构成。
6. 一种电路装置的制造方法,其特征在于,在电路衬底表面形成具有第一连接部的第一配线层的工序,该第一连接部在电路衬底的上面部分地连续延伸而突出;夹着含有填充物的一层绝缘层在所述第一配线层上层积第二导电膜的工序;部分地除去对应形成所述第一连接部的区域的所述第二导电膜的工序;除去通过埋入所述第一连接部而较薄地形成的区域的所述绝缘层,形成通孔,使所述第一连接部上面在所述通孔下面露出的工序;通过在所述通孔形成由镀膜构成的第二连接部,使所述第二导电膜和所述第一配线层导通,并且使与所述第一连接部与所述第二连接部接触的部分位于所述绝缘层厚度方向的中间部的工序;通过构图所述第二导电膜,形成第二配线层的工序。
7. 如权利要求6所述的电路装置的制造方法,其特征在于,所述通孔的形成如下进行,即部分地除去所述第二导电膜,使所述绝缘层露出,在露出的所述绝缘层上照射激光将其除去形成所述通孔。
8. 如权利要求6所述的电路装置的制造方法,其特征在于,在利用无电解镀敷处理在所述通孔的侧壁形成镀膜后,通过进行电解镀敷处理并在所述通孔形成新的镀膜,使所述第一配线层和所述第二导电膜导通。
9. 如权利要求6所述的电路装置的制造方法,通过进行将所述第二导电膜作为电极使用的电解镀敷处理,从位于所述通孔周边部的所述第二导电膜朝向所述通孔的内侧形成镀膜,利用所述镀膜将所述第一配线层和所述第二导电膜导通。
10. 如权利要求9所述的电路装置的制造方法,其特征在于,在所述通孔的周边部形成由所述第二导电膜构成的遮檐,从所述遮檐朝向所述通孔内侧形成镀膜。
11. 一种电路装置的制造方法,其特征在于,在电路衬底表面形成具有部分地延伸而突出的第一连接部的第一配线层,覆盖所述第一配线层形成一层绝缘层,除去对应所述第一连接部的位置的所述绝缘层,形成露出所述第一连接部上面的通孔,和所述第一连接部接触,形成埋入所述通孔的第二连接部及和所述第二连接部构成一体的第二配线层,并且使所述第一连接部与所述第二连接部接触的部分位于所述绝缘层厚度方向的中间部,固定和所述第二配线层电连接的半导体元件。
12. 如权利要求11所述的电路装置的制造方法,其特征在于,在所述绝缘层中混入有填充物。
13. 如权利要求11所述的电路装置的制造方法,其特征在于,在露出所述第一连接部时,使用YAG激光。
14. 一种电路装置,至少具有至少表面被绝缘处理的支承衬底和形成于该支承衬底上的半导体元件,其特征在于,在位于所述支承衬底上的第一配线层上夹着一层绝缘层设有第二配线层,在所述第一配线层和所述第二配线层的对应电连接部的部分设置和第一配线层一体且部分地朝向上方的第一连接部、和所述第二配线层一体且部分地朝向下方的第二连接部,第一连接部与第二连接部的接触部分位于第一连接部上面和第二连接部下面之间。
15. 如权利要求14所述的电路装置,其特征在于,所述接触部分设置在厚度方向上,比所述第一配线层更靠近所述第二配线层的位置。
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JP (1) | JP2005347353A (zh) |
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CN1705108A (zh) | 2005-12-07 |
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JP2005347353A (ja) | 2005-12-15 |
TW200539764A (en) | 2005-12-01 |
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US7315083B2 (en) | 2008-01-01 |
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