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Publication numberCN100397218 C
Publication typeGrant
Application numberCN 200410085055
Publication date25 Jun 2008
Filing date27 Mar 2001
Priority date27 Mar 2000
Also published asCN1197141C, CN1319781A, CN1598677A, US7218361, US7486344, US20010052950, US20070138480
Publication number200410085055.3, CN 100397218 C, CN 100397218C, CN 200410085055, CN-C-100397218, CN100397218 C, CN100397218C, CN200410085055, CN200410085055.3
Inventors小山润, 小野幸治, 山崎舜平, 荒尾达也, 须泽英臣
Applicant株式会社半导体能源研究所
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Semiconductor display device and making method thereof
CN 100397218 C
Abstract  translated from Chinese
提供了一种高可靠性的半导体显示器件。 It provides a highly reliable semiconductor display device. 半导体显示器件中的半导体层具有沟道形成区、LDD区、以及源区和漏区,且LDD区与第一栅电极重叠,栅绝缘膜夹于其间。 The semiconductor display device of the semiconductor layer having a channel forming region, LDD region, and a source region and a drain region, and the LDD region overlaps with the first gate electrode, a gate insulating film interposed therebetween.
Claims(30)  translated from Chinese
1. 一种液晶显示器件,包括: 像素TFT和驱动电路TFT,各具有:制作在绝缘表面上的半导体层;制作在所述半导体层上的栅绝缘膜;制作在所述栅绝缘膜上的第一栅电极;以及制作在所述第一栅电极上的第二栅电极; 其中所述像素TFT的所述半导体层包含: 与所述第二栅电极重叠的沟道形成区,所述栅绝缘膜夹于其间; 与所述沟道形成区接触并与所述第一栅电极重叠的第一LDD区,所述栅绝缘膜夹于其间; 与所述第一LDD区接触的第二LDD区; 与所述第二LDD区接触的源区和漏区, 其中所述驱动电路TFT的半导体层包含: 与所述第二栅电极重叠的沟道形成区,所述栅绝缘膜夹于其间; 与所述沟道形成区接触并与所述第一栅电极重叠的第三LDD区,所述栅绝缘膜夹于其间; 与所述第三LDD区接触的源区和漏区, 其中所述第一栅电极沿所述沟道形成区纵向的宽度大于所述第二栅电极的宽度,以及其中所述栅绝缘膜在所述第一栅电极覆盖所述栅绝缘膜的区域中具有第一厚度和在所述第一栅电极没有覆盖所述栅绝缘膜的区域中具有第二厚度,并且所述第二厚度小于所述第一厚度。 A liquid crystal display device, comprising: a pixel TFT and the driver circuit TFT, each having: an insulating surface formed on a semiconductor layer; a gate insulating film on the semiconductor layer; said gate insulating film in the production of and formed on said first gate electrode of the second gate electrode;; wherein said first semiconductor layer is a gate electrode of said pixel TFT comprising: a second gate electrode overlaps with the channel formation region, the gate an insulating film interposed therebetween; contact with the channel forming region and overlapping with the first gate electrode of the first LDD region, said gate insulating film interposed therebetween; a second contact with the first LDD region LDD region; source and drain regions in contact with the second LDD regions, wherein said driver circuit TFT semiconductor layer comprising: a second gate electrode overlaps with the channel formation region, the gate insulating film interposed therebetween ; contact with the channel forming region and overlapping the first gate electrode with the third LDD region, said gate insulating film interposed therebetween; a source region and a drain region in contact with the third LDD regions, wherein said first gate electrode along the longitudinal direction of the channel region is formed wider than the width of the second gate electrode, and wherein said gate insulating film covering the first gate electrode of the gate insulating film having a first region having a thickness and a second thickness in a region not covered with the gate electrode of the first gate insulating film, and said second thickness less than the first thickness.
2. 按照权利要求1的液晶显示器件,其特征是其中的所述第一栅电极在边缘部分具有锥形剖面。 2. The liquid crystal display device according to claim 1, characterized in that one of the edge portions of the first gate electrode has a tapered cross-section.
3. 按照权利要求1的液晶显示器件,其特征是其中的所述第一或第三LDD区含有一个区域,其所述杂质浓度梯度至少为1 x 1017-' 1 x 1018原子/cm3的范围,而且随距所述沟道形成区距离的增加而增大。 3. The liquid crystal display device according to claim 1, characterized in that one of said first or third LDD region contains a region that the impurity concentration gradient in a range of at least 1 x 1017- '1 x 1018 atoms / cm3 and with the distance from the channel forming region increases and increases.
4. 按照权利要求1的液晶显示器件,其特征是所述第一或第三LDD区是以所述第二栅电极作掩模按自对准方式向所述半导体层掺入杂质元素而形成的。 4. A liquid crystal display device according to claim 1, wherein said first or third LDD region is the second gate electrode as a mask in a self-aligning manner by adding an impurity to the semiconductor layer to form element a.
5. —种液晶显示器件,包括:制作在绝缘表面上的半导体层,所述半导体层具有沟道形成区、与所述沟道形成区接触的LDD区、以及与所述LDD区接触的源区和漏区;制作在所述半导体层上的栅绝缘膜; 制作在所述栅绝缘膜上的第一栅电极和第一引线; 第二栅电极形成于所述第一栅电极上,和第二引线形成于所述第一引线上;制作在所述第一栅电极、所述第一引线、所述第二栅电极和所述第二引线上的第一层间绝缘膜;制作在所述第一层间绝缘膜上的第二层间绝缘膜;制作在所述第二层间绝缘膜上,并经所述第二层间绝缘膜中开的第一接触孔与所述第一层间绝缘膜接触的中间引线;其中所述沟道形成区与所述第二栅电极重叠,所述栅绝缘膜夹于其间;其中所述LDD区与所述第一栅电极重叠,所述栅绝缘膜夹于其间;其中所述中间引线与所述第二引线重叠,所述第一层间绝缘膜在所述第一接触孔中夹于其间,且其中所述中间引线经形成于所述栅绝缘膜、所述第一层间绝缘膜和所述第二层间绝缘膜中的第二接触孔,与所述源区或所述漏区相连。 5. - Species liquid crystal display device, comprising: an insulating surface formed on the semiconductor layer, the semiconductor layer having a channel forming region, LDD regions in contact with the source of the channel forming region, and in contact with the LDD regions region and a drain region; a gate insulating film on the semiconductor layer; a first gate electrode made of the first lead and the gate insulating film; a second gate electrode formed on said first gate electrode, and The second lead is formed on the first lead; produced in the first gate electrode, the first lead, the second gate electrode and the first interlayer insulating film on said second lead; fabricated a first contact hole made in the second interlayer insulating film, and through said second interlayer insulating film with the first opening; second interlayer insulating film of the first interlayer insulating film inter-layer insulating film in contact with the intermediate lead; wherein said channel forming region overlaps with the second gate electrode, said gate insulating film interposed therebetween; wherein the LDD regions overlap with the first gate electrode, the said gate insulating film interposed therebetween; wherein the intermediate wiring overlaps with the second lead, the first interlayer insulating film in the first contact hole interposed therebetween, and wherein the intermediate wiring is formed by said gate insulating film, the first interlayer insulating film and the second interlayer insulating film in the second contact hole, is connected to the source region or the drain region.
6. 按照权利要求5的液晶显示器件,其特征是,包括制作在所述第二层间绝缘膜上的屏蔽膜,所述屏蔽膜由与所述中间引线相同的材料制成;以及其中所述屏蔽膜与沟道形成区重叠。 6. A liquid crystal display device according to claim 5, characterized in that, including the production of the second layer between the insulating film barrier film, the shielding film is made of the same material as the intermediate lead; and wherein said shielding film overlaps with the channel forming region.
7. —种液晶显示器件,包括:制作在绝缘表面上的半导体层,所述半导体层具有沟道形成区、 与所述沟道形成区接触的LDD区、以及与所述LDD区接触的源区和漏区;制作在所述半导体层上的栅绝缘膜; 制作在所述栅绝缘膜上的第一栅电极和第一引线; 第二栅电极形成于所述第一栅电极上,和第二引线形成于所述第一引线上;制作在所述第一栅电极、所述第一引线、所述第二栅电极和所述第二引线上的第一层间绝缘膜;制作在所述第一层间绝缘膜上的第二层间绝缘膜;制作在所述第二层间绝缘膜上,并经所述第二层间绝缘膜中开的接触孔与所述第一层间绝缘膜接触的中间引线;制作在所述第二层间绝缘膜上的屏蔽膜,所述屏蔽膜由与所述中间引线相同的材料制成;其中所述沟道形成区与所述第二栅电极重叠,所述栅绝缘膜夹于其间;其中所述LDD区与所述第一栅电极重叠,所述栅绝缘膜夹于其间;其中所述中间引线与所述第二引线重叠,所述第一层间绝缘膜在所述接触孔中夹于其间,且其中所述屏蔽膜与沟道形成区重叠。 7. - Liquid crystal display device, comprising: an insulating surface formed on the semiconductor layer, the semiconductor layer having a channel forming region, LDD region in contact with the channel forming region, and the LDD regions in contact with the source region and a drain region; a gate insulating film on the semiconductor layer; a first gate electrode made of the first lead and the gate insulating film; a second gate electrode formed on said first gate electrode, and The second lead is formed on the first lead; produced in the first gate electrode, the first lead, the second gate electrode and the first interlayer insulating film on said second lead; fabricated production in the second interlayer insulating film, and through said second interlayer insulating film in the opening of the first contact hole layer; the first layer of the second interlayer insulating film between the insulating film an intermediate insulating film in contact with the lead; the second layer is produced between the shielding film of the insulating film, the shielding film is made of the same material as the intermediate wiring; wherein said channel formation region and the first two overlapping the gate electrode, the gate insulating film interposed therebetween; wherein the LDD regions overlap with the first gate electrode, said gate insulating film interposed therebetween; wherein the intermediate wiring overlaps with the second lead, the first interlayer insulating film in the contact hole interposed therebetween, and wherein the shielding film overlaps with the channel forming region.
8. —种液晶显示器件,包括: 制作在衬底上的屏蔽膜; 制作在所述屏蔽膜上的绝缘膜;制作在所述绝缘膜上的半导体层,所述半导体层具有沟道形成区、与所述沟道形成区接触的LDD区、以及与所述LDD区接触的源区和漏区;制作在所述半导体层上的栅绝缘膜;制作在所述栅绝缘膜上的第一栅电极;第二栅电极形成于所述第一栅电极上;其中所述沟道形成区与所述第二栅电极重叠,所述栅绝缘膜夹于其间;其中所述LDD区与所述第一栅电极重叠,所述栅绝缘膜夹于其间,且其中所述屏蔽膜与所述沟道形成区重叠,所述绝缘膜夹于其间。 8. - Liquid crystal display device, comprising: a substrate formed on the shielding film; film produced in said insulating shield film; produced having a channel region formed in a semiconductor layer of the insulating film, the semiconductor layer , LDD region in contact with the channel forming region, LDD regions in contact with said source region and a drain region; a semiconductor layer formed on said gate insulating film; said gate insulating film in the production of a first a gate electrode; a second gate electrode formed on said first gate electrode; wherein said channel forming region overlaps the second gate electrode, said gate insulating film interposed therebetween; wherein the LDD region and the a first gate electrode overlaps said gate insulating film interposed therebetween, and wherein the shielding film overlaps with the channel forming region, said insulating film interposed therebetween.
9. 按照权利要求8的液晶显示器件,其特征是其中所述绝缘膜是用CMP抛光来抛平的。 9. A liquid crystal display device according to claim 8, characterized in that wherein said insulating film is polished by CMP for polishing flat.
10. 按照权利要求1、 5、 7和8的任一权利要求的液晶显示器件, 其特征是其中所述液晶显示器件被组合到选自摄象机、数码相机、投影^义、头戴式显示i殳备、游戏机、车辆导航系统、个人计算机以及袖珍信息终端的电子学设备中。 10. according to claim 1, 5, to any one of claims 7 and 8 wherein the liquid crystal display device, wherein the liquid crystal display device which is incorporated into selected cameras, digital cameras, projectors ^ justice, headphones i Shu display devices, game consoles, car navigation systems, personal computers and portable electronics equipment information terminal.
11. 一种制作液晶显示器件的方法,包括以下步骤:在绝缘表面上制作半导体层; 在所述半导体层上制作栅绝缘膜; 在所述栅绝缘膜上制作第一导电膜; 在所述第一导电膜上制作第二导电膜;将所述第一导电膜和所述第二导电膜图形化成第一栅电极和第二栅电极;在所述半导体层中掺入第一杂质元素;在所述半导体层上制作掩模,使之覆盖所述第一栅电极和所述第二栅电极;在所述半导体层中掺入与所述第一杂质元素导电类型相同的第二杂质元素,以形成沟道形成区、与所述沟道形成区接触的笫一LDD 区、与所述第一LDD区接触的第二LDD区、以及与所述第二LDD区接触的源区和漏区;在所述半导体层、所述第一栅电极和所述第二栅电极上制作层间绝缘膜;在所述层间绝缘膜中开接触孔;以及制作经所述接触孔电连接到所述源区或所述漏区的像素电极, 其中所述第一栅电极沿沟道形成区纵向的宽度大于所述第二栅电极的宽度;其中所述沟道形成区与所述第二栅电极重叠,栅绝缘膜夹于其间;其中所述第一LDD区与所述第一栅电极重叠,所述栅绝缘膜夹于其间;以及其中所述栅绝缘膜在所述第一栅电极覆盖所述栅绝缘膜的区域中具有第一厚度和在所述第一栅电极没有覆盖所述栅绝缘膜的区域中具有第二厚度,并且所述第二厚度小于所述第一厚度。 11. A method of making a liquid crystal display device, comprising the steps of: forming a semiconductor layer on an insulating surface; the semiconductor layer on a gate insulating film; said gate insulating film made of the first conductive film; in the a first conductive film made of the second conductive film; the first conductive film and the second conductive film pattern into a first gate electrode and second gate electrode; a first impurity element incorporated in said semiconductor layer; making a mask on the semiconductor layer, so as to cover the first gate electrode and the second gate electrode; said first impurity element incorporated with the same conductivity type impurity element in said second semiconductor layer , to form a channel forming region, LDD regions Zi in contact with the channel forming region, second LDD regions in contact with the first LDD regions, and a source region and a drain contact with the second LDD region region; in said semiconductor layer, an interlayer insulating film forming on the first gate electrode and the second gate electrode; opening a contact hole in the interlayer insulating film; and the production through the contact hole is electrically connected to the source region or the drain region of the pixel electrode, wherein the first gate electrode along the longitudinal direction of the channel region is formed wider than the width of the second gate electrode; wherein said channel formation region and the second overlapping the gate electrode, a gate insulating film interposed therebetween; wherein the first LDD regions overlap with the first gate electrode, said gate insulating film interposed therebetween; and wherein said gate insulating film on the first gate electrode covering a region of the gate insulating film having a first thickness and a second thickness in a region having the first gate electrode does not cover the gate insulating film, and said second thickness less than the first thickness.
12. —种制造半导体显示器件的方法,包括以下步骤: 在绝缘表面上制作半导体层; 在所述半导体层上制作栅绝缘膜;在所述栅绝缘膜上制作第一导电层,以及在所述第一导电层上制作第二导电层;腐蚀所述第一导电层和所迷笫二导电层以形成带有锥形部分的第一栅电极和带有锥形部分的第二栅电极;在所述半导体层中掺入呈一种导电类型的杂质元素以形成第一LDD区和第二LDD区;在所述半导体层中掺入呈一种导电类型的杂质元素以形成源区和漏区;在所述半导体层、所述第一栅电极和所述第二栅电极上制作层间绝缘膜;在所述层间绝缘膜中开接触孔;制作经所述接触孔电连接到所述源区或所述漏区的像素电极;以及其中所述栅绝缘膜在所述第一栅电极覆盖所述栅绝缘膜的区域中具有第一厚度和在所述第一栅电极没有覆盖所述栅绝缘膜的区域中具有第二厚度,并且所述第二厚度小于所述第一厚度。 12. The - method of manufacturing a semiconductor display device, comprising the steps of: forming a semiconductor layer on an insulating surface; the semiconductor layer on a gate insulating film; said gate insulating film made of the first conductive layer, and in the said forming a second conductive layer on the first conductive layer; and etching the first conductive layer of the second conductive layer Zi fans to form a gate electrode having a first tapered portion and a second gate electrode having a tapered portion; incorporated in said semiconductor layer of one conductivity type with as an impurity element to form a first and a second LDD region LDD region; was incorporated into an impurity element of one conductivity type in the semiconductor layer to form the source and drain region; in said semiconductor layer, said first gate electrode and the second gate electrode, an interlayer insulating film; opening contact holes in the interlayer insulating film; produced through the contact hole is electrically connected to the a source region of said pixel electrode or said drain region; and wherein said gate insulating film covering the gate electrode of the first gate insulating film region having a first thickness and without covering said first gate electrode having a thickness of said second region of the gate insulating film, and said second thickness less than the first thickness.
13. —种制造半导体显示器件的方法,包括以下步骤:在绝缘表面上制作半导体层;在所述半导体层上制作栅绝缘膜;在所述栅绝缘膜上制作第一导电膜;在所述第一导电膜上制作第二导电膜;腐蚀所述第二导电膜以制作第一形状第二导电层;腐蚀所述第一导电膜以制作第一形状第一导电层;腐蚀所述第一形状第一导电层和第一形状第二导电层,以分别制作具有锥形部分的第一栅电极和具有锥形部分的第二栅电极;在所述半导体层中掺入呈一种导电类型的杂质元素以形成第一LDD区和第二LDD区;在所述半导体层中掺入呈一种导电类型的杂质元素以形成源区或漏区;在所述半导体层、所述第一栅电极和所述第二栅电极上制作层间绝缘膜;在所述层间绝缘膜中开接触孔;制作经所述接触孔电连接到所述源区或所迷漏区的像素电极;以及其中所迷栅绝缘膜在所迷第一栅电极覆盖所迷栅绝缘膜的区域中具有第一厚度和在所述第一栅电极没有覆盖所迷栅绝缘膜的区域中具有第二厚度,并且所述第二厚度小于所述第一厚度。 13. - method of manufacturing a semiconductor display device, comprising the steps of: forming a semiconductor layer on an insulating surface; the semiconductor layer on a gate insulating film; said gate insulating film made of the first conductive film; in the a first conductive film made of the second conductive film; etching the second conductive film to produce a first shape of the second conductive layer; etching the first conductive film to produce a first shape of the first conductive layer; etching the first shape of the first conductive layer and the first shape second conducting layer, respectively forming a first gate electrode having a tapered portion and a second gate electrode having a tapered portion; incorporated in said semiconductor layer of one conductivity type form to form a first impurity element and the second LDD region LDD region; incorporated in said semiconductor layer of one conductivity type in the form of an impurity element to form a source or drain region; in said semiconductor layer, said first gate the second gate electrode, an interlayer insulating film and the electrode; contact holes in the interlayer insulating film; a pixel electrode produced through the contact hole electrically connected to the source or drain region of the fan; and wherein the fan in the first gate insulating film covering the gate electrode a gate insulating film fans fans region having a first thickness and a second thickness in a region having a gate electrode of the first fan does not cover the gate insulating film, and said second thickness less than the first thickness.
14. 一种包括液晶显示器件的电子装置,所述液晶显示器件包括: 像素TFT和驱动电路TFT,各具有:制作在绝缘表面上的半导体层;制作在所述半导体层上的栅绝缘膜;制作在所述栅绝缘膜上的第一栅电极;以及制作在所述第一栅电极上的第二栅电极; 其中所述像素TFT的所述半导体层包含:与所述第二栅电极重叠的沟道形成区,所述栅绝缘膜夹于其间; 与所述沟道形成区接触并与所述第一栅电极重叠的第一LDD 区,所述栅绝缘膜夹于其间;与所述第一LDD区接触的第二LDD区; 与所述第二LDD区接触的源区和漏区, 其中所述驱动电路TFT的半导体层包含:与所述第二栅电极重叠的沟道形成区,所述栅绝缘膜夹于其间; 与所述沟道形成区接触并与所述第一栅电极重叠的第三LDD 区,所述栅绝缘膜夹于其间;与所述第三LDD区接触的源区和漏区,其中所述第一栅电极沿所述沟道形成区纵向的宽度大于所述第二栅电极的宽度;以及其中所述栅绝缘膜在所述第一栅电极覆盖所述栅绝缘膜的区域中具有第一厚度和在所述第一栅电极没有覆盖所迷栅绝缘膜的区域中具有第二厚度,并且所述第二厚度小于所述第一厚度。 14. An electronic apparatus comprising a liquid crystal display device, the liquid crystal display device comprising: a pixel TFT and the driver circuit TFT, each having: an insulating surface formed on a semiconductor layer; a gate insulating film on the semiconductor layer; production of the gate insulating film of the first gate electrode; and a first gate formed on the gate electrode of the second electrode; wherein said semiconductor layer of said pixel TFT comprising: a second gate electrode overlaps with the the channel forming region, said gate insulating film interposed therebetween; contact with the channel forming region and overlapping with the first gate electrode of the first LDD region, said gate insulating film interposed therebetween; and the second LDD regions contacting the first LDD region; a source region and a drain region in contact with the second LDD regions, wherein said driver circuit TFT semiconductor layer comprises: a second gate electrode overlaps with the channel formation region , said gate insulating film interposed therebetween; contact with the channel forming region and overlapping the first gate electrode with the third LDD region, said gate insulating film interposed therebetween; said third LDD regions in contact with The source and drain regions, wherein the first gate electrode along the longitudinal direction of the channel region is formed wider than the width of the gate electrode of the second; and wherein said gate insulating film covering the gate electrode of the first said gate insulating film region having a first thickness and a second thickness in a region having a gate electrode of the first fan does not cover the gate insulating film, and said second thickness less than the first thickness.
15. 按照权利要求14的电子装置,其特征是其中所述第一栅电极在边缘部分具有锥形剖面。 15. The electronic device according to claim 14, characterized in that said first gate electrode wherein the edge portion having a tapered cross-section.
16. 按照权利要求14的电子装置,其特征是其中的所述第一或第三LDD区含有一个区域,其所述杂质浓度梯度至少为lxl017-1 x 1018原子/cm3的范围,而且随距所述沟道形成区距离的增加而增大。 16. The electronic device according to claim 14, characterized in that one of said first or third LDD region contains a region that the impurity concentration gradient in a range of at least lxl017-1 x 1018 atoms / cm3, and with the distance increasing distance from the channel forming region increases.
17. 按照权利要求14的电子装置,其特征是其中所述第一或第三LDD区是以所迷第二栅电极作掩模按自对准方式向所述半导体层掺入杂质元素而形成的。 17. The electronic device according to claim 14, characterized in that wherein the first or the third LDD regions is lost the second gate electrode as a mask in a self-aligning manner by adding an impurity to the semiconductor layer to form element a.
18. —种包括液晶显示器件的电子装置,所迷液晶显示器件包括:制作在绝缘表面上的半导体层,所述半导体层具有沟道形成区、与所述沟道形成区接触的LDD区、以及与所述LDD区接触的源区和漏区;制作在所述半导体层上的栅绝缘膜; 制作在所述栅绝缘膜上的第一栅电极和第一引线; 第二栅电极形成于所述第一栅电极上,和第二引线形成于所述第一引线上;制作在所述第一栅电极、所述第一引线、所述第二栅电极和所述第二引线上的第一层间绝缘膜;制作在所述第一层间绝缘膜上的第二层间绝缘膜;制作在所述第二层间绝缘膜上,并经所述第二层间绝缘膜中开的第一接触孔与所述第一层间绝缘膜接触的中间引线;其中所述沟道形成区与所述第二栅电极重叠,所述栅绝缘膜夹于其间;其中所述LDD区与所述第一栅电极重叠,所述栅绝缘膜夹于其间;其中所述中间引线与所述第二引线重叠,所述第一层间绝缘膜在所述第一接触孔中夹于其间,且其中所述中间引线经形成于所述栅绝缘膜、所述第一层间绝缘膜和所述第二层间绝缘膜中的第二接触孔,与所述源区或所述漏区相连。 18. - kind comprising an electronic device liquid crystal display device, a liquid crystal display device of the fan comprising: an insulating surface formed on the semiconductor layer, the semiconductor layer having a channel forming region, LDD region and the channel forming region of the contact, and in contact with said source region and a drain region LDD region; a gate insulating film on the semiconductor layer; making a first gate electrode on the gate insulating film and the first lead; a second gate electrode formed on the the first gate electrode, and the second lead is formed on the first lead; formed on the first gate electrode, the first lead, the second gate electrode and said second lead The first interlayer insulating film; produced in the second interlayer insulating film of the first interlayer insulating film; production in the second interlayer insulating film, and opening through the second interlayer insulating film a first contact hole and the first intermediate wiring interlayer insulating film in contact; and wherein said channel forming region overlaps the second gate electrode, said gate insulating film interposed therebetween; wherein said LDD region overlaps the first gate electrode, said gate insulating film interposed therebetween; wherein said intermediate lead and the second lead overlay, the first interlayer insulating film in the first contact hole interposed therebetween, and wherein the intermediate wiring is formed via the gate insulating film, between the first interlayer insulating film and the second interlayer insulating film in the second contact hole, is connected to the source region or the drain region .
19. 按照权利要求18的电子装置,其特征是在所述第二层间绝缘膜上制作一个屏蔽膜,所述屏蔽膜由与所述中间引线相同的材料制成;以及其中所述屏蔽膜与沟道形成区重叠。 19. The electronic device according to claim 18, characterized in that between the second interlayer insulating film made of a shielding film, a shielding film made of the same material as the intermediate lead; and wherein the shielding film overlap with the channel forming region.
20. —种包括液晶显示器件的电子装置,所述液晶显示器件包括:制作在绝缘表面上的半导体层,所述半导体层具有沟道形成区、 与所述沟道形成区接触的LDD区、以及与所述LDD区接触的源区和漏区;制作在所述半导体层上的栅绝缘膜; 制作在所述栅绝缘膜上的第一栅电极和第一引线; 笫二栅电极形成于所述第一栅电极上,和第二引线形成于所迷第一引线上;制作在所述第一栅电极、所述第一引线、所述第二栅电极和所述第二引线上的第一层间绝缘膜;制作在所述第一层间绝缘膜上的第二层间绝缘膜;制作在所述第二层间绝缘膜上,并经所述第二层间绝缘膜中开的接触孔与所述第一层间绝缘膜接触的中间引线;制作在所述第二层间绝缘膜上的屏蔽膜,所述屏蔽膜由与所述中间引线相同的材料制成;其中所述沟道形成区与所述第二栅电极重叠,所述栅绝缘膜夹于其间;其中所述LDD区与所述第一栅电极重叠,所述栅绝缘膜夹于其间;其中所述中间引线与所述第二引线重叠,所述第一层间绝缘膜在所述接触孔中夹于其间,且其中所述屏蔽膜与沟道形成区重叠。 20. - kind comprising an electronic device liquid crystal display device, the liquid crystal display device comprising: an insulating surface formed on the semiconductor layer, the semiconductor layer having a channel forming region, LDD region and the channel forming region of the contact, and in contact with said source region and a drain region LDD region; a gate insulating film on the semiconductor layer; making a first gate electrode on the gate insulating film and a first lead; a gate electrode formed on the second Zi the first gate electrode, and the second lead of the fan is formed on the first lead; formed on the first gate electrode, the first lead, the second gate electrode and said second lead The first interlayer insulating film; produced in the second interlayer insulating film of the first interlayer insulating film; production in the second interlayer insulating film, and opening through the second interlayer insulating film said first contact hole with the contact interlayer insulating film intermediate wiring; produced between the second barrier film layer insulating film, the shielding film is made of the same material as the intermediate wiring; wherein said channel forming region overlaps the second gate electrode, said gate insulating film interposed therebetween; wherein the LDD regions overlap with the first gate electrode, said gate insulating film interposed therebetween; wherein said intermediate lead and the second lead overlay, the first interlayer insulating film in the contact hole interposed therebetween, and wherein the shielding film overlaps with the channel forming region.
21. —种包括液晶显示器件的电子装置,所述液晶显示器件包括:制作在衬底上的屏蔽膜; 制作在所述屏蔽膜上的绝缘膜;制作在所述绝缘膜上的半导体层,所述半导体层具有沟道形成区、与所述沟道形成区接触的LDD区、以及与所述LDD区接触的源区和漏区;制作在所述半导体层上的栅绝缘膜;制作在所述栅绝缘膜上的第一栅电极;第二栅电极形成于所述第一栅电极上;其中所述沟道形成区与所述第二栅电极重叠,所述栅绝缘膜夹于其间;其中所述LDD区与所述第一栅电极重叠,所述栅绝缘膜夹于其间,且其中所述屏蔽膜与所述沟道形成区重叠,所述绝缘膜夹于其间。 21. - kind comprising an electronic device liquid crystal display device, the liquid crystal display device comprising: a substrate formed on the shielding film; shielding film produced in the insulating film; produced in the semiconductor interlayer insulating film, said semiconductor layer having a channel forming region, LDD region in contact with the channel forming region, and the source and drain regions in contact with the LDD regions; a gate insulating film on the semiconductor layer; fabricated the gate electrode of the first gate insulating film; a second gate electrode formed on said first gate electrode; wherein said channel forming region overlaps the second gate electrode, said gate insulating film interposed therebetween ; wherein the LDD regions overlap the first gate electrode, said gate insulating film interposed therebetween, and wherein the shielding film overlaps with the channel forming region, said insulating film interposed therebetween.
22. 按照权利要求21的电子装置,其特征是其中所述绝缘膜是用CMP抛光来抛平的。 22. The electronic device according to claim 21, characterized in that wherein said insulating film is polished by CMP for polishing flat.
23. 按照权利要求14、 18、 20、 21中的任一项的电子装置,其特征在于所述电子设备是摄象机。 23. A process according to claim 14, 18, 20, 21 of the electronic device according to any one of claims, wherein said electronic device is a video camera.
24. 按照权利要求14、 18、 20、 21中的任一项的电子装置,其特征在于所述电子设备是数码相机。 24. A process according to claim 14, 18, 20, the electronic device according to any one of claim 21, wherein said electronic device is a digital camera.
25. 按照权利要求14、 18、 20、 21中的任一项的电子装置,其特征在于所述电子设备是投影仪。 25. A process according to claim 14, 18, 20, 21 of the electronic device according to any one of claims, wherein said electronic device is a projector.
26. 按照权利要求14、 18、 20、 21中的任一项的电子装置,其特征在于所述电子设备是头戴式显示设备。 26. A process according to claim 14, 18, 20, 21 of the electronic device according to any one of claims, wherein said electronic device is a head-mounted display device.
27. 按照权利要求14、 18、 20、 21中的任一项的电子装置,其特征在于所述电子设备是游戏机。 27. A process according to claim 14, 18, 20, 21 of the electronic device according to any one of claims, wherein said electronic device is a game machine.
28. 按照权利要求14、 18、 20、 21中的^f壬一项的电子装置,其特征在于所述电子设备是车辆导航系统。 28. A process according to claim 14, 18, 20, 21 ^ f azelaic one electronic device, characterized in that said electronic device is a car navigation system.
29. 按照权利要求14、 18、 20、 21中的任一项的电子装置,其特征在于所述电子设备是个人计算机。 29. A process according to claim 14, 18, 20, 21 The electronic device according to any one of claims, wherein said electronic device is a personal computer.
30. 按照权利要求14、 18、 20、 21中的任一项的电子装置,其特征在于所述电子设备是袖珍信息终端。 30. A process according to claim 14, 18, 20, 21 The electronic device according to any one of claims, wherein said electronic device is a portable information terminal.
Description  translated from Chinese

半导体显示器件及其制作方法 The semiconductor display device and manufacturing method thereof

本申请是申请号为"01112073.8"、申请日为"2001年3月27 曰,,以及发明名称为"半导体显示器件及其制作方法"的申请的分案申 This application is a number "01112073.8" filed "on March 27, 2001 and titled ,, said," semiconductor display device and manufacturing method, "the application of a divisional application

请,,。 Please ,,.

本发明涉及到使用半导体元件(半导体薄膜元件)的半导体显示器件,尤其是液晶显示器件。 The present invention relates to a semiconductor element (semiconductor thin film element) of the semiconductor display device, particularly a liquid crystal display device. 而且,本发明涉及到在显示部分使用半导体显示器件的电子学设备, Further, the present invention relates to a display portion of a display device using a semiconductor electronics device,

在具有绝缘表面的衬底上形成半导体薄膜(厚为几个至几百nm) 以制作薄膜晶体管(TFT)的技术近些年来已受到关注。 Forming a semiconductor thin film (having a thickness of several to several hundred nm) to produce a thin film transistor (TFT) technology in recent years has been concern over a substrate having an insulating surface. 薄膜晶体管被广泛地用于电子器件如IC以及半导体显示器件,并得到了迅速的发展,尤其是用于液晶显示器件作为开关元件。 Thin-film transistors are widely used in electronic devices such as IC and semiconductor display devices, and has been the rapid development, especially for a liquid crystal display device as a switching element.

有源矩阵液晶显示器件的像素部分由多个像素组成,每个像素含有TFT和液晶盒。 Pixel portion of the active matrix liquid crystal display device composed of a plurality of pixels, each pixel comprising TFT and the liquid crystal cell. 液晶盒具有像素电极、对电极(opposing electrode )、 以及形成在像素电极与对电极之间的液晶。 The liquid crystal cell has a pixel electrode, a counter electrode (opposing electrode), and formed in the pixel electrode and the liquid crystal between electrodes. 控制由像素TFT供给像素电极的电压可在像素部分显示困像。 Controlled by the pixel electrode voltage supplied to the pixel TFT displays like trapped in the pixel portion.

特别是,用晶体结构的半导体膜作为TFT的有源层(晶体TFT )可获得高迁移率,因此能够将功能电路集成在同一衬底上,从而实现高清晰度图像显示的液晶显示器件。 In particular, the crystal structure of the semiconductor film as an active layer of a TFT (crystalline TFT) to obtain high mobility, it is possible to integrate functional circuits on the same substrate, a liquid crystal display device in order to achieve high-definition image display.

本说明书中具有晶体结构的半导体膜包括单晶半导体、多晶半导体和微晶半导体,还包括公开于日本专利公开Hei 7-130652号、Hei 8-78329号、Hei 10-135468号和Hei 10-135469号的半导体。 The specification of the semiconductor film having a crystal structure including a single crystal semiconductor, a polycrystalline semiconductor and microcrystalline semiconductors, also include those disclosed in Japanese Patent Publication No. Hei 7-130652, Hei No. 8-78329, Hei No. 10-135468 and Hei 10- 135 469 Number of semiconductors.

为构成有源矩阵液晶显示器件,仅像素部分就需要100万至200 万个晶体TFT,而在其周围形成附加的功能电路则需更多的晶体TFT。 Constituting the active matrix liquid crystal display device, only a pixel portion will need 1 million to 2 million crystal TFT, and around it to form additional functional circuits need more crystal TFT. 液晶显示器件所需的规格是严格的,为了实现稳定的液晶显示,必须保证每个晶体TFT的可靠性。 LCD required specification is critical, in order to achieve a stable LCD, TFT must guarantee the reliability of each crystal.

TFT的特性可按开态和关态来考虑。 Characteristics of the TFT on-state and off-state may be considered. 一些特性参数如开态电流、迁移率、S值和阈值都是开态特性,而关态电流则是最重要的关态特性。 Some parameters, such as on-state current, mobility, S and thresholds are open state properties, and the off current is the most important off-state characteristics.

然而,有一个问題是晶体TFT的关态电流容易升高。 However, one problem is crystal TFT off current easily increased.

而且,从可靠性的观点出发,晶体TFT还没有用于LSI的MOS晶 Moreover, from the viewpoint of reliability point of view, crystal TFT yet for LSI MOS transistor

体管(在晶体半导体衬底上制作晶体管)。 Transistors (in the crystalline semiconductor substrate manufacturing transistors). 例如,已观察到晶体TFT 被连续驱动时发生退化现象,其中迁移率和开态电流(TFT开态时流过的电流)下降,关态电流(TFT关态时流过的电流)上升。 For example, it has been observed to occur degradation crystal TFT is continuously driven, where mobility and on-state current (TFT ON state when the current flow) decreased, off-state current (TFT OFF state when the current flow) increases. 设想其原因是热栽流子效应,即在漏极附近的高电场产生的热载流子导致了退化现象。 The reason is conceive heat plant carrier effect, hot carriers that produce high electric field near the drain leads to degradation.

已经知道,使用轻掺杂漏区(LDD)结构来减轻漏极附近的高电场是降低MOS晶体管关态电流的方法。 It is known that the use of lightly doped drain regions (LDD) structure to reduce the high electric field near the drain of the MOS transistor is a method of reducing the off current. 这种结构在沟道区外面形成低掺杂区,此低掺杂区称作LDD区。 This structure is formed on the outside of the channel region of low doped region, this low-doped region called the LDD region.

特别是,有一种结构其LDD区经栅绝缘膜与栅电极重叠(栅-漏重叠LDD结构,G0LD结构),漏极附近的高电场区被减弱,可防止热栽流子效应,从而提高可靠性。 In particular, there is a structure in which the LDD region through a gate insulating film overlaps with the gate electrode (gate - drain overlap LDD structure, G0LD structure), a high electric field near the drain region is reduced to prevent thermal plant carrier effect, thereby increasing reliability sex. 注意,在本说明书中LDD区经栅绝缘膜与栅电极重叠的区域称作Lov区(第一LDD区)。 Note that in this specification LDD region through the gate insulating film and the gate electrode overlap region is called Lov region (first LDD region).

还要注意,已知的一些结构如LATID (大倾角注入漏区)结构和ITLDD (反型T LDD)结构都是G0LD结构。 Also note that some structure known as LATID (large dip injection drain) structure and ITLDD (inversion T LDD) structures are G0LD structure. 有一种GOLD结构,例如, 据HatanoM. , AkimotoH. , and Sakai T. , IE,7 Technical Diges t, positive. 523-6, 1997才艮导,其側壁是由硅形成的,已证实与其他的TFT结构相比可得到极优越的可靠性。 There is a GOLD structure, for example, according to HatanoM., AkimotoH., And Sakai T., IE, 7 Technical Diges t, positive. 523-6, 1997 was Gen guide, its side walls are formed of silicon, has been confirmed with other TFT structure very superior reliability compared to available.

注意,在本说明书中,LDD区不与栅电极经栅绝缘膜而重叠的区域称作Loff区(第二LDD区)。 Note that, in this specification, LDD region and the gate electrode is not through the gate insulating film is called Loff region overlapping region (second LDD region).

已提出了几种方法来制作具有Loff区和Lov区二者的TFT。 Several methods have been proposed to make Loff region and Lov region has both the TFT. 一种方法只使用掩模而没有自对准, 一种方法使用具有不同宽度的两层栅电极而栅绝缘膜是自对准的,这些都可作为形成Lov区和Loff区的方法。 One method uses not only a self-alignment mask, a method of using two layers of gate electrodes having different widths and the gate insulating film is self-aligned, these methods can be used as Lov region and the Loff region are formed.

然而,用掩模形成Lov区和Loff区时需用两个掩模,工序也增多了。 However, when you need to use two masks mask Lov region and the Loff region is formed, the process also increased. 另一方面,用自对准形成Lov区和Loff区时,不需增加掩模数, 因而能够减少工序。 On the other hand, when the formation of a self-aligning Lov region and the Loff region, without increasing the number of masks, it is possible to reduce the process. 然而,栅电极的宽度和栅绝缘膜的厚度会影响形成的Lov区和Loff区的位置。 However, the width and thickness of the gate insulating film of the gate electrode can affect the location of the Lov region and the Loff region are formed. 栅电极和栅绝缘膜的腐蚀速率常有很大的差异,很难精确控制Lov区和Loff区的位置对准。 The gate electrode and the etching rate of the gate insulating film are often very different, difficult to precisely control the location of the Lov region and the Loff region is aligned.

鉴于上述,本发明的目的是在形成Lov区和Loff区时减少掩模数目,还要易于在所希望的位置形成Lov区和Loff区。 In view of the foregoing, an object of the present invention is to reduce the number of masks when forming an Lov region and the Loff region, but also easy to be formed at a desired position of the Lov region and the Loff region. 而且,本发明的目的还在于实现具有良好的开态和关态特性的晶体TFT。 It is another object of the present invention is to realize a good on-state and off-state properties of crystal TFT. 本发明的另一个目的是实现高可靠性的半导体显示器件,其半导体电路是由这种类型的晶体TFT构成的。 Another object of the present invention is to realize a high reliability semiconductor display device, which is composed of a semiconductor circuit of this type TFT formed crystals.

利用栅电极的自对准以及掩模向半导体层中掺入杂质来形成Lov The self-aligned using the gate electrode and the semiconductor layer mask to form impurity is Lov

区和Loff区。 Region and Loff region. 栅电极由两层导电膜构成,更靠近半导体层的那一层(第一栅电极)沿沟道纵向要长于离半导体层较远的层(第二栅电极)。 The layer (first gate electrode) of the gate electrode conductive film composed of two layers, the semiconductor layer closer to the channel longitudinal direction is longer than a layer farther from the semiconductor layer (second gate electrode). 注意,在本说明书中,沟道纵向一词指栽流子在源区和漏区间移动 Note that in this specification, the term refers to the longitudinal channel planted carrier source and drain regions to move in

的方向。 Direction.

在本发明中,第一栅电极和第二栅电极沿沟道纵向(栽流子移动方向)的长度(此后简称作栅电极宽度)是不同的。 In the present invention, the first gate electrode and the second gate electrode along the channel direction (plant carrier movement direction) length (hereinafter referred to as the gate electrode width) it is different. 用第一栅电极和第二栅电极作掩模进行离子注入,由于栅电极厚度不同,利用离子透入深度之差,可使第二栅电极下面半导体层中的离子浓度低于在第一栅电极之下而又不在第二栅电极下面的半导体层中的离子浓度。 A first gate electrode and second gate electrode as a mask ion implantation, due to the different thickness of the gate electrode, the use of the difference between the depth of ion penetration, allow the second semiconductor layer below the gate electrode lower than the ion concentration in the first gate under the electrode but not the second gate electrode below the semiconductor layer ion concentration. 此外, 还能使在第一栅电极之下而又不在第二栅电极下面的半导体层中的离子浓度低于不在第一栅电极下面的半导体层的离子浓度。 In addition, also brought under the first gate electrode but not the second gate electrode below the semiconductor layer ion concentration is less than the ion concentration is not below the first gate electrode of the semiconductor layer.

而且,Loff区是用掩模来形成的,因此只须用腐蚀来控制第一栅电极和第二栅电极的宽度,Loff区和Lov区位置的控制就比常规的实例容易了。 Further, Loff region is formed using a mask, and thus to control the width by etching only the first gate electrode and second gate electrode, control of the Loff region and Lov region positions is easier than the conventional examples. 所以,Lov区和Loff区的精确对准以及制作具有所需特性的TFT都变得容易了。 Therefore, precise alignment of the Lov region and the Loff region and the production of TFT having desired characteristics becomes easy.

本发明的结构如下所示。 Structure of the present invention are shown below.

按照本发明,提供了一种半导体显示器件,它包括:在绝缘表面上形成的半导体层;与半导体层相连的栅绝缘膜;与栅绝缘膜相连的第一栅电极;与第一栅电极相连的第二栅电极;以及液晶盒,其特点为: According to the present invention, there is provided a semiconductor display device, comprising: a semiconductor layer formed on an insulating surface; a gate insulating film and the semiconductor layer is connected; a first gate electrode connected to the gate insulating film; a gate electrode connected to the first a second gate electrode; and a liquid crystal cell, which is characterized by:

半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及与LDD区接触的源区和漏区; The semiconductor layer has: a channel forming region; and the channel forming region contacting the LDD regions; and a source region and a drain region in contact with the LDD regions;

沿沟道纵向的第一栅电极的宽度大于沿沟道纵向的第二栅电极的 Channel longitudinal direction of the first gate electrode is wider than the channel longitudinal direction of the second gate electrode

宽度; Width;

LDD区与第一栅电极重叠,栅绝缘膜夹于其间; 液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间的液晶;以及 The LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween; liquid crystal cell having: a pixel electrode; electrode; and a liquid crystal formed between the pixel electrode and the electrode; and

源区或漏区与像素电极电连接. Power source or drain region and the pixel electrode.

按照本发明,提供一种半导体显示器件,它包括:在绝缘表面上形成的半导体层;与半导体层相连的栅绝缘膜;与栅绝缘膜相连的第一栅电极;与第一栅电极相连的第二栅电极;以及液晶盒,其特点为: According to the present invention, there is provided a semiconductor display device, comprising: a semiconductor layer formed on an insulating surface; a gate insulating film and the semiconductor layer is connected; a first gate electrode connected to the gate insulating film; a gate electrode connected to the first a second gate electrode; and a liquid crystal cell, which is characterized by:

半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及与源区和漏区接触的LDD区;沿沟道纵向的第一栅电极的宽度大于沿沟道纵向的第二栅电极的 The semiconductor layer has: a channel forming region; LDD region in contact with the channel forming region; and LDD region in contact with the source region and the drain region; the channel longitudinal direction of the first gate electrode is wider than the channel longitudinal direction of the second the gate electrode

宽度; Width;

LDD区与第一栅电极重叠,栅绝缘膜夹于其间; 沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; 液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间的液晶;以及 The LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween; and the channel forming region overlaps the second gate electrode, a gate insulating film interposed therebetween; liquid crystal cell having: a pixel electrode; electrode; and formed in the pixel electrode and between the electrodes of the liquid crystal; and

源区或漏区与像素电极电连接。 Power source or drain region and the pixel electrode.

按照本发明,提供了一种半导体显示器件,它包括:在绝缘表面上形成的带有半导体层的TFT;与半导体层相连的栅绝缘膜;与栅绝缘膜相连的第一栅电极;与第一栅电极相连的第二栅电极;以及液晶盒, 其特点为: According to the present invention, there is provided a semiconductor display device, comprising: TFT having a semiconductor layer formed on an insulating surface; a gate insulating film and the semiconductor layer is connected; a first gate electrode connected to the gate insulating film; first a gate electrode connected to the second gate electrode; and a liquid crystal cell, which is characterized by:

沿沟道纵向的第一栅电极的宽度大于沿沟道纵向的第二栅电极的宽度; A first gate electrode along the longitudinal direction of the channel width greater than the width of the channel longitudinal direction of the second gate electrode;

笫一栅电极的边缘部分具有锥形剖面; Zi edge portion of the gate electrode has a tapered cross-section;

半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及 The semiconductor layer has: a channel forming region; LDD region in contact with the channel forming region; and

与LDD区接触的源区和漏区; The source and drain regions in contact with the LDD region;

LDD区与第一栅电极重叠,栅绝缘膜夹于其间; 沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; 液晶盒具有:像素电极;对电极;及形成在〗象素电极与对电极之间 The LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween; and the channel forming region overlaps the second gate electrode, a gate insulating film interposed therebetween; liquid crystal cell having: a pixel electrode; electrode; and a pixel formed〗 between the electrode and the counter electrode

的液晶;以及 LCD; and

源区或漏区与像素电极电连接. Power source or drain region and the pixel electrode.

本发明的特点在于,用第二栅电极作掩模在半导体层中自对准掺入杂质元素而形成LDD区。 Feature of the present invention is that, with the second gate electrode as a mask in the semiconductor layer and an impurity element incorporated in a self-aligned LDD region is formed.

本发明的特点在于,在LDD区中有一区域,其杂质浓度梯度至少为1 x 10I7~ 1 x 10"原子/cm3,而且LDD区杂质元素的浓度随距沟道形成区距离的增加而增大。 Feature of the present invention is that there is a region in the LDD region, the impurity concentration gradient of at least 1 x 10I7 ~ 1 x 10 "atoms / cm3, and the concentration of the impurity element LDD region with increasing distance from the channel forming region increases .

按照本发明,提供了一种半导体显示器件,它包括:像素TFT和驱动电路TFT,每个都具有在绝缘表面上形成的半导体层;与半导体层 According to the present invention, there is provided a semiconductor display device, comprising: a pixel TFT and the driver circuit TFT, each having a semiconductor layer formed on an insulating surface; the semiconductor layer

相连的栅绝缘膜;与栅绝缘膜相连的笫一栅电极,和与第一栅电极相连的第二栅电极;以及液晶盒,其特点为: Connected to the gate insulating film; Zi a gate electrode connected with the gate insulating film, and a second gate electrode connected to the first gate electrode; and a liquid crystal cell, which is characterized by:

沿沟道纵向的第一栅电极的宽度大于沿沟道纵向的第二栅电极的 Channel longitudinal direction of the first gate electrode is wider than the channel longitudinal direction of the second gate electrode

宽度; Width;

像素TFT的半导体层具有:与第二栅电极重叠的沟道形成区,栅绝缘膜夹于其间;第一LDD区与沟道形成区接触,并与第一栅电极重叠,栅绝缘膜夹于其间;第二LDD区与第一LDD区接触;源区和漏区与第二LDD区接触; The semiconductor layer of the pixel TFT comprising: a second gate electrode overlaps with a channel formation region, a gate insulating film interposed therebetween; a first LDD regions in contact with the channel forming region and overlapping the first gate electrode, a gate insulating film interposed therebetween; a second LDD regions in contact with the first LDD regions; source and drain regions in contact with the second LDD regions;

驱动电路TFT的半导体层具有:与第二栅电极重叠的沟道形成区, 栅绝缘膜夹于其间;第三LDD区与沟道形成区接触,并与第一栅电极重叠,栅绝缘膜夹于其间;源区或漏区与第三LDD区接触; The driver circuit TFT semiconductor layer having: a second gate electrode overlaps with the channel forming region, a gate insulating film interposed therebetween; third LDD regions in contact with the channel forming region and overlapping the first gate electrode, a gate insulating film interposed in the meantime; the source and drain regions in contact with the third LDD region;

液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间的液晶;以及 The liquid crystal cell having: a pixel electrode; electrode; and a liquid crystal formed between the pixel electrode and the electrode; and

像素TFT的源区或漏区与像素电极电连接。 The source or drain region of the pixel TFT is electrically connected to the pixel electrode.

按照本发明,提供了一种半导体显示器件,它包括:像素TFT和驱动电路TFT,每个都具有在绝缘表面上形成的半导体层;与半导体层相连的栅绝缘膜;与栅绝缘膜相连的第一栅电极,和与第一栅电极相连的第二栅电极;以及液晶盒,其特点为: According to the present invention, there is provided a semiconductor display device, comprising: a pixel TFT and the driver circuit TFT, each having a semiconductor layer formed on an insulating surface; a gate insulating film and the semiconductor layer is connected; connected with the gate insulating film the first gate electrode, and a second gate electrode connected to the first gate electrode; and a liquid crystal cell, which is characterized by:

沿沟道纵向的第一栅电极的宽度大于沿沟道纵向的第二栅电极的 Channel longitudinal direction of the first gate electrode is wider than the channel longitudinal direction of the second gate electrode

宽度; Width;

第一栅电极的边缘部分具有锥形剖面; An edge portion of the first gate electrode having a tapered cross-section;

像素TFT的半导体层具有:与第二栅电极重叠的沟道形成区,栅绝缘膜夹于其间;第一LDD区与沟道形成区接触,并与第一栅电极重叠,栅绝缘膜夹于其间;第二LDD区与第一LDD区接触;源区和漏区与第二LDD区接触; The semiconductor layer of the pixel TFT comprising: a second gate electrode overlaps with a channel formation region, a gate insulating film interposed therebetween; a first LDD regions in contact with the channel forming region and overlapping the first gate electrode, a gate insulating film interposed therebetween; a second LDD regions in contact with the first LDD regions; source and drain regions in contact with the second LDD regions;

驱动电路TFT的半导体层具有:与第二栅电极重叠的沟道形成区, 栅绝缘膜夹于其间;笫三LDD区与沟道形成区接触,并与第一栅电极重叠,栅绝缘膜夹于其间;源区或漏区与第三LDD区接触; The driver circuit TFT semiconductor layer having: a second gate electrode overlaps with the channel forming region, a gate insulating film interposed therebetween; Zi third LDD regions in contact with the channel forming region and overlapping the first gate electrode, a gate insulating film interposed in the meantime; the source and drain regions in contact with the third LDD region;

液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间的液晶; The liquid crystal cell having: a pixel electrode; electrode; and a liquid crystal formed between the pixel electrode and the electrodes;

像素TFT的源区或漏区与像素电极电连接。 The source or drain region of the pixel TFT is electrically connected to the pixel electrode.

本发明的特点在于,在第一LDD区中有一区域,其杂质浓度梯度至少为1 x 10" ~ 1 x 1(T原子/cm3,而且LDD区杂质元素的浓度随距沟道形成区距离的增加而增大。 Feature of the present invention is that there is a region in the first LDD region, the impurity concentration gradient of at least 1 x 10 "~ 1 x 1 (T atoms / cm3, and the concentration of the LDD region with an impurity element from the channel forming region from increases.

本发明的特点在于,在第三LDD区中有一区域,其杂质浓度梯度至少为1 x 10'7~ 1 x 10"原子/cm3,而且LDD区杂质元素的浓度随距沟 Feature of the present invention is that there is a region in the third LDD region, the impurity concentration gradient of at least 1 x 10'7 ~ 1 x 10 "atoms / cm3, and the concentration of the LDD region with an impurity element from the groove

道形成区距离的增加而增大。 Increase from the channel forming region increases.

本发明的特点在于,用第二栅电极作掩模在半导体层中自对准掺入 Feature of the present invention is that with the second gate electrode as a mask in the semiconductor layer self-aligned incorporation

杂质而形成第一LDD区或第三LDD区。 A first impurity to form LDD regions or the third LDD regions.

按照本发明,提供了一种半导体显示器件,它包括:在绝缘表面上形成的半导体层;栅绝缘膜;第一栅电极;第二栅电极;第一引线; 第二引线;第一层间绝缘膜;第二层间绝缘膜;中间引线;以及液晶 According to the present invention, there is provided a semiconductor display device, comprising: a semiconductor layer formed on an insulating surface; a gate insulating film; a first gate electrode; a second gate electrode; a first lead; a second lead; a first interlayer the second interlayer insulating film;; intermediate wiring insulating film; and a liquid crystal

盒,其特点为: Box, which is characterized by:

在绝缘表面上形成覆盖半导体层的栅绝缘膜; A gate insulating film covering the semiconductor layer is formed on an insulating surface;

制作与栅绝缘膜接触的第一栅电极和第一引线; 制作分别与第一栅电极和第一引线接触的第二栅电极和第二引 A first gate electrode and the first lead making contact with the gate insulating film; a second gate electrode are made in contact with the first gate electrode and a first lead and a second lead

线; Line;

第一栅电极和第一引线由第一导电膜构成; A first gate electrode and a first lead composed of the first conductive film;

第二栅电极和第二引线由第二导电膜构成; The second gate electrode and the second lead composed of a second conductive film;

制作第一层间绝缘膜,它褒盖:第一栅电极和第二栅电极;第一引线和第二引线;以及栅绝缘膜; Forming a first interlayer insulating film, it praised the cover: the first gate electrode and the second gate electrode; a first lead and a second lead; and a gate insulating film;

在第一层间绝缘膜上制作第二层间绝缘膜; In the first interlayer insulating film between the second interlayer insulating film forming;

制作覆盖第二层间绝缘膜的中间引线,使之经过在第二层间绝缘膜中开的接触孔而与第一层间绝缘膜接触; Making a second interlayer insulating film covering the intermediate wiring, so that after the second interlayer insulating film in the opening of the contact hole in contact with the first interlayer insulating film;

中间引线与第二引线在接触孔处重叠,第一层间绝缘膜夹于其间; Intermediate lead and the second lead of the overlap in the contact hole, a first interlayer insulating film interposed therebetween;

半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及与LDD区接触的源区和漏区; The semiconductor layer has: a channel forming region; and the channel forming region contacting the LDD regions; and a source region and a drain region in contact with the LDD regions;

沿沟道纵向的笫一栅电极的宽度大于沿沟道纵向的笫二栅电极的 Zi channel longitudinal direction is wider than a gate electrode along the longitudinal direction of Zi two-channel gate electrode

宽度; Width;

沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; LDD区与第一栅电极重叠,栅绝缘膜夹于其间。 The channel forming region overlaps the second gate electrode, a gate insulating film interposed therebetween; LDD region overlaps with the first gate electrode, a gate insulating film interposed therebetween. 液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间的液晶;以及 The liquid crystal cell having: a pixel electrode; electrode; and a liquid crystal formed between the pixel electrode and the electrode; and

源区或漏区与像素电极电连接。 Power source or drain region and the pixel electrode.

按照本发明,提供了一种半导体显示器件,它包括:在绝缘表面上形成的半导体层;栅绝缘膜;笫一栅电极;第二栅电极;第一引线; 第二引线;第一层间绝缘膜;第二层间绝缘膜;中间引线;以及液晶盒,其特点为: According to the present invention, there is provided a semiconductor display device, comprising: a semiconductor layer formed on an insulating surface; a gate insulating film; Zi a gate electrode; a second gate electrode; a first lead; a second lead; a first interlayer insulating film; a second interlayer insulating film; an intermediate lead; and a liquid crystal cell, which is characterized by:

在绝缘表面上形成覆盖半导体层的栅绝缘膜; 制作与栅绝缘膜接触的第一栅电极和第一引线; 制作分别与第一栅电极和第一引线接触的第二栅电极和第二引 A gate insulating film covering the semiconductor layer is formed on an insulating surface; a first gate electrode made contact with the gate insulating film and the first lead; a second gate electrode are respectively made contact with the first gate electrode and a first lead and a second lead

线; Line;

第一栅电极和笫一引线由第一导电膜构成; 第二栅电极和第二引线由第二导电膜构成; 制作第一层间绝缘膜,它袭盖:第一栅电极和第二栅电极;第一引线和第二引线;以及栅绝缘膜; Zi first gate electrode and a first conductive lead film; a second gate electrode and the second lead of the second conductive film; forming a first interlayer insulating film, which covers the passage: the first gate electrode and a second gate a first lead and a second lead;; electrode and the gate insulating film;

在第一层间绝缘膜上制作第二层间绝缘膜; 制作覆盖第二层间绝缘膜的中间引线,使之经过在第二层间绝缘膜中开的第一接触孔而与第一层间绝缘膜接触; In the first interlayer insulating film made of the second interlayer insulating film; intermediate lead made covering the second interlayer insulating film, so that after the first contact hole in the second interlayer insulating film with the opening of the first layer insulating film in contact;

中间引线与第二引线在第一接触孔处重叠,第一层间绝缘膜夹于其 Intermediate lead and a second lead in the first contact hole overlaps the first interlayer insulating film interposed thereon

间; Room;

半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及 The semiconductor layer has: a channel forming region; LDD region in contact with the channel forming region; and

与LDD区接触的源区和漏区; The source and drain regions in contact with the LDD region;

LDD区与第一栅电极重叠,栅绝缘膜夹于其间; 沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; 中间引线经过第二接触孔与源区或漏区相连,笫二接触孔开在栅绝 The LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween; and the channel forming region overlaps the second gate electrode, a gate insulating film interposed therebetween; intermediate lead through the second contact hole connected to the source region or the drain region, Zi the second contact hole in the gate must open

缘膜、第一层间绝缘膜、以及第二层间绝缘膜中; Inter-insulating film, a first interlayer insulating film, and a second interlayer insulating film;

液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间 The liquid crystal cell having: a pixel electrode; electrode; and is formed between the pixel electrode and the counter electrode

的液晶;以及 LCD; and

像素TFT的源区或漏区与像素电极电连接。 The source or drain region of the pixel TFT is electrically connected to the pixel electrode.

按照本发明,提供了一种半导体显示器件,它包括:在绝缘表面上形成的半导体层;栅绝缘膜;第一栅电极;第二栅电极;第一引线; 第二引线;第一层间绝缘膜;第二层间绝缘膜;中间引线;屏蔽膜; 以及液晶盒,其特点为: According to the present invention, there is provided a semiconductor display device, comprising: a semiconductor layer formed on an insulating surface; a gate insulating film; a first gate electrode; a second gate electrode; a first lead; a second lead; a first interlayer The second interlayer insulating film;; intermediate lead; insulating film shielding film; and a liquid crystal cell, which is characterized by:

在绝缘表面上形成覆盖半导体层的栅绝缘膜; A gate insulating film covering the semiconductor layer is formed on an insulating surface;

制作与栅绝缘膜接触的第一栅电极和笫一引线; The first gate electrode and gate insulating film produced in contact and Zi lead;

制作分别与第一栅电极和第一引线接触的第二栅电极和第二引 Forming a second gate electrode are in contact with the first gate electrode and a first lead and a second lead

线; Line;

第一栅电极和第一引线由第一导电膜构成; 第二栅电极和第二引线由第二导电膜构成; 制作第一层间绝缘膜,它袭盖:第一栅电极和第二栅电极;第一引线和第二引线;以及栅绝缘膜; A first gate electrode and a first lead of a first conductive film; a second gate electrode and the second lead of the second conductive film; forming a first interlayer insulating film, which covers the passage: the first gate electrode and a second gate a first lead and a second lead;; electrode and the gate insulating film;

在第一层间绝缘膜上制作第二层间绝缘膜; In the first interlayer insulating film between the second interlayer insulating film forming;

制作覆盖第二层间绝缘膜的中间引线,使之经过在第二层间绝缘膜中开的接触孔而与第一层间绝缘膜接触; Making a second interlayer insulating film covering the intermediate wiring, so that after the second interlayer insulating film in the opening of the contact hole in contact with the first interlayer insulating film;

中间引线与第二引线在接触孔处重叠,第一层间绝缘膜夹于其间; 半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及 Intermediate lead and the second lead of the overlap in the contact hole, a first interlayer insulating film sandwiched therebetween; a semiconductor layer having: a channel forming region; LDD region in contact with the channel forming region; and

与LDD区接触的源区和漏区; The source and drain regions in contact with the LDD region;

LDD区与第一栅电极重叠,栅绝缘膜夹于其间; 沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; 屏蔽膜是由与中间引线相同的导电膜制成的; 在第二层间绝缘膜上制作屏蔽膜,使之与沟道形成区重叠; 液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间 The LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween; and the channel forming region overlaps the second gate electrode, a gate insulating film interposed therebetween; shielding film is made of the same conductive film intermediate lead made; in the second interlayer insulating film made shielding film, so that overlap with the channel forming region; liquid crystal cell having: a pixel electrode; electrode; and is formed between the pixel electrode and the counter electrode

的液晶;以及 LCD; and

源区或漏区与像素电极电连接。 Power source or drain region and the pixel electrode.

按照本发明,提供了一种半导体显示器件,它包括:在绝缘表面上形成的半导体层;栅绝缘膜;第一栅电极;笫二栅电极;笫一引线; 第二引线;第一层间绝缘膜;第二层间绝缘膜;中间引线;屏蔽膜; According to the present invention, there is provided a semiconductor display device, comprising: a semiconductor layer formed on an insulating surface; a gate insulating film; a first gate electrode; Zi second gate electrode; Zi lead; a second lead; a first interlayer the second interlayer insulating film;; intermediate wiring insulating film; shielding film;

以及液晶盒,其特点为: And a liquid crystal cell, which is characterized by:

在绝缘表面上形成袭盖半导体层的栅绝缘膜; Xi cover the semiconductor layer gate insulating film formed on an insulating surface;

制作与栅绝缘膜接触的第一栅电极和笫一引线; The first gate electrode and gate insulating film produced in contact and Zi lead;

制作分别与第一栅电极和第一引线接触的第二栅电极和第二引 Forming a second gate electrode are in contact with the first gate electrode and a first lead and a second lead

线; Line;

第一栅电极和第一引线由第一导电膜构成; 第二栅电极和第二引线由第二导电膜构成; 制作第一层间绝缘膜,它褒盖:第一栅电极和第二栅电极;第一引线和第二引线;以及栅绝缘膜; A first gate electrode and a first lead of a first conductive film; a second gate electrode and the second lead of the second conductive film; forming a first interlayer insulating film, which covers praise: a first gate electrode and a second gate a first lead and a second lead;; electrode and the gate insulating film;

在第一层间绝缘膜上制作第二层间绝缘膜; In the first interlayer insulating film between the second interlayer insulating film forming;

制作覆盖笫二层间绝缘膜的中间引线,使之经过在第二层间绝缘膜中开的第一接触孔而与第一层间绝缘膜接触; Zi floor covering made between the intermediate wiring insulating film, so that after the first contact hole in the second interlayer insulating film in contact with the opening of the first interlayer insulating film;

中间引线与第二引线在笫一接触孔处重叠,笫一层间绝缘膜夹于其 Intermediate lead and the second lead in the contact hole overlapping Zi, Zi layer insulating film sandwiched between its

半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及 The semiconductor layer has: a channel forming region; LDD region in contact with the channel forming region; and

与LDD区接触的源区和漏区; The source and drain regions in contact with the LDD region;

LDD区与第一栅电极重叠,栅绝缘膜夹于其间; 沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; 中间引线经过第二接触孔与源区或漏区相连,第二接触孔开在栅绝 The LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween; and the channel forming region overlaps the second gate electrode, a gate insulating film interposed therebetween; intermediate lead through the second contact hole connected to the source and drain regions, the first the second contact hole in the gate must open

缘膜、第一层间绝缘膜、以及第二层间绝缘膜中; 屏蔽膜是由与中间引线相同的导电膜制成的; 在第二层间绝缘膜上制作屏蔽膜,使之与沟道形成区重叠; Insulating film, a first interlayer insulating film, and a second interlayer insulating film; shielding film is made of the same conductive film as the intermediate wiring is formed; in the second interlayer insulating film made shielding film, so that the groove channel forming region overlaps;

液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间的液晶;以及 The liquid crystal cell having: a pixel electrode; electrode; and a liquid crystal formed between the pixel electrode and the electrode; and

源区或漏区与像素电极电连接。 Power source or drain region and the pixel electrode.

按照本发明,提供了一种半导体显示器件,它包括:在衬底上形成光屏蔽膜;在衬底上形成覆盖光屏蔽膜的绝缘膜;在绝缘膜上形成半导体层;与半导体层接触的栅绝缘膜;与栅绝缘膜接触的第一栅电极; According to the present invention, there is provided a semiconductor display device, comprising: forming a light shielding film on a substrate; a light shielding film covering the insulating film formed on a substrate; a semiconductor layer formed on the insulating film; contact with the semiconductor layer a gate insulating film; a first gate electrode in contact with the gate insulating film;

与第一栅电极接触的第二栅电极;以及液晶盒,其特点为: The second gate electrode in contact with the first gate electrode; and a liquid crystal cell, which is characterized by:

半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及 The semiconductor layer has: a channel forming region; LDD region in contact with the channel forming region; and

与LDD区接触的源区和漏区; The source and drain regions in contact with the LDD region;

LDD区与第一栅电极重叠,栅绝缘膜夹于其间; 沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; 光屏蔽膜经绝缘膜而与沟道形成区重叠; The LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween; and the channel forming region overlaps the second gate electrode, a gate insulating film interposed therebetween; light shielding film through an insulating film and overlaps with the channel forming region;

液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间的液晶;以及 The liquid crystal cell having: a pixel electrode; electrode; and a liquid crystal formed between the pixel electrode and the electrode; and

源区或漏区与像素电极电连接。 Power source or drain region and the pixel electrode.

按照本发明,提供了一种半导体显示器件,它包括:在衬底上形成光屏蔽膜;在衬底上形成覆盖光屏蔽膜的绝缘膜;在绝缘膜上形成半导体层;与半导体层接触的栅绝缘膜;与栅绝缘膜接触的第一栅电极; According to the present invention, there is provided a semiconductor display device, comprising: forming a light shielding film on a substrate; a light shielding film covering the insulating film formed on a substrate; a semiconductor layer formed on the insulating film; contact with the semiconductor layer a gate insulating film; a first gate electrode in contact with the gate insulating film;

与第一栅电极接触的第二栅电极;以及液晶盒,其特点为: The second gate electrode in contact with the first gate electrode; and a liquid crystal cell, which is characterized by:

半导体层具有:沟道形成区;与沟道形成区接触的LDD区;以及 The semiconductor layer has: a channel forming region; LDD region in contact with the channel forming region; and

与LDD区接触的源区和漏区; The source and drain regions in contact with the LDD region;

LDD区与第一栅电极重叠,栅绝缘膜夹于其间; The LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween;

沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; 光屏蔽膜经绝缘膜而与沟道形成区重叠; The channel forming region overlaps the second gate electrode, a gate insulating film interposed therebetween; a light shielding film through the insulating film overlaps with the channel forming region;

液晶盒具有:像素电极;对电极;及形成在像素电极与对电极之间的液晶;以及 The liquid crystal cell having: a pixel electrode; electrode; and a liquid crystal formed between the pixel electrode and the electrode; and

源区或漏区与像素电极电连接。 Power source or drain region and the pixel electrode.

本发明的特点在于:绝缘膜是用CMP抛光法抛平的。 Feature of the present invention is that: the insulating film is polished by CMP polishing method level.

本发明可以是以使用半导体显示器件为其特征的摄象机、放像设备、头戴显示设备或个人计算机。 The present invention may be based on the use of its semiconductor display device features a camera, playback equipment, wearing a display device or a personal computer.

按照本发明,提供了一种制作半导体显示器件的方法,包括以下步 According to the present invention, there is provided a method of fabricating a semiconductor display device, comprising the steps

骤: Steps of:

在绝缘表面上形成半导体层; 制作栅绝缘膜使之与半导体层接触; 制作第一导电膜使之与栅绝缘膜接触; 制作第二导电膜使之与第一导电膜接触; A semiconductor layer formed on an insulating surface; a gate insulating film so as to contact with the semiconductor layer; forming a first conductive film to make contact with the gate insulating film; forming a second conductive film is brought into contact with the first conductive film;

对第一导电膜和第二导电膜刻困形来制作第一栅电极和第二栅电 The first conductive film and the second conductive film is patterned to form the storm produced the first gate electrode and a second gate electrode

极; Pole;

以半导体层的第一栅电极和第二栅电极向半导体层掺入第一杂 A first gate electrode and the second semiconductor layer, a gate electrode to be incorporated into the first hetero semiconductor layer

质; Quality;

在半导体层上形成復盖第一栅电极和第二栅电极的掩模,并在半导体层中,借助于从形成在半导体层上的掩模掺入导电类型与第一杂质 Forming a mask covering the first gate electrode and second gate electrode on the semiconductor layer and the semiconductor layer, by means of the mask formed on the semiconductor layer, doping impurity of the first conductivity type

相同的第二杂质而制作:沟道形成区;与沟道形成区接触的笫一LDD 区;与第一LDD区接触的第二LDD区;以及与第二LDD区接触的源区和漏区; The same second impurity production: a channel forming region; Zi LDD region in contact with the channel forming region; a second LDD region in contact with the first LDD region; and a source region and a drain region in contact with the second LDD region ;

制作由单层或多层组成的层间绝缘膜,它覆盖半导体层、第一栅电极和第二栅电极; An interlayer made of a single layer or multiple layers of insulating film which covers the semiconductor layer, a first gate electrode and second gate electrode;

在层间绝缘膜中开接触孔; Opening a contact hole in the interlayer insulating film;

制作像素电极,它经过接触孔与源区或漏区相连,其特点为: 第一栅电极在沿沟道纵向方向上比第二栅电极长; 沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; Making the pixel electrode, which is connected via a contact hole to the source and drain regions, which is characterized by: a first gate electrode in a direction along the longitudinal direction of the channel length than the second gate electrode; a channel forming region overlaps the second gate electrode, the gate an insulating film sandwiched therebetween;

第一LDD区与笫一栅电极重叠,栅绝缘膜夹于其间, Zi a first LDD region overlaps the gate electrode, the gate insulating film interposed therebetween,

按照本发明,提供了一种制作半导体显示器件的方法,包括以下步 According to the present invention, there is provided a method of fabricating a semiconductor display device, comprising the steps

骤: Steps of:

在绝缘表面上形成半导体层; A semiconductor layer formed on an insulating surface;

制作栅绝缘膜使之与半导体层接触; A gate insulating film so as to contact with the semiconductor layer;

制作第一导电膜使之与栅绝缘膜接触; Forming a first conductive film is brought into contact with the gate insulating film;

制作第二导电膜使之与第一导电膜接触; Forming a second conductive film is brought into contact with the first conductive film;

对第一导电膜和第二导电膜刻图形来制作第一栅电极和第二栅电 On the first conductive film and patterning the second conductive film to produce a first gate electrode and a second gate electrode

极; Pole;

从半导体层的第一栅电极和第二栅电极向半导体层掺入第一杂 Incorporation of the first hybrid from the first semiconductor layer, a gate electrode and a second gate electrode to the semiconductor layer

质; Quality;

在半导体层上形成覆盖第一栅电极和第二栅电极的掩模,并在半导体层中,借助于从形成在半导体层上的掩模掺入导电类型与第一杂质 Forming a mask covering the first gate electrode and second gate electrode on the semiconductor layer and the semiconductor layer, by means of the mask formed on the semiconductor layer, doping impurity of the first conductivity type

相同的第二杂质而制作:沟道形成区;与沟道形成区接触的第一LDD 区;与第一LDD区接触的第二LDD区;以及与第二LDD区接触的源区和漏区; To prepare a second impurity same: a channel forming region; a first LDD region in contact with the channel forming region; a second LDD region in contact with the first LDD region; and a source region and a drain region in contact with the second LDD region ;

制作由单层或多层组成的层间绝缘膜,它覆盖半导体层、第一栅电 An interlayer made of a single layer or multiple layers of insulating film which covers the semiconductor layer, a first gate electrode

极和第二栅电极; Pole and a second gate electrode;

在层间绝缘膜中开接触孔; Opening a contact hole in the interlayer insulating film;

制作像素电极,它经过接触孔与源区或漏区相连,其特点为: 第一栅电极在沿沟道纵向方向上比第二栅电极长; 沟道形成区与第二栅电极重叠,栅绝缘膜夹于其间; 第一LDD区与第一栅电极重叠,栅绝缘膜夹于其间。 Making the pixel electrode, which is connected via a contact hole to the source and drain regions, which is characterized by: a first gate electrode in a direction along the longitudinal direction of the channel length than the second gate electrode; a channel forming region overlaps the second gate electrode, the gate an insulating film interposed therebetween; a first LDD regions overlap the first gate electrode, a gate insulating film interposed therebetween.

按照本发明,提供了一种制作半导体显示器件的方法,包括以下步 According to the present invention, there is provided a method of fabricating a semiconductor display device, comprising the steps

骤: Steps of:

在绝缘表面上形成半导体层; 制作栅绝缘膜使之与半导体层接触; A semiconductor layer formed on an insulating surface; a gate insulating film so as to contact with the semiconductor layer;

制作第一形状第一导电层使之与栅绝缘膜接触,并制作第一形状第二导电层; Forming a first shape of the first conductive layer makes contact with the gate insulating film, and forming a first shape of the second conductive layer;

腐蚀第一形状第一导电层和第一形状第二导电层,形成具有锥形部分的第一栅电极和具有锥形部分的第二栅电极; Etching the first shape first shape first conductive layer and a second conductive layer, forming a first gate electrode and second gate electrode has a tapered portion having a tapered portion;

经过栅绝缘膜向半导体层掺入呈单一导电类型的杂质元素,形成第二LDD区;同时,经过第一栅电极的锥形部分向半导体层掺入呈单一导电类型的杂质元素,形成第一LDD区,其中的杂质浓度向半导体层 After the gate insulating film was incorporated into the semiconductor layer of a single conductivity type impurity element, a second LDD region is formed; the same time, through the tapered portion of the first semiconductor layer, the gate electrode was incorporated in a single conductive type impurity element, forming a first LDD regions, wherein the impurity concentration of the semiconductor layer,

的边缘部分增高; The edge portion increased;

用第一和第二栅电极的锥形部分作掩模掺入呈单一导电类型的杂 With the tapered portion of the first and second gate electrode as a mask was incorporated into a single conductivity type hybrid

质元素,形成源区或漏区; Quality elements, to form the source and drain regions;

制作单层或多层的层间绝缘膜,它覆盖:半导体层;第一栅电极; 以及第二栅电极; Making monolayer or multilayer interlayer insulating film, which covers: a semiconductor layer; a first gate electrode; and a second gate electrode;

在层间绝缘膜中开接触孔; Opening a contact hole in the interlayer insulating film;

制作经接触孔与源区或漏区接触的像素电极。 Making the pixel electrode through the contact hole in contact with the source or drain region.

按照本发明,提供了一种制作半导体显示器件的方法,包括以下步 According to the present invention, there is provided a method of fabricating a semiconductor display device, comprising the steps

骤: Steps of:

在绝缘表面上形成半导体层; A semiconductor layer formed on an insulating surface;

制作栅绝缘膜使之与半导体层接触; A gate insulating film so as to contact with the semiconductor layer;

制作第一导电膜使之与栅绝缘膜接触; 制作第二导电膜使之与第一导电膜接触; Forming a first conductive film is brought into contact with the gate insulating film; forming a second conductive film is brought into contact with the first conductive film;

腐蚀第二导电膜,制成第一形状第二导电层; Etching the second conductive film, forming the first shape of the second conductive layer;

腐蚀第一导电膜,制成第一形状第一导电层; Etching the first conductive film, made of a first shape of the first conductive layer;

腐蚀第一形状第一导电层和第一形状第二导电层,形成具有锥形部分的第一栅电极和具有锥形部分的第二栅电极; Etching the first shape first shape first conductive layer and a second conductive layer, forming a first gate electrode and second gate electrode has a tapered portion having a tapered portion;

经过栅绝缘膜向半导体层掺入呈羊一导电类型的杂质元素,形成第二LDD区;同时,经过笫一栅电极的锥形部分向半导体层掺入呈单一导电类型的杂质元素,形成第一LDD区,其中的杂质浓度向半导体层的边缘部分增高; After the gate insulating film of the semiconductor layer to form an impurity element incorporated sheep one conductivity type, a second LDD region is formed; the same time, through the tapered portion of the gate electrode Zi to be incorporated into the semiconductor layer form a single conductive type impurity element to form a first an LDD region, wherein the impurity concentration increases toward the edge portion of the semiconductor layer;

用第一和第二栅电极的锥形部分作掩模掺入呈单一导电类型的杂质元素,形成源区或漏区; As with the tapered portions of the first and the second gate electrode mask was incorporated into a single conductivity type impurity element to form the source and drain regions;

制作单层或多层的层间绝缘膜,它覆盖:半导体层;第一栅电极; 以及第二栅电极; Making monolayer or multilayer interlayer insulating film, which covers: a semiconductor layer; a first gate electrode; and a second gate electrode;

在层间绝缘膜中开接触孔; Opening a contact hole in the interlayer insulating film;

制作经接触孔与源区或漏区接触的像素电极。 Making the pixel electrode through the contact hole in contact with the source or drain region.

在附图中: In the drawings:

图1A-1F是制作本发明的液晶显示器件的工艺过程图; Figure 1A-1F of the present invention is to produce a liquid crystal display device of the process diagram;

图2A和2B是TFT栅电极的放大图; 2A and 2B is an enlarged view TFT gate electrode;

图3A~ 3D是制作本发明的液晶显示器件的工艺过程图; Figure 3A ~ 3D is the production of liquid crystal display device of the present invention, the process diagram;

图4A-4D表示制作本发明的液晶显示器件的工艺过程图; Figures 4A-4D show manufacturing liquid crystal display device of the present invention is a process diagram;

图5A和5B表示制作本发明的液晶显示器件的工艺过程图; 5A and 5B show the production of liquid crystal display device of the present invention, the process diagram;

图6是制作本发明的液晶显示器件的工艺过程困; Figure 6 is a process of making a liquid crystal display device of the present invention is trapped;

图7A和7B分别为本发明液晶显示器件像素的俯视困和电路图; 7A and 7B of the present invention are trapped and schematic plan view of a liquid crystal display device pixels;

图8是本发明液晶显示器件的剖面图; 图9是本发明液晶显示器件的剖面图; 图IO是本发明液晶显示器件的剖面图; 图ll是本发明液晶显示器件的剖面图; Figure 8 is a cross-sectional view of the present invention, a liquid crystal display device; FIG. 9 is a sectional view of the present invention, a liquid crystal display device; Fig. IO is a cross-sectional view of the present invention, a liquid crystal display device; Fig. Ll is a sectional view of a liquid crystal display device of the present invention;

图12A和12B分别为本发明液晶显示器件像素的俯视图和剖面 A plan view and a sectional view of the present invention. 12A and 12B, respectively, pixel LCD

图; Figure;

图13A和13B表示晶化半导体层的方法; 图14A和14B表示晶化半导体层的方法; 图15A和15B表示晶化半导体层的方法; 图16是本发明液晶显示器件的方框图; 图17A-17F是使用本发明液晶显示器件的电子学设备; 图18A-18D是制作本发明的液晶显示器件的工艺过程图; 图19A和19B是TFT栅电极的放大图; 图20表示对于形状A, TaN的膜厚与电子温度的关系; 图21表示对于形状B, TaN的膜厚与电子温度的关系; 图22为对于形状B,电子温度与水平方向电场强度的比较; 图23表示在形状A和B中磷的浓度分布。 13A and 13B show a method of crystallizing a semiconductor layer; FIGS. 14A and 14B show a method of crystallizing a semiconductor layer; FIGS. 15A and 15B show a method of crystallizing a semiconductor layer; Fig. 16 is a block diagram of a liquid crystal display device of the present invention; Figure 17A- 17F is a liquid crystal display device of the present invention, an electronic apparatus; Fig. 18A-18D is the production of liquid crystal display device of the present invention process; Figures 19A and 19B is an enlarged view TFT gate electrode; Fig. 20 shows the shape of A, TaN Relationship between film thickness and electron temperature; FIG. 21 shows the relationship between the shape of B, TaN film thickness and electron temperature; FIG. 22 is Comparative shape B, the electron temperature and horizontal direction electric field strength; FIG. 23 shows the shape of the A and B concentration distribution of phosphorus. 模型实施方案 Embodiment Mode

图1A-1F表示本发明薄膜晶体管的结构及其制作方法。 Figure 1A-1F shows the structure of the thin film transistor and manufacturing method of the present invention. 在衬底100上形成基膜101。 A base film 101 on the substrate 100. 不一定要形成基膜IOI,但有它可防 Not necessarily a base film IOI, but it can prevent

止衬底100的杂质向半导体层扩散。 Only 100 of the substrate impurity diffusion into the semiconductor layer. 由已知方法制作的晶体半导体膜 A crystalline semiconductor film manufactured by a known method

在基膜101上形成半导体层102和103。 101 is formed on the base film semiconductor layers 102 and 103.

制作覆盖半导体层102和103的栅绝缘膜104。 Making the semiconductor layer 102 and the cover 103 of the gate insulating film 104. 然后在栅绝缘膜 Then the gate insulating film

104上制作第一导电膜105和笫二导电膜106,以构成栅电极。 Forming a first conductive film 105 and the second conductive film 106 on the sleeping mat 104 to form a gate electrode. 注意, Note,

第一导电膜105和第二导电膜106必须是具有腐蚀选择性的导电材料(见图1A)。 The first conductive film 105 and the second conductive film 106 must be a conductive material having etching selectivity (see FIG. 1A).

接着在半导体层102和103上形成抗蚀剂掩模107和108。 Then a resist mask 107 and 108 on the semiconductor layers 102 and 103. 然后用掩模107和108腐蚀第一导电膜105和第二导电膜106 (第一腐蚀过程)来形成第一形状导电层109和110 (第一导电层109a和110a,及第二导电层109b和110b)(见困1B)。 Then the mask 107 and etching the first conductive film 108 and the second conductive film 106 105 (first etching process) to form the first shape conductive layers 109 and 110 (first conductive layers 109a and 110a, and the second conductive layer 109b and 110b) (see sleepy 1B).

图2A为图1B的第一形状导电层109和110的放大图。 2A is an enlarged view of the first shape conductive layers 109 and 110 in FIG. 1B of. 第一导电层109a和110a的边缘部分,及第二导电层109b和110b的边缘部分 A first conductive layer 109a and the edge portion 110a, 109b and the second conductive layer and the edge portion 110b of

都成了锥形,如图2A所示.进而腐蚀栅绝缘膜104,使未被第一形状导电层109和IIO覆盖的区域减薄,成为笫一形状栅绝缘膜104a。 Have become tapered, as shown in Figure 2A. Further etching the gate insulating film 104, so that the shape is not the first conductive layer 109 and the thinned region covered IIO become Zi shape gate insulating film 104a.

接下来进行第二腐蚀过程,如图1C所示。 Next, a second etching process, as shown in Figure 1C. 各向异性腐蚀第一形状第二导电层109b和110b及第一导电层109a和110a,但后者的腐蚀速率慢于前者,从而形成第二形状导电层113和114(第一导电层113a 和114a,及第二导电层113b和114b)。 Anisotropically etching the first shape of the second conductive layer 109b and 110b and the first conductive layers 109a and 110a, but the corrosion rate which is slower than the former, thereby forming a second shape conducting layers 113 and 114 (first conductive layers 113a and 114a, and the second conductive layer 113b and 114b).

图1C的第二形状导电层113和114的放大图示于图2B。 Figure 1C second shape conducting layers 113 and 114 is shown in enlarged FIG. 2B. 在第二腐蚀过程中对第二导电层113b和114b的腐蚀要多于第一导电层113a和114a,如图2B所示。 In the second etching process, second conductive layers 113b and 114b to corrosion than the first conductive layer 113a and 114a, shown in Figure 2B. 进而在第二腐蚀过程中将掩模107和108腐蚀成掩模111和112。 Furthermore mask in the second etching process 107 and 108 etched in the mask 111 and 112. 再腐蚀第一形状栅绝缘膜104a,使未被第二形状导电层113和114覆盖的区域减薄而成为第二形状栅绝缘膜104b。 Then etching the first shape gate insulating film 104a, 113 and 114 are not so covered area of the second shape conducting layers become thinner second shape gate insulating film 104b.

除去掩模111和112,并在半导体层102和103中进行第一步掺杂,掺入n型导电杂质元素,如图1D所示。 Removing the mask 111 and 112, and 103 in the semiconductor layer and doped with a first step 102, the incorporation of n-type conductivity impurity element, shown in Figure 1D. 掺杂时用第二形状导电层113和114作为掩模以阻挡杂质元素.而且,完成的掺杂使之在第二形状导电层113a和114a下面的区域也加入了杂质元素。 With the second shape conductive layers 113 and 114 as a mask to block doping impurity element. Furthermore, the completion of doping so that in the second shape conductive layers 113a and 114a following regions have joined the impurity elements.

这样就形成了与第一导电层113a和114a重叠的第一杂质区115 和116,和杂质浓度高于第一杂质区的第二杂质区117和118。 Thus forming a first conductive layer 113a and 114a overlaps the first impurity regions 115 and 116, and the impurity concentration higher than the first impurity region of the second impurity regions 117 and 118. 注意, 虽然在此模型实施方案中是在除去掩模111和112后掺入n型杂质的,但本发明不限于此。 Note that although this embodiment mode removing the masks 111 and 112 after the incorporation of n-type impurity, but the present invention is not limited thereto. 在图1D的工艺过程中也可在掺入n型导电杂质元素后再除去掩模111和112。 In the process of FIG. 1D may also be incorporated into the n-type conductivity impurity element 111 and 112 and then removing the mask.

在半导体层103上用抗蚀剂形成掩模119以覆盖第二形状导电层114,掩模119与第二杂质区118的一部分重叠,第二形状栅绝缘膜104b夹于其间。 On the semiconductor layer 103 is formed using a resist mask to cover 119 partially overlap the second shape conductive layer 114, the mask 119 and the second impurity region 118, a second shape gate insulating film 104b interposed therebetween. 然后进行第二步掺杂,掺入n型杂质元素。 Then the second step doping, n-type impurity element. n型掺杂是在这样的条件下进行的,即剂量比第一步掺杂增大而加速电压降低。 n-type doping is carried out under such conditions, i.e., the dose and the acceleration voltage is lower than in the first step is increased doping. 除了沟道形成区124和Lov区123外,在第二步掺杂中以自对准的方式在半导体层103中还形成了源区120、漏区121和Loff区122。 In addition to the channel forming region 124 and an Lov region 123, the second step of doping in a self-aligning manner in the semiconductor layer 103 is also formed a source region 120, drain region 121 and the Loff region 122. 在第二步掺杂中用第二形状第一导电层113a作掩模,还形成了第三杂质区125 (见图1E)。 In a second step a first doping with the second shape conductive layer 113a as a mask, is also formed a third impurity region 125 (see FIG. 1E).

在本发明中控制掩模119的尺寸,可自由地设置Loff区122的尺寸。 Control the size of the mask 119 in the present invention can be freely set Loff region 122 size.

然后在形成n沟道TFT的半导体层103的全部表面上覆盖抗蚀剂掩模126,如图1F所示。 Covering the semiconductor layer and the n-channel TFT is formed on the entire surface of the resist mask 103, 126, as shown in FIG 1F. 用第二形状导电层113作掩模以阻挡杂质元素由第三步掺杂在源区127、漏区128和Lov区129掺入呈p型导电的杂质元素;在制作p沟道TFT的半导体层102中就以自对准的方式制成了沟道形成区130。 With the second shape conductive layer 113 as a mask to block doping an impurity element from the third step in the source region 127, drain region 128 and an Lov region 129 was incorporated into the p-type conductivity impurity element; p-channel TFT in the semiconductor fabrication layer 102 in a self-aligning manner on the channel forming region 130 is made.

不同浓度的n型杂质已掺入源区127、漏区128和Lov区129,但在掺入的p型杂质浓度远高于n型杂质时,源区127、漏区128和Lov 区129的导电类型就成为p型, Different concentrations of n-type impurity is incorporated into the source region 127, drain region 128 and an Lov region 129, but in the p-type impurity concentration is much higher than the incorporation of n-type impurity, a source region 127, drain region 128 and the Lov region 129 Become a p-type conductivity type,

由上述工艺过程在半导体层102和103中制成了杂质区(源区、 漏区、Lov区和Loff区).与半导体层102和103重叠的第二形状导电层113和114作为栅电极。 Prepared by the above process of the impurity region (source region, drain region, Lov regions, and Loff regions) 103 and the semiconductor layer 102 and the semiconductor layers 102 and 103 overlap the second shape conductive layers 113 and 114 as the gate electrode. 第二形状第一导电层113a和114a称为第一栅电极,而第二形状第二导电层113b和114b称为第二栅电极。 The second shape first conducting layer 113a and 114a is called a first gate electrode, and the second shape of the second conductive layer 113b and 114b as a second gate electrode.

接着激活掺入各个半导体层的杂质以控制导电性。 Then activating the impurity for controlling the respective semiconductor layers conductive. 然而,如果第一导电膜105和第二导电膜106所用的导电材料不耐热的话,最好在形成层间绝缘膜(含有硅为其主要成分)后再进行激活,以保护一些部分如引线。 However, if the first conductive film 105 and the conductive material of the second conductive film 106 with heat-labile, it is preferably formed in the interlayer insulating film (containing silicon as its main component) and then activated, in order to protect portions such as the leads .

另外,在含3-100X氢的气氛中进行热处理可实现半导体层102和103的氢化。 In addition, in an atmosphere containing hydrogen 3-100X heat treatment can be achieved in the hydrogenation of the semiconductor layers 102 and 103. 这个过程是用热激活的氢来饱和半导体层中的悬键。 This process is thermally activated hydrogen to unsaturated dangling bonds in the semiconductor layer. 等离 Plasma

子氢化(用等离子体激活的氢)也可作为另一种氢化手段。 Sub hydrogenation (using hydrogen activated by a plasma) may also be used as another means of hydrogenation.

当上述工艺过程结束时,就完成了p沟道TFT 141和n沟道TFT When the completion of the process, to complete the p-channel TFT 141 and n-channel TFT

142。 142.

注意,虽然图1A〜1F和图2A与图2B中所示的各个表面都是平的, 对于在沟道纵向上第二形状第一栅电极113a和114a比第二栅电极113b和114b长的区域,实际上是有锥度的,存在着极小的锥角。 Note that, although FIG. 2A and FIG 1A~1F respective surface shown in FIG. 2B are flat, the longitudinal direction of the channel for the second shape first gate electrodes 113a and 114a than the second gate electrode 113b and 114b length area, in fact, have tapered, there is a very small cone angle. 还要注意,依赖于腐蚀条件,也可能做成平的。 Also note that, depending on the etching conditions, it may be flat.

如上所述,第一栅电极和笫二栅电极沿沟道纵向(栽流子移动方向)的长度(此后简称栅电极宽度)在本发明中是不同的。 As described above, the first gate electrode and second gate electrode Zi channel longitudinal direction (plant carrier movement direction) length (hereinafter referred to as the gate electrode width) is different in the present invention. 在用第一栅电极和第二栅电极作掩模进行离子注入时,利用了因栅电极厚度的不同而产生的离子透入深度的差别。 When using the first gate electrode and second gate electrode as a mask by ion implantation using the gate electrode due to the different thickness of the resulting difference in ion penetration depth. 因此就能够使在第二栅电极下面半导体层内的离子浓度低于在第一栅电极下面而又不在第二栅电极之下的半导体层的离子浓度。 Therefore, it is possible to make the ion concentration within the semiconductor layer under the second gate electrode lower than the ion concentration of the semiconductor layer under the first but not the second gate electrode below the gate electrode. 另外,也能够使在第一栅电极下面而又不在第二栅电极之下的半导体层的离子浓度低于不在第一栅电极下面的半导体层的离子浓度。 Further, it is possible to make the ion concentration in the first semiconductor layer below the gate electrode but not below the second gate electrode is not less than a first gate electrode below the ion concentration of the semiconductor layer.

再者,为了用掩模形成Loff区,只需由腐蚀控制第一栅电极和第 Furthermore, in order to form the Loff regions using a mask, simply controlled by etching the first gate electrode and the first

二栅电极的宽度,因此控制Loff区和Lov区的位置就比常规的实例容易。 The width of the second gate electrode, thereby controlling the position of the Loff region and the Lov region is easier than conventional examples. 这样就容易做到Lov区和Loff区的精确定位对准,制作具有所需特性的TFT也就容易了。 Thus it is easy to achieve precise positioning of the Lov region and the Loff region is aligned to produce a TFT having desired characteristics also easy. 实施方案 Embodiments

本发明的一些实施方案说明如下。 Some embodiments of the present invention are described below. [实施方案1] [Embodiment 1]

实施方案1中详细说明了在同一衬底上同时制作像素部分和形成在^f象素部分周围的驱动电路TFT (n沟道和p沟道TFT)的方法。 1 embodiment, the method described in detail at the same time on the same substrate, making the pixel portion and the pixel portion is formed in ^ f around the driver circuit TFT (n-channel and p-channel TFT) is.

首先,如图3A所示,在衬底300上形成由绝缘膜,如二氧化硅膜、 氮化硅膜或氮氧化硅膜,制成的基膜301,衬底由玻璃或石英制成,如硼硅酸钡或硼硅酸铝玻璃,典型地如康宁公司(Corning Corp.)的#7059或#1737玻璃。 First, as shown in FIG. 3A, a substrate 300 is formed on an insulating film such as silicon oxide film, a silicon nitride film or a silicon oxynitride film, the base film 301 made of a substrate made of glass or quartz, such as barium borosilicate glass or aluminum borosilicate, typically as Corning Incorporated (Corning Corp.) in # 7059 or # 1737 glass. 例如,用等离子CVD法由SiH" NH3和N』制作的氮氧化硅膜,厚度10 - 200 nm (最好50 - 100 nm),类似地由SiH4 和10制作厚为50 ~ 200 nm (最好在100 - 150 nm之间)的氢化氮氧化硅膜,并形成叠层。注意,两层结构的基膜301在图3A中被表示为一层。注意,实施方案1所示的是基膜301为两层结构的实例,但也可形成上述绝缘膜之一的单层或者三层或多层叠成的叠层结构。 For example, a silicon oxynitride film formed by plasma CVD method by the SiH "NH3 and N 'production, the thickness of 10 - 200 nm (preferably 50 - 100 nm), is similarly produced from SiH4 and a thickness of 10 50 ~ 200 nm (preferably 100 - between 150 nm) of a hydrogenated silicon oxynitride film, and to form a laminate noted that two-layer structure of the base film 301 in FIG. 3A is represented as a layer of note, in the embodiment shown is a base film. Examples of two-layer structure is 301, but the insulating film may be formed of a single layer or three or more layers of the folded laminate structure.

半导体层302 ~ 304是由晶体半导体膜构成的,是用无定形结构的半导体膜进行激光晶化,或用已知的热晶化法制作的。 The semiconductor layer 302 to 304 by the crystalline semiconductor film is the amorphous structure of the semiconductor film by laser crystallization, or thermal crystallization method known production. 半导体层302 ~ 304的厚度为25 - 80 nra (最好在30 - 60 nm之间)。 Thickness of the semiconductor layers 302 to 304 for 25 - 80 nra (preferably 30 - between 60 nm). 对晶体半导体膜的材料没有什麽限制,但最好由半导体材料如硅或锗硅合金(SiGe) 来制成。 There is no limit on the crystalline semiconductor film material, but is preferably such as silicon or silicon germanium (SiGe) alloy to be made of a semiconductor material.

至于已知的晶化方法,有使用电炉的热晶化法、用激光的激光退火晶化法、用红外灯的灯照退火晶化法、及用催化金属的晶化法。 As a known crystallization method using an electric furnace has a thermal crystallization method using laser laser annealing crystallization method using infrared light, a lamp annealing crystallization method, and with catalytic metal crystallization method.

脉冲发射或连续发射型的受激准分子激光器、YAG激光器和YV0a 激光器都可作为激光源用于激光晶化法制作晶体半导体膜.在用这种类型的激光器时,可使用将激光器发射的光经光学系统聚成线状,再照射到半导体膜上的方法。 Pulse emission or continuous emission type excimer laser, YAG laser and YV0a laser can be used as a laser light source laser crystallization method crystal semiconductor film used in this type of laser, it can use the light emitted by the laser through an optical system into a linear shape, and then irradiated to the semiconductor film approach. 操作者可以适当地选择晶化条件,但在使用准分子激光器时,脉冲发射的频率为30Hz,激光能量密度为100-400nJ/cm2 (典型地在200 - 300 mJ/c迈2之间)。 The operator may be suitably selected crystallization conditions, but when using the excimer laser, the pulse emission frequency is 30Hz, the laser energy density is 100-400nJ / cm2 (typically 200 - 300 mJ / c between step 2). 此外,在使用YAG激 In addition, the use of YAG laser

光器时利用其二次谐波,脉冲发射频率为1~10 KHz,激光能量密度可为300 - 600 mJ/cm2 (典型地在350 - 500 mJ/cm2之间)。 When utilizing the second harmonic light is pulse emission frequency is 1 ~ 10 KHz, the laser energy density may be 300 - 600 mJ / cm2 (typically 350 - 500 mJ / between cm2). 聚成线状 Into a linear shape

的激光,宽100~ 1000 nm,例如400 pm,然后照射到衬底的整个表面。 Laser, width of 100 ~ 1000 nm, e.g., 400 pm, and then irradiated to the entire surface of the substrate. 对于线状的激光,这是以80 - 98?4的重叠比(overlap ratio)来进行的。 For linear laser, which is 80 -? 98 4 overlapping ratio (overlap ratio) to carry out.

制作栅绝缘膜305,夜盖在半导体层302 - 304上。 A gate insulating film 305, the night cover the semiconductor layer 302 - 304. 厚为40 - 150 nm 的含硅栅绝缘膜305是用等离子CVD或溅射法制作的。 A thickness of 40 - 150 nm in the gate insulating film 305 is a silicon-containing plasma produced by CVD or sputtering. 在实施方案1 中制成了120mn厚的氮氧化硅膜。 In the embodiment 1, it made a 120mn-thick silicon oxynitride film. 当然,栅绝缘膜不限于这种氮氧化硅膜,其他单层或叠层结构的含硅绝缘膜也可使用。 Of course, the gate insulating film is not limited to such a silicon oxynitride film, a silicon-containing insulating film is a single layer or other laminate structures may also be used. 例如,在使用氧化硅膜时,可用等离子CVD法,使TE0S (原硅酸四乙酯)与02的混合物在40Pa的反应压力下,衬底温度为300 ~ 400X:,在0. 5-0. 8W/cm2 的高频(13. 56MHz)电功率密度下放电来形成氧化硅膜。 For example, when using a silicon oxide film, a plasma CVD method can be used, so TE0S (tetraethyl orthosilicate) and the mixture was reacted at 02 40Pa of pressure, substrate temperature of 300 ~ 400X :, in 0. 5-0 . 8W / cm2 frequency (13. 56MHz) at a discharge electric power density to form a silicon oxide film. 这样制作的氧化硅膜接着在400 - 5001C下进行热退火,可得到良好特性的栅绝缘膜。 The silicon oxide film thus manufactured then at 400 - 5001C under thermal annealing, good characteristics can be obtained a gate insulating film.

然后在栅绝缘膜305上制作第一导电膜306和第二导电膜307以形成栅电极。 The first conductive film 306 and the second conductive film is then formed on the gate insulating film 305 to form a gate electrode 307. 在实施方案l中,第一导电膜306是由50 - 100 nm厚的Ta (钽)制成的,而第二导电膜307是由100~ 300 nm厚的W (鴒) 制成的。 L In an embodiment, the first conductive film 306 is made 50 - Ta 100 nm thickness (Ta) made of the second conductive film 307 is composed of 100 ~ 300 nm thick W (ling) made.

Ta膜是用滅射法制作的,用Ar溅射Ta靶.若在溅射时在Ar中加入适量的Xe和Kr,可消除Ta膜的内应力,因而防止膜的剥落。 Ta film is shot off method produced by Ar sputtering Ta target. If added during sputtering in Ar in an appropriate amount of Xe and Kr, can eliminate the stress of the Ta film, thus preventing peeling of the film. oc相的Ta膜电阻率为20n Ocm,可用作栅电极,但p相的Ta膜电阻率为180nQcm,不适于作栅电极,如果形成厚10〜50nm而晶体结构接近oc相Ta的氮化钽作为Ta的基底来形成a相Ta膜的话,a相的Ta膜可以容易地得到。 oc phase Ta film resistor was 20n Ocm, can be used as a gate electrode, but the p-phase Ta film resistivity of 180nQcm, not suitable for the gate electrode, if the crystal structure to form a thick 10~50nm close oc phase Ta nitride tantalum Ta as a base to form a phase Ta film, then, Ta film of a phase can be easily obtained.

W膜是用W作靶溅射而成的,W膜也可用热CVD法由六氟化钨(WF6) 来制成。 W W film is formed by sputtering as the target, W film can also be used by the thermal CVD tungsten hexafluoride (WF6) be made. 不论使用哪一种方法,必须将膜制成低阻的以用之作为栅电极,最好使制成的W膜电阻率等于或小于20MOcm。 Regardless of which method to use, it must be made of low resistance film to use it as a gate electrode, it is preferable that the resistivity of the W film be made equal to or less than 20MOcm. 增大W膜的晶粒可以降低电阻率,但在W膜中有许多杂质元素如氧的情形,会妨碍晶化,并且膜变为高阻的。 Crystal grains of the W film increases the resistivity can be reduced, but there are many situations in impurity elements such as oxygen in the W film, crystallization will hinder, and the film becomes high resistance. 因此纯度为99.9999X或99.99X的W靶用于溅射。 Therefore purity W target 99.9999X or 99.99X for sputtering. 另外,若在形成W膜时特别注意不从气相中引入杂质,则可做到9-20p Qcm的电阻率。 In addition, special attention if the W film is formed without introducing impurities from the gas phase can be done 9-20p Qcm resistivity.

注意,虽然在实施方案l中,第一导电膜306的材料是Ta,第二导电膜307的材料是W,但导电膜不限于这些,只要是具有腐蚀选择性的导电材料即可。 Note that, although in the embodiments l, the material of the first conductive film 306 is Ta, the material of the second conductive film 307 is W, a conductive film but not limited to these, as long as the electrically conductive material having etching selectivity to. 第一导电膜306和第二导电膜307也可由选自Ta、W、 Ti、 Mo、 Al和Cu这组元素中的一种,或以这些元素之一为主要成分的合金材料,或由这些元素的化合物来制成.而且,也可使用半导体膜,典型地为多晶硅膜,膜中掺有杂质元素,如磷。 The first conductive film 306 and the second conductive film 307 may also be selected from Ta, W, Ti, Mo, Al, and Cu in which a set of elements, one of these elements or an alloy material as its main component, or from these compounds of elements to be made. Further, a semiconductor film may also be used, typically a polycrystalline silicon film, the film doped with an impurity element such as phosphorus. 除了实施方案l 中所用者外,优选的实例组合还包括:由氮化钽(TaN)制成的第一导电膜和由W制成的第二导电膜;由氮化钽(TaN)制成的第一导电膜和由Al制成的第二导电膜;由氮化钽(TaN)制成的笫一导电膜和由Cu 制成的第二导电膜(见图3B)。 In addition to those embodiments l wearer, the preferred examples of the combination further comprising: a first conductive film and the second conductive film made of W formed by tantalum nitride (TaN) formed; made of tantalum nitride (TaN) The first conductive film and the second conductive film made of Al; Zi conductive film and the second conductive film made of tantalum nitride (TaN) made of Cu formed (see FIG. 3B).

接着,由抗蚀剂形成掩模308 ~311,进行第一腐蚀过程以制作电极和引线。 Next, a resist mask is formed by 308 ~ 311, a first etching process for the production of electrodes and leads. 在实施方案1中使用ICP(感应耦合等离子体)腐蚀法。 In Embodiment 1 using ICP (inductively coupled plasma) etching method. CF, 和Ch的混合气体用作腐蚀气体,并在1 Pa的压力下对线團状的电极施加500W的射频功率(13. 56MHz)来产生等离子体,衬底側(样品台) 也施加100W的射频功率(13. 56MHz),有效地施加负的自偏压。 CF, and the mixed gas is used as etching gas Ch, and pressure is applied at 1 Pa RF power 500W (13. 56MHz) of the coil-shaped electrode to generate a plasma, the substrate side (sample stage) also applying 100W RF power (13. 56MHz), effectively applying a negative self-bias voltage. 在Ch和Ch合用时,W膜和Ta膜都以同样的量级被腐蚀。 When combined Ch and Ch, W film and the Ta film are both on the same order of corrosion.

注意,虽然图3C中未示出,在上述的腐蚀条件下,使用适当形状的抗蚀剂掩模,按照衬底側所加的偏压,第一导电层和第二导电层的边缘部分被做成锥形。 Note that, although not shown in Fig. 3C, under the above etching conditions, the use of a suitably shaped resist mask, according to the applied bias the substrate side edge portion of the first conductive layer and the second conductive layer is He is tapered. 锥形部分的角度为15 ~ 45 。 Angle of the tapered portion is 15 ~ 45 . 腐蚀时间可增加10-20 %,以使腐蚀后在栅绝缘膜上没有残留物。 Etching time can be increased 10-20%, so that after etching the gate insulating film without residue. 氮氣化硅膜对W 膜的选择比为2-4 (典型地为3),因此在此过腐蚀过程中约有20-50 nm暴露出的氮化硅膜被腐蚀掉。 Nitrogen selectivity of the silicon film on the W film was 2-4 (typically 3), and therefore in this over-etching process is about 20-50 nm of the silicon nitride film is exposed is etched. 此外,虽然在图3C中未示出,栅绝缘膜305未被第一形状导电层312-315覆盖的区域也被减薄20-50 nm,形成了第一形状栅绝缘膜305a。 In addition, although not shown in FIG. 3C, 305 are not covered by the 312-315 region of the gate insulating film of the first shape conducting layer is also thinned 20-50 nm, forming a first shape gate insulating film 305a.

于是,在第一腐蚀过程中由第一导电层和第二导电层形成了第一形状导电层312-315 (第一导电层312a~315a和第二导电层312b~ 315b)。 Thus, in the first etching process, the first conductive layer and the second conductive layer is formed of a first conductive layer 312-315 shape (first conductive layers 312a ~ 315a and second conductive layers 312b ~ 315b).

接下来进行第二腐蚀过程,如图3D所示.同样地使用ICP腐蚀法, 用CF" Ch和(h的混合物作为腐蚀气体,在lPa的压力下向线團状的电极施加500W的射频功率(13. 56MHz )来产生等离子体。50W的射频 Next, a second etching process, as shown in Figure 3D. Likewise using ICP etching method using CF "Ch mixture and (h as an etching gas, pressure is applied at lPa 500W of RF power to the coil-shaped electrode (13. 56MHz) to generate the RF plasma .50W

(13. 56MHz)功率加到衬底側(样品台),并施加比第一腐蚀过程低的自偏压。 (13. 56MHz) power is applied to the substrate side (sample stage), and lower than the first etching process is applied to the self-bias. 在这些腐蚀条件下,W膜被各向异性腐蚀,而Ta膜(第一导电层)以较慢的速率被各向异性腐蚀,形成第二形状导电层320 - 323 Under these etching conditions, W film is anisotropically etched, and the Ta film (first conductive layer) at a slower rate by anisotropic etching, forming second shape conductive layers 320--323

(第一导电层320a〜3"a和第二导电层320b~ 323b)。此外,虽然图3D中未示出,栅绝缘膜305未被第二形状导电层320 - 323覆盖的 (First conductive layer 320a~3 "a and second conductive layers 320b ~ 323b) Furthermore, although not shown in FIG. 3D, the gate insulating film 305 is not the second shape conductive layers 320 - 323 covered

区域再被腐蚀掉20〜50nm,变得更薄,形成第二形状栅绝缘膜305b。 Is then etched away region 20~50nm, it becomes thinner, forming a second shape gate insulating film 305b. 掩模308 ~ 311在第二腐蚀过程中被腐蚀,成为掩模316 ~ 319。 Mask 308 ~ 311 in the second etching process is etched to become a mask 316 ~ 319.

按照混合气体Ch和CL, W膜和Ta膜的腐蚀反应可由所产生的基团及反应产物的离子类型和蒸汽压来估计。 The hybrid gas Ch and CL, corrosion reaction W film and the Ta film is produced by the group and a reaction product of ion types and vapor pressures to estimate. 比较W和Ta的氟化物和氯化物的蒸汽压,W的氟化物WF6蒸汽压是极高的,WCls、 TaF5和TaCl; 的蒸汽压则具有相似的量级。 Comparison of W and Ta fluorides and chlorides vapor pressure, W WF6 fluoride vapor pressure is high, WCls, TaF5 and TaCl; vapor pressure is a similar magnitude. 因此W膜和Ta膜都被C&和CL的气体混合物腐蚀。 Therefore the W film and the Ta film are both C & CL gas mixture and corrosion. 然而,如果在这种气体混合物中添加适量的02, CF4与0, 反应,生成CO和F,并产生大量的F基团和F离子。 However, if you add the right amount of this gas mixture 02, CF4 and 0, the reaction of CO and F, and a large amount of F radicals and F ions. 结果,具有高氟化物蒸汽压的W膜腐蚀速率增高。 Results, W film having a high fluoride vapor pressure corrosion rate increased. 另一方面,即使F增多,Ta的腐蚀速率也未相对增加。 On the other hand, even if F increases, the etching rate of the Ta does not relatively increase also. 此外,Ta比W容易氧化,因此添加02后Ta的表面被氣化。 Further, Ta is easily oxidized than W, Ta and therefore after the addition of surface 02 is vaporized. Ta膜的腐蚀速率会进一步降低,因为Ta的氧化物不与氟化物和氯化物起反应。 The corrosion rate of the Ta film is further reduced because Ta oxides do not react with fluoride and chloride. 因此能使W膜和Ta膜的腐蚀速率有差别,并使W 膜的腐蚀速率大于Ta膜。 Thus enabling the W film and the Ta film etching rate difference, and the etching rate of the W film larger than Ta film.

除去掩模316-319,进行如图4A所示第一掺杂过程,掺入呈n 型导电的杂质。 316-319 removing the mask, a first doping process is shown in Figure 4A, the incorporation of n-type conductivity impurity. 例如,可在70-120keV的加速电压和1 x lt)"原子/cm2 For example, at an acceleration voltage 70-120keV and 1 x lt) "atoms / cm2

的剂量下进行掺杂.用第二导电层320b〜322b作掩模进行掺杂,使杂质掺入第一导电层320a~ 322a下面的区域,这样,就形成了与第一导电层320a~ 322a重叠的第一杂质区325 ~ 327,以及杂质浓度高于第一杂质区的第二杂质区328 - 330,注意,在实施方案l中是在除去掩模316-319后进行n型掺杂的,但本发明不限于此。 The next dose doping with a second conductive layer as a mask 320b~322b doping impurity incorporation 320a ~ 322a The following area of the first conductive layer, so that to form a first conductive layer 320a ~ 322a a first impurity region 325 overlaps ~ 327, and an impurity concentration higher than the first impurity region of the second impurity region 328--330, noted that in the embodiment l is carried out after removing the mask 316-319 n-type doped However, the present invention is not limited thereto. 也可在图4A的步骤中进行n型掺杂,然后除去掩模316-319. N-type doping may be performed in the step of FIG. 4A, the mask is then removed 316-319.

接下来在半导体层304上制作掩模331来盖住第二导电层318。 Next, on the semiconductor layer 331 to cover the mask 304 made of the second conductive layer 318. 掩模331的一部分与第二杂质区330重叠,第二形状栅绝缘膜305b夹于其间。 A portion of the mask 331 overlaps with the second impurity region 330, a second shape gate insulating film 305b interposed therebetween. 然后进行第二掺杂过程,掺入n型杂质。 Then second doping process, the incorporation of n-type impurity. 在剂量高于第一掺杂过程和低加速电压的条件下进行n型掺杂(见图4B)。 N-type doping (see FIG. 4B) at a dose higher than the first doping process and a low acceleration voltage conditions. 可用离子掺杂或离子注入来进行掺杂。 Available ion doping or ion implantation doping. 离子掺杂是在1 x io13 ~ 5 x 10"原子/cm2的剂量和60~ 100keV的加速电压下进行的。周期表中的V族元素,典型地磷(P)或砷(As ),用作n型杂质,这里使用的是磷(P)。在此情况下,第二形状导电层320和321成为n型杂质的掩模,而以自对准方式形成源区332 ~ 334、漏区335 ~ 337、中间区338和Lov区339 和340。此外,由掩模331形成Loff区341。 掺入源区332 ~ 334和漏区335 - 337的n型杂质的浓度为1 x 102-1 x 102'原子/cm3的范围。 Ion doping is at 1 x io13 ~ 5 x 10 "atoms / cm2 dose and acceleration voltage of 60 ~ 100keV conducted. V of the periodic table of elements, typically phosphorus (P) or arsenic (As), with for the n-type impurity, phosphorus is used here (P). In this case, the second shape conductive layers 320 and 321 become masks n-type impurity, and a self-aligning manner to form a source region 332 ~ 334, the drain region 335 - 337, 338 and the intermediate region and the Lov region 339 340. In addition, a mask 331 is formed by the incorporation of Loff region 341. The source region 334 and drain region 332 - 335 - 337 n-type impurity concentration of 1 x 102 - 'range of 1 x 102 atoms / cm3.

按照本发明,控制掩模331的尺寸可以自由地设置沿栽流子移动方向上Loff区341的长度。 According to the present invention, the control 331 of the mask size can be set freely planted along the moving direction of carriers length Loff region 341.

掺入n型杂质元素,4吏在Loff区形成lxlo"-lxio"原子/cm3 和在Lov区形成1 x 10" ~ 3 x 10'8原子/cm3的杂质浓度。 N-type impurity element, four officials in the Loff region formed lxlo "-lxio" atoms / cm3 and an impurity concentration of 1 x 10 "~ 3 x 10'8 atoms / cm3 in the Lov region.

注意,在图4B中,也可在半导体层304上制作掩模之前或之后, 在70 - 120 keV加速电压下进行n型掺杂。 Note that, in FIG. 4B before, may be made in a mask on the semiconductor layer 304, or after, in the 70 - 120 keV acceleration voltage n-type doping. 上述工艺过程使成为像素TFT的Loff区341部分的n型杂质浓度降低,而使驱动电路用的n沟道TFT的Lov区340部分的n型杂质浓度升高。 N-type impurity concentration of the above-described process makes the Loff region becomes the pixel TFT portion 341 is lowered, leaving the driving circuit of the n n-type impurity concentration of the channel portion of the TFT Lov region 340 is increased. 抑制成为像素TFT的Loff区341部分的n型杂质浓度能降低像素TFT的关态电流。 N-type impurity concentration becomes inhibitory Loff region 341 of the pixel TFT portion can reduce the off current of the pixel TFT. 而且, 升高驱动电路用的n沟道TFT的Lov区340部分的n型杂质浓度,可防止因漏区附近高电场产生热载流子,由于热载流子效应而导致的退化现象。 Moreover, n-type impurity concentration in the channel TFT of Lov region 340 to be raised driving circuit n, can be prevented due to the high electric field near the drain region of hot carriers, degradation due to hot carrier effects caused. 在驱动电路用的n沟道TFT的Lov区340部分的n型杂质浓度最好为5 x 10'7~ 5 x 10"原子/cm3。 N-type impurity concentration in the driving circuit n-channel TFT portion Lov region 340 is preferably 5 x 10'7 ~ 5 x 10 "atoms / cm3.

然后在形成p沟道TFT的半导体层302中,掺入与上述单一导电类型相反的杂质元素,形成源区360、漏区361及Lov区342,如图4C 所示。 Then the semiconductor layer 302 is formed in the p-channel TFT, and the incorporation of a single conductivity type opposite to said impurity element to form a source region 360, drain region 361 and an Lov region 342, shown in Figure 4C. 第二形状导电层320用作杂质掩模,以自对准方式形成杂质区。 The second shape conducting layers 320 as an impurity mask, a self-aligning impurity regions are formed. 制作n沟道TFT的半导体层303和304的整个表面上这时覆盖以抗蚀剂掩模343。 Then cover the production of an n-channel TFT 303 and the entire surface of the semiconductor layer 304 to resist mask 343. 不同浓度的裤已掺入源区360、漏区361及Lov区342, 在这里用乙硼烷(BdO进行离子掺杂,使每个区域掺硼的浓度达到2 x 102~ 2 x 102'原子/^3。实际上,源区360、漏区361及Lov区342 所含的硼浓度受导电层和绝缘膜厚度的影响,与第二掺杂过程相似, 在半导体层上面导电层和绝缘膜边沿的剖面部分是有锥度的。所以掺入的杂质元素的浓度也是变化的。 Different concentrations of pants 360 has been incorporated into the source region, the drain region 361 and an Lov region 342, here with diborane (BdO ion doping, the concentration of each of the boron-doped region reaches 2 x 102 ~ 2 x 102 ' atom / ^ 3. In fact, a source region 360, a drain region 361 and the Lov region 342 contains a conductive layer and the insulating effect of the film thickness by the boron concentration, and a second doping process is similar to the semiconductor layer on top of the conductive layer and the insulation in cross-sectional portion of the film edge is tapered, so the concentration of the impurity element is also incorporated changes.

由上述工艺过程在各个半导体层302 ~ 304中形成了杂质区(源区、漏区、Lov区和Loff区)。 Formed by the above process impurity region (source region, drain region, Lov region and the Loff region) in the respective semiconductor layers 302 to 304. 与半导体层302 ~ 304重叠的第二形状导电层320 - 322用作栅电极。 The semiconductor layer of the second shape conducting layers 302 to 304 overlapping 320--322 as a gate electrode. 此外,第二形状导电层323用作电容引线。 In addition, the shape of the second conductive layer 323 is used as capacitor lead wires.

然后对各个半导体层掺入的杂质进行激活,以控制导电类型。 Then each of the semiconductor layers incorporated impurities activated to control the conductivity type. 用退火炉作热退火来进行这一工艺过程。 Thermal annealing using an annealing furnace as to make this process. 此外,也可使用激光退火和快速热退火UTA)。 It is also possible to use laser annealing and rapid thermal annealing UTA). 热退火是在氣浓度等于或小于lpp迈的氮气氛中,最好等于或小于0. lppm,在400〜7001C,典型地在500 ~ 6001C之间进行的。 Thermal annealing is performed in a gas concentration equal to or less than lpp step in a nitrogen atmosphere, preferably equal to or less than 0. lppm, in 400~7001C, typically between 500 ~ 6001C conducted. 在实施方案1中热处理是在500t:下进行4小时。 In one embodiment, the heat treatment is at 500t: the next four hours. 然而,对于第 However, for the first

一导电层306和第二导电层307所用的导电材料不耐热的情形,最好在制成层间绝缘膜(主要成分为硅)之后进行激活,以保护栅电极和引线等。 Case 1 conductive layer 306 and the second conductive layer 307 is used for heat-conductive material, preferably made in the inter-layer insulation film (mainly composed of silicon) after activation, in order to protect the gate electrode and the lead and the like.

另外,在含3~100?4氢的气氛中在300〜4501C下热处理1-12小时来对岛状半导体层进行氯化.这个过程是用热激活的氪使岛状半导体层中的悬键饱和。 In addition, containing 3 to 100? 4 hydrogen atmosphere in 300~4501C heat treatment for 12 hours to conduct chlorination island semiconductor layer. This process is thermally activated so that the island-like semiconductor layers krypton dangling bonds saturation. 也可用等离子氢化(用等离子体激活的氢)作为另一种氢化手段。 It may also be plasma hydrogenation (hydrogen excited by plasma) as another means of hydrogenation.

下一步,用厚为100 - 200 n迈的氮氧化硅膜制成第一层间绝缘膜344。 Next, with a thickness of 100 - 200 n silicon oxynitride film made of a first step of the interlayer insulating film 344. 然后在第一层间绝缘膜344上用有机绝缘材料制成第二层间绝缘膜345。 Then on the first interlayer insulating film 344 is formed a second interlayer insulating film 345 with an organic insulating material.

然后在电容引线323上面的第二层间绝缘膜345中开接触孔,露出一部分第一层间绝缘膜344.制作中间引线346,它经过电容引线323 上面的接触孔与第一层间绝缘膜344接触(见困4D)。 Then open the contact hole above the capacitor wiring 323 of the second interlayer insulating film 345, the exposed portion of the first interlayer insulating film 344. The wiring 346 made in the middle, which leads via a capacitor contact hole 323 above the first interlayer insulating film 344 contacts (see sleepy 4D).

下一步,在第二层间绝缘膜345上由有机绝缘材料制成第三层间绝缘膜347。 Next, the second interlayer insulating film 345 made of an organic insulating material between the third interlayer insulating film 347 formed.

然后在第二形状栅绝缘膜305b、第一层间绝缘膜344和第二层间绝缘膜345中开接触孔,并制成源极线348 ~ 350,使之经接触孔与源区360、 333、和334接触。 Then in the second shape gate insulating film 305b, a first interlayer insulating film 344 and the second interlayer insulating film in the contact holes 345, and the source lines 348 formed to 350, so that the source region through a contact hole 360, 333, and 334 contacts. 此外,同时制成与漏区361、 336接触的漏极引线351 (见图5A)。 In addition, while the drain wiring made of the drain region 361, 336 of the contact 351 (see FIG. 5A). 漏极线352将漏区337与中间引线346连起来。 Drain line 352 to the drain region 337 and the intermediate lead 346 connected together.

注意,当第二形状栅绝缘膜305b、第一层间绝缘膜344、第二层间绝缘膜345和第三层间绝缘膜347为Si(h膜或SiON膜时,最好用Ch和(L进行干法腐蚀来开接触孔。而当第二形状栅绝缘膜305b、第一层间绝缘膜344、第二层间绝缘膜345和第三层间绝缘膜347为有机树脂膜时,开接触孔最好用CHF3或BHF (緩冲氟化氢,HF+NILF)进行干法腐蚀。此外,若第二形状栅绝缘膜305b、第一层间绝缘膜344、 第二层间绝缘膜345和第三层间绝缘膜347由不同的材料制成时,最好对每种膜改变腐蚀方法和腐蚀剂或腐蚀气体的类型。然而,也可用同样的腐蚀方法和同样的腐蚀剂或腐蚀气体来开接触孔。 Note that when the shape of the second inter-gate insulating film 305b, a first interlayer insulating film 344, the second interlayer insulation film 345 and the third interlayer insulating film 347 is Si (h film or SiON film, preferably with Ch and ( L dry etching to form the contact holes between the second shape when the gate insulating film 305b, a first interlayer insulating film 344, the second interlayer insulation film 345 and the third interlayer insulating film 347 is an organic resin film, opening the contact hole is preferably (buffered hydrogen fluoride, HF + NILF) CHF3 or by BHF dry etching. Further, when the second shape gate insulating film 305b, a first interlayer insulating film 344, the second interlayer insulating film 345 and the second three-layer insulating film 347 is made of a different material, preferably changing the type etching method and etchant or etching gas for each film. However, it can also be the same etching method and the same etchant or etching gas to form the contact hole .

在第一层间绝缘膜344介于电容引线323和中间引线346之间并与它们接触的部分,形成了储能电容。 In a first interlayer insulating film 344 interposed therebetween and in contact with the capacitor wiring 323 and the intermediate lead portion 346, a storage capacitor is formed.

下一步,由有机树脂制成笫四层间绝缘膜353。 Next, an organic resin insulating film 353 between the undertaking of four. 有机树脂如聚酰亚胺、聚酰胺、丙烯酸类树脂和BCB(环笨丁烯)都可使用。 Organic resins such as polyimide, polyamide, acrylic resin, and BCB (ring stupid butene) can be used. 尤其是最好使用具有优越平滑性的丙蜂酸类树脂,因为形成第四层间绝缘膜353 主要是为了补偿表面的平整度.在实施方案1中制成的丙烯酸类树脂膜,其厚度可充分填平tft形成的台阶。 Particularly preferable to use a resin having excellent propionic acid bee smoothness, because the formation of the fourth inter-layer insulating film 353 is primarily to compensate for the flatness of the surface of the acrylic resin film prepared in Embodiment 1, the thickness can be fully formed tft filled stairs. 膜的厚度最好在1 - 5 mm( 2 ~ 4 nm间更好)。 The thickness of the film is in the 1 - 5 mm (between 2 ~ 4 nm better).

下一步,在第四层间绝缘膜353中制作达到中间引线352的接触孔,并制成像素电极354,在实施方案1中制成110 nm厚的氧化铟锡(IT0)膜,然后刻图形,制成像素电极354,此外,也可使用2-20X 氧化锌与氧化铟的混合物作为透明导电膜。 Next, in the fourth interlayer insulating film 353 produced in the contact hole to reach the intermediate lead wire 352, and the pixel electrode 354 formed to prepare a 110 nm thick in embodiment 1 of the indium tin oxide (IT0) film, then patterning , the pixel electrode 354 made of, in addition, can also be used a mixture of zinc oxide and indium oxide 2-20X as the transparent conductive film. 像素电极354就成为液晶盒的像素电极(见图5B), The pixel electrode 354 of the liquid crystal cell becomes a pixel electrode (see FIG. 5B),

下一步,在图5B状态下的有源矩阵衬底上制作取向膜355,如图6 所示。 Next, make an alignment film 355 on the active matrix substrate of FIG. 5B state, as shown in Figure 6. 聚酰亚胺树脂通常用作液晶显示元件的取向膜。 Polyimide resin generally used as a liquid crystal display element alignment film. 制作取向膜后, 进行擦除处理,使液晶分子具有固定的预倾角。 After alignment film production, erasing processing, the liquid crystal molecules with a fixed pretilt angle. 而且,虽然图6未示出,可在对衬底(opposing substrate)与有源矩阵衬底间设置间隔。 Furthermore, although not shown in FIG. 6, in the substrate (opposing substrate) and set the interval between the active matrix substrate.

另一方面,在对衬底356的背面制作对电极357和取向膜358。 On the other hand, in the production of the back electrode 357 of the substrate 356 and an alignment film 358. 虽然图6未示出,对衬底356也可有屏蔽膜。 Although not shown in Figure 6, the substrate 356 may also have a shielding film. 在此情形下,厚为150 - 300 nm的屏蔽膜可由Ti膜、Cr膜或Al膜制成.然后用密封剂(图中未示出)将形成有像素部分和驱动电路的有源矩阵衬底与对衬底连接起来。 In this case, a thickness of 150 - 300 nm shielding film may be formed of a Ti film, Cr film or an Al film is formed and then the sealing agent (not shown) is formed with a pixel portion and the driver circuit of an active matrix substrate. end and connected to the substrate. 将填充剂(图中未示出)混入密封剂,两个衬底间按照填充剂(或间隔,视情况而定)保持一均匀的间隙。 The filler (not shown) into a sealant between the two substrates in accordance with the filler (or gap, as the case may be) to maintain a uniform gap. 然后在两个衬底间注入液晶材料359。 A liquid crystal material 359 is then injected between the two substrates. 可以使用已知的液晶材料。 You can use the known liquid crystal material. 例如,除了TN液晶外,可使用具有光电响应特性的无阈值反铁电混合液晶,其透射率随电场连续改变。 For example, in addition to the TN liquid crystal, the photoelectric response characteristics can be used without a threshold anti-ferroelectric blended liquid crystal, the transmittance continuously changes with the electric field. 也有一些无阈值反铁电混合液晶呈V型光电响应特性。 There are also some non-threshold anti-ferroelectric mixed liquid crystal in a V-type photoelectric response characteristics. 这样,就完成了图6所示的有源矩阵液晶显示器件. This completes the active matrix liquid crystal display device shown in Figure 6.

在实施方案1中,源区404、漏区405、 Loff区406、 Lov区407、 沟道形成区408、以及中间区409都包含在像素tft 401的半导体层中。 In Embodiment 1, a source region 404, drain region 405, Loff region 406, Lov region 407, a channel forming region 408, and 409 are included in the intermediate region of the semiconductor layer 401 of the pixel in tft. 形成Loff区406,使之不经过第二形状栅绝缘膜305b与栅电极318重叠。 Loff region 406 is formed so as not to pass the second shape gate insulating film 318 overlaps with the gate electrode 305b. 而是形成Lov 407区使之经过第二形状栅绝缘膜305b与栅电极318重叠。 But the formation of Lov 407 area make it through the second shape gate insulating film 305b overlaps with the gate electrode 318. 这种结构对降低因热栽流子效应引起的关态电流是极其有效的。 This structure reduces the off current carriers due to thermal effects caused by plant is extremely effective.

此外,在实施方案1中像素tft 401使用双栅结构,但在本发明中像素TFT也可使用单栅结构或多栅结构。 Further, in Embodiment 1 pixel tft 401 using a double gate structure, but in the present invention, the pixel TFT may also be used a single gate structure or a multi-gate structure. 两个双栅结构的TFT可以 Two dual-gate structure TFT can

有效地串联起来,从而进一步降低关态电流。 Effectively together, thus further reducing the off current.

此外,在实施方案1中像素TFT 401为n沟道TFT,但也可使用p 沟道TFT。 Further, in Embodiment 1 pixel TFT 401 is an n-channel TFT, it is also possible to use p-channel TFT.

注意,实施方案1的有源矩阵衬底,因在像素部分和驱动电路部分都安排有优选结构的TFT,所以表现出极高的可靠性,性能也有改善。 Note that the embodiment of the active matrix substrate 1, due to the pixel portion and the driver circuit portion arrangements are preferred structure of TFT, so showing a high reliability, performance also improved.

首先,构成驱动电路的CMOS电路所用的n沟道TFT 403,具有减少热载流子注入而又不降低工作速度的结构,注意,这里所谓的驱动电路包含这样一些电路,如移位寄存器、緩冲器、电平移相器(level shifter)、以及取样电路(取样和保持电路)。 First, a CMOS circuit forming a driving circuit used in the n-channel TFT 403, a reduced hot carrier injection without decreasing the operation speed of the structure, attention, where the so-called drive circuit comprises a number of such circuits such as a shift register, buffer Chong, a level shifter (level shifter), and a sampling circuit (sample and hold circuit). 在进行数字驱动时, 也可包括信号转换电路,如D/A转换电路. When performing digital driving, a signal conversion circuit may also comprise, as D / A conversion circuit.

在实施方案1中,CMOS电路的n沟道TFT 403 (驱动电路n沟道TFT)的半导体层包含源区421、漏区422、 Lov区423和沟道形成区424。 In Embodiment 1, CMOS circuit n-channel TFT 403 (n-channel driving circuit TFT) semiconductor layer including a source region 421, drain region 422, Lov region 423 and a channel forming region 424.

驱动电路p沟道TFT 402的半导体层包含源区410、漏区411、 Lov 区412和沟道形成区413.形成Lov区412,使之经第二形状栅绝缘膜305b而与栅电极320重叠.注意,在实施方案1中驱动电路p沟道TFT 402没有Loff区,但也可使用有Loff区的结构。 A driving circuit p-channel TFT semiconductor layer 402 comprises a source region 410, drain region 411, Lov region 412 and a channel forming region 413. The Lov region 412 is formed, so that by the second shape gate insulating film 305b which overlaps with the gate electrode 320 Note that, in Embodiment 1 driving circuit p-channel TFT 402 does not Loff region, but there may also be used Loff region structure.

本发明沟道纵向的栅电极长度(此后简称为栅电极宽度)是不同的。 The gate electrode of the present invention, the length of the longitudinal channel (hereinafter referred to simply as gate electrode width) differ. 因此,在用栅电极作掩模进行离子注入时,利用因栅电极厚度不同而引起的离子透入深度不同,可使第一栅电极下面半导体层中的离子浓度低于未安排在第一栅电极下面半导体层中的离子浓度。 Therefore, when using the gate electrode as a mask by ion implantation using the gate electrode thickness varies ions caused by different penetration depth, can first semiconductor layer below the gate electrode lower than the ion concentration in the first gate is not arranged electrode below the ion concentration in the semiconductor layer.

此外,Loff区是用掩模来形成的,因此只须用腐蚀来控制第一栅电极和第二栅电极的宽度。 Further, Loff region is formed using a mask, and therefore only be controlled by etching the gate width of the first electrode and the second gate electrode. 与常规的实例相比,控制Loff区和Lov区的位置变得容易了。 Compared with the conventional examples, to control the position Loff region and Lov region becomes easy. 因此,Lov区和Loff区的精确定位和制作具有所需特性的TFT也就变得容易了, Thus, precise positioning and making Lov region and the Loff region TFT having desired characteristics will become easy,

此外,在常规实例中必须腐蚀栅绝缘膜和第一层间绝缘膜来开接触孔,以制作连接像素TFT漏区的漏极引线,因此难于由漏极引线、电 Further, in the conventional example need etching the gate insulating film and the first interlayer insulating film to form the contact hole, is connected to the drain wiring made of the pixel TFT drain region, it is difficult by the drain wiring, electrical

容引线和第一层间绝缘膜来形成储能电容。 Lead and the first interlayer insulating film formed by the storage capacitor capacitance. 然而,本发明是在第二层间绝缘膜和第三层间绝缘膜间新制作中间引线,因此,可由连接像素TFT漏极引线的中间引线352、第一层间绝缘膜344、以及同时制成的 However, the present invention is between the second interlayer insulating film and the third interlayer insulating film newly produced intermediate lead, therefore, may be connected to the drain of the pixel TFT intermediate lead wire 352, a first interlayer insulating film 344, and at the same time the system into

作为栅极信号线的电容引线323形成储能电容。 As the gate signal line capacitance wire 323 form the storage capacitor.

注意,虽然在实施方案1中说明的是透射型液晶显示器件,本发明 Note that, although in the first embodiment described is a transmission type liquid crystal display device of the present invention

不限于此,也可制作反射型液晶显示器件.此外,在实施方案1中说 Not limited thereto, can be made reflective liquid crystal display device. Further, in the embodiment 1, said

明的是像素TFT使用n沟道TFT的情形,但本发明不限于此,也可使用p沟道TFT作为像素TFT。 Invention is the use of a pixel TFT of an n-channel TFT situation, but the present invention is not limited thereto, the p-channel TFT may also be used as a pixel TFT.

而且,在实施方案1中说明的是,在像素TFT中Lov区和Lof f区二者都形成的情形,但也可使用像素TFT只有Lov区的结构。 Further, in the embodiment 1 is explained in the case of the pixel TFT, the Lov region and Lof f formed in both regions, but the structure of a pixel TFT may use only the Lov region. 此外、 在实施方案1中说明了在驱动电路TFT中只形成Lov区的结构,但也可使用在驱动电路TFT中Lov区和Loff区二者都形成的结构。 Further, in the embodiment 1 is illustrated in the driver circuit TFT, the Lov region is formed only of the structure, but the structure may be used in the driver circuit TFT, the Lov region and the Loff region both formed.

[实施方案2] [Embodiment 2]

在实施方案2中说明了本发明液晶显示器件像素部分的上表面图。 In embodiments 2 illustrates a top view of a liquid crystal display pixel portion of the present invention.

实施方案2的液晶显示器件的上表面图示于图7A。 The illustrated embodiment, the upper surface of the liquid crystal display device 2 in FIG 7A. 而实施方案2 的液晶显示器件像素部分的电路图示于图7B.参考数字501代表源极信号线,而参考数字502代表栅极信号线.在源极信号线501上制成的引线503是电容引线,它与源极信号线501重叠。 The circuit illustrated embodiment, the liquid crystal display element of the pixel portion 2 in Figure 7B. Reference numeral 501 denotes a source signal line, and reference numeral 502 denotes a gate signal line on the source signal line 501 is made of lead 503 capacitor wiring, which overlaps with the source signal line 501.

参考数字504代表像素TFT,像素TFT具有半导体层505。 Reference numeral 504 denotes a pixel TFT, a pixel TFT having a semiconductor layer 505. 在半导体层505上形成的那部分栅极信号线502作为栅电极。 That portion of the gate signal line 505 is formed on the semiconductor layer 502 as the gate electrode. 半导体层505 的源区和漏区之一与源极信号线501相连,而源区和漏区的另一个利用漏极线510与中间引线511相连。 One of the source region of the semiconductor layer and the drain region 505 and the source signal line 501 is connected to the other of the source and drain regions 510 and the drain line utilizing intermediate lead 511 is connected. 由参考数字512代表的那部分电容引线503连接至第一层间绝缘膜(图中未示出),而电容引线503、 第一层间绝缘膜和中间引线511在参考数字512代表的那部分则形成储能电容。 That part of the capacitance wiring 503 represented by reference numeral 512 is connected to the first interlayer insulating film (not shown), and the capacitor wiring 503, a first interlayer insulating film and an intermediate lead wire 511 at reference numeral 512 the portion represented by storage capacitor is formed.

漏极引线510与像素电极509相连, Drain wiring 510 and the pixel electrode 509 is connected,

注意,可将实施方案2与实施方案1任意地结合起来。 Note that you can Embodiment 2 Embodiment 1 arbitrarily combined.

[实施方案3] [Embodiment 3]

除了由电容引线、第一层间绝缘膜和中间引线形成储能电容的结构外,实施方案3表示由电容引线、栅绝缘膜和半导体层形成储能电容的实例。 In addition to the structure of the capacitor wiring, a first interlayer insulating film and the intermediate energy storage capacitor wiring is formed, Embodiment 3 shows an example of the wiring capacitance, the gate insulating film and the semiconductor layer of the storage capacitor. 注意,使用了与在困3A〜6所示部分相同的参考符号。 Note that using the parts shown with the same reference symbols 3A~6 sleepy.

图8表示实施方案3的液晶显示器件的剖面图。 Figure 8 shows the embodiment of a sectional view of a liquid crystal display device 3. 实施方案3的液晶显示器件不同于图5B所示者,它具有半导体层600。 A liquid crystal display device of embodiment 3 differs from that shown in Figure 5B, which has a semiconductor layer 600. 其他结构已在实施方案l中作了说明,因此,关于实施方案3的液晶显示器件的详细结构可参见实施方案l,这里从略。 Other structures have been described in the embodiments l, and therefore, the detailed structure of the liquid crystal display device with respect to embodiment 3 of the embodiment can be found in l, omitted here.

半导体层600与第一电容引线323a和第二电容引线323b重叠, The semiconductor layer 600 and the first capacitor lead wire 323a and 323b overlaps the second capacitor,

第二形状栅绝缘膜305b夹于其间。 A second shape gate insulating film 305b interposed therebetween. 半导体层600具有沟道形成区603、 与沟道形成区603边缘部分接触的第一杂质区602以及与第一杂质区602接触的第二杂质区601.第一杂质区602中的杂质浓度低于第二杂质区601中的杂质浓度。 The semiconductor layer 600 has a channel forming region 603, a second impurity region of low impurity concentration of the first impurity region in contact with the channel forming region 603 and the edge portion 602 of the contact 602 and the first impurity region 601. The impurity region 602 of the first impurity concentration of the second impurity region 601. 此外,第一杂质区602与第一电容引线323a 重叠,第二形状栅绝缘膜305b夹于其间。 Further, the first impurity region 602 overlaps with the first capacitor wiring 323a, a second shape gate insulating film 305b interposed therebetween.

注意,在电容引线323上总是施加一个电压从而在半导体层600 的沟道形成区603中形成沟道。 Note, the capacitor wiring 323, a voltage is always applied so as to form a channel in the channel forming region 603 of the semiconductor layer 600 in.

中间引线346由漏极线352与像素TFT 201的漏区405相连。 Intermediate lead 346 are connected by a drain line 352 and the drain region of the pixel TFT 201 405. 而中间引线346经笫二层间绝缘膜345中开的接触孔与第二电容引线323b上的第一层间绝缘膜344接触。 The first interlayer insulating film 344 contacts the intermediate lead 346 through the second interlayer insulating film 345 between the sleeping mat in the opening of the contact hole 323b on the second capacitor lead.

按照实施方案3的结构储能电容的电容值可增大.注意,如杲储能电容的表面积增大,由于孔径比下降,液晶显示器件的亮度减弱。 According to an embodiment of the structure of the storage capacitance value of the capacitor 3 can be increased. Note that as the surface area of Gao storage capacitor increases, due to the decline in the aperture ratio, brightness of the LCD display device weakened. 然而,用实施方案3的结构,由电容引线323、第二形状栅绝缘膜305b 和半导体层600形成的储能电容与由中间引线346、第一层间绝缘膜344和电容引线323形成的储能电容相重叠,因此储能电容的电容值可升高而没有降低孔径比。 However, with the structure of Embodiment 3, the capacitor wiring 323, the second storage capacitor and the gate insulating film 305b and the semiconductor layer 600 is formed by the intermediate lead wire 346 with the reservoir, a first interlayer insulating film 344 and the capacitance wiring 323 is formed You can overlap capacitance, and therefore the capacitance value of the storage capacitor can be raised without lowering the aperture ratio.

注意,虽然在实施方案3中说明的实例是像素TFT为n沟道TFT, 但本发明不限于此,也可使用p沟道TFT作为像素TFT。 Note that, although in the example described in Embodiment 3 is the pixel TFT is an n-channel TFT, but the present invention is not limited thereto, the p-channel TFT may also be used as a pixel TFT.

注意,可与实施方案1或2结合作为对实施方案3的补充。 Note that can be combined with Embodiment 1 or 2 as a complement to the implementation of the program 3.

[实施方案4] [Embodiment 4]

实施方案4中说明了同时形成电源线和屏蔽膜(黑矩阵)的实例。 Embodiment 4 illustrates an example of forming power line and simultaneously shielding film (black matrix). 注意,使用了与图3A-6所示部分相同的参考符号。 Note that, with the use of the part shown in FIG. 3A-6 the same reference symbols.

图9表示实施方案4的液晶显示器件的剖面图.实施方案4的液晶显示器件不同于图5B所示者,它具有屏蔽膜701。 Figure 9 shows a cross-sectional view of an embodiment of the liquid crystal display device 4. The liquid crystal display device of embodiment 4 differs from that shown in Figure 5B, having a shielding film 701. 注意,其他结构已在实施方案1中作了说明。 Note that other structures have been described in Embodiment 1. 因此,实施方案4的液晶显示器件的详细结构可参见实施方案l,这里从略。 Accordingly, the detailed structure of the liquid crystal display device of embodiment 4 can be found in embodiments l, omitted here.

中间引线346经过在第二层间绝缘膜345中开的接触孔与在第二电容引线323b上的第一层间绝缘膜344接触。 The intermediate wiring 346 through the second interlayer insulating film 345 to open a contact hole 344 of the first interlayer insulating film in contact with on the second capacitor wiring 323b.

在第二层间绝缘膜345上与中间引线346同时形成屏蔽膜701。 On the second interlayer insulating film 345 is formed simultaneously with the intermediate lead shielding film 346 701. 形成屏蔽膜701可防止因液晶显示器件外部的光射入像素TFT的沟道形成区而引起关态电流的增大。 Forming a shielding film 701 can be prevented because the channel formation region of the liquid crystal display device of externally incident light caused by pixel TFT off current increases.

此外,可与中间引线346同时形成实施方案4的屏蔽膜701,因此, Further, the intermediate lead wire 346 can be formed simultaneously with the embodiment 4 of the shielding film 701, and therefore,

无需增加工序数。 Without increasing the number of steps.

注意,在实施方案4中很重要的是,屏蔽膜701和中间引线346 都是由不易透光的材料制成的。 Note that, in embodiment 4 it is important that the shielding film 701 and the intermediate lead wire 346 is made of light-transmissive material is not easy.

虽然在实施方案4中说明的是像素TFT为n沟道TFT的实例,本发明不限于此,p沟道TFT也可用作像素TFT。 Although described in Embodiment 4 is an n-channel TFT pixel TFT instance, the present invention is not limited thereto, p-channel TFT may be used as the pixel TFT. 此外,屏蔽膜只形成在像素TFT的沟道形成区408上,但本发明不限于此,屏蔽膜也可形成在驱动电路TFT的沟道形成区上。 In addition, the shielding film is formed only in the pixel TFT is formed on the channel region 408, but the present invention is not limited thereto, the shielding film may be formed on the driver circuit TFT formed on the channel region.

注意,可与实施方案l-3的任一个相结合来作为对实施方案4的补充。 Note that, with the implementation of the program l-3 combination of any of the implementation of the program as a supplement 4.

[实施方案5] [Embodiment 5]

实施方案5说明了一个不同于实施方案1的实例,这是在笫二形状栅绝缘膜305b、第一层间绝缘膜344、第二层间绝缘膜345和第三层间绝缘膜347中开接触孔来制作源极引线和漏极引线。 5 illustrates an embodiment different from the embodiment of Example 1, which is in the second shape gate insulating film Zi 305b, between the first interlayer insulating film 344, the second interlayer insulating film 345 and the third interlayer insulating film 347 in the open contact holes to make the source wiring and a drain wiring. 注意,所用的参考符号与图3A ~ 6所示者相同, Note that, as shown by 3A ~ 6 used the same reference symbols in Fig,

图IO表示实施方案5的液晶显示器件的剖面图。 Figure IO shows embodiment of a sectional view of a liquid crystal display device 5. 实施方案5的液晶显示器件与图5B所示者不同之处在于其接触孔的结构。 Embodiment 5 of the liquid crystal display device of FIG. 5B differs from that shown in the contact hole in its structure. 注意,在实施方案1中已阐述了除接触孔以外的一些结构,因此关于实施方案5 的液晶显示器件的详细结构可参考实施方案1,这里从略。 Note that, in Embodiment 1 has been described in some structures other than the contact hole, and therefore a detailed embodiment of the structure on the liquid crystal display device 5 of Embodiment 1 can be referred to, is omitted here.

在实施方案5中,为制作中间引线346而在第二层间绝缘膜345 中开接触孔的同时,以及在制作中间引线346之前,在第二层间绝缘膜345中用来制作源极线348 ~ 350和漏极线351与352的接触孔。 In Embodiment 5, for the production of intermediate lead 346 and the contact hole in the second interlayer insulating film 345 at the same time, and before the production of the intermediate wiring 346, the second interlayer insulating film 345 for forming the source line 348 to 350 and the drain line contact holes 351 and 352. 此时,接触孔不开在第一层间绝缘膜344和第二形状栅绝缘膜305b中。 At this time, the contact hole is not opened in the first interlayer insulating film 344 and the second shape gate insulating film 305b in.

接着,在制成中间引线346后,制作第三层间绝缘膜347。 Subsequently, after the formed intermediate lead 346, making the third interlayer insulating film 347. 然后在第三层间绝缘膜3W、第一层间绝缘膜344、以及第二形状栅绝缘膜305b中开接触孔,制作源极引线348 ~ 350和漏极引线351与352,使与源区410、 422和404、漏区411、 421和405、以及漏极引线346 相连。 Then the third interlayer insulating film 3W, a first interlayer insulating film 344, and a second shape gate insulating film 305b in the contact holes, source wirings 348 made to 350 and drain wirings 351 and 352, so that the source region 410, 422 and 404, a drain region 411, 421 and 405, and a drain connected to lead 346.

用上述实施方案5的结构可制作用于与源区410、 422和404以及漏区411、 421和405连接的接触孔而无须腐蚀第二层间绝缘膜345, 且腐蚀也简单化了。 Using the above-described embodiments of structure 5 can be made to the source region 410, drain regions 422 and 404, and 411, 421 and 405 connected to the contact hole without etching the second interlayer insulating film 345, and the etching is also simplified.

注意,在实施方案5中说明的是用n沟道TFT作为像素TFT的情形,但本发明不限于此,也可使用p沟道TFT作为像素TFT。 Note that, in Embodiment 5 is explained in the case of an n-channel TFT as the pixel TFT, but the present invention is not limited thereto, the p-channel TFT may also be used as a pixel TFT. 注意,实施方案5可与实施方案1〜4中的任一个相结合。 Note that Embodiment 5 can be combined with one embodiment of any of ~ 4. [实施方案6] [Embodiment 6]

实施方案6说明了衬底和在TFT的半导体层之间形成光屏蔽膜的实例。 6 illustrates an embodiment of the substrate between the semiconductor layer and examples TFT light shielding film. 注意,使用了与图3A〜6所示部分同样的符号。 Note that using the same symbols and parts shown 3A~6 map.

图11表示实施方案6的液晶显示器件的剖面图。 Figure 11 shows a sectional view of the liquid crystal display device of the embodiment of Figure 6. 实施方案6的液晶显示器件与图5B所示者的区别在于它具有屏蔽膜801。 Embodiment 6 of the liquid crystal display device with those shown in FIG. 5B difference that it has a shielding film 801. 注意,其他结构已在实施方案1中作了说明。 Note that other structures have been described in Embodiment 1. 因此,关于实施方案6的液晶显示器件的详细结构可参考实施方案1,这里从略。 Accordingly, the detailed structure of the liquid crystal display device on the implementation of the program 6 may refer to Embodiment 1, is omitted here.

在实施方案6的液晶显示器件中,屏蔽膜801形成在像素TFT的半导体层304下面。 In an embodiment of the liquid crystal display device 6, the shielding film 801 is formed on the semiconductor layer 304 below the pixel TFT. 屏蔽膜801与像素TFT的半导体层304的沟道形成区408重叠,绝缘膜(在实施方案6中为氧化物膜)803夹于其间。 Shielding film 801 and the pixel TFT 304 formed on a channel region of the semiconductor layer 408 overlaps the insulating film (in Embodiment 6 as an oxide film) 803 sandwiched therebetween.

屏蔽膜801可屏蔽光,它可使用任何材料,只要其材料能耐受形成屏蔽膜后各个热处理工艺步骤的温度。 Shielding film 801 may shield light, it can use any material, as long as the temperature of the material forming the shielding film can withstand various heat treatment process steps. 可以使用不易透光的材料,如金属和硅,实施方案6中用的是W。 You can use the easy opaque materials such as metal and silicon is used in Embodiment 6 W. 注意,屏蔽膜801的厚度最好为0. i〜0.5iim的量级。 Note that the thickness of the shielding film 801 is preferably 0. i~0.5iim the order. 而氧化膜803的厚度最好为0. 5〜L5 Pm的量级。 The thickness of the oxide film 803 is preferably of the order of 0. 5~L5 Pm. 此外,屏蔽膜801与半导体层304间的距离最好为0. l〜 0.5um的量级。 In addition, the shielding film 801 and the semiconductor layer 304 is preferably 0. l~ 0.5um distance of the order.

注意,在实施方案6中虽然屏蔽膜只形成在像素部分的像素TFT 半导体层304下面,但实施方案6不限于这种结构。 Note that, although in embodiments shielding film 6 is formed only in the pixel TFT of the pixel portion below the semiconductor layer 304, but the embodiment is not limited to this structure 6. 屏蔽膜也可同样形成在驱动电路TFT的半导体层302和303下面。 Shielding film may be similarly formed in the semiconductor layer 302 and the driver circuit TFT 303 below.

按照上述的实施方案6的结构可防止光由衬底下侧照到沟道形成区而引起TFT关态电流升高。 According to the above embodiment of the structure 6 prevents the light caused by TFT off current is increased from the substrate side to shine under the channel forming region.

如果氧化膜803没有平整的表面,就会发生问题,在氧化膜803 上面形成的半导体层在晶化过程中不能均匀地晶化。 If there is no smooth surface oxide film 803, the problem arises, the semiconductor layer formed over the oxide film 803 in the crystallization process can not be uniformly crystallized. 半导体层是直接制作在氧化膜803上的,因此,在形成半导体层之前最好先平整氧化膜803的表面。 The semiconductor layer is directly formed on the oxide film 803, and therefore, before forming the first semiconductor layer is preferably a flat surface 803 of the oxide film.

例如,氧化膜803可用CMP (化学机械抛光)抛平。 For example, the oxide film 803 is available CMP (chemical mechanical polishing) polishing flat. 可用已知的方法进行CMP抛光。 Using known methods CMP polishing.

在实施方案6中用硅凝胶和电解液的混合物进行抛光。 Electrolyte gel and a mixture of silicon embodiment 6 by polishing. 在用电解 Using electrolysis

液进行抛光时向抛光板施加100 kg/cm2的压力。 Pressure of 100 kg / cm2 is applied to the polishing pad during polishing liquid. 抛光时的压力可在 Pressure during polishing in

50〜150 kg/cm2的范围内选择。 Selected within the range of 50~150 kg / cm2 for. 此外,进行抛光时,抛光面与抛光板 In addition, when polishing, the polishing surface of the polishing pad

间留有0. lum的间隙。 A gap of between 0. lum.

按照上述结构可抑制TFT的关态电流和防止半导体层晶化的不均匀性。 According to the above structure can inhibit the TFT off-state current and prevent crystallization of the semiconductor layer uniformity.

虽然实施方案6说明的是用n沟道TFT作为像素TFT的情形,但本发明不限于此,也可使用p沟道TFT作为像素TFT。 Although Embodiment 6 is described in the case of an n-channel TFT as the pixel TFT, but the present invention is not limited thereto, the p-channel TFT may also be used as a pixel TFT.

注意,可与实施方案1-5中的任一个相结合作为对实施方案6的补充。 Note that the embodiments can be used with any combination of 1-5 as a supplement to the embodiment 6. [实施方案7] [Embodiment 7]

实施方案7说明了在制作源极信号线后再制作栅极信号线的实例。 Embodiment 7 illustrates the production of the gate signal line in the production of the source signal line after instance.

图12A表示实施方案7的液晶显示器件的上表面图,注意,图12B 是图12A沿AA,线剖开的剖面困.参考数字901代表源极信号线, 参考数字902代表栅极信号线.在栅极信号线902下形成的引线903 是中间引线,它与栅极信号线902重叠„ Figure 12A shows a top view of a liquid crystal display device of embodiment 7, note that FIG 12B is a view along 12A AA, cross-sectional view taken line trapped Reference numeral 901 denotes a source signal line, reference numeral 902 denotes a gate signal line. In the lead gate signal line 902 is formed in the intermediate wiring 903, which overlaps with the gate signal line 902 "

参考数字904代表像素TFT,它具有半导体层905。 Reference numeral 904 represents that the pixel TFT, which has a semiconductor layer 905. 在半导体层905 上制作与栅极信号线902相连的栅电极920,半导体层905的源区和漏区之一利用源极引线921与源极信号线901相连,源区和漏区的另一个利用漏极引线910与电容引线911相连。 On the semiconductor layer 905 with the source of the gate electrode production and 902 connected to the gate signal line 920, the semiconductor layer source region and a drain region 905 of the gate wiring 921 is connected to the source signal line 901, another source region and a drain region use the drain wiring 910 is connected to the capacitor wiring 911. 中间引线903由参考数字912所代表的部分与笫一层间绝缘膜923相连,而中间引线903、 第一层间绝缘膜923以及电容引线911则构成储能电容。 An intermediate portion between the lead 903 and connected by Zi layer represented by reference numeral 912 an insulating film 923, and the intermediate lead 903, a first interlayer insulating film 923 and a capacitor 911 constituting a lead storage capacitor.

漏极引线910与像素电极909相连。 Drain wiring 910 and the pixel electrode 909 is connected.

按照本发明,中间引线903形成在第二层间绝缘膜924与第三层间绝缘膜925之间。 According to the present invention, intermediate lead 903 is formed between the second interlayer insulation film 924 and the third interlayer insulating film 925. 这样,可使电源线与栅极信号线902重叠,因而可增大孔径比。 This allows the power supply line overlaps with the gate signal line 902, thus increasing the aperture ratio. [实施方案8] [Embodiment 8]

在实施方案8中说明的是用催化元素热晶化法制成的晶体半导体膜作为本发明的半导体层的实例.在使用催化元素时,最好采用曰本专利公开Hei 7-130652号和Hei 8-78329号所公开的技术。 In the embodiment 8 is described thermal crystallization using a catalytic element into the legal system as an example of a crystalline semiconductor film semiconductor layer of the present invention is in the use of a catalytic element, preferably said this Patent Publication No. Hei 7-130652 and Hei 8 -78,329 Number technique disclosed.

图13A和13B中所示的实例,是将日本专利公开Hei 7-130652号所公开的技术用于本发明。 The example shown in FIGS. 13A and 13B, is disclosed in Japanese Patent Publication No. Hei 7-130652 technique used in the present invention. 在衬底1201上先制成氧化硅膜1202,在其上制作无定形硅膜1203。 On a substrate made of a silicon oxide film is 1201 to 1202, in which the production of an amorphous silicon film 1203. 再用含镍重量为10ppm的醋酸镍溶液在其上形成含镍层1204 (见图13A)。 Then nickel 10ppm by weight of nickel acetate solution in which nickel-containing layer 1204 is formed (see FIG. 13A).

其次,在脱氢l小时后,在500 - 650lC下热处理4-12小时,例 Secondly, in the dehydrogenation l hours, in 500-- 650lC 4-12 hours under heat treatment, for example,

如550TC8小时,来形成晶体硅膜1205。 As 550TC8 hours to form a crystalline silicon film 1205. 这样得到的晶体硅膜1205具有极优越的结晶性(见图13B)。 Thus obtained crystalline silicon film 1205 has a very excellent crystallinity (Figure 13B).

再者,日本专利公开Hei 8-78329号所公开的技术能够用选择掺入催化元素来选择晶化无定形硅膜,图14A和14B,说明了将这一技术用于本发明的一种情形。 Further, Japanese Patent Publication No. Hei 8-78329 disclosed technology can be incorporated into a catalytic element with the Select to select the crystallization of amorphous silicon films 14A and 14B, illustrates a situation of this technology used in the present invention. .

先在玻璃衬底1301上形成氧化硅膜1302,然后在其上依次制成无定形硅膜1303和氧化硅膜1304。 1302 first silicon oxide film formed on a glass substrate 1301, and then turn into an amorphous silicon film and the silicon oxide film 1303 1304 thereon. 此时,氧化硅膜1304的厚度为150 nm。 In this case, the thickness of the silicon oxide film 1304 is 150 nm.

接着在氧化硅膜1304上刻图形来选择形成开孔1305,用含镍重量为10 ppm的醋酸镍溶液在其上制成含镍层1306,而含镍层1306只在开孔1305的底部与无定形硅膜1303接触(见图14A)。 Then engraved on the silicon oxide film 1304 to select the graphic form openings 1305, containing 10 ppm of nickel by weight of nickel acetate solution containing nickel layer formed thereon 1306, and nickel-containing layer 1306 and the bottom opening 1305 contacting the amorphous silicon film 1303 (see FIG. 14A).

然后在500 - 650"C下热处理4 ~ 24小时,例如570"C14小时,来形成晶体硅膜1307,在此晶化过程中,与镍接触的无定形硅膜部分首先被晶化,然后沿横向进行晶化。 Then at 500 - "Heat Treatment C for 4 to 24 hours, for example, 570" 650 C14 hours to form crystalline silicon film 1307, in this crystallization process, the amorphous silicon film portion in contact with the nickel is crystallized first, then along transverse crystallization. 这样形成的晶体硅膜1307是杆状和针状晶体的集合,其中的每个晶体宏观上都按特定的取向生长。 Crystalline silicon film 1307 thus formed is a collection of rod-like and needle-like crystals, wherein each of the crystals are grown in a specific orientation on a macro. 因此, 这种晶化过程具有调整结晶性的优点(见图14B)。 Thus, the crystallization process has the advantage of adjusting the crystallinity (Figure 14B).

注意,在上述的两项晶化技术中,除镍(Ni)外,下列元素也可用作催化元素-.锗(Ge)、铁(Fe)、钯(Pd )、锡(Sn )、铅(Pb )、 钴(Co )、铂(Pt )、铜(Cu )和金(Au )。 Note that, in the above two crystallization techniques, in addition to nickel (Ni), the following elements are also used as the catalytic element - germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu) and gold (Au).

对由上述技术制作的晶体半导体膜(包括诸如晶体硅膜、晶体锗硅膜)刻图形可制成晶体TFT的半导体层。 Crystal semiconductor film produced by the technology (including films such as crystalline silicon, crystalline silicon germanium film) may be formed by patterning the semiconductor layer crystal TFT. 用实施方案8的技术制作晶体半导体膜而制成的TFT具有优良的特性,因而有很高的可靠性,然而,采用本发明的TFT结构,可最大限度地使用实施方案8的技术来制作TFT。 TFT technology to produce with embodiment 8 of the crystalline semiconductor film made of excellent properties, and thus has a high reliability, however, a TFT structure of the present invention, can be used to maximize the embodiment 8 to the production of TFT technology .

下面参照图15A和15B来说明一个实例,这是用实施方案1所用 Referring to Figures 15A and 15B illustrate an example of this embodiment is used a

的制作半导体层的方法,即以无定形半导体膜作为初始膜,用催化元素使之成为晶体半导体膜后,除去催化元素的工艺过程。 The method of fabricating a semiconductor layer, i.e., an amorphous semiconductor film as a starting film, using a catalytic element to become a crystalline semiconductor film, the process of removing the catalytic element. 在实施方案8 中用日本专利/^开Hei 10-135468号和日本专利乂>开Hei 10-135469 号所记载的技术作为这样的方法。 In Embodiment 8 by Japanese Patent / ^ open Hei No. 10-135468 and Japanese Patent qe> open Hei No. 10-135469 described the technology as such methods.

上述日本专利记栽的技术,是在晶化后利用裤的吸杂作用来除去无定形硅膜晶化所用的催化元素,使用这种技术,可使晶体半导体膜中催化元素的浓度降至1 x 10"原子/cm3或更低,优选地为lxio"原子 Japanese Patent remember planting techniques in use after crystallization pants gettering action to remove the catalytic element crystallization of amorphous silicon films used, the use of this technology will enable the concentration of the catalytic element in the crystalline semiconductor film is reduced to 1 x 10 "atoms / cm3 or less, preferably lxio" atom

/cm3或更低。 / Cm3 or less.

这里使用无硷玻璃衬底,典型地如Corning公司的#1737衬底。 As used herein, non-alkaline glass substrate, typically companies such as Corning # 1737 substrate. 用实施方案4所示的晶化技术制作基膜1402和晶体硅膜1403的情形示于图15A。 With the embodiment of the base film crystallization technology to produce crystalline silicon film 1402 and 1403 the situation shown in Figure 4 is shown in Figure 15A. 然后,在晶体硅膜1403的表面制成150 nm厚的氧化硅膜1404作为掩模,按照图形制作开孔,形成露出晶体硅膜的区域。 Then, the surface of the crystalline silicon film 1403 is made 150 nm-thick silicon oxide film 1404 as a mask, the opening made in accordance with the graphic, the region forming the crystalline silicon film is exposed. 接着掺磷,在晶体硅膜中形成掺鳞的区域1405。 Then phosphorus-doped to form a regional scale in 1405-doped crystalline silicon film.

在这种状况下,如果在550-800TC下的氮气氛中热处理5-24小时,例如600X:i2小时,在晶体硅中的掺裤区域1405则起吸杂中心的作用,使留在晶体硅膜1403中的催化元素分凝至掺磷区1405中。 In this situation, if the heat treatment under a nitrogen atmosphere 550-800TC in 5-24 hours, for example 600X: i2 hours, mixed with pants area of crystalline silicon in 1405 in the central role played gettering, remaining in the crystalline silicon 1403 film catalytic element to segregation of phosphorus-doped region in 1405.

腐蚀掉作掩模的氧化硅膜1404和掺磷区1405,可使晶体硅膜中因晶化过程所用的催化元素浓度降为1 x 10'7原子/^3或更低。 Etched silicon oxide film as a mask phosphorus-doped region 1404 and 1405, allows the crystalline silicon film due to the concentration of the catalytic element used for crystallization process is reduced to 1 x 10'7 atoms / ^ 3 or less. 这种晶体硅膜可用作本发明TFT的半导体层。 This film can be used as a semiconductor layer of crystalline silicon TFT of the present invention. [实施方案9] [Embodiment 9]

说明了本发明液晶显示器件的驱动方法.本发明液晶显示器件实例的框困示于图16。 Description of the method for driving a liquid crystal display device of the present invention. Frame liquid crystal display device of the present invention is an example of the storm is shown in Fig.

参考数字1601代表源极信号线驱动电路,参考数字1602代表栅极信号线驱动电路,而参考数字1603代表像素部分。 Reference numeral 1601 denotes a source signal line driver circuit, reference numeral 1602 denotes a gate signal line driver circuit, and reference numeral 1603 represents that the pixel portion. 在实施方案9中各形成一个源极信号线驱动电路和一个栅极信号线驱动电路,但本发明不限于这种结构。 In the embodiment 9 each form a source signal line driver circuit and a gate signal line driver circuit, but the present invention is not limited to this structure. 也可形成两个源极信号线驱动电路和两个栅极信号线驱动电路。 It may also be formed two source signal line driver circuit and two gate signal line driver circuit.

源极信号线驱动电路1601含有移位寄存器电路1601_1、电平移相电路1601-2和取样电路1601_3。 A source signal line driver circuit comprising a shift register circuit 1601_1 1601, a level shifter circuit and the sampling circuit 1601_3 1601-2. 注意,必要时可使用电平移相电路, 但不是必须使用。 Note that, if necessary, make electricity shifter circuit, but it is not necessarily used. 此外,在实施方案9中,电平移相电路1601 —2形成在移位寄存器1601-1与取样电路1601-3之间,但本发明不限于这种结构。 Further, in Embodiment 9, a level shifter circuit 1601-2 is formed between the shift register and the sampling circuit 1601-3 1601-1, but the present invention is not limited to this structure. 也可使用将电平移相电路1601-2包含在移位寄存器1601_1中的结构。 A level shifter circuit 1601-2 also be used in the shift register will contain the structure of 1601_1.

时钟信号CL和起始脉冲信号SP输入至移位寄存器电路1601_1。 CL clock signal and a start pulse signal SP input to the shift register circuit 1601_1. 对视频信号进行取样的取样信号由移位寄存器电路1601_1输出。 The video signal is sampled sampled signal output by the shift register circuit 1601_1. 输出的取样信号输入电平移相电路1601-2,使其电位的幅度增大而输出。 The output sample signal input level shifter circuit 1601-2, it increases the magnitude of potential output.

由电平移相电路1601 — 2输出的取样信号输入取样电路1601 —3。 From the level shifter circuit 1601--2 output sample signal input sampling circuit 1601-3. 与此同时,视频信号经視頻信号线(未示出)输入取样电路1601 — 3。 At the same time, the video signal by the video signal line (not shown) the input sampling circuit 1601--3.

输入的视频信号按照取样信号在取样电路1601 — 3中被取样,其结 The input video signal in accordance with the sampling signal sampling circuit 1601--3 is sampled, its knot

果经源极信号线1604输入预定的像素。 If the source signal line 1604 through a predetermined input pixel.

源极信号线1604与源极信号线驱动电路1601相连,而与栅极信号线驱动电路1602相连的栅极信号线1605贯穿像素部分1603。 The source signal line 1604 and the source signal line driver circuit 1601 is connected with the gate signal line driver circuit 1602 connected to the gate signal line 1605 through the pixel portion 1603. 像素1606的薄膜晶体管(像素TFT) 1607、液晶夹于对电极与像素电极之间的液晶盒1608、以及储能电容1609都形成在源极信号线1604和栅极信号线1605所包围的区域中。 The thin film transistor of the pixel 1606 (pixel TFT) 1607, a liquid crystal sandwiched between the counter electrode and the pixel electrode of the liquid crystal cell 1608, and a storage capacitor 1609 are formed in the region of the source signal line 1604 and the gate signal line surrounded 1605 .

像素TFT 1607是依照选通信号来工作的,选通信号是来自栅极信号线驱动电路1602经栅极信号线1605输入的。 Pixel TFT 1607 is in accordance with strobe to work, strobe driving circuit 1602 via a gate signal line from the input gate signal line 1605. 已被取样的视频信号输入至被像素TFT 1607选取的源极信号线1604,并同时写入预定的像素电极。 Has been sampled video signal input to the pixel TFT 1607 is the selected source signal line 1604, and at the same time writes a predetermined pixel electrode.

注意,虽然在实施方案9中源极信号线驱动电路1601和栅极信号线驱动电路1602都形成在制作了像素部分1603的衬底上,但本发明不限于此。 Note that, although in the embodiment 9 of the source signal line driver circuit 1601 and the gate signal line driver circuit 1602 are formed on the pixel portion 1603 made of a substrate, but the present invention is not limited thereto. 源极信号线驱动电路1601和栅极信号线驱动电路1602也可形成在IC芯片上,并经FPC或TAB与像素部分1603相连。 The source signal line driver circuit 1601 and the gate signal line driver circuit 1602 may be formed on an IC chip, and by the FPC or TAB is connected with the pixel portion 1603.

此外,驱动本发明液晶显示器件的方法不限于实施方案9所示的方法。 In addition, driving the liquid crystal display device of the present invention is not limited to the embodiment shown in Method 9.

可将实施方案1 ~ 8的任一个与实施方案9任意地结合。 It may be any one of the embodiments Embodiment 9 optionally combined 1-8. [实施方案10〗 [Embodiment 10〗

在实施方案1的一组腐蚀条件下进行第一腐蚀过程来形成第一形状导电层,但这一腐蚀过程也可在多组腐蚀条件下进行,以在膜的减 Carried out in the embodiment 1, a first set of etching conditions etching process to form the first shape conductive layers, but the corrosion process can also be carried out in the plurality of sets of etching conditions, to a reduction in film

薄和栅绝缘膜的形状方面提高均匀性,实施方案10表示在两组腐蚀条件下进行第一腐蚀过程来形成第一形状导电层的实例。 Shape of the gate insulating film is thin and improve the uniformity, showing a first embodiment 10 in the etching process to form two sets of etching conditions of the first instance of the shape of the conductive layer.

另外,按照本发明,导电层的两側都形成了锥度,LDD区形成在沟道形成区的两側。 Further, according to the present invention, the conductive layer is formed on both sides of the taper, LDD regions are formed on both sides of the channel forming region. 然而,实施方案10是按照图18A~ 18D中驱动电路的n沟道TFT导电层一側附近的放大图来对制作过程进行说明的。 However, according to the embodiment of FIG. 10 is a driving circuit 18A ~ 18D in the vicinity of the n-channel TFT enlarged view of the conductive layer side of the production process to be described. 注意,为简单起见,图中未示出基膜和衬底. Note that for simplicity, not shown in the base film and the substrate.

首先,按照实施方案l得到了与困3B相同的状态。 First, according to the embodiment l got trapped 3B and the same state. 然而,虽然在 However, although the

实施方案1中用Ta作为第一导电膜,但在实施方案10中用具有极高耐热特性的TaN作为第一导电膜。 Embodiment 1 with Ta as the first conductive film, but in the embodiment 10 with TaN having high heat resistance as the first conductive film. 制成的第一导电膜厚20~100 nm,而制成的第二导电膜厚度可为100~ 400 nm。 Made of the first conductive film thickness of 20 ~ 100 nm, while the thickness of the second conductive film may be made of 100 ~ 400 nm. 在实施方案10中, 厚为30nm的TaN第一导电膜与厚为370 nm的W第二导电膜形成叠层。 In Embodiment 10, the thickness of the TaN first conductive film 30nm thick W and the second conductive film 370 nm is formed laminate.

其次,由抗蚀剂形成第一形状掩模1505a,用ICP进行腐蚀,制成 Next, a first shape mask 1505a is formed by the resist, etching by ICP, made

第一形状第二导电膜1504a。 A first shape second conductive film 1504a. 这里用CF" CL和02的混合物作为腐蚀气体,它对TaN具有高选择性,因此得到了图1 8 A所示的状态。几种腐蚀条件及其与第二导电层(W)腐蚀速率、第一导电层(TaN)腐蚀速率以及第二导电层(W)锥角的关系示于表l。 Here with CF "mixture of CL and 02 as an etching gas, it TaN with high selectivity, thereby obtaining the state A shown in FIG. 18. Several corrosive conditions and with the second conductive layer (W) corrosion rate, relationship between the first conductive layer (TaN) and the second conductive layer, the corrosion rate (W) cone angle are shown in Table l.

[表l] W和TaN腐蚀速率(ER)及W锥角 [Table l] W and TaN corrosion rate (ER) and W taper angle

<table>table see original document page 43</column></row> <table> <Table> table see original document page 43 </ column> </ row> <table>

')表中"-"表示不能测量,因为w表面在腐蚀中被破坏了。 ') Table, "-" indicates not be measured, because w surface corrosion was destroyed.

注意,本说明书中的锥角表示材料层側面与水平面间的夹角,如图 Note that in this specification taper angle indicates the angle between the horizontal sides of the material layer, as shown in

18A右上图所示。 18A as shown above right. 而且为了方便起见,在本说明书中将有锥角的側面称为锥形,有锥形的部分称为锥形部分。 And for convenience, in this specification with side called cone angle tapered conical part is called a tapered portion.

而且,例如,使用表1的条件4~15中的一种作为第一组腐蚀条件,可将第二导电层(W)側面与水平面间形成的夹角(锥角otl )自由地定在19~70的范围内。 Also, for example, using the conditions of Table 1 is a 4 to 15 as the first set of etching conditions, a second conductive layer (W) angle (cone angle otl) formed between the side and the freedom to set the level at 19 within a range of 70 . 注意,腐蚀时间可由操作者适当地确定。 Note that the etching time is appropriately determined by the operator.

另外,在图1 8 A中参考数字1501代表半导体层,参考数字1502 代表栅绝缘膜,参考数字1503代表第一导电膜。 Further, reference numeral 1501 in FIG. Representative semiconductor layer 1 8 A, reference numeral 1502 denotes a gate insulating film, reference numeral 1503 denotes a first conductive film.

接着,保留掩模1505a,在第二组腐蚀条件下进行腐蚀,形成第一形状笫一导电层1503a,注意,在笫二组腐蚀条件下进行腐蚀时,栅绝缘膜1502也被腐蚀拌一些而成为第一形状栅绝缘膜1502a。 Then, leave the mask 1505a, the corrosion in the second set of etching conditions to form the shape of Zi a first conductive layer 1503a, note that in the undertaking of corrosion when two groups of etching conditions, the gate insulating film 1502 is also mixed with some, but corrosion becoming a first shape gate insulating film 1502a. 这里用CF, Here with CF,

和Ch的混合气体作为第二组腐蚀条件下的腐蚀气体。 Ch mixed gas as an etching gas at a second set of etching conditions. 例如,表l中条件1 ~3中的任一个都可用作第二组腐蚀条件.因此在两组腐蚀条件下进行第一腐蚀过程,就可抑制栅绝缘膜1502的减薄(见图18B)。 For example, any one of 1 to 3 in Table l in the conditions can be used as a second set of etching conditions. Therefore, a first etching process under two etching conditions, can suppress the thinning of the gate insulating film 1502 (see FIG. 18B ).

注意,在第二组腐蚀条件下进行腐蚀时,图18B中的第一形状第二导电层1504a也被腐蚀掉一些。 Note that when the etching under the second set of etching conditions, 18B of the first shape of the second conductive layer 1504a is also etched a number. 但腐烛量是微小的(约0. 15ym, 即总的线宽0. 3 Mm),因此图中所示者与图18A具有同样的形状。 But the amount is small candle rot (about 0. 15ym, i.e., the total width 0. 3 Mm), and thus those shown in FIG. 18A having the same shape in FIG.

下一步,保留掩模1505a进行第二腐蚀过程,得到图18C所示的第二形状导电层。 Next, a mask 1505a to retain the second etching process, FIG. 18C to obtain the second shape conducting layer shown in Fig. 实施方案10中的第二腐蚀过程,是在用CF" CL和O,的混合气体的那些腐蚀条件下进行腐蚀的。表1的条件4~ 15中的任一个都可用作这里的腐蚀条件,腐蚀时间可适当确定。而且,每个导电层沿沟道纵向的宽度可按照腐蚀条件自由地规定。第二形状 Under those conditions the corrosion corrosion embodiment 10 second etching process is used CF "CL and O, the mixed gas of 4 to 15 in any of the conditions shown in Table 1 can be used as a corrosion conditions here , the etching time may be appropriately determined. Further, each of the conductive layers along the longitudinal direction of the channel width can be freely predetermined according to the etching conditions. The second shape

掩模1505b、第二形状第一导电层1503b、第二形状第二导电层1504b以及第二形状栅绝缘膜1502b都由第二腐蚀过程来制成。 Mask 1505b, a second shape first conducting layer 1503b, a second shape second conducting layer 1504b and the second shape gate insulating film 1502b formed by the second etching procedure.

注意,在实施方案10中第二形状第一导电层1503b相应于第一栅电极,第二形状第二导电层1504b相应于第二栅电极。 Note that in the embodiment 10 of the second shape first conducting layer 1503b corresponds to the first gate electrode, the second shape second conducting layer 1504b corresponds to the second gate electrode.

在第二形状第二导电层1504b中形成的锥角a2大于锥角al,而在第二形状第一导电层1503b中形成了极小的锥角P 。 Taper angle a2 in the second shape second conducting layer 1504b formed larger than the taper angle al, whereas in the second shape first conducting layer 1503b is formed in a very small cone angle P.

接着,保留掩模1505b进行第一掺杂过程(见图1 8 C )。 Next, the mask 1505b reserved first doping process (see Figure 1 8 C). 这里用第二形状第二导电层1504b作掩模,用离子掺杂法向半导体层1501掺入n型导电杂质辨。 Here with the second shape second conducting layer 1504b as a mask, the semiconductor layer 1501 n-type conductivity impurity incorporation identified by an ion doping method. 此外,第一掺杂过程是在保留掩模1505b的状况下进行的,但也可在除去掩模1505b后进行第一掺杂过程。 In addition, the first doping process is retained in the status 1505b of the mask, but may also be carried out after removing the mask 1505b of the first doping process.

杂质区1501a和1501b是由第一掺杂过程形成的。 Impurity regions 1501a and 1501b are formed by the first doping process. 此外,半导体层与第二导电层重叠,栅绝缘膜和第一导电层夹于其间,半导体层的这部分则成为沟道形成区。 In addition, the semiconductor layer and the second conductive layer overlap, a gate insulating film and the first conductive layer is sandwiched therebetween, this portion of the semiconductor layer becomes the channel forming region. 注意,虽然围中未示出,杂质区1501a和1501b形成在沟道形成区的两側,而且是轴对称(linear symmtry ) 的。 Note that, although not shown in circumference, impurity regions 1501a and 1501b are formed on both sides of the channel forming region, and is axially symmetric (linear symmtry) of.

此外,在半导体层上安排的材料层的膜厚越厚,掺杂时掺杂离子的透入深度就越浅。 In addition, the film thickness of the material layer arranged on the semiconductor layer thicker dopant ions doping the penetration depth more shallow. 因此,与第一导电层重叠,栅绝缘膜夹于其间的杂质区1501a,亦即第一LDD区(Lov区)受側壁具有锥角P的锥形部分的影响,掺入半导体层的杂质浓度是变化的.膜越厚,杂质浓度越低, 膜越薄,杂质浓度越高。 Thus, overlaps with the first conductive layer, a gate insulating film interposed therebetween impurity regions 1501a, i.e., a first LDD region (Lov region) on the side walls having a taper angle of the tapered portion of the subject P, the incorporation of the impurity concentration of the semiconductor layer is varied. thicker film, the lower the impurity concentration, the thinner the film, the higher the impurity concentration.

此外,在进行第二腐蚀过程时,依照腐蚀条件,也可以有这样的情 In addition, during the second etching process, according to the etching conditions, you can have such a situation

形,即锥形部分形成在栅绝缘膜中,在这种情况下,半导体层也受此锥形部分的影响,掺入半导体膜的杂质浓度也是变化的。 Shape, i.e., a tapered portion formed on the gate insulating film, in this case, the semiconductor layer is also affected by the tapered portion, the incorporation of the impurity concentration of the semiconductor film is varied.

另一方面,在不与第一导电层重叠的杂质区1501b,亦即第二LDD 区(Loff区)中,栅绝缘膜的厚度是几乎不变的,因而第二LDD区(Loff 区)中的杂质浓度也是几乎不变的, On the other hand, in the non-overlapping with the first conductive layer of the impurity region 1501b, i.e., a second LDD region (Loff region), the thickness of the gate insulating film is nearly constant, so that the second LDD region (Loff region) The impurity concentration is almost constant,

下一步,虽然图中没有示出,形成覆盖像素TFT的抗蚀剂掩模。 Next, although not shown in FIG, formed to cover the pixel TFT resist mask. 这里,由控制抗蚀剂掩模的尺寸来确定像素TFT的Loff区长度。 Here, the resist mask by a control to determine the size of the length of the Loff region of the pixel TFT.

接着进行第二掺杂过程.用第二形状第一导电层1503b和第二形状第二导电层1504b作掩模,用离子掺杂法在半导体层1501中掺入呈一种导电类型的杂质元素,这里为n型导电杂质磷。 Followed by the second doping process. With the second shape first conducting layer 1503b and the second shape second conducting layer 1504b as a mask by an ion doping method was the incorporation of an impurity element of one conductivity type in the semiconductor layer 1501 , where n-type conductivity impurity is phosphorus. 笫二掺杂过程的掺杂浓度高于第一掺杂过程,并形成杂质区1501C和1501d。 Zi second doping process doping concentration is higher than the first doping process, and the formation of impurity regions 1501C and 1501d.

除了由笫一掺杂过程掺入的杂质浓度外,杂质区1501d,即源区或漏区,因第二掺杂过程而具有更高的浓度。 In addition to the process of incorporation of the impurity concentration doped by Zi, the impurity region 1501d, namely a source region or a drain region, a second doping process by having a higher concentration.

而杂质区1501C没有掺杂,因为它与第一导电层重叠,并具有与杂质区1501a相同的杂质分布.因此杂质区1501C也是第一LDD区。 The impurity-doped region 1501C does not, because it overlaps with the first conductive layer, and having the same impurity regions 1501a impurity profile. Thus also the first impurity region LDD region 1501C. 然而,与掺杂条件有关,杂质区1501C会具有更高的浓度,在这种情况下,第二掺杂过程也像第一掺杂过程那样,掺入半导体层中的杂质受側壁具有锥角P的锥形部分的影响。 However, with the doping conditions, impurity regions will have a higher concentration of 1501C, in this case, the second doping process, like that of the first doping process, the impurity introduced into the semiconductor layer by the sidewall having a taper angle the impact of the tapered portion P.

另一方面,只在像素TFT未被抗蚀剂掩模覆盖的区域进行掺杂, 形成源区或漏区。 On the other hand, only in the region of the pixel TFT is not doped resist mask covering, forming source and drain regions. 而被抗蚀刑掩模覆盖且未与导电层重叠的第二LDD 区1501b則保持不变。 The punishment by the resist mask covering the conductive layer and not the second LDD region overlaps 1501b unchanged.

接着除去开关TFT的抗蚀剂掩模。 Followed by removing the resist mask of the switching TFT.

图6B的有源矩阵衬底可按照实施方案1的工艺过程由图4C开始 6B, the active matrix substrate 1 can be started by the process according to the embodiment of FIG. 4C

一步步来制作。 Step by step to make.

按照上述的方法分别制作驱动电路n沟道TFT和像素TFT。 According to the above method were produced driver circuit n-channel TFT and pixel TFT. 驱动电路n沟道TFT含有:与笫二导电层重叠的沟道形成区,栅绝缘膜夹于其间;第一LDD区在沟道形成区两側;源区或漏区与第一LDD区接触。 The driver circuit comprising an n-channel TFT: Zi second conductive layer overlaps with the channel forming region, a gate insulating film interposed therebetween; a first LDD regions on both sides of the channel forming region; a source or drain region in contact with the first LDD regions . 像素TFT含有:与第二导电层重叠的沟道形成区,栅绝缘膜夹于其间;第一LDD区在沟道形成区两側;第二LDD区与第一LDD 区接触;源区或漏区与第二LDD区接触。 The pixel TFT comprising: a second conductive layer overlaps with the channel formation region, a gate insulating film interposed therebetween; a first LDD regions on both sides of the channel forming region; a second LDD regions in contact with the first LDD regions; source region or the drain LDD regions in contact with the second region.

而且,第一LDD区与第一导电层重叠,栅绝缘膜夹于其间,其杂质浓度随距沟道形成区的距离增大而增高。 Further, the first LDD regions overlap with the first conductive layer, a gate insulating film interposed therebetween, the impurity concentration with distance from the channel forming region increases higher. 注意,在第一LDD区内有 Note that in the first LDD region has

一个区域,其杂质浓度梯度至少为lxl0"〜lxl0's原子/cn)3的范围。 倘若LDD区具有这样的连续浓度分布,会有效地降低关态电流。而且, A region whose impurity concentration gradient of at least lxl0 "~lxl0's atomic / cn) range 3. If the LDD region has a continuous concentration profile will effectively reduce the off current. Also,

第一LDD区沿沟道纵向的长度越大,可靠性越高。 First LDD region along the longitudinal length of the channel greater, higher reliability.

实际上,在驱动电路p沟道TFT的区域149 - 152中由硼掺杂过程(见图4C)掺入的硼,与第一掺杂过程相似,也受到第一导电层厚度的影响,在半导体层上的这一层有一锥度,因而掺入杂质区的杂质浓度是变化的。 In fact, in the region of the p-channel TFT driving circuit 149 - boron boron doping process (see Fig. 4C) incorporated 152, similar to the first doping process, is also affected by the thickness of the first conductive layer, in This layer of the semiconductor layer has a taper, so that the incorporation of the impurity concentration of the impurity region is varied. 膜越厚,杂质浓度越低,膜越薄,杂质浓度越高。 The thicker the film, the lower the impurity concentration, the thinner the film, the higher the impurity concentration.

注意,可以任意地将实施方案10与实施方案1 ~ 9的任一个结合起来。 Note that the embodiments can be arbitrarily Embodiment 10 according to any one of 1 to 9 together.

而且,当实施方案IO的腐蚀气体(Ch和CL的混合气体)代之以SF6和Ch的混合气体,或当CF" CL和02的混合气体代之以SF" Ch 和(h的混合气体时,栅绝缘膜1502的选择性是极高的,因此膜的减薄更可得到进一步的抑制。 Moreover, when the mixed gas mixed gas of etching gas embodiment IO (Ch and CL mixed gas) instead of SF6 and Ch, or when the CF "CL and 02 mixed gas instead SF" Ch and (h when selective gate insulating film 1502 is extremely high, and therefore more thinned film can be further suppressed.

[实施方案11] [Embodiment 11]

按照各种腐蚀条件,如实施方案IO所记录的,第二形状第一栅电极(TaN)可有不同的形状.在实施方案11中,对图19A的形状A和图19B的形状B进行了模拟和比较. According to various etching conditions, such as IO recorded embodiment, the second shape of the first gate electrode (TaN) may have different shapes. In an embodiment 11, the shape A and shape B of FIG. 19A and 19B were Simulation and comparison.

实施方案IO所示的形状A示于图19A.图19A与图18D是一样的, 因此使用了相同的参考符号.困20是表示电子温度与第一栅电极膜厚的关系图,Lov区长度(沿沟道纵向的Lov区长度)取0. 4 pm、 0. 8 nm和1.5um,第一栅电极膜厚在图19A中为15-40 nm。 IO shape illustrated embodiment A shown in FIG. 19A. FIG. 19A and FIG. 18D is the same, and therefore the use of the same reference symbols. 20 is a trapped electron temperature and the film thickness of the gate electrode of the first graph, Lov region length (Lov region along the longitudinal direction of the channel length) to take 0. 4 pm, 0. 8 nm 1.5um, the first gate electrode thickness and FIG. 19A in the 15-40 nm. 注意,模拟是用图23所示的沟道纵向杂质浓度分布(半导体层表面下lOnm深处的浓度分布)来进行的。 Note that, the channel simulation with a longitudinal impurity concentration distribution shown in FIG. 23 (lOnm deep lower semiconductor layer surface concentration distribution) carried out. 然而,模拟是在第一栅电极側面部分有锥角改变的情况下作的,改变的部分从剖面看,是在离第一栅电极10nm 的膜厚范围内,从上表面看,是在离笫一栅电极边缘部分0. 13nm的范围内。 However, the simulation is the first side portion of the gate electrode has a cone angle change under conditions of change from a cross-sectional portion of view, it is in the range from the first gate electrode thickness of 10nm, from the surface, is off Zi a gate electrode edge portion of the range of 0. 13nm.

此外,图19B表示实施方案11的形状B.图19B不同于图19A, 侧面部分没有锥角改变的部位。 In addition, FIG 19B shows the shape of embodiment 19B differs from FIG. 11 B. FIG 19A, a side portion without taper angle change portion. 只是形成了锥角Y。 Just forming a cone angle Y.

对第一栅电极1700同样进行的模拟示于图19B,电子温度与第一栅电极(TaN)膜厚的关系示于图21, Lov区长度为0. 4 nm、 0. 8 pm 和1.5nm,第一栅电极膜厚为15~40nm.注意,模拟是用图23所示的沟道纵向杂质浓度分布来进行的。 A first analog gate electrode 1700 in the same manner as shown in FIG. 19B, the electron temperature and a first gate electrode (TaN) film thickness relationship shown in FIG. 21, Lov region length 0. 4 nm, 0. 8 pm and 1.5nm , a thickness of the first gate electrode 15 ~ 40nm. Note that the analog with the channel 23 as shown in FIG impurity concentration distribution in the longitudinal direction carried out. 此外,对于图19B所示的第一槺电极1700,当TaN膜厚为30 nm 时,沟道纵向电场强度与Lov区长度的关系以及Lov区长度与电子温度的关系示于图22。 In addition, the first electrode 1700 shown in FIG. 19B 槺, when the TaN film thickness is 30 nm, the relationship between the channel and the longitudinal electric field intensity and the relationship between the length of the Lov region Lov length and the electron temperature region shown in FIG. 22. 图22所示的电场强度和电子温度的变化趋势是几乎相同的。 Change of the electric field strength and the electron temperature is shown in FIG. 22 is almost identical. 因此,可以说,这表示电子温度越低,TFT退化的趋势越弱。 Therefore, we can say that the lower the electron temperature, TFT degradation trend weaker.

在比较图21和图22时,图21所示的图19B的形状表现出较低的电子温度。 Comparing Figure 21 and 22, the shape shown in FIG. 21 19B exhibits low electron temperature. 换言之,从TFT退化的观点来看,最好使用图19B的形状, 因为电子温度可降低。 In other words, from the viewpoint of TFT degradation, using the shape of FIG. 19B preferable because the electron temperature can be lowered.

此外,当Lov区长度为1. 5 pm时,电子温度^(氐,因此可以推断, 长的Lov区是优选的。 In addition, when the Lov length 1. 5 pm, the electron temperature ^ (Di, it can be inferred, long Lov region is preferred.

可将实施方案1 ~ 10的任一个与实施方案11任意地结合。 It may be any one of embodiments Embodiment 11 optionally combined 1-10.

[实施方案12] [Embodiment 12]

本发明的液晶显示器件可用作各种电子学设备的显示媒体。 A liquid crystal display device of the present invention can be used for various electronic devices display media.

下面可以给出这样的电子学设备:摄象机、数码相机、投影仪(背投式或正投式)、头戴式显示设备(风镜式显示设备)、游戏机、车辆导航系统、个人计算机、袖珍信息终端(如汽车计算机、袖珍电话或电子书籍)等。 The following can be given such an electronic apparatus: cameras, digital cameras, projectors (rear type or front-type), a head mounted display device (goggle type display device), a game machine, a car navigation system, a personal computer , portable information terminals (such as car computers, portable telephone or electronic book) and the like. 电子学设备的一些具体实例如图17A〜17F所示。 Some specific examples of electronic apparatus shown in FIG 17A~17F.

图17A表示一种图像显示设备,包括外壳2001、支座2002、显示部分2003等。 17A shows an image display apparatus includes a housing 2001, a support 2002, a display portion 2003 and the like. 本发明可用于其显示部分2003。 The present invention can be used in its display section 2003.

图17B所示的是摄象机,包括主体2101、显示部分2102,音频输入部分2103、操作开关2104、电池2105、以及图像接收部分2106。 FIG. 17B is a video camera, comprising a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. 本发明可用于其显示部分2102。 The present invention can be used in its display section 2102.

图17C所示为头戴型显示设备的一部分(右半部),包括主体2201 、信号电缆2202、头带2203、屏幕部分2204、光学系统2205、 显示部分2206等。 FIG. 17C shows a part of the device (right half) of the headset, comprising a main body 2201, signal cables 2202, 2203 headband, the screen portion 2204, an optical system 2205, a display portion 2206 and the like. 本发明可用于其显示部分2206。 The present invention can be used in its display section 2206.

图17D表示的是含记录媒体的图像重现设备(具体地,DVD机), 包括主体2301 、记录媒体(如DVD) 2302、操作开关2303、显示部分(a) 2304、显示部分(b) 2305等。 FIG. 17D shows an image reproducing device having a recording medium (specifically, DVD player), includes a main body 2301, a recording medium (e.g. DVD) 2302, operation switches 2303, a display portion (a) 2304, a display portion (b) 2305 and so on. 显示部分(a) 2304主要用于显示图像信息,而显示部分(b) 2305主要用于显示字符信息。 A display portion (a) 2304 is mainly used for displaying image information, while the display portion (b) 2305 is mainly used for displaying character information. 本发明可用于其显示部分(a) 2304和(b) 2305。 The present invention can be used in its display portion (a) 2304 and (b) 2305. 注意,含记录媒体的图像重现设备还包括如家庭游戏机等。 Note that the image reproducing device including a recording medium further comprises as household game consoles.

图17E表示个人计算机,包括主体2401、图像输入部分2402、显示部分2403、以及键盘2404。 Figure 17E shows a personal computer including a main body 2401, an image input portion 2402, a display portion 2403, and a keyboard 2404. 本发明可用于其显示部分2403。 The present invention can be used in its display section 2403.

图17F表示风镜式显示设备,包括主体2501、显示部分2502、以及镜腿部分2503。 FIG 17F shows a goggle type display device, comprising a main body 2501, a display portion 2502, and the temple part 2503. 本发明可用于其显示部分2502。 The present invention can be used in its display section 2502.

如上所述,本发明的应用范闺是极宽广的,可将本发明用于一切领域的电子学设备。 As described above, the application of the present invention is extremely broad scope boudoir, the invention can be used in all areas of electronics equipment. 而且,实施方案12的电子学设备可用实施方案1~ 11的任意组合来实现。 Further, embodiments of an electronic apparatus 12 can be used in any combination of embodiments 1 to 11 to achieve.

如上所述,本发明沟道纵向(栽流子运动方向)第一和第二栅电极的长度(此后简称为栅电极宽度)是不同的。 As described above, the present invention longitudinal channel (plant carrier movement direction) of the first and second gate electrode length (hereinafter referred to as the gate electrode width) is different. 因此,在用第一和第二栅电极作掩模进行离子注入时,利用因栅电极厚度不同而致的离子透入深度不同,可使第二栅电极下面半导体层中的离子浓度低于在第一栅电极下面但不在第二栅电极之下的半导体层中的离子浓度。 Therefore, when using the first and the second gate electrode as a mask by ion implantation using the gate electrode due to the different thickness caused the iontophoresis different depth, enable the second semiconductor layer below the gate electrode lower than the ion concentration a first gate electrode below the semiconductor layer but not the second gate electrode below the ion concentration. 此外, 也能使在第一栅电极下面但不在第二栅电极之下的半导体层中的离子浓度低于不在第一栅电极下面的半导体层中的离子浓度。 Further, under the first gate electrode to make but not below the second gate electrode in the semiconductor layer is not lower than the ion concentration in the gate electrode of the first semiconductor layer below the ion concentration.

此外,为了用掩模来形成Loff区,只须用腐蚀来控制第一栅电极和第二栅电极的宽度.与常规的实例相比,控制Loff区和Lov区的位置变得容易了。 Further, in order to form the Loff regions using a mask, by etching only to control the width of the first gate electrode and second gate electrode. Compared with the conventional examples, to control the position of the Loff region and the Lov region becomes easy. 因此,Lov区和Loff区的精确定位和制作具有所需特性的TFT也就变得容易了。 Thus, precise positioning and making Lov region and the Loff region of TFT having desired properties will become easier.

此外,中间引线制作在第二层间绝缘膜和第三层间绝缘膜之间。 In addition, between the intermediate lead made the second interlayer insulating film and the third interlayer insulating film. 因此,中间引线可做得与栅极信号线或源极信号线重叠,因而可增大孔径比。 Therefore, the intermediate wire can be made to overlap with the gate signal line or the source signal line, thus increasing the aperture ratio.

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Classifications
International ClassificationG02F1/136, G02F1/1362, H01L29/786, G02F1/133, H01L21/00, G02F1/1368, H01L21/336
Cooperative ClassificationG02F1/13454, G02F1/1368, H01L27/1214
European ClassificationH01L27/12T, G02F1/1368
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