CN100388255C

CN100388255C - Interface modular converter and method for configuration of FPGA

Info

Publication number: CN100388255C
Application number: CNB2004100649757A
Authority: CN
Inventors: 杨思远; 吴边; 邵贵阳; 孟春才; 段晓雪
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2004-10-10
Filing date: 2004-10-10
Publication date: 2008-05-14
Anticipated expiration: 2024-10-10
Also published as: CN1758232A

Abstract

The present invention relates to an interface converting module and a method for the configuration of FPGA. The interface converting module comprises an LPC bus interface part, a command register, a data register, a state register and an FPGA configuration time sequence generating part. The method for the configuration of FPGA comprises that a processor sends a starting configuration instruction to the interface converting module to generate the initialization time sequence which is downloaded by FPGA and initialize the time sequence by an LPC bus; configuration data is transmitted to the interface converting module to generate FPGA downloaded time sequence by the LPC bus, and the data is downloaded in FPGA; a configuration ending instruction is sent to the interface converting module to generate corresponding configuration ending time sequence by the LPC bus, or the interface converting module automatically finishes the corresponding configuration ending time sequence after finishing data configuration. The present invention enhances the configuration speed and reliability of FPGA. The standard LPC bus is used as an interface, the compatibility of the module is good, and the flexibility of the system design of hardware can also be enhanced.

Description

A kind of interface modular converter and the method that FPGA is configured

Technical field

The present invention relates to a kind of method that FPGA is configured, in particular, be the method that on circuit board, FPGA (field programmable gates array field programmable gate array) is configured by LPC (LowPin count hangs down the pin number) bus.

Background technology

The field upgrade of product and reduce personality PROM (the ProgrammableRead-Only Memory programmable read-only memory) chip cost that is used to dispose FPGA for convenience, a lot of products require all that FPGA can carry out Configuration Online by CPU (processor) on the circuit board.

Under normal conditions, generally be that I/O (input and output) pin processor and the series arrangement pin of FPGA directly link to each other, ordered pair FPGA is configured during configuration by software simulation FPGA.

But at the X86 framework with Intel is in the product of processor platform, processor does not have general I/O pin and can link to each other with FPGA, though can link to each other with FPGA by the I/O of bridge sheet, and ordered pair FPGA downloads during the I/O analog configuration by software control bridge sheet, but so not only take the I/O resource of bridge sheet, very flexible (because needing the fixedly I/O pin of bridge sheet), versatility bad (because the I/O of different bridge sheets definition is not necessarily the same), and configuration speed is slow, the complexity of software increases, and reliability reduces.

At the deficiency of present FPGA on-line loaded method, can adopt general bus interface to replace the fixedly I/O pin of bridge sheet to come FPGA is configured.Present most bridge sheet all has the lpc bus interface, is used for replacing ISA (Industry Standard Architecture industrial standard architectures) interface, and the signal wire that lpc bus needs significantly reduces than ISA, only needs 6 signal wires.

Summary of the invention:

The problem to be solved in the present invention provides a kind of interface modular converter that FPGA is configured by lpc bus, and the method that by lpc bus FPGA is configured with this interface modular converter is provided.

Interface modular converter among the present invention comprises lpc bus interface section, command register, data register, status register and FPGA configuration sequential generating portion; The sequential of lpc bus read-write register group is finished in described lpc bus interface section; The FPGA configuration data of the temporary byte of described data register; The operational order that described command register control is write by lpc bus by processor; Described status register is used for inquiring about this interface modular converter duty; Described FPGA configuration sequential generating portion is finished the series arrangement sequential, converts the configuration data in the data register to the series arrangement data stream and downloads among the FPGA.

The method that FPGA is configured among the present invention comprises:

Processor is sent out through lpc bus and is started configuration order to interface modular converter, and interface modular converter receives startup command, begins to generate the initialization sequential of FPGA download and FPGA is carried out initialization; If the initialization sequential is finished, can skip this step;

Processor is provided and delivered by lpc bus and is put data to interface modular converter, after interface modular converter receives configuration data, generates FPGA and downloads sequential, and configuration data is downloaded among the FPGA; In the process of configuration data, dispose the data of a byte at every turn;

Processor is transported to by lpc bus and is put the finish command to interface modular converter, after interface modular converter receives configuration the finish command, begins to generate the needed configuration of FPGA layoutprocedure and finishes sequential; Perhaps interface modular converter is finished the needed configuration of FPGA layoutprocedure automatically and is finished sequential after data configuration is finished.

Whether in the method, after each step that initialization, configuration data and configuration finish, trace routine is arranged all, it is successful to detect corresponding operation; The last operation successfully just carried out next operation.Whether trace routine successfully is to realize by the status register of reading in the interface modular converter.

Compared with prior art: 1,, improved FPGA configuration speed and reliability greatly because software no longer needs to simulate the configuration sequential of FPGA; 2, the lpc bus that uses standard is as interface, and the module compatibility is fine, adopts the software and hardware of this method design can use in the processor system of the various models of being with lpc bus the dirigibility that has improved Hardware Design.

Description of drawings:

Fig. 1 is the system architecture block diagram of applied environment of the present invention;

Fig. 2 is the interface modular converter inner structure block diagram among the present invention;

Fig. 3 is a LPC interface section state machine transition diagram;

Fig. 4 is FPGA configuration sequential generating portion state machine transition diagram;

Fig. 5 is the method flow diagram among the present invention.

Embodiment:

Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme:

As shown in Figure 1, applied environment system architecture diagram of the present invention, this system comprises:

Processor mini system 101 can comprise processor, internal memory, bridge sheet and BIOS etc., be one can working procedure the separate processor system, can the operation system and the present invention in configurator.

Interface modular converter 102, this module hangs on the lpc bus as a lpc bus device, finishes the sequential translation function of lpc bus to the FPGA series arrangement, and processor is finished Configuration Online to FPGA by this module.This hardware module inner structure block diagram mainly comprises lpc bus interface section 201, registers group (202-204) and FPGA configuration sequential generating portion 205 as shown in Figure 2.The sequential of lpc bus read-write register group is mainly finished in the lpc bus interface section; The FPGA configuration data of data register 203 temporary bytes; FPGA configuration sequential generating portion is finished the series arrangement sequential, converts the configuration data in the data register to the series arrangement data stream and downloads among the FPGA103; Command register 202 and status register 204 mainly offer control of software and detect the interface of this module status.

Interface modular converter 102 inner each several part principle of work and process description are as follows:

The state machine flow chart diagram of interface modular converter 102 inner lpc bus interface sections, 201 designs as shown in Figure 3.State machine is initially located in initial state 301, detect frame synchronizing signal and enter next state acquisition type of transaction 302 later on, ensuing several cycle is obtained address 303, if address right, and be to write transaction, so just receive data 307 from lpc bus, through bus synchronous 308 with after driving conversion 309, transaction is finished then.If read transaction, so through after bus driver conversion 304 and the bus synchronous 305, send the status register data to the lpc bus 306, through after the bus driver conversion 309, bus trade is finished then.

Interface modular converter 102 internal command registers 202 describe in detail for example, and are as shown in the table:

Table one

State	Meaning
State	Meaning	State 1	Start FPGA configuration (telling module to carry out FPGA configuration initialization)
State 2	Configuration data finishes (tell all end of transmissions of all configuration datas of module, module begins to monitor the configuration of FPGA side and finishes signal)	State 1
State 2		Other	Undefined

Interface modular converter 102 internal state registers 204 describe in detail for example, and are as shown in the table:

Table two

State	Meaning
State	Meaning	State 1	Initialization mistake (not monitoring nstatus)
State 2	Initialization success (expression initialization success tells that software can begin to have sent data)	State 1	Initialization mistake (not monitoring nstatus)
State 2		State 3	Bit-errors appears in the byte layoutprocedure
State 4	(telling software to have sent the data of next byte) finished in a byte data transmission.	State 3	Bit-errors appears in the byte layoutprocedure
State 4		State 5	Configuration successful
State 6	Configuration failure	State 5	Configuration successful
State 6	Configuration failure	State 7	Module is being monitored configuration and is being finished signal (for inquiry usefulness, inessential)
State 8	Module is being carried out byte data layoutprocedure (for inquiry usefulness, inessential)	State 7
State 8		Other	Undefined

Interface modular converter 102 inner FPGA configuration sequential generating portion 205 state machine diagrams as shown in Figure 4.The FPGA configuration interface is an example to dispose (Passive Serial Configration) interface from string.State machine is initially located in initial state 401, receive startup command after, enter initial configuration 402, finish the initialization sequential, detect the whether success 403 and write corresponding status register 404 of FPGA init state; Begin data configuration then, comprise receiving configuration data 406, generate data configuration sequential 407 and detecting configuration completion status 408; If all data configurations finish 405, delay time the corresponding time 409, detect the FPGA configuration and finish signal 410, finish signal if detect configuration, the layoutprocedure success.

The method flow diagram of the present invention by interface modular converter 102 configuration FPGA be (specific coding of command register 202 and status register 204 and corresponding implication see Table one and table two) as shown in Figure 5:

Step 1: at first to command register 202 write-enable orders.

Step 2: read through model status register 204 after time-delay a period of time, judge init state.If the initialization mistake enters error handler, configuration failure.

Step 3: if the initialization success then writes configuration data in data register 203.

Step 4: the read through model state is posted device 204, judges in this byte data layoutprocedure whether bit-errors is arranged.If bit-errors is arranged, enter error handler, configuration failure.

Step 5:, continue in data register 203, to write next data if there is not bit-errors; So repeatedly, finish up to all data configurations.

Step 6: write configuration data the finish command to command register 202.

Step 7: read through model status register 204 after time-delay a period of time, judge the configuration completion status.If configuration failure enters the configuration error handling procedure, configuration failure.

Step 8: if the state of status register 204 is a configuration successful, then represent the FPGA configuration successful, whole layoutprocedure finishes.

Claims

1. an interface modular converter is characterized in that, comprises low pin number transfer bus interface section (201), command register (202), data register (203), status register (204) and FPGA configuration sequential generating portion (205); The sequential of low pin number transfer bus read-write register group is finished in described low pin number transfer bus interface section; The FPGA configuration data of the temporary byte of described data register (203); The operational order that described command register (202) control is write by low pin number transfer bus by processor; Described status register (204) is used for inquiring about this interface modular converter duty; Described FPGA configuration sequential generating portion (205) is finished the series arrangement sequential, converts the configuration data in the data register to the series arrangement data stream and downloads among the FPGA.

2. an interface modular converter as claimed in claim 1 comprises the method that FPGA is configured:

Start configuration order to interface modular converter 2.1 processor is sent out through low pin number transfer bus, interface modular converter receives startup command, begins to generate the initialization sequential of FPGA download and described FPGA is carried out initialization;

2.2 processor is provided and delivered by low pin number transfer bus and is put data to interface modular converter, after interface modular converter receives described configuration data, generates FPGA and downloads sequential, and described configuration data is downloaded among the FPGA;

2.3 processor is transported to by low pin number transfer bus and is put the finish command to interface modular converter, after interface modular converter receives configuration the finish command, begins to generate the needed configuration of FPGA layoutprocedure and finishes sequential; Perhaps interface modular converter is finished the needed configuration of FPGA layoutprocedure automatically and is finished sequential after data configuration is finished.

3. the described method that FPGA is configured of claim 2 is characterized in that, after each step that initialization, configuration data and configuration finish, trace routine is arranged all, and whether detect corresponding operation successful; The last operation successfully just carried out next operation.

4. the described method that FPGA is configured of claim 3 is characterized in that, trace routine detects whether corresponding operation successfully is to realize by the status register of reading in the interface modular converter.

5. the described method that FPGA is configured of claim 2 is characterized in that, in the process of configuration data, processor sends the configuration data data of a byte to described interface modular converter at every turn.