CA2473245A1 - Functional pipelines - Google Patents
Functional pipelines Download PDFInfo
- Publication number
- CA2473245A1 CA2473245A1 CA002473245A CA2473245A CA2473245A1 CA 2473245 A1 CA2473245 A1 CA 2473245A1 CA 002473245 A CA002473245 A CA 002473245A CA 2473245 A CA2473245 A CA 2473245A CA 2473245 A1 CA2473245 A1 CA 2473245A1
- Authority
- CA
- Canada
- Prior art keywords
- programming engines
- functional
- programming
- functional pipeline
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Software Systems (AREA)
- Multi Processors (AREA)
- Advance Control (AREA)
Abstract
A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.
Description
FUNCTIONAL PIPELINES
BACKGROUND
This invention relates to functional pipelines.
Parallel processing is an efficient form of information processing of concurrent events of a computing system.
Parallel processing demands concurrent execution of many programs, in contrast to sequential processing. In the context of parallel processing, parallelism involves doing more than one thing at the same time. Unlike a serial paradigm where all tasks are performed,sequentially at a single station or a pipelined machine where tasks are performed at specialised stations, with parallel processing, many stations are provided, each capable of performing and carrying out various tasks and functions simultaneously. A
number of stations work simultaneously and independently on the same or common elements of a computing task.
Accordingly, parallel processing solves various types of computing tasks and certain problems are suitable for solution by applying several instruction processing units and several data streams.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a processing system.
FIG. 2 is a detailed block diagram of the processing system of FIG. 1.
FIG. 3 is a block diagram of a programming engine of the processing system of FIG. 1.
FIG. 4 is a block diagram of a functional pipeline unit of the processing system of FIG. 1.
FIG. 5 is a block diagram illustrating details of the processing system of FIG. 1.
DESCRIPTION
Architecture:
Referring to FIG. 1, a computer processing system 10 includes a parallel, hardware-based multithreaded network processor 12. The hardware-based multithreaded processor 12 is coupled to a memory system or memory resource 14. Memory system 14 includes dynamic random access memory (DRAM) 14a and static random access memory 14b (SRAM). The processing system 10 is especially useful for tasks that can be broken into parallel subtasks or functions. Specifically, the hardware-based multithreaded processor 12 is useful for tasks that are bandwidth oriented rather than latency oriented. The hardware-based multithreaded processor 12 has multiple functional microengines or programming engines 16 each with multiple hardware controlled threads that are simultaneously active and independently work on a specific task.
The programming engines 16 each maintain program counters in hardware and states associated with the program counters. Effectively, corresponding sets of context or threads can be simultaneously active on each of the programming engines 16 while only one is actually operating at any one time.
In this example, eight programming engines 16a-16h are illustrated in FIG. 1. Each engine from the programming engines 16a-16h processes eight hardware threads or contexts. The eight programming engines 16a-16h operate with shared resources including memory resource 14 and bus interfaces (not shown). The hardware-based multithreaded processor 12 includes a dynamic random access memory (DRAM) controller 18a and a static random access memory (SRAM) controller 18b. The DRAM memory 14a and DRAM controller 18a are typically used for processing large volumes of data, e.g., processing of network payloads from network packets.
The SRAM memory 14b and SRAM controller 18b are used in a networking implementation for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor 20, and the like.
The eight programming engines 16a-16h access either the DRAM memory 14a or SRAM memory 14b based on characteristics of the data. Thus, low latency, low bandwidth data is stored in and fetched from SRAM memory 14b, whereas higher bandwidth data for which latency is not as important, is stored in and fetched from DRAM memory 14a. The programming engines 16a-16h can execute memory reference instructions to either the DRAM controller 18a or SRAM controller 18b.
The hardware-based multithreaded processor 12 also includes a processor core 20 for loading microcode control for the programming engines 16a-16h. In this example, the processor core 20 is an XScalez"' based architecture.
The processor core 20 performs general purpose computer type functions such as handling protocols, exceptions, and extra support for packet processing where the programming engines 16 pass the packets off for more detailed processing such as in boundary conditions.
The processor core 20 has an operating system (not shown). Through the operating system (OS), the processor core 20 can call functions to operate on the programming engines 16a-16h. The processor core 20 can use any supported OS, in particular, a real time OS. For the core processor 20 implemented as an XScaleT"' architecture, operating systems such as Microsoft NT real-time, VXWorks and uCOS, or a freeware OS available over 'the Internet can be used.
Advantages of hardware multithreading can be explained by SRAM or DRAM memory accesses. As an example, an SRAM
access requested by a context (e.g., Thread-0), from one of the programming engines 16 will cause the SRAM controller 18b to initiate an access to the SRAM memory 14b. The SRAM
controller 18b accesses the SRAM memory 14b, fetches the data from the SRAM memory 14b, and returns data to a requesting programming engine 16.
During an SRAM access, if one of the programming engines 16a-16h had only a single thread that could operate, that programming engine would be dormant until data was returned from the SRAM memory 14b.
By employing hardware context swapping within each of the programming engines 16a-16h, the hardware context swapping enables other contexts with unique program counters to execute in that same programming engine. Thus, another thread e.g., Thread 1 can function while the first thread, Thread-0, is awaiting the read data to return. During execution, Thread 1 may access the DRAM memory 14a. While Thread_1 operates on the DRAM unit, and Thread_0 is operating on the SRAM unit, a new thread, e.g., Thread 2 can now operate in the programming engine 16. Thread 2 can operate for a certain amount of time until it needs to access memory or perform some other long latency operation, such as making an access to a bus interface. Therefore, simultaneously, the mufti-threaded processor 12 can have a bus operation, an SRAM operation, and a DRAM operation all being completed or operated upon by one of the programming engines 16 and have one more threads or contexts available to process more work.
The hardware context swapping also synchronies the completion of tasks. For example, two threads can access the shared memory resource, e.g., the SRAM memory 14b. Each one of the separate functional units, e.g., the SRAM
controller 18b, and the DRAM controller 18a, when they complete a requested task from one of the programming engine threads or contexts reports back a flag signaling completion of an operation. When the programming engines 16a-16h receive the flag, the programming engines 16a-16h can determine which thread to turn on.
One example of an application for the hardware-based multithreaded processor 12 is as a network processor. As a network processor, the hardware-based multithreaded processor 12 interfaces to network devices such as a Media Access Controller (MAC) device, e,g., a 10/100BaseT Octal MAC 13a or a Gigabit Ethernet device 13b. In general, as a network processor, the hardware-based multithreaded processor 12 can interface to any type of communication device or interface that receives or sends large amount of data. The computer processing system 10 functioning in a networking application can receive network packets and process those packets in a parallel manner.
Programming Engine Contexts:
Referring to FIG. 2, one exemplary programming engine 16a from the programming engines 16a-16h, is shown. The programming engine 16a includes a control store 30, which in one example includes a RAM of 4096 instructions, each of which is 40-bits wide. The RAM stores a microprogram that the programming engine 16a executes. The microprogram in the control store 30 is loadable by the processor core 20 (FIG. 1) .
In addition to event signals that are local to,an executing thread, the programming engine 16a employs signaling states that are global. With signaling states, an executing thread can broadcast a signal state to all programming engines 16a-16h. Any and all threads in the programming engines can branch on these signaling states.
These signaling states can be used to determine availability of a resource or whether a resource is due for servicing.
The context event logic has arbitration for the eight (8) threads. In one example, the arbitration is a round robin mechanism. Other techniques could be used including priority queuing or weighted fair queuing.
As described above, the programming engine 16a supports multi-threaded execution of eight contexts. This allows one thread to start executing just after another thread issues a memory reference and must wait until that reference completes before doing more work. Multi-threaded execution is critical to maintaining efficient hardware execution of the programming engine 16a because memory latency is significant. Multi-threaded execution allows the programming engines 16 to hide memory latency by performing useful independent work across several threads.
The programming engine 16a, to allow for efficient context swapping, has its own register set, program counter, and context specific local registers. Having a copy per context eliminates the need to move context specific information to and from shared memory and programming engine registers for each context swap. Fast context swapping allows a context to do computation while other contexts wait for input-output (I/0), typically, external memory accesses to complete or for a signal from another context or hardware unit.
For example, the programming engine 16a executes the eight contexts by maintaining eight program counters and eight context relative sets of registers. There can be six different types of context relative registers, namely, general purpose registers (GPRs) 32, inter-programming agent registers (not shown), Static Random Access Memory (SRAM) input transfer registers 34, Dynamic Random Access Memory (DRAM) input transfer registers 36, SRAM output transfer registers 38, DRAM output transfer registers 40.
The GPRs 32 are used for general programming purposes.
The GPRs 32 are read and written exclusively under program control. The GPRs 32, when used as a source in an instruction, supply operands to an execution datapath 44.
When used as a destination in an instruction, the GPRs 32 are written with the result of the execution datapath 44.
The programming engine 16a also includes I/O transfer registers 34, 36, 38 and 40 which are used for transferring s data to and from the programming engine 16a and locations external to the programming engines 16a, e.g., the DRAM
memory 14a, the SRAM memory 14b, and etc.
A local memory 42 is also used. The local memory 42 is addressable storage located in the programming engine 16a.
The local memory 42 is read and written exclusively under program control. The local memory 42 also includes variables shared by all the programming engines 16a-16h.
Shared variables are modified in various assigned tasks during functional pipeline stages by the programming engines 16a-16h, which are described next. The shared variables include a critical section, defining the read-modify-write times. The implementation and use of the critical section in the computing processing system 10 is also described below.
Functional Pipelining and Pipeline Stages:
Referring to FIG. 3, the programming engine 16a is shown in a functional pipeline unit 50. The functional pipeline unit 50 includes the programming engine 16a and a data unit 52 that includes data, operated on by the programming engine, e.g., network packets 54. The programming engine 16a is shown having a local register unit 56. The local register unit 56 stores information from the data packets 54. This information can be for example, a payload from a network packet, or data from other sources.
~ao~
In the functional pipeline unit 50, the contexts 58 of the programming engines 16a, namely, Programming Engine0.1 (PE0.1) through Programming Engine0.n (PEO.n), remain with the programming engine 16a while different functions are performed on the data packets 54 as time 66 progresses from time = 0 to time = t. A programming execution time is divided into "m" functional pipeline stages or pipe-stages 60a-60m. Each pipeline stage of the pipeline stages 60a-60m performs different pipeline functions 62a, 64, or 62p on data in the pipeline.
The pipeline stage 60a is, for example, a regular time interval within which a particular processing function, e.g., the function 62 is applied to one of the data packets 54. A processing function 62 can last one or more pipelines stages 62. The function 64, for example, lasts two pipeline stages, namely pipeline stages 60b and 60c.
A single programming engine such as the programming engine 16a can constitute a functional pipeline unit 50. In the functional pipeline unit 50, the functions 62a, 64, and 62p move through the functional pipeline unit 50 from one programming engine 16 to another programming engine 16, as will be described next.
Referring to FIG. 4, the data packets 54 are assigned to programming engine contexts 58 in order. Thus, if "n"
threads or contexts 58 execute in the programming engine 16a, the first context 58, "PE0.1" completes processing of the data packet 54 before the data packets 54 from the "PEO.n" context arrives. With this approach the programming engine 16b can begin processing the "n+1" packet.
Dividing the execution time of the programming engines l6 into functional pipeline stages 60a-60c results in more than one programming engine 16 executing an equivalent functional pipeline unit 70 in parallel. The functional pipeline stage 60a is distributed across two programming engines 16a and 16b, with each of the programming engines 16a and 16b executing eight contexts each.
In operation, each of the data packets 54 remains with one of the contexts 58 for a longer period of time as more programming engines 16 are added to the functional pipeline units 50 and 70. In this example, the data packet 54 remains with a context sixteen data packet arrival times (8 contexts x 2 programming engines) because context PE0.1 is not required to accept another data packet 58 until the ' other contexts 58 have received their data packets.
In this example, the function 62 of the functional pipeline stage 60a can be passed from the programming engine 16a to the programming engine 16b. Passing of the function 62 is accomplished by passing the processing functions from one programming engine to another, as illustrated by dotted lines 80a-80c in FIG. 4.
The number of functional pipeline stages 60a-60m is equal to the number of the programming engines 16a and 16b in the functional pipeline units 50 and 70. This ensures that a particular pipeline stage executes in only one programming engine 16 at any one time.
Referring to FIG. 5, functional pipeline units 50, 70, and 90 are shown to include the programming engines 16a (PEO), 16b (PEl), and 16c (PE2), respectively, in addition to the data units 52a-52c. Between the programming engines 16a-16c, critical sections 82a-82c and 84a-84c are provided.
The critical sections 82a-82c and 84a-84c are used in conjunction with shared data 86a-86c and 88a-88c.
In the critical sections 82a-82c and 84a-84c, the programming engine contexts 58a-58c are given exclusive access to the shared data 86a-86c (e. g., cyclic redundancy check residue (CRC), reassembly context, or a statistic) in external memory.
In operation, functions can be distributed across one or more functional pipeline stages 60a-60d. For example, the critical section 82a represents a section of code where only one programming engine context, in this case, the context 58a of the programming engine 16a, has exclusive modification privileges for a global resource (i.e., shared data 86a), such as a location in memory, at any one time.
Thus, the critical section 82a provides exclusive modification privileges to a particular functional pipeline stage of the programming engine 16a. The critical section 82a also provides support for exclusive access between the contexts 58a-58c in the programming engines 16a-16c.
In certain implementations only one function modifies the shared data 86a-86c between the programming engines 16a-16c, to ensure exclusive modification privileges between the programming engines 16a-16c. The function that modifies the shared data 86a-86c executes, e.g., in a single functional pipeline stage 60a, and the functional pipeline unit 50 is designed so that only one programming engine from all the programming engines 16a-16c executes the functional pipeline stage 60a at any one time.
Still referring to FIG. 5, each of the programming engines 16a-16c is assigned exclusive modification privileges to the non-shared data 86a-86c and 88a-88c, satisfying the requirement that only one function modifies the non-shared data 86a-86c and 88a-88c between the programming engines 16a-16c.
In this example, by optimizing the control flow through the functional pipeline units 50, 70, and 90, the architectural solution described above presents greater network processing power to the hardware-based multithreaded network processor 12.
In the functional pipeline unit 50, the programming engine 16a transitions into the critical section 82a of the functional pipeline stage 60a unless it can be assured that its "next" programming engine 16b has transitioned out of the critical section 82a. The programming engine 16b uses inter-thread signaling where the signaling states can be used to determine availability of a memory resource or whether a memory resource is due for servicing. There are four ways to signal a next context using inter-thread signaling:
Thread Signaling Mechanism 1. Signal next thread in the same PE Local Control and Status Registers (CSR) write 2. Signal a specific thread in the Local CSR write same PE
3. Signal the thread in the next PE Local CSR write 4. Signal any thread in an PE CSR write Critical sections such as CRC calculations are performed in the order of incoming data packets 54a-54c because inter-thread signaling is performed in order.
When the functional pipeline stage 60a transition occurs between the programming engines 16a and 16b, the elasticity buffer 92, implemented as a ring, is used. Each functional pipeline stage 60a is implemented to execute within the time allocated to the functional pipeline stage 60a. However, the elasticity buffer 92 accommodates fitter in the execution of the functional pipeline unit 50. Thus, if a functional pipeline stage 60a falls behind in execution due to system anomalies such as high utilization of memory units over a short period of time, the elasticity buffer 92 allows the context 58a of the functional pipeline stage 60a to be buffered so that the previous functional pipeline stages will not be stalled waiting for the next pipeline stage to complete. The elasticity buffer 92 as shown in FIG. 5 also allows different heartbeats to the different functional pipelines units 70 and 90.
By using the functional pipeline stages, as described above, the functional pipeline units 50, 70, and 90 cover memory latency and provides sufficient computation cycles for data packets 54 arriving faster than a single stream computation stage. By providing a mechanism for fast synchronization from one programming engine to the next programming engine which performs the same set of functions on a new set of data packets 54, parallel processing capability of the programming engines are greatly enhanced.
Multiple means for passing functional state and control is thus provided.
Other Embodiments:
In the example described above in conjunction with FIGS. 1-5, the computer processing system 10 may implement programming engines 16 using a family of network processors, namely, Intel Network Processor Family chips designed by Intel° Corporation, of Santa Clara, CA.
It is to be understood that while the invention has been described in conjunction with the detailed description thereof, the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims. Other aspects, advantages, and modifications are within the scope of the following claims.
BACKGROUND
This invention relates to functional pipelines.
Parallel processing is an efficient form of information processing of concurrent events of a computing system.
Parallel processing demands concurrent execution of many programs, in contrast to sequential processing. In the context of parallel processing, parallelism involves doing more than one thing at the same time. Unlike a serial paradigm where all tasks are performed,sequentially at a single station or a pipelined machine where tasks are performed at specialised stations, with parallel processing, many stations are provided, each capable of performing and carrying out various tasks and functions simultaneously. A
number of stations work simultaneously and independently on the same or common elements of a computing task.
Accordingly, parallel processing solves various types of computing tasks and certain problems are suitable for solution by applying several instruction processing units and several data streams.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a processing system.
FIG. 2 is a detailed block diagram of the processing system of FIG. 1.
FIG. 3 is a block diagram of a programming engine of the processing system of FIG. 1.
FIG. 4 is a block diagram of a functional pipeline unit of the processing system of FIG. 1.
FIG. 5 is a block diagram illustrating details of the processing system of FIG. 1.
DESCRIPTION
Architecture:
Referring to FIG. 1, a computer processing system 10 includes a parallel, hardware-based multithreaded network processor 12. The hardware-based multithreaded processor 12 is coupled to a memory system or memory resource 14. Memory system 14 includes dynamic random access memory (DRAM) 14a and static random access memory 14b (SRAM). The processing system 10 is especially useful for tasks that can be broken into parallel subtasks or functions. Specifically, the hardware-based multithreaded processor 12 is useful for tasks that are bandwidth oriented rather than latency oriented. The hardware-based multithreaded processor 12 has multiple functional microengines or programming engines 16 each with multiple hardware controlled threads that are simultaneously active and independently work on a specific task.
The programming engines 16 each maintain program counters in hardware and states associated with the program counters. Effectively, corresponding sets of context or threads can be simultaneously active on each of the programming engines 16 while only one is actually operating at any one time.
In this example, eight programming engines 16a-16h are illustrated in FIG. 1. Each engine from the programming engines 16a-16h processes eight hardware threads or contexts. The eight programming engines 16a-16h operate with shared resources including memory resource 14 and bus interfaces (not shown). The hardware-based multithreaded processor 12 includes a dynamic random access memory (DRAM) controller 18a and a static random access memory (SRAM) controller 18b. The DRAM memory 14a and DRAM controller 18a are typically used for processing large volumes of data, e.g., processing of network payloads from network packets.
The SRAM memory 14b and SRAM controller 18b are used in a networking implementation for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor 20, and the like.
The eight programming engines 16a-16h access either the DRAM memory 14a or SRAM memory 14b based on characteristics of the data. Thus, low latency, low bandwidth data is stored in and fetched from SRAM memory 14b, whereas higher bandwidth data for which latency is not as important, is stored in and fetched from DRAM memory 14a. The programming engines 16a-16h can execute memory reference instructions to either the DRAM controller 18a or SRAM controller 18b.
The hardware-based multithreaded processor 12 also includes a processor core 20 for loading microcode control for the programming engines 16a-16h. In this example, the processor core 20 is an XScalez"' based architecture.
The processor core 20 performs general purpose computer type functions such as handling protocols, exceptions, and extra support for packet processing where the programming engines 16 pass the packets off for more detailed processing such as in boundary conditions.
The processor core 20 has an operating system (not shown). Through the operating system (OS), the processor core 20 can call functions to operate on the programming engines 16a-16h. The processor core 20 can use any supported OS, in particular, a real time OS. For the core processor 20 implemented as an XScaleT"' architecture, operating systems such as Microsoft NT real-time, VXWorks and uCOS, or a freeware OS available over 'the Internet can be used.
Advantages of hardware multithreading can be explained by SRAM or DRAM memory accesses. As an example, an SRAM
access requested by a context (e.g., Thread-0), from one of the programming engines 16 will cause the SRAM controller 18b to initiate an access to the SRAM memory 14b. The SRAM
controller 18b accesses the SRAM memory 14b, fetches the data from the SRAM memory 14b, and returns data to a requesting programming engine 16.
During an SRAM access, if one of the programming engines 16a-16h had only a single thread that could operate, that programming engine would be dormant until data was returned from the SRAM memory 14b.
By employing hardware context swapping within each of the programming engines 16a-16h, the hardware context swapping enables other contexts with unique program counters to execute in that same programming engine. Thus, another thread e.g., Thread 1 can function while the first thread, Thread-0, is awaiting the read data to return. During execution, Thread 1 may access the DRAM memory 14a. While Thread_1 operates on the DRAM unit, and Thread_0 is operating on the SRAM unit, a new thread, e.g., Thread 2 can now operate in the programming engine 16. Thread 2 can operate for a certain amount of time until it needs to access memory or perform some other long latency operation, such as making an access to a bus interface. Therefore, simultaneously, the mufti-threaded processor 12 can have a bus operation, an SRAM operation, and a DRAM operation all being completed or operated upon by one of the programming engines 16 and have one more threads or contexts available to process more work.
The hardware context swapping also synchronies the completion of tasks. For example, two threads can access the shared memory resource, e.g., the SRAM memory 14b. Each one of the separate functional units, e.g., the SRAM
controller 18b, and the DRAM controller 18a, when they complete a requested task from one of the programming engine threads or contexts reports back a flag signaling completion of an operation. When the programming engines 16a-16h receive the flag, the programming engines 16a-16h can determine which thread to turn on.
One example of an application for the hardware-based multithreaded processor 12 is as a network processor. As a network processor, the hardware-based multithreaded processor 12 interfaces to network devices such as a Media Access Controller (MAC) device, e,g., a 10/100BaseT Octal MAC 13a or a Gigabit Ethernet device 13b. In general, as a network processor, the hardware-based multithreaded processor 12 can interface to any type of communication device or interface that receives or sends large amount of data. The computer processing system 10 functioning in a networking application can receive network packets and process those packets in a parallel manner.
Programming Engine Contexts:
Referring to FIG. 2, one exemplary programming engine 16a from the programming engines 16a-16h, is shown. The programming engine 16a includes a control store 30, which in one example includes a RAM of 4096 instructions, each of which is 40-bits wide. The RAM stores a microprogram that the programming engine 16a executes. The microprogram in the control store 30 is loadable by the processor core 20 (FIG. 1) .
In addition to event signals that are local to,an executing thread, the programming engine 16a employs signaling states that are global. With signaling states, an executing thread can broadcast a signal state to all programming engines 16a-16h. Any and all threads in the programming engines can branch on these signaling states.
These signaling states can be used to determine availability of a resource or whether a resource is due for servicing.
The context event logic has arbitration for the eight (8) threads. In one example, the arbitration is a round robin mechanism. Other techniques could be used including priority queuing or weighted fair queuing.
As described above, the programming engine 16a supports multi-threaded execution of eight contexts. This allows one thread to start executing just after another thread issues a memory reference and must wait until that reference completes before doing more work. Multi-threaded execution is critical to maintaining efficient hardware execution of the programming engine 16a because memory latency is significant. Multi-threaded execution allows the programming engines 16 to hide memory latency by performing useful independent work across several threads.
The programming engine 16a, to allow for efficient context swapping, has its own register set, program counter, and context specific local registers. Having a copy per context eliminates the need to move context specific information to and from shared memory and programming engine registers for each context swap. Fast context swapping allows a context to do computation while other contexts wait for input-output (I/0), typically, external memory accesses to complete or for a signal from another context or hardware unit.
For example, the programming engine 16a executes the eight contexts by maintaining eight program counters and eight context relative sets of registers. There can be six different types of context relative registers, namely, general purpose registers (GPRs) 32, inter-programming agent registers (not shown), Static Random Access Memory (SRAM) input transfer registers 34, Dynamic Random Access Memory (DRAM) input transfer registers 36, SRAM output transfer registers 38, DRAM output transfer registers 40.
The GPRs 32 are used for general programming purposes.
The GPRs 32 are read and written exclusively under program control. The GPRs 32, when used as a source in an instruction, supply operands to an execution datapath 44.
When used as a destination in an instruction, the GPRs 32 are written with the result of the execution datapath 44.
The programming engine 16a also includes I/O transfer registers 34, 36, 38 and 40 which are used for transferring s data to and from the programming engine 16a and locations external to the programming engines 16a, e.g., the DRAM
memory 14a, the SRAM memory 14b, and etc.
A local memory 42 is also used. The local memory 42 is addressable storage located in the programming engine 16a.
The local memory 42 is read and written exclusively under program control. The local memory 42 also includes variables shared by all the programming engines 16a-16h.
Shared variables are modified in various assigned tasks during functional pipeline stages by the programming engines 16a-16h, which are described next. The shared variables include a critical section, defining the read-modify-write times. The implementation and use of the critical section in the computing processing system 10 is also described below.
Functional Pipelining and Pipeline Stages:
Referring to FIG. 3, the programming engine 16a is shown in a functional pipeline unit 50. The functional pipeline unit 50 includes the programming engine 16a and a data unit 52 that includes data, operated on by the programming engine, e.g., network packets 54. The programming engine 16a is shown having a local register unit 56. The local register unit 56 stores information from the data packets 54. This information can be for example, a payload from a network packet, or data from other sources.
~ao~
In the functional pipeline unit 50, the contexts 58 of the programming engines 16a, namely, Programming Engine0.1 (PE0.1) through Programming Engine0.n (PEO.n), remain with the programming engine 16a while different functions are performed on the data packets 54 as time 66 progresses from time = 0 to time = t. A programming execution time is divided into "m" functional pipeline stages or pipe-stages 60a-60m. Each pipeline stage of the pipeline stages 60a-60m performs different pipeline functions 62a, 64, or 62p on data in the pipeline.
The pipeline stage 60a is, for example, a regular time interval within which a particular processing function, e.g., the function 62 is applied to one of the data packets 54. A processing function 62 can last one or more pipelines stages 62. The function 64, for example, lasts two pipeline stages, namely pipeline stages 60b and 60c.
A single programming engine such as the programming engine 16a can constitute a functional pipeline unit 50. In the functional pipeline unit 50, the functions 62a, 64, and 62p move through the functional pipeline unit 50 from one programming engine 16 to another programming engine 16, as will be described next.
Referring to FIG. 4, the data packets 54 are assigned to programming engine contexts 58 in order. Thus, if "n"
threads or contexts 58 execute in the programming engine 16a, the first context 58, "PE0.1" completes processing of the data packet 54 before the data packets 54 from the "PEO.n" context arrives. With this approach the programming engine 16b can begin processing the "n+1" packet.
Dividing the execution time of the programming engines l6 into functional pipeline stages 60a-60c results in more than one programming engine 16 executing an equivalent functional pipeline unit 70 in parallel. The functional pipeline stage 60a is distributed across two programming engines 16a and 16b, with each of the programming engines 16a and 16b executing eight contexts each.
In operation, each of the data packets 54 remains with one of the contexts 58 for a longer period of time as more programming engines 16 are added to the functional pipeline units 50 and 70. In this example, the data packet 54 remains with a context sixteen data packet arrival times (8 contexts x 2 programming engines) because context PE0.1 is not required to accept another data packet 58 until the ' other contexts 58 have received their data packets.
In this example, the function 62 of the functional pipeline stage 60a can be passed from the programming engine 16a to the programming engine 16b. Passing of the function 62 is accomplished by passing the processing functions from one programming engine to another, as illustrated by dotted lines 80a-80c in FIG. 4.
The number of functional pipeline stages 60a-60m is equal to the number of the programming engines 16a and 16b in the functional pipeline units 50 and 70. This ensures that a particular pipeline stage executes in only one programming engine 16 at any one time.
Referring to FIG. 5, functional pipeline units 50, 70, and 90 are shown to include the programming engines 16a (PEO), 16b (PEl), and 16c (PE2), respectively, in addition to the data units 52a-52c. Between the programming engines 16a-16c, critical sections 82a-82c and 84a-84c are provided.
The critical sections 82a-82c and 84a-84c are used in conjunction with shared data 86a-86c and 88a-88c.
In the critical sections 82a-82c and 84a-84c, the programming engine contexts 58a-58c are given exclusive access to the shared data 86a-86c (e. g., cyclic redundancy check residue (CRC), reassembly context, or a statistic) in external memory.
In operation, functions can be distributed across one or more functional pipeline stages 60a-60d. For example, the critical section 82a represents a section of code where only one programming engine context, in this case, the context 58a of the programming engine 16a, has exclusive modification privileges for a global resource (i.e., shared data 86a), such as a location in memory, at any one time.
Thus, the critical section 82a provides exclusive modification privileges to a particular functional pipeline stage of the programming engine 16a. The critical section 82a also provides support for exclusive access between the contexts 58a-58c in the programming engines 16a-16c.
In certain implementations only one function modifies the shared data 86a-86c between the programming engines 16a-16c, to ensure exclusive modification privileges between the programming engines 16a-16c. The function that modifies the shared data 86a-86c executes, e.g., in a single functional pipeline stage 60a, and the functional pipeline unit 50 is designed so that only one programming engine from all the programming engines 16a-16c executes the functional pipeline stage 60a at any one time.
Still referring to FIG. 5, each of the programming engines 16a-16c is assigned exclusive modification privileges to the non-shared data 86a-86c and 88a-88c, satisfying the requirement that only one function modifies the non-shared data 86a-86c and 88a-88c between the programming engines 16a-16c.
In this example, by optimizing the control flow through the functional pipeline units 50, 70, and 90, the architectural solution described above presents greater network processing power to the hardware-based multithreaded network processor 12.
In the functional pipeline unit 50, the programming engine 16a transitions into the critical section 82a of the functional pipeline stage 60a unless it can be assured that its "next" programming engine 16b has transitioned out of the critical section 82a. The programming engine 16b uses inter-thread signaling where the signaling states can be used to determine availability of a memory resource or whether a memory resource is due for servicing. There are four ways to signal a next context using inter-thread signaling:
Thread Signaling Mechanism 1. Signal next thread in the same PE Local Control and Status Registers (CSR) write 2. Signal a specific thread in the Local CSR write same PE
3. Signal the thread in the next PE Local CSR write 4. Signal any thread in an PE CSR write Critical sections such as CRC calculations are performed in the order of incoming data packets 54a-54c because inter-thread signaling is performed in order.
When the functional pipeline stage 60a transition occurs between the programming engines 16a and 16b, the elasticity buffer 92, implemented as a ring, is used. Each functional pipeline stage 60a is implemented to execute within the time allocated to the functional pipeline stage 60a. However, the elasticity buffer 92 accommodates fitter in the execution of the functional pipeline unit 50. Thus, if a functional pipeline stage 60a falls behind in execution due to system anomalies such as high utilization of memory units over a short period of time, the elasticity buffer 92 allows the context 58a of the functional pipeline stage 60a to be buffered so that the previous functional pipeline stages will not be stalled waiting for the next pipeline stage to complete. The elasticity buffer 92 as shown in FIG. 5 also allows different heartbeats to the different functional pipelines units 70 and 90.
By using the functional pipeline stages, as described above, the functional pipeline units 50, 70, and 90 cover memory latency and provides sufficient computation cycles for data packets 54 arriving faster than a single stream computation stage. By providing a mechanism for fast synchronization from one programming engine to the next programming engine which performs the same set of functions on a new set of data packets 54, parallel processing capability of the programming engines are greatly enhanced.
Multiple means for passing functional state and control is thus provided.
Other Embodiments:
In the example described above in conjunction with FIGS. 1-5, the computer processing system 10 may implement programming engines 16 using a family of network processors, namely, Intel Network Processor Family chips designed by Intel° Corporation, of Santa Clara, CA.
It is to be understood that while the invention has been described in conjunction with the detailed description thereof, the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims. Other aspects, advantages, and modifications are within the scope of the following claims.
Claims (25)
1. A system comprising:
a parallel processor that assigns system functions for processing data including a plurality of programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the plurality of programming engines.
a parallel processor that assigns system functions for processing data including a plurality of programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the plurality of programming engines.
2. The system of claim 1 further comprising:
a synchronization unit across the functional pipeline unit.
a synchronization unit across the functional pipeline unit.
3. The system of claim 1 wherein the functional pipeline unit includes a plurality of functional pipeline stages.
4. The system of claim 3 wherein the plurality of programming engines have an execution time for processing a task and the execution time is partitioned into a number of time intervals corresponding to the number of the plurality of functional pipeline stages.
5. The system of claim 4 wherein each of the plurality of functional pipeline stages perform a different system function.
6. The system of claim 1 wherein at least one of the plurality of programming engines is the functional pipeline unit.
7. The system of claim 1 wherein the plurality of programming engines are configured to process a data packet in order.
8. The system of claim 7 wherein the data packet are assigned to the multiple contexts of the plurality of programming engines.
9. The system of claim 1 wherein the plurality of programming engines are configured to execute a data packet processing function using the functional pipeline unit of the system.
10. The system of claim 9 wherein a data packet is maintained in the plurality of programming engines for a period of time corresponding to the number of the plurality of programming engines.
11. The system of claim 3 wherein the number of the plurality of pipeline stages is equal to the number of the plurality of programming engines.
12. The system of claim 3 wherein the plurality of pipeline stages include a critical section.
13. The system of claim 12 wherein the critical section provides exclusive access for the multiple contexts to non-shared data required for processing data packets.
14. The system of claim 3 wherein the plurality of programming engines include inter-thread signaling.
15. The system of claim 3 wherein the plurality of programming engines include an elasticity buffer that accommodates jitter between the plurality of pipeline stages upon execution of a data packet processing function.
16. A method of transferring data between a plurality of programming engines, the method comprising:
assigning system functions for processing data in a parallel processor to corresponding ones of a plurality of programming engines that provide a functional pipeline unit, which supports execution of multiple contexts in each of the plurality of programming engines; and passing functional data among the plurality of programming engines in the functional pipeline unit.
assigning system functions for processing data in a parallel processor to corresponding ones of a plurality of programming engines that provide a functional pipeline unit, which supports execution of multiple contexts in each of the plurality of programming engines; and passing functional data among the plurality of programming engines in the functional pipeline unit.
17. The method of claim 16 further comprising synchronizing the system functions across the functional pipeline unit.
18. The method of claim 17 further comprising partitioning an execution time into a number of time intervals corresponding to the number of plurality of pipeline stages.
19. The method of claim 16 wherein the plurality of programming engines use multiple contexts to process the data packet in order.
20. The method of claim 16 wherein the plurality of programming engines execute a data packet processing functions using the functional pipeline unit of the system.
21. The method of claim 16 further comprising using a critical section that provides exclusive access for the multiple contexts to non-shared data required for processing data packets.
22. The method of claim 16 further comprising employing an elasticity buffer to accommodate jitter between the plurality of pipeline stages upon execution of a data packet processing function.
23. A computer program product residing on a computer readable medium for causing a parallel processor to perform a function comprises instructions causing the processor to:
assign system functions for processing data in a parallel processor to corresponding ones of a plurality of programming engines that provide a functional pipeline unit, which supports execution of multiple contexts in each of the plurality of programming engines; and pass functional data among the plurality of programming engines in the functional pipeline unit.
assign system functions for processing data in a parallel processor to corresponding ones of a plurality of programming engines that provide a functional pipeline unit, which supports execution of multiple contexts in each of the plurality of programming engines; and pass functional data among the plurality of programming engines in the functional pipeline unit.
24. The computer program product of claim 23 further comprising instructions causing the processor to synchronize the system functions across the functional pipeline unit.
25. The computer program product of claim 23 wherein the plurality of programming engines execute a data packet processing functions using the functional pipeline unit of the system.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/053,172 | 2002-01-17 | ||
US10/053,172 US6934951B2 (en) | 2002-01-17 | 2002-01-17 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section |
PCT/US2003/001578 WO2003063018A2 (en) | 2002-01-17 | 2003-01-16 | Functional pipelines |
Publications (1)
Publication Number | Publication Date |
---|---|
CA2473245A1 true CA2473245A1 (en) | 2003-07-31 |
Family
ID=21982381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002473245A Abandoned CA2473245A1 (en) | 2002-01-17 | 2003-01-16 | Functional pipelines |
Country Status (8)
Country | Link |
---|---|
US (2) | US6934951B2 (en) |
EP (1) | EP1470496A2 (en) |
KR (1) | KR100611860B1 (en) |
CN (1) | CN1618061B (en) |
AU (1) | AU2003225523A1 (en) |
CA (1) | CA2473245A1 (en) |
TW (1) | TWI265430B (en) |
WO (1) | WO2003063018A2 (en) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6983350B1 (en) | 1999-08-31 | 2006-01-03 | Intel Corporation | SDRAM controller for parallel processor architecture |
WO2001016702A1 (en) | 1999-09-01 | 2001-03-08 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
US6532509B1 (en) | 1999-12-22 | 2003-03-11 | Intel Corporation | Arbitrating command requests in a parallel multi-threaded processing system |
US6694380B1 (en) | 1999-12-27 | 2004-02-17 | Intel Corporation | Mapping requests from a processing unit that uses memory-mapped input-output space |
US6625654B1 (en) * | 1999-12-28 | 2003-09-23 | Intel Corporation | Thread signaling in multi-threaded network processor |
US6661794B1 (en) | 1999-12-29 | 2003-12-09 | Intel Corporation | Method and apparatus for gigabit packet assignment for multithreaded packet processing |
US7681018B2 (en) * | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US20020053017A1 (en) * | 2000-09-01 | 2002-05-02 | Adiletta Matthew J. | Register instructions for a multithreaded processor |
US6934951B2 (en) * | 2002-01-17 | 2005-08-23 | Intel Corporation | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section |
US7437724B2 (en) * | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
US7240164B2 (en) * | 2003-08-14 | 2007-07-03 | Intel Corporation | Folding for a multi-threaded network processor |
US7441245B2 (en) * | 2003-08-14 | 2008-10-21 | Intel Corporation | Phasing for a multi-threaded network processor |
US7376952B2 (en) * | 2003-09-15 | 2008-05-20 | Intel Corporation | Optimizing critical section microblocks by controlling thread execution |
US7418540B2 (en) * | 2004-04-28 | 2008-08-26 | Intel Corporation | Memory controller with command queue look-ahead |
US7733857B2 (en) * | 2004-12-17 | 2010-06-08 | Samsung Electronics Co., Ltd. | Apparatus and method for sharing variables and resources in a multiprocessor routing node |
US20060236011A1 (en) * | 2005-04-15 | 2006-10-19 | Charles Narad | Ring management |
US7920584B2 (en) * | 2005-05-04 | 2011-04-05 | Arm Limited | Data processing system |
US7630388B2 (en) * | 2005-05-04 | 2009-12-08 | Arm Limited | Software defined FIFO memory for storing a set of data from a stream of source data |
KR20080013993A (en) * | 2005-05-04 | 2008-02-13 | 에이알엠 리미티드 | Use of a data engine within a data processing apparatus |
CN100407701C (en) * | 2005-06-25 | 2008-07-30 | 华为技术有限公司 | Network processor |
US20070044103A1 (en) * | 2005-07-25 | 2007-02-22 | Mark Rosenbluth | Inter-thread communication of lock protected data |
US7853951B2 (en) * | 2005-07-25 | 2010-12-14 | Intel Corporation | Lock sequencing to reorder and grant lock requests from multiple program threads |
US20070094664A1 (en) * | 2005-10-21 | 2007-04-26 | Kimming So | Programmable priority for concurrent multi-threaded processors |
US20070124728A1 (en) * | 2005-11-28 | 2007-05-31 | Mark Rosenbluth | Passing work between threads |
US20070140282A1 (en) * | 2005-12-21 | 2007-06-21 | Sridhar Lakshmanamurthy | Managing on-chip queues in switched fabric networks |
US20070245074A1 (en) * | 2006-03-30 | 2007-10-18 | Rosenbluth Mark B | Ring with on-chip buffer for efficient message passing |
US8179896B2 (en) | 2006-11-09 | 2012-05-15 | Justin Mark Sobaje | Network processors and pipeline optimization methods |
US8059650B2 (en) * | 2007-10-31 | 2011-11-15 | Aruba Networks, Inc. | Hardware based parallel processing cores with multiple threads and multiple pipeline stages |
US7926013B2 (en) * | 2007-12-31 | 2011-04-12 | Intel Corporation | Validating continuous signal phase matching in high-speed nets routed as differential pairs |
MY155586A (en) * | 2008-01-02 | 2015-11-03 | Mimos Berhad | System for increasing throughput for memory device |
US8055719B2 (en) * | 2008-07-16 | 2011-11-08 | International Business Machines Corporation | Performance and reduce network traffic for remote hardware data scan operations |
WO2016000170A1 (en) * | 2014-06-30 | 2016-01-07 | 华为技术有限公司 | Data processing method executed by network apparatus, and associated device |
US9804843B1 (en) | 2014-09-05 | 2017-10-31 | Altera Corporation | Method and apparatus for linear function processing in pipelined storage circuits |
JP6816027B2 (en) * | 2015-05-21 | 2021-01-20 | ゴールドマン サックス アンド カンパニー エルエルシー | Multipurpose parallel processing architecture |
US11449452B2 (en) | 2015-05-21 | 2022-09-20 | Goldman Sachs & Co. LLC | General-purpose parallel computing architecture |
US20230071278A1 (en) * | 2021-09-03 | 2023-03-09 | International Business Machines Corporation | Using a machine learning module to determine a group of execution paths of program code and a computational resource allocation to use to execute the group of execution paths |
Family Cites Families (167)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US563641A (en) * | 1896-07-07 | bemis | ||
US643438A (en) * | 1899-05-10 | 1900-02-13 | Joseph Edward Wormald | Heating stove or furnace. |
US644337A (en) * | 1900-01-11 | 1900-02-27 | Seng Co | Lid-operating mechanism for box-couches. |
US726757A (en) * | 1903-01-12 | 1903-04-28 | Alexander Laughlin | Gas-producer. |
US3373408A (en) | 1965-04-16 | 1968-03-12 | Rca Corp | Computer capable of switching between programs without storage and retrieval of the contents of operation registers |
US3478322A (en) | 1967-05-23 | 1969-11-11 | Ibm | Data processor employing electronically changeable control storage |
BE795789A (en) | 1972-03-08 | 1973-06-18 | Burroughs Corp | MICROPROGRAM CONTAINING A MICRO-RECOVERY INSTRUCTION |
IT986411B (en) | 1973-06-05 | 1975-01-30 | Olivetti E C Spa | SYSTEM TO TRANSFER THE CONTROL OF PROCESSING FROM A FIRST PRIORITY LEVEL TO A SECOND PRIORITY LEVEL |
US4130890A (en) | 1977-06-08 | 1978-12-19 | Itt Industries, Inc. | Integrated DDC memory with bitwise erase |
JPS56164464A (en) | 1980-05-21 | 1981-12-17 | Tatsuo Nogi | Parallel processing computer |
US4400770A (en) | 1980-11-10 | 1983-08-23 | International Business Machines Corporation | Cache synonym detection and handling means |
CA1179069A (en) | 1981-04-10 | 1984-12-04 | Yasushi Fukunaga | Data transmission apparatus for a multiprocessor system |
US4745544A (en) | 1985-12-12 | 1988-05-17 | Texas Instruments Incorporated | Master/slave sequencing processor with forced I/O |
US5297260A (en) | 1986-03-12 | 1994-03-22 | Hitachi, Ltd. | Processor having a plurality of CPUS with one CPU being normally connected to common bus |
US5142683A (en) | 1987-03-09 | 1992-08-25 | Unisys Corporation | Intercomputer communication control apparatus and method |
US4866664A (en) | 1987-03-09 | 1989-09-12 | Unisys Corporation | Intercomputer communication control apparatus & method |
EP0357768B1 (en) | 1988-03-14 | 1994-03-09 | Unisys Corporation | Record lock processor for multiprocessing data system |
US5155854A (en) | 1989-02-03 | 1992-10-13 | Digital Equipment Corporation | System for arbitrating communication requests using multi-pass control unit based on availability of system resources |
US5155831A (en) | 1989-04-24 | 1992-10-13 | International Business Machines Corporation | Data processing system with fast queue store interposed between store-through caches and a main memory |
US5168555A (en) | 1989-09-06 | 1992-12-01 | Unisys Corporation | Initial program load control |
US5263169A (en) | 1989-11-03 | 1993-11-16 | Zoran Corporation | Bus arbitration and resource management for concurrent vector signal processor architecture |
DE3942977A1 (en) | 1989-12-23 | 1991-06-27 | Standard Elektrik Lorenz Ag | METHOD FOR RESTORING THE CORRECT SEQUENCE OF CELLS, ESPECIALLY IN AN ATM SWITCHING CENTER, AND OUTPUT UNIT THEREFOR |
US5179702A (en) * | 1989-12-29 | 1993-01-12 | Supercomputer Systems Limited Partnership | System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling |
EP0446721B1 (en) | 1990-03-16 | 2000-12-20 | Texas Instruments Incorporated | Distributed processing memory |
US5390329A (en) | 1990-06-11 | 1995-02-14 | Cray Research, Inc. | Responding to service requests using minimal system-side context in a multiprocessor environment |
US5404482A (en) | 1990-06-29 | 1995-04-04 | Digital Equipment Corporation | Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills |
US5432918A (en) | 1990-06-29 | 1995-07-11 | Digital Equipment Corporation | Method and apparatus for ordering read and write operations using conflict bits in a write queue |
US5347648A (en) | 1990-06-29 | 1994-09-13 | Digital Equipment Corporation | Ensuring write ordering under writeback cache error conditions |
AU630299B2 (en) | 1990-07-10 | 1992-10-22 | Fujitsu Limited | A data gathering/scattering system in a parallel computer |
US5367678A (en) | 1990-12-06 | 1994-11-22 | The Regents Of The University Of California | Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically |
KR960001273B1 (en) * | 1991-04-30 | 1996-01-25 | 가부시키가이샤 도시바 | Single chip microcomputer |
US5255239A (en) | 1991-08-13 | 1993-10-19 | Cypress Semiconductor Corporation | Bidirectional first-in-first-out memory device with transparent and user-testable capabilities |
US5623489A (en) | 1991-09-26 | 1997-04-22 | Ipc Information Systems, Inc. | Channel allocation system for distributed digital switching network |
US5392412A (en) | 1991-10-03 | 1995-02-21 | Standard Microsystems Corporation | Data communication controller for use with a single-port data packet buffer |
GB2260429B (en) | 1991-10-11 | 1995-05-24 | Intel Corp | Versatile cache memory |
US5392391A (en) | 1991-10-18 | 1995-02-21 | Lsi Logic Corporation | High performance graphics applications controller |
DE69231957T2 (en) | 1991-10-21 | 2002-04-04 | Toshiba Kawasaki Kk | High speed processor capable of handling multiple interruptions |
US5452437A (en) | 1991-11-18 | 1995-09-19 | Motorola, Inc. | Methods of debugging multiprocessor system |
US5442797A (en) | 1991-12-04 | 1995-08-15 | Casavant; Thomas L. | Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging |
JP2823767B2 (en) | 1992-02-03 | 1998-11-11 | 松下電器産業株式会社 | Register file |
US5459842A (en) | 1992-06-26 | 1995-10-17 | International Business Machines Corporation | System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory |
DE4223600C2 (en) | 1992-07-17 | 1994-10-13 | Ibm | Multiprocessor computer system and method for transmitting control information and data information between at least two processor units of a computer system |
US5404484A (en) * | 1992-09-16 | 1995-04-04 | Hewlett-Packard Company | Cache system for reducing memory latency times |
WO1994015287A2 (en) | 1992-12-23 | 1994-07-07 | Centre Electronique Horloger S.A. | Multi-tasking low-power controller |
EP0680640A1 (en) * | 1993-01-22 | 1995-11-08 | University Corporation For Atmospheric Research | Multipipeline multiprocessor system |
US5404464A (en) | 1993-02-11 | 1995-04-04 | Ast Research, Inc. | Bus control system and method that selectively generate an early address strobe |
US5448702A (en) | 1993-03-02 | 1995-09-05 | International Business Machines Corporation | Adapters with descriptor queue management capability |
EP0617361B1 (en) * | 1993-03-26 | 2001-11-28 | Cabletron Systems, Inc. | Scheduling method and apparatus for a communication network |
US6311286B1 (en) | 1993-04-30 | 2001-10-30 | Nec Corporation | Symmetric multiprocessing system with unified environment and distributed system functions |
CA2122182A1 (en) | 1993-05-20 | 1994-11-21 | Rene Leblanc | Method for rapid prototyping of programming problems |
CA2107299C (en) | 1993-09-29 | 1997-02-25 | Mehrad Yasrebi | High performance machine for switched communications in a heterogenous data processing network gateway |
US5446736A (en) | 1993-10-07 | 1995-08-29 | Ast Research, Inc. | Method and apparatus for connecting a node to a wireless network using a standard protocol |
US5450351A (en) | 1993-11-19 | 1995-09-12 | International Business Machines Corporation | Content addressable memory implementation with random access memory |
US5490204A (en) | 1994-03-01 | 1996-02-06 | Safco Corporation | Automated quality assessment system for cellular networks |
US5835755A (en) | 1994-04-04 | 1998-11-10 | At&T Global Information Solutions Company | Multi-processor computer system for operating parallel client/server database processes |
JP3547482B2 (en) | 1994-04-15 | 2004-07-28 | 株式会社日立製作所 | Information processing equipment |
US5542088A (en) | 1994-04-29 | 1996-07-30 | Intergraph Corporation | Method and apparatus for enabling control of task execution |
US5721870A (en) | 1994-05-25 | 1998-02-24 | Nec Corporation | Lock control for a shared main storage data processing system |
US5544236A (en) | 1994-06-10 | 1996-08-06 | At&T Corp. | Access to unsubscribed features |
US5574922A (en) | 1994-06-17 | 1996-11-12 | Apple Computer, Inc. | Processor with sequences of processor instructions for locked memory updates |
US5781774A (en) | 1994-06-29 | 1998-07-14 | Intel Corporation | Processor having operating modes for an upgradeable multiprocessor computer system |
JP3810449B2 (en) | 1994-07-20 | 2006-08-16 | 富士通株式会社 | Queue device |
JP3169779B2 (en) | 1994-12-19 | 2001-05-28 | 日本電気株式会社 | Multi-thread processor |
US5550816A (en) | 1994-12-29 | 1996-08-27 | Storage Technology Corporation | Method and apparatus for virtual switching |
DE19503160A1 (en) | 1995-02-01 | 1996-08-08 | Bayer Ag | Use of phenylcyclohexylcarboxylic acid amides |
US5784712A (en) | 1995-03-01 | 1998-07-21 | Unisys Corporation | Method and apparatus for locally generating addressing information for a memory access |
US5649157A (en) | 1995-03-30 | 1997-07-15 | Hewlett-Packard Co. | Memory controller with priority queues |
US5886992A (en) | 1995-04-14 | 1999-03-23 | Valtion Teknillinen Tutkimuskeskus | Frame synchronized ring system and method |
US5758184A (en) * | 1995-04-24 | 1998-05-26 | Microsoft Corporation | System for performing asynchronous file operations requested by runnable threads by processing completion messages with different queue thread and checking for completion by runnable threads |
US5592622A (en) | 1995-05-10 | 1997-01-07 | 3Com Corporation | Network intermediate system with message passing architecture |
JPH08320797A (en) | 1995-05-24 | 1996-12-03 | Fuji Xerox Co Ltd | Program control system |
US5828746A (en) | 1995-06-07 | 1998-10-27 | Lucent Technologies Inc. | Telecommunications network |
US5828863A (en) | 1995-06-09 | 1998-10-27 | Canon Information Systems, Inc. | Interface device connected between a LAN and a printer for outputting formatted debug information about the printer to the printer |
US5613071A (en) | 1995-07-14 | 1997-03-18 | Intel Corporation | Method and apparatus for providing remote memory access in a distributed memory multiprocessor system |
US5680641A (en) | 1995-08-16 | 1997-10-21 | Sharp Microelectronics Technology, Inc. | Multiple register bank system for concurrent I/O operation in a CPU datapath |
US5940612A (en) | 1995-09-27 | 1999-08-17 | International Business Machines Corporation | System and method for queuing of tasks in a multiprocessing system |
US5689566A (en) | 1995-10-24 | 1997-11-18 | Nguyen; Minhtam C. | Network with secure communications sessions |
US5809530A (en) | 1995-11-13 | 1998-09-15 | Motorola, Inc. | Method and apparatus for processing multiple cache misses using reload folding and store merging |
KR0150072B1 (en) | 1995-11-30 | 1998-10-15 | 양승택 | Device for controlling memory data path in parallel processing computer system |
US5796413A (en) | 1995-12-06 | 1998-08-18 | Compaq Computer Corporation | Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering |
US5940866A (en) | 1995-12-13 | 1999-08-17 | International Business Machines Corporation | Information handling system having a local address queue for local storage of command blocks transferred from a host processing side |
US5699537A (en) | 1995-12-22 | 1997-12-16 | Intel Corporation | Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions |
WO1997024825A2 (en) | 1995-12-29 | 1997-07-10 | Tixi.Com Gmbh Telecommunication Systems | Method and microcomputer system for the automatic, secure and direct transmission of data |
US6201807B1 (en) * | 1996-02-27 | 2001-03-13 | Lucent Technologies | Real-time hardware method and apparatus for reducing queue processing |
US5761507A (en) | 1996-03-05 | 1998-06-02 | International Business Machines Corporation | Client/server architecture supporting concurrent servers within a server with a transaction manager providing server/connection decoupling |
US5809235A (en) | 1996-03-08 | 1998-09-15 | International Business Machines Corporation | Object oriented network event management framework |
US5797043A (en) | 1996-03-13 | 1998-08-18 | Diamond Multimedia Systems, Inc. | System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs |
US5784649A (en) | 1996-03-13 | 1998-07-21 | Diamond Multimedia Systems, Inc. | Multi-threaded FIFO pool buffer and bus transfer control system |
US6199133B1 (en) * | 1996-03-29 | 2001-03-06 | Compaq Computer Corporation | Management communication bus for networking devices |
KR100219597B1 (en) | 1996-03-30 | 1999-09-01 | 윤종용 | Queuing control method in cd-rom drive |
US5956518A (en) * | 1996-04-11 | 1999-09-21 | Massachusetts Institute Of Technology | Intermediate-grain reconfigurable processing device |
US5946487A (en) | 1996-06-10 | 1999-08-31 | Lsi Logic Corporation | Object-oriented multi-media architecture |
KR980004067A (en) | 1996-06-25 | 1998-03-30 | 김광호 | Data Transceiver and Method in Multiprocessor System |
JP3541335B2 (en) | 1996-06-28 | 2004-07-07 | 富士通株式会社 | Information processing apparatus and distributed processing control method |
US5937187A (en) | 1996-07-01 | 1999-08-10 | Sun Microsystems, Inc. | Method and apparatus for execution and preemption control of computer process entities |
US6023742A (en) | 1996-07-18 | 2000-02-08 | University Of Washington | Reconfigurable computing architecture for providing pipelined data paths |
US5745913A (en) | 1996-08-05 | 1998-04-28 | Exponential Technology, Inc. | Multi-processor DRAM controller that prioritizes row-miss requests to stale banks |
US6058465A (en) | 1996-08-19 | 2000-05-02 | Nguyen; Le Trong | Single-instruction-multiple-data processing in a multimedia signal processor |
JP2970553B2 (en) | 1996-08-30 | 1999-11-02 | 日本電気株式会社 | Multi-thread execution method |
US5928736A (en) * | 1996-09-09 | 1999-07-27 | Raytheon Company | Composite structure having integrated aperture and method for its preparation |
US5812868A (en) | 1996-09-16 | 1998-09-22 | Motorola Inc. | Method and apparatus for selecting a register file in a data processing system |
US6072781A (en) * | 1996-10-22 | 2000-06-06 | International Business Machines Corporation | Multi-tasking adapter for parallel network applications |
US5860158A (en) | 1996-11-15 | 1999-01-12 | Samsung Electronics Company, Ltd. | Cache control unit with a cache request transaction-oriented protocol |
US6212542B1 (en) * | 1996-12-16 | 2001-04-03 | International Business Machines Corporation | Method and system for executing a program within a multiscalar processor by processing linked thread descriptors |
US5905876A (en) | 1996-12-16 | 1999-05-18 | Intel Corporation | Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system |
US6073159A (en) * | 1996-12-31 | 2000-06-06 | Compaq Computer Corporation | Thread properties attribute vector based thread selection in multithreading processor |
US5854922A (en) | 1997-01-16 | 1998-12-29 | Ford Motor Company | Micro-sequencer apparatus and method of combination state machine and instruction memory |
US5961628A (en) | 1997-01-28 | 1999-10-05 | Samsung Electronics Co., Ltd. | Load and store unit for a vector processor |
US6256115B1 (en) * | 1997-02-21 | 2001-07-03 | Worldquest Network, Inc. | Facsimile network |
US5742587A (en) | 1997-02-28 | 1998-04-21 | Lanart Corporation | Load balancing port switching hub |
US5905889A (en) | 1997-03-20 | 1999-05-18 | International Business Machines Corporation | Resource management system using next available integer from an integer pool and returning the integer thereto as the next available integer upon completion of use |
US5983274A (en) | 1997-05-08 | 1999-11-09 | Microsoft Corporation | Creation and use of control information associated with packetized network data by protocol drivers and device drivers |
US6092158A (en) * | 1997-06-13 | 2000-07-18 | Intel Corporation | Method and apparatus for arbitrating between command streams |
US6182177B1 (en) * | 1997-06-13 | 2001-01-30 | Intel Corporation | Method and apparatus for maintaining one or more queues of elements such as commands using one or more token queues |
US6006321A (en) * | 1997-06-13 | 1999-12-21 | Malleable Technologies, Inc. | Programmable logic datapath that may be used in a field programmable device |
US6067585A (en) * | 1997-06-23 | 2000-05-23 | Compaq Computer Corporation | Adaptive interface controller that can operate with segments of different protocol and transmission rates in a single integrated device |
US5938736A (en) | 1997-06-30 | 1999-08-17 | Sun Microsystems, Inc. | Search engine architecture for a high performance multi-layer switch element |
US5887134A (en) | 1997-06-30 | 1999-03-23 | Sun Microsystems | System and method for preserving message order while employing both programmed I/O and DMA operations |
US6393483B1 (en) * | 1997-06-30 | 2002-05-21 | Adaptec, Inc. | Method and apparatus for network interface card load balancing and port aggregation |
KR100216371B1 (en) * | 1997-06-30 | 1999-08-16 | 윤종용 | Large scale atm switch with fault tolerant scheme and self routing method in 2nxn multiplexing switches |
US6247025B1 (en) * | 1997-07-17 | 2001-06-12 | International Business Machines Corporation | Locking and unlocking mechanism for controlling concurrent access to objects |
US6170051B1 (en) * | 1997-08-01 | 2001-01-02 | Micron Technology, Inc. | Apparatus and method for program level parallelism in a VLIW processor |
US6014729A (en) | 1997-09-29 | 2000-01-11 | Firstpass, Inc. | Shared memory arbitration apparatus and method |
US6085294A (en) * | 1997-10-24 | 2000-07-04 | Compaq Computer Corporation | Distributed data dependency stall mechanism |
US5915123A (en) | 1997-10-31 | 1999-06-22 | Silicon Spice | Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements |
US6360262B1 (en) * | 1997-11-24 | 2002-03-19 | International Business Machines Corporation | Mapping web server objects to TCP/IP ports |
US6070231A (en) * | 1997-12-02 | 2000-05-30 | Intel Corporation | Method and apparatus for processing memory requests that require coherency transactions |
US5948081A (en) | 1997-12-22 | 1999-09-07 | Compaq Computer Corporation | System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed |
JPH11203860A (en) * | 1998-01-07 | 1999-07-30 | Nec Corp | Semiconductor memory device |
US6415338B1 (en) * | 1998-02-11 | 2002-07-02 | Globespan, Inc. | System for writing a data value at a starting address to a number of consecutive locations equal to a segment length identifier |
US5970013A (en) | 1998-02-26 | 1999-10-19 | Lucent Technologies Inc. | Adaptive addressable circuit redundancy method and apparatus with broadcast write |
US6223238B1 (en) * | 1998-03-31 | 2001-04-24 | Micron Electronics, Inc. | Method of peer-to-peer mastering over a computer bus |
US6079008A (en) * | 1998-04-03 | 2000-06-20 | Patton Electronics Co. | Multiple thread multiple data predictive coded parallel processing system and method |
KR100280460B1 (en) * | 1998-04-08 | 2001-02-01 | 김영환 | Data processing device and its multiple thread processing method |
US6092127A (en) * | 1998-05-15 | 2000-07-18 | Hewlett-Packard Company | Dynamic allocation and reallocation of buffers in links of chained DMA operations by receiving notification of buffer full and maintaining a queue of buffers available |
US6067300A (en) * | 1998-06-11 | 2000-05-23 | Cabletron Systems, Inc. | Method and apparatus for optimizing the transfer of data packets between local area networks |
US6373848B1 (en) * | 1998-07-28 | 2002-04-16 | International Business Machines Corporation | Architecture for a multi-port adapter with a single media access control (MAC) |
US6073215A (en) * | 1998-08-03 | 2000-06-06 | Motorola, Inc. | Data processing system having a data prefetch mechanism and method therefor |
US6347344B1 (en) * | 1998-10-14 | 2002-02-12 | Hitachi, Ltd. | Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor |
US6212611B1 (en) * | 1998-11-03 | 2001-04-03 | Intel Corporation | Method and apparatus for providing a pipelined memory controller |
US6718457B2 (en) * | 1998-12-03 | 2004-04-06 | Sun Microsystems, Inc. | Multiple-thread processor for threaded software applications |
US6389449B1 (en) * | 1998-12-16 | 2002-05-14 | Clearwater Networks, Inc. | Interstream control and communications for multi-streaming digital processors |
US6356692B1 (en) * | 1999-02-04 | 2002-03-12 | Hitachi, Ltd. | Optical module, transmitter, receiver, optical switch, optical communication unit, add-and-drop multiplexing unit, and method for manufacturing the optical module |
US6327650B1 (en) * | 1999-02-12 | 2001-12-04 | Vsli Technology, Inc. | Pipelined multiprocessing with upstream processor concurrently writing to local register and to register of downstream processor |
US6256713B1 (en) * | 1999-04-29 | 2001-07-03 | International Business Machines Corporation | Bus optimization with read/write coherence including ordering responsive to collisions |
US6745317B1 (en) * | 1999-07-30 | 2004-06-01 | Broadcom Corporation | Three level direct communication connections between neighboring multiple context processing elements |
US6668317B1 (en) * | 1999-08-31 | 2003-12-23 | Intel Corporation | Microengine for parallel processor architecture |
US6606704B1 (en) * | 1999-08-31 | 2003-08-12 | Intel Corporation | Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode |
US6427196B1 (en) * | 1999-08-31 | 2002-07-30 | Intel Corporation | SRAM controller for parallel processor architecture including address and command queue and arbiter |
US6532509B1 (en) * | 1999-12-22 | 2003-03-11 | Intel Corporation | Arbitrating command requests in a parallel multi-threaded processing system |
US6694380B1 (en) * | 1999-12-27 | 2004-02-17 | Intel Corporation | Mapping requests from a processing unit that uses memory-mapped input-output space |
US6625654B1 (en) * | 1999-12-28 | 2003-09-23 | Intel Corporation | Thread signaling in multi-threaded network processor |
US6324624B1 (en) * | 1999-12-28 | 2001-11-27 | Intel Corporation | Read lock miss control and queue management |
US6560667B1 (en) * | 1999-12-28 | 2003-05-06 | Intel Corporation | Handling contiguous memory references in a multi-queue system |
US6631430B1 (en) * | 1999-12-28 | 2003-10-07 | Intel Corporation | Optimizations to receive packet status from fifo bus |
US6307789B1 (en) * | 1999-12-28 | 2001-10-23 | Intel Corporation | Scratchpad memory |
US6661794B1 (en) * | 1999-12-29 | 2003-12-09 | Intel Corporation | Method and apparatus for gigabit packet assignment for multithreaded packet processing |
US6584522B1 (en) * | 1999-12-30 | 2003-06-24 | Intel Corporation | Communication between processors |
US6631462B1 (en) * | 2000-01-05 | 2003-10-07 | Intel Corporation | Memory shared between processing threads |
US7007153B1 (en) * | 2000-03-30 | 2006-02-28 | Agere Systems Inc. | Method and apparatus for allocating functional units in a multithreaded VLIW processor |
WO2001095101A2 (en) * | 2000-06-02 | 2001-12-13 | Sun Microsystems, Inc. | Synchronizing partially pipelined instructions in vliw processors |
US6665755B2 (en) * | 2000-12-22 | 2003-12-16 | Nortel Networks Limited | External memory engine selectable pipeline architecture |
US6868476B2 (en) * | 2001-08-27 | 2005-03-15 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
EP1436724A4 (en) * | 2001-09-28 | 2007-10-03 | Consentry Networks Inc | Multi-threaded packet processing engine for stateful packet pro cessing |
US7072970B2 (en) * | 2001-10-05 | 2006-07-04 | International Business Machines Corporation | Programmable network protocol handler architecture |
US6934951B2 (en) * | 2002-01-17 | 2005-08-23 | Intel Corporation | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section |
US7181594B2 (en) * | 2002-01-25 | 2007-02-20 | Intel Corporation | Context pipelines |
-
2002
- 2002-01-17 US US10/053,172 patent/US6934951B2/en not_active Expired - Lifetime
-
2003
- 2003-01-16 EP EP20030731990 patent/EP1470496A2/en not_active Ceased
- 2003-01-16 CA CA002473245A patent/CA2473245A1/en not_active Abandoned
- 2003-01-16 CN CN038023156A patent/CN1618061B/en not_active Expired - Fee Related
- 2003-01-16 WO PCT/US2003/001578 patent/WO2003063018A2/en not_active Application Discontinuation
- 2003-01-16 AU AU2003225523A patent/AU2003225523A1/en not_active Abandoned
- 2003-01-16 KR KR1020037017304A patent/KR100611860B1/en not_active IP Right Cessation
- 2003-01-17 TW TW092100997A patent/TWI265430B/en not_active IP Right Cessation
-
2005
- 2005-03-29 US US11/092,366 patent/US7302549B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050216710A1 (en) | 2005-09-29 |
TWI265430B (en) | 2006-11-01 |
EP1470496A2 (en) | 2004-10-27 |
KR20040017253A (en) | 2004-02-26 |
WO2003063018A2 (en) | 2003-07-31 |
CN1618061A (en) | 2005-05-18 |
US6934951B2 (en) | 2005-08-23 |
CN1618061B (en) | 2010-06-16 |
TW200402631A (en) | 2004-02-16 |
US20030135351A1 (en) | 2003-07-17 |
AU2003225523A1 (en) | 2003-09-02 |
WO2003063018A3 (en) | 2004-04-08 |
US7302549B2 (en) | 2007-11-27 |
KR100611860B1 (en) | 2006-08-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6934951B2 (en) | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section | |
EP1381939B1 (en) | Registers for data transfers within a multithreaded processor | |
US6671827B2 (en) | Journaling for parallel hardware threads in multithreaded processor | |
EP0502680B1 (en) | Synchronous multiprocessor efficiently utilizing processors having different performance characteristics | |
US6587906B2 (en) | Parallel multi-threaded processing | |
EP1242883B1 (en) | Allocation of data to threads in multi-threaded network processor | |
EP1236088B1 (en) | Register set used in multithreaded parallel processor architecture | |
US6944850B2 (en) | Hop method for stepping parallel hardware threads | |
CA2473551C (en) | Context pipelines | |
US9286114B2 (en) | System and method for launching data parallel and task parallel application threads and graphics processing unit incorporating the same | |
EP1504349B1 (en) | Signal aggregation | |
US20050039182A1 (en) | Phasing for a multi-threaded network processor | |
US7191309B1 (en) | Double shift instruction for micro engine used in multithreaded parallel processor architecture | |
WO2001016697A9 (en) | Local register instruction for micro engine used in multithreadedparallel processor architecture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
FZDE | Dead |