CA2205830A1 - A processor for performing shift operations on packed data - Google Patents

A processor for performing shift operations on packed data

Info

Publication number
CA2205830A1
CA2205830A1 CA2205830A CA2205830A CA2205830A1 CA 2205830 A1 CA2205830 A1 CA 2205830A1 CA 2205830 A CA2205830 A CA 2205830A CA 2205830 A CA2205830 A CA 2205830A CA 2205830 A1 CA2205830 A1 CA 2205830A1
Authority
CA
Canada
Prior art keywords
location
packed data
processor
source address
shift operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2205830A
Other languages
French (fr)
Other versions
CA2205830C (en
Inventor
Alexander Peleg
Yaakov Yaari
Millind Mittal
Larry M. Menneneier
Benny Eitan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corporation
Alexander Peleg
Yaakov Yaari
Millind Mittal
Larry M. Menneneier
Benny Eitan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation, Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Menneneier, Benny Eitan filed Critical Intel Corporation
Publication of CA2205830A1 publication Critical patent/CA2205830A1/en
Application granted granted Critical
Publication of CA2205830C publication Critical patent/CA2205830C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants

Abstract

The processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
CA002205830A 1994-12-01 1995-12-01 A processor for performing shift operations on packed data Expired - Fee Related CA2205830C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US34973094A 1994-12-01 1994-12-01
US08/349,730 1994-12-01
PCT/US1995/015682 WO1996017289A1 (en) 1994-12-01 1995-12-01 A novel processor having shift operations

Publications (2)

Publication Number Publication Date
CA2205830A1 true CA2205830A1 (en) 1996-06-06
CA2205830C CA2205830C (en) 2000-08-15

Family

ID=23373704

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002205830A Expired - Fee Related CA2205830C (en) 1994-12-01 1995-12-01 A processor for performing shift operations on packed data

Country Status (9)

Country Link
US (2) US5666298A (en)
JP (2) JPH10512069A (en)
KR (1) KR100252411B1 (en)
AU (1) AU4595596A (en)
BR (1) BR9509841A (en)
CA (1) CA2205830C (en)
DE (1) DE19581873C2 (en)
WO (1) WO1996017289A1 (en)
ZA (1) ZA9510127B (en)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6738793B2 (en) 1994-12-01 2004-05-18 Intel Corporation Processor capable of executing packed shift operations
US6275834B1 (en) * 1994-12-01 2001-08-14 Intel Corporation Apparatus for performing packed shift operations
US7301541B2 (en) * 1995-08-16 2007-11-27 Microunity Systems Engineering, Inc. Programmable processor and method with wide operations
US6295599B1 (en) * 1995-08-16 2001-09-25 Microunity Systems Engineering System and method for providing a wide operand architecture
US5953241A (en) * 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US5742840A (en) 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US6006316A (en) * 1996-12-20 1999-12-21 International Business Machines, Corporation Performing SIMD shift and arithmetic operation in non-SIMD architecture by operation on packed data of sub-operands and carry over-correction
JP3790607B2 (en) * 1997-06-16 2006-06-28 松下電器産業株式会社 VLIW processor
US5864703A (en) 1997-10-09 1999-01-26 Mips Technologies, Inc. Method for providing extended precision in SIMD vector arithmetic operations
US7197625B1 (en) * 1997-10-09 2007-03-27 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US5933650A (en) 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6243803B1 (en) * 1998-03-31 2001-06-05 Intel Corporation Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry
US6098087A (en) * 1998-04-23 2000-08-01 Infineon Technologies North America Corp. Method and apparatus for performing shift operations on packed data
EP1046100A1 (en) 1998-08-06 2000-10-25 Trimedia Technologies, Inc. Data processor and method of processing data
GB0024312D0 (en) 2000-10-04 2000-11-15 Advanced Risc Mach Ltd Single instruction multiple data processing
US7711763B2 (en) 2001-02-21 2010-05-04 Mips Technologies, Inc. Microprocessor instructions for performing polynomial arithmetic operations
US7162621B2 (en) 2001-02-21 2007-01-09 Mips Technologies, Inc. Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
US7599981B2 (en) 2001-02-21 2009-10-06 Mips Technologies, Inc. Binary polynomial multiplier
US7181484B2 (en) * 2001-02-21 2007-02-20 Mips Technologies, Inc. Extended-precision accumulation of multiplier output
US7818356B2 (en) 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
US7685212B2 (en) * 2001-10-29 2010-03-23 Intel Corporation Fast full search motion estimation with SIMD merge instruction
US6986023B2 (en) * 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags
GB2411974C (en) * 2003-12-09 2009-09-23 Advanced Risc Mach Ltd Data shift operations
US20060031272A1 (en) * 2004-08-05 2006-02-09 International Business Machines Corporation Alignment shifter supporting multiple precisions
US8289324B1 (en) 2007-12-17 2012-10-16 Nvidia Corporation System, method, and computer program product for spatial hierarchy traversal
US8502819B1 (en) 2007-12-17 2013-08-06 Nvidia Corporation System and method for performing ray tracing node traversal in image rendering
JP5182053B2 (en) * 2008-12-10 2013-04-10 日本電気株式会社 Barrel shifter device and barrel shift method
US9747105B2 (en) 2009-12-17 2017-08-29 Intel Corporation Method and apparatus for performing a shift and exclusive or operation in a single instruction
US8555036B1 (en) 2010-05-17 2013-10-08 Nvidia Corporation System and method for performing predicated selection of an output register
US8564589B1 (en) 2010-05-17 2013-10-22 Nvidia Corporation System and method for accelerated ray-box intersection testing
US9442731B2 (en) * 2014-03-13 2016-09-13 Intel Corporation Packed two source inter-element shift merge processors, methods, systems, and instructions

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3711692A (en) * 1971-03-15 1973-01-16 Goodyear Aerospace Corp Determination of number of ones in a data field by addition
US3723715A (en) * 1971-08-25 1973-03-27 Ibm Fast modulo threshold operator binary adder for multi-number additions
US4141005A (en) * 1976-11-11 1979-02-20 International Business Machines Corporation Data format converting apparatus for use in a digital data processor
US4161784A (en) * 1978-01-05 1979-07-17 Honeywell Information Systems, Inc. Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands
US4418383A (en) * 1980-06-30 1983-11-29 International Business Machines Corporation Data flow component for processor and microprocessor systems
US4393468A (en) * 1981-03-26 1983-07-12 Advanced Micro Devices, Inc. Bit slice microprogrammable processor for signal processing applications
US4451883A (en) * 1981-12-01 1984-05-29 Honeywell Information Systems Inc. Bus sourcing and shifter control of a central processing unit
US4498177A (en) * 1982-08-30 1985-02-05 Sperry Corporation M Out of N code checker circuit
US4583197A (en) * 1983-06-30 1986-04-15 International Business Machines Corporation Multi-stage pass transistor shifter/rotator
US4653019A (en) * 1984-04-19 1987-03-24 Concurrent Computer Corporation High speed barrel shifter
US4707800A (en) * 1985-03-04 1987-11-17 Raytheon Company Adder/substractor for variable length numbers
JPH073653B2 (en) * 1987-06-30 1995-01-18 三菱電機株式会社 Shifter
US4989168A (en) * 1987-11-30 1991-01-29 Fujitsu Limited Multiplying unit in a computer system, capable of population counting
US4931971A (en) * 1989-01-13 1990-06-05 International Business Machines Corporation Partial decode shifter/rotator
KR920007505B1 (en) * 1989-02-02 1992-09-04 정호선 Multiplier by using neural network
JPH03248226A (en) * 1990-02-26 1991-11-06 Nec Corp Microprocessor
US5327571A (en) * 1990-04-03 1994-07-05 Advanced Micro Devices, Inc. Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right
US5201056A (en) * 1990-05-02 1993-04-06 Motorola, Inc. RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output
US5418915A (en) * 1990-08-08 1995-05-23 Sumitomo Metal Industries, Ltd. Arithmetic unit for SIMD type parallel computer
WO1992009968A1 (en) * 1990-11-27 1992-06-11 Cray Research, Inc. VECTOR WORD SHIFT BY Vo SHIFT COUNT IN VECTOR SUPERCOMPUTER PROCESSOR
US5187679A (en) * 1991-06-05 1993-02-16 International Business Machines Corporation Generalized 7/3 counters
US5408670A (en) * 1992-12-18 1995-04-18 Xerox Corporation Performing arithmetic in parallel on composite operands with packed multi-bit components
US5379240A (en) * 1993-03-08 1995-01-03 Cyrix Corporation Shifter/rotator with preconditioned data
US5477543A (en) * 1994-08-03 1995-12-19 Chromatic Research, Inc. Structure and method for shifting and reordering a plurality of data bytes

Also Published As

Publication number Publication date
US5666298A (en) 1997-09-09
KR100252411B1 (en) 2000-04-15
JPH10512069A (en) 1998-11-17
DE19581873C2 (en) 1999-04-15
ZA9510127B (en) 1996-06-06
DE19581873T1 (en) 1997-12-11
US5818739A (en) 1998-10-06
BR9509841A (en) 1997-11-25
AU4595596A (en) 1996-06-19
JP3924307B2 (en) 2007-06-06
WO1996017289A1 (en) 1996-06-06
CA2205830C (en) 2000-08-15
JP2006172486A (en) 2006-06-29

Similar Documents

Publication Publication Date Title
CA2205830A1 (en) A processor for performing shift operations on packed data
EP1302848A3 (en) A microprocessor having a multiply operation
AU643693B2 (en) Image processor
HK1099095A1 (en) An apparatus and a system for performing operations of multimedia applications and a method for performing the same
CA2168335A1 (en) Virtual addressing buffer circuit
DE69332070T2 (en) Control circuit for Galois field
KR960006396A (en) Multiprotocol Data Bus System
CA2056221A1 (en) Programmable integrated circuit using control data for selecting either serial or parallel data
EP0996267A3 (en) Interface device
DE8904936U1 (en)
KR970078676A (en) Color Correction Device Using Second Order Primary Color Division and Method Thereof
EP0349236A3 (en) Reload-timer/counter circuit
JPS5537609A (en) Terminal equipment
JPS5710846A (en) Information processing equipment
JPS5510620A (en) Output change-over circuit
JPS57164338A (en) Selection circuit for priority
JPS52106628A (en) Information input terminal unit
JPS57157363A (en) Address stop controlling circuit
JPS5730196A (en) Information processor
JPS55138132A (en) Signal processor
KR960009667B1 (en) Common circuit for vesa local bus and isa bus
KR900016857A (en) Clear blue circuit
JPS5374856A (en) Data process system
KR970060160A (en) One-chip circuit for shock control and graphic control
JPS56145422A (en) Terminal device

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20131203