CA2203124A1 - Handling of exceptions in speculative instructions - Google Patents

Handling of exceptions in speculative instructions

Info

Publication number
CA2203124A1
CA2203124A1 CA002203124A CA2203124A CA2203124A1 CA 2203124 A1 CA2203124 A1 CA 2203124A1 CA 002203124 A CA002203124 A CA 002203124A CA 2203124 A CA2203124 A CA 2203124A CA 2203124 A1 CA2203124 A1 CA 2203124A1
Authority
CA
Canada
Prior art keywords
exception
speculative
exceptions
instructions
resolution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002203124A
Other languages
French (fr)
Other versions
CA2203124C (en
Inventor
Gabriel Mauricio Silberman
Kemal Ebcioglu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
Gabriel Mauricio Silberman
Kemal Ebcioglu
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gabriel Mauricio Silberman, Kemal Ebcioglu, International Business Machines Corporation filed Critical Gabriel Mauricio Silberman
Publication of CA2203124A1 publication Critical patent/CA2203124A1/en
Application granted granted Critical
Publication of CA2203124C publication Critical patent/CA2203124C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

CPU overhead is minimized through tracking speculative exceptions (202) for later processing during exception resolution (204) including pointing to the addresses of these speculative instructions, and resolving (204) these exceptions by correcting (206) what caused the exception and re-executing (208) the instructions which are known to be in a taken path. Tracking speculative exceptions has two components which use an exception bit which is set in response to an exception condition (213). The invention tracks an original speculative exception which occurs when a speculative instruction whose operand(s) do not have any exception bits set encounters an exception condition. Speculative exception resolution is triggered when a non-speculative instruction - which is in the taken path of a conditional branch -uses an operand from a register having ist exception bit set. The presence of an exception condition and a non-speculative instruction yields an exception signal (220) to exception resolution (204). Speculative exception resolution (204) includes responding to output signals from the extra register and extra exception bit for correcting (204) the exception condition which caused the exception and re-executing (208) the instructions which depended on the results of the instructions causing the speculative exception.
CA002203124A 1995-01-24 1996-01-09 Handling of exceptions in speculative instructions Expired - Fee Related CA2203124C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/377,563 1995-01-24
US08/377,563 US5799179A (en) 1995-01-24 1995-01-24 Handling of exceptions in speculative instructions
PCT/EP1996/000060 WO1996023254A1 (en) 1995-01-24 1996-01-09 Handling of exceptions in speculative instructions

Publications (2)

Publication Number Publication Date
CA2203124A1 true CA2203124A1 (en) 1996-08-01
CA2203124C CA2203124C (en) 2002-11-19

Family

ID=23489627

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002203124A Expired - Fee Related CA2203124C (en) 1995-01-24 1996-01-09 Handling of exceptions in speculative instructions

Country Status (10)

Country Link
US (1) US5799179A (en)
EP (1) EP0804759B1 (en)
JP (1) JP3093624B2 (en)
KR (1) KR100290269B1 (en)
CN (1) CN1109966C (en)
CA (1) CA2203124C (en)
CZ (1) CZ293714B6 (en)
DE (1) DE69600995T2 (en)
PL (1) PL181901B1 (en)
WO (1) WO1996023254A1 (en)

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US6185668B1 (en) * 1995-12-21 2001-02-06 Intergraph Corporation Method and apparatus for speculative execution of instructions
US5872990A (en) * 1997-01-07 1999-02-16 International Business Machines Corporation Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment
US6505296B2 (en) 1997-10-13 2003-01-07 Hewlett-Packard Company Emulated branch effected by trampoline mechanism
EP1031076A1 (en) * 1997-10-13 2000-08-30 Institute for the Development of Emerging Architectures, L.L.C. Method and apparatus for optimizing execution of load and store instructions
US6044454A (en) * 1998-02-19 2000-03-28 International Business Machines Corporation IEEE compliant floating point unit
US6260190B1 (en) * 1998-08-11 2001-07-10 Hewlett-Packard Company Unified compiler framework for control and data speculation with recovery code
US6301705B1 (en) * 1998-10-01 2001-10-09 Institute For The Development Of Emerging Architectures, L.L.C. System and method for deferring exceptions generated during speculative execution
US6519694B2 (en) 1999-02-04 2003-02-11 Sun Microsystems, Inc. System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity
US6453463B1 (en) 1999-06-07 2002-09-17 Sun Microsystems, Inc. Method and apparatus for providing finer marking granularity for fields within objects
US6513109B1 (en) 1999-08-31 2003-01-28 International Business Machines Corporation Method and apparatus for implementing execution predicates in a computer processing system
US6487716B1 (en) 1999-10-08 2002-11-26 International Business Machines Corporation Methods and apparatus for optimizing programs in the presence of exceptions
US6658555B1 (en) * 1999-11-04 2003-12-02 International Business Machines Corporation Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline
US6766447B1 (en) * 2000-01-25 2004-07-20 Dell Products L.P. System and method of preventing speculative reading during memory initialization
US6631460B1 (en) 2000-04-27 2003-10-07 Institute For The Development Of Emerging Architectures, L.L.C. Advanced load address table entry invalidation based on register address wraparound
US7240186B2 (en) * 2001-07-16 2007-07-03 Hewlett-Packard Development Company, L.P. System and method to avoid resource contention in the presence of exceptions
WO2003032154A1 (en) * 2001-10-08 2003-04-17 Telefonaktiebolaget Lm Ericsson Hidden job start preparation in an instruction-parallel processor system
US7114059B2 (en) * 2001-11-05 2006-09-26 Intel Corporation System and method to bypass execution of instructions involving unreliable data during speculative execution
JP3900485B2 (en) * 2002-07-29 2007-04-04 インターナショナル・ビジネス・マシーンズ・コーポレーション Optimization device, compiler program, optimization method, and recording medium
KR20050085281A (en) * 2002-12-04 2005-08-29 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Software-based control of microprocessor power dissipation
US7263600B2 (en) * 2004-05-05 2007-08-28 Advanced Micro Devices, Inc. System and method for validating a memory file that links speculative results of load operations to register values
CN100451950C (en) * 2004-08-27 2009-01-14 松下电器产业株式会社 Information processing apparatus and exception control circuit
WO2006115219A1 (en) * 2005-04-21 2006-11-02 Matsushita Electric Industrial Co., Ltd. Program illegiblizing device and method
US8024714B2 (en) 2006-11-17 2011-09-20 Microsoft Corporation Parallelizing sequential frameworks using transactions
US7860847B2 (en) * 2006-11-17 2010-12-28 Microsoft Corporation Exception ordering in contention management to support speculative sequential semantics
US8010550B2 (en) 2006-11-17 2011-08-30 Microsoft Corporation Parallelizing sequential frameworks using transactions
JP5154119B2 (en) * 2007-03-26 2013-02-27 テレフオンアクチーボラゲット エル エム エリクソン（パブル） Processor
US8458684B2 (en) * 2009-08-19 2013-06-04 International Business Machines Corporation Insertion of operation-and-indicate instructions for optimized SIMD code
US20110047358A1 (en) * 2009-08-19 2011-02-24 International Business Machines Corporation In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication
US8825982B2 (en) 2010-06-10 2014-09-02 Global Supercomputing Corporation Storage unsharing
US9996348B2 (en) * 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
US11068271B2 (en) 2014-07-28 2021-07-20 Apple Inc. Zero cycle move using free list counts
CN104598808B (en) * 2015-01-08 2018-02-16 中国科学院信息工程研究所 Android application integrity verification methods based on register architecture
US10120656B1 (en) 2017-11-07 2018-11-06 Bank Of America Corporation Robotic process automation system for functional evaluation and improvement of back end instructional constructs
US11416254B2 (en) 2019-12-05 2022-08-16 Apple Inc. Zero cycle load bypass in a decode group
US11436830B2 (en) 2020-03-11 2022-09-06 Bank Of America Corporation Cognitive robotic process automation architecture

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US4539635A (en) * 1980-02-11 1985-09-03 At&T Bell Laboratories Pipelined digital processor arranged for conditional operation
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
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Also Published As

Publication number Publication date
EP0804759B1 (en) 1998-11-18
JP3093624B2 (en) 2000-10-03
CN1136182A (en) 1996-11-20
CZ293714B6 (en) 2004-07-14
US5799179A (en) 1998-08-25
EP0804759A1 (en) 1997-11-05
KR100290269B1 (en) 2001-05-15
JPH08263287A (en) 1996-10-11
PL181901B1 (en) 2001-10-31
DE69600995T2 (en) 1999-07-08
WO1996023254A1 (en) 1996-08-01
CN1109966C (en) 2003-05-28
PL321542A1 (en) 1997-12-08
KR19980701774A (en) 1998-06-25
CZ208497A3 (en) 1997-12-17
DE69600995D1 (en) 1998-12-24
CA2203124C (en) 2002-11-19

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