CA2184064A1 - Transmitter and receiver having charge-coupled-device based signal processing - Google Patents

Transmitter and receiver having charge-coupled-device based signal processing

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Publication number
CA2184064A1
CA2184064A1 CA002184064A CA2184064A CA2184064A1 CA 2184064 A1 CA2184064 A1 CA 2184064A1 CA 002184064 A CA002184064 A CA 002184064A CA 2184064 A CA2184064 A CA 2184064A CA 2184064 A1 CA2184064 A1 CA 2184064A1
Authority
CA
Canada
Prior art keywords
ccd
receiver
signals
digital
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002184064A
Other languages
French (fr)
Inventor
Aaron Weinberg
Kenneth D. Cunningham
Daniel Urban
Mathew S. Simmons
Thomas Land
Martin W. Tucker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2184064A1 publication Critical patent/CA2184064A1/en
Abandoned legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20Modulator circuits; Transmitter circuits
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28Details of pulse systems
    • G01S7/285Receivers
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02BINTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B75/00Other engines
    • F02B75/02Engines characterised by their cycles, e.g. six-stroke
    • F02B2075/022Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
    • F02B2075/027Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle four

Abstract

This invention relates to a novel receiver architecture, the Charge-Coupled-Device Integrated Receiver (IR) (5-10), which simplifies electronic circuitry requirements and reduce baseband processing rates through efficient signal processing. The focus of this receiver's design is its use of Charge-Coupled-Device (CCD) technology (5-11). By using CCD's (5-11), in conjunction with other key technologies, to implement the signal processing techniques disclosed herein, it is possible to provide a receiver that is suitable for a wide range of applications (e.g., communications, sonar, radar, etc.). Information is presented which outlines the fundamental receiver architecture that is appropriate for a wide range of commercial services (e.g., AMPS, NAMPS, Digital Cellular, GSM, PCS, ISM, CTI, CT2, etc.).
Furthermore, the versatility of this architecture makes it suited for uses ranging from simple AM/FM receivers to complex high-order modulation TDMA/CDMA receivers.

Description

Wo gs/24079 ~ t ~ 2 1 8 4 0 6 4 . ~
"TRANSMITTER AND RECEIVER HAVING CHARGE-COUPLED-DEVICE BASED SIGNAL
PROCESSING "
Ba~l~ and Brief Discussion of the Invention As the use of digital communications has increased over the p~st few decades, engineers have been faced with the challenge of building receivers that arQ of a practical size and reasonable cost. nhile driven in the past to reduce size and cost, a large portion of the marketplace was composed of users - such as the military - that required small to moderate quantities of a particular receiver model. In addition, requirements for substantial capability/functionality and extreme environmental/reliability characteristics resulted in receivers that were large and bulky: albeit they were virtually "bullet-proof . ThQ marketplace has now changed and a large part of the user community is composed of the commercial sector. As such, the requirements placed on communication equipment have also changed with increased pressure to meet price points acceptable for high volume product markets. Within this market, simpler receivers with very focused functionality, low power consumption, and reduced size are desired, and the ob~ect of the invention is to provide receivers meeting this criteria.
The receiver disclosed herein is called the Integrated Receiver (IR. ) The name reflects both its inherent nature for overlapping several receiver processes within a common processing path and its amenability for implementation using highly integrated circuitry. The IR's operating advantages stem from its unique signal processing characteristics that are achieved through novel use of charge coupled devices (CCD) technology and integrated tracking loop techniques.
CCD technology has been used for many years. Probably, its most notable application has been in the camera industry.
However, recent advances in CCD design and fabrication have led designers to consider new uses for this technology. For example, see Weinberg et al. U.S. Patent 5,126,682, which relates to a demodulation system incorporating CCD devices, which is incorporated herein by reference. The present invention is SUBSTITUTE SHEET ~ULE 26) W09s/24079 '~!h~ 2~840~4 }~
directed to receivers for communication, sonar and radar applications .
The CCD is a combination of analog and digital circuitry whose properties exploit the best from both worlds. Its analog input matches well with signals provided by receiver front-ends and the device is capable of directly producing a digital output when integr; ted with an A/D converter. Furth~ ~L~, the device may be controlled and clocked digitally thereby providing a natural interface with a system processor. When configured as a transversal filter (see patent 5,126,682), the CCD offers several key features including:
Wide input dynamic range.
Variable clocking speeds.
Variable/fixed tap weights.
Multibit tap weights.
Large number of stages.
Length control.
Auxiliary processing functions.
Given the features noted above, the CCD becomes an extremely useful device for receivers as disclosed herein. Through its proper use, the device can:
. Filter, Demodulate, Store samples, Decimate, Despread, Tune, Amplify/Attenuate, incoming signals. The IR according to this invention exploits the CCD' s features so as to simplify digital signal processing requirements within the receiver.
Description of the Drawinqs The above and other objects, advantages and features of the invention will become more apparent when considered with the SUBSTITUTE SHE~T (RULE 26) Wo9s/24079 ~ ~ 3;`~ "J,, following specification and accompanying drawings wherein:
Figure 1 is a diagrammatic overview of the fundamental Integrated Receiver architecture incorporating the invention, Figure 2 is an overview of the Integrated Receiver signal processing according to the invention, Figure 3 shows the characteristic6 of conventional digital matched filtering and correlation, Figure 4 shows the characteri3tics of CCD matched filtering and correlation, Figure 5 illustrnte6 a CCD-based FM receiver design, Figures 6a, 6b and 6c 6how data, collected from an Integrated Receiver prototype for a CD~A application, that illustrates closure of the three tracking loops (PN, carrier, and symbol) using the common output provided by the matched filter, Figure 7 is an example of an integrated receiver embodiment of the invention designed for a CDMA application, Figure 8 is an overview of the signal processing performed by another embodiment receiver, Figure 9 illustrates the PN acquisition processing performed by receiver incorporating the invention, Figure 10 illustrates the carrier acquisition proce6sing perf ormed by the example receiver incorporating the invention, Figure 11 illustrates the tracking signal processing performed by the example receiver incorporating the invention, Figure 12 is a block diagram of a CCD-based, multichannel GPS
receiver incorporating the invention, Figure 13 is a block diagram of a CCD-based, single channel direct-sequence receiver incorporating the invention, Figure 14 is a block diagram of a CCD-based FH or ~EI/DS
receiver incorporating the invention, and Figure 15 is a block diagram of a CCD-based digital modem incorporating the invention.
Detailed Description of the Invention The specific composition of an Integrated Receiver is very dependent on the targeted application. Data rates, coding requirements, performance (e.g., acquisition speed), SUBSTITUTE SHEET (RULE 26) .. . . . .. . .. .... . ... . _ _ . .

b ` r ~
W0 9:~i/24079 2 1 8 4 0 6 4 FDMA/TDMA/CDMA operation, carrier frequency, tuning range, input dynamic range, configurability, reliability, environment, unit cost, etc. all have a bearing on design selections. Because there are so many variables to consider, the following IR
description is constrained to the most fundamental aspects of the invention .
The undamental IR architecture is depicted in Figure 1. Note that a specific IR implementation might require fewer (or perhaps additional) ~ ts. For instance, downconverter 3 and CCD 4 (and digital signal processor (DSP) 6 in some instances) have a frequency translation capability. As a result, certain applications could have carrier frequency assignments that would preclude one or more of these components while still using IR
signal processing. In contrast to these reductions in IR
complexity, one may to add/enhance components in order to satisfy other requirements. For instance, built-in performance monitoring, higher order modulation (with perhaps frequency hopping), and special interfacing circuitry could all be added within the scope of the IR architecture of this invention.
Antenna 1 and Low Noise Amplifier (INA) 2 form the IR's front end. Their selection is based upon link budget calculations for a specific application. Output from LNA 2 is passed to Downconverter 3. Downconverter 3 can be implemented in many ways. For example, it can translate the received RF by mixing with a fixed or variable local oscillator (LO) from Synthesizer 9. It could also use a sample and hold technique to subsample the RF and produce an aliased signal at the desired IF. In addition to frequency translation, the downconverter can provide gain control and filtering as required.
The IF produced by Downconverter 3 is passed to CCD 4. The CCD
is clocked by Numerically Controlled Oscillator (NCO) 8. The CCD
may also accept tap weights from Digital Signal Processor (DSP) 6 in some applications. The analog output of the CCD is passed to Analog to Digital Converter (A/D) 5. Finally, the digitized signal i8 passed to DSP 6. DSP 6 executes the IR acquisition and tracking algorithms and updates feedback paths to Synthesizer 9 and NCO 8 as needed. Tap weight generation is also performed by SUBSTITUTE SHEET (RULE 26) WO95/2'(079 , ' ~ 21 84064 1~I/IJ~
DSP 6 as well as generating all control signals required for receiver operation. Decoder 7 performs any block or viterbi decoding, descrambling, differential decoding and deinterleaving that may be required.
An overview of the signal proces6ing performed within the IR
architecture of this invention is depicted in Figure 2. This figure illustrates a receiver configuration employing IF
sampling. Note that the single signal path beginning with antenna 10, amplifier 11, and extending through CCD 13 provides all the input necessary to perform the digital signal processing.
This is unlike classical designs that would separate the various acquisition and tracking functions thereby requiring additional circuitry to process the received signal.
Extensive signal processing is accomplished with the CCD. For example, a 512 stage CCD with 256 tapped stages performs the equivalent of about 6 billion floating point multiply/accumulate operations each second when clocked at a 24 MHz rate. This high processing capacity enables the CCD to collapse the bandwidth of its input signal so as to dramatically slow down processing rates of the subsequent digital signal processing. Figures 3 and 4 contrast conventional digital technology and CCD technology for receiver applications.
The following is a summary of the key functions performed by the CCD.
1 ation . Because of the CCD ~ s variable clocking rate, the recovered waveform can be aligned within the CCD so that the tap weights cancel the carrier component. This process acts to demodulate the recovered wavef orm . For example, the carrier component of a 8PSK waveform can be removed by correlating its peaks and zero crossings with tap weights of the form al, O, +a~, O, -a3, O, +a4, O,... Note that this sequence generates both inphase and quadrature components within a single path. In general, the same applies for higher order modulation.
Additionally, discriminators may also be imbedded within the CCD
for d2tection of analog modulated signals. Figure 5 illustrates Hn example of this. Figure 5 shows a single integrated circuit CCD 5-10 having a CCD portion 5-11 having, for example, 500 SUBSTITUTE S~IEET ~F~ULE 26) W09~/24079 !~ 2 1 84064 r~~
stages with the stages being fed to a fixed weighting/6ummer 5-12 whose output is fed to a four stage delay portion 5-13, which, in turn, supplies an FM diseriminator portion 5-14. The analog output is fed to analog-to-digital converter portion 5-15. The output from chip 5-10 is supplied to a digital application specific integrated cireuit chip 5-16. One output is supplied to tuner 5-17, whieh provides a variable sampling rate (48-60 MHz) to the CCD portion 5-11. Thus, this single CCD chip incorporates change domain processing and embeds multiple functions in the single chip and eliminates components. There is no mixing and n~lrrow band filtering. The CCD serves as the downconverter/narrow band-tuned FIR filter, FM discriminator on ehip (charge domain) and the chip incorporates analog-to-digital (A/D) on chip and at a low rate due to CCD pre-processing. The single chip can also serve as the front-end for multiple applications, embedded in tailored application specific~
integrated circuit chips, for example, as in a mono or stereo commercial FM receiver, for sub-carrier processing (e.g., for IVHS). The invention can be used in digital audio broadcast systems employing frequency hopping as disclosed in Schuchman et al. U.S. Patent 5,283,780, incorporated herein by reference.
Filtering. The CCD is a tapped analog delay line. This is the same configuration that is used for correlators and finite impulse response filters. The filter characteristics of this device are det~rmi ned by the tap weights contained in the CCD.
Filtering for PN despreading using ternary tap weights provides a SinX/X roll-of f while multibit tap weights may be used for sharp cut-of f to guard against adjacent channel interference --important for such applications as GSM. Further influencing the filter is the clock rate applied to the CCD which can be used to ad~ust the filter bandwidth and center frequency. Ad~ustment of the filt~ring characteristics by changing the sample rate is an important feature in multichannel applications.
Decimation. Typieally, the CCD is configured to span a portion of a symbol period. In some cases it may be necessary to sample the SUBSTITUTE SHEET (RULE 26) W0 95/24~79 ' ` ~ 1 A ~ 2 1 8 4 0 6 4 ~ U~ .
recovered waveform at a rate much higher than the symbol rate (e.g. CD~ signals where the chip rate det~ n~r; the sample rate). The CCD permits decimation of the waveform by collapsing the output rate of the CCD by a factor that is proportional to the length of the CCD. Thus the CCD may be clocked at a very high rate but its effective output rate is much closer to the actual symbol rate.
Sample Storage. The CCD is capable of holding analog signal samples for relatively long periods of time. This feature enables designers to collect samples at very high rates and then read them from the CCD at substantially lower rates. This can be accomplished by suspending the CCD clock once the samples are collected or by adding sample and hold circuits after the CCD
summation node for the purpose of capturing only selected data.
Despreading. CDMA applications require correlation of a recovered waveform with a locally generated code sequence. While this process is an extremely efiective communication technique, the process of aligning the codes during the initial acquisition phase can be very computationally intensive. The CCD's correlation architecture is well suited for this task.
P1UYL -hle ternary (or higher order) weighting at the taps facilitates code alignment and length control for matching to the data rates of interest.
Tuning. Communication systems with multiple adjacent eh~nn~l~
are quite common. Channel selection is typically accomplished by ad~usting the receiver LO so as to move the desired channel into the pass band. When using IF sampling techniques, the CCD is able to perform this function as well. By adjusting the CCD's clock rate, it is possible to match with the recovered waveform's carrier and thereby select a desired channel. This effectively tunes to filter to match the selected carrier frequency. This process may greatly reduce or even eliminate the need for a variable LOs.
SUBSTITUTE SHEET (RULE 26) W09sl24079 ^ ` r A ~o ~
Amplify/Attenuate. The CCD does much of its signal processing in the analog domain. As such, it is possible to adjust signal levels (and biases ) as needed. Functions such as gain control may benefit from this feature.
Once the recovered waveform exits the CCD, it is digitized and buf fered. The d 1 Ated signal samples are then selectively collected by the DSP. The DSP then processes the samples according to its acquisition and tracking algorithms. Figs. 8-11 disclose novel and very efficient set of algorithms which permit use of a common set of recovered samples so as to simplify the hardware design while achieving excellent receiver perf ormance .
In a spread spectrum application, the receiver would first execute its PN acquisition routine followed by carrier acquisition. Once signal acquisition were cDmpleted, these routines could be disabled and the tracking routines enabled. At this point all three tracking loops begin to close in on the received signal. Figures 6a, 6c and 6c illustrate the ability of the IR to perform this task. Note the Figure 6A is the first to converge thereby commencing coherent carrier tracking. Soon thereafter, the PN tracking loop (Figure 6s) is closed and followed by the symbol sync (Figure 6C. ) Once symbol sync is attained, decoding (if present) is activated and data recovery is initiated. The net affect of this integrated process is faster signal recovery at the start of a service interval while making efficient use of the receiver circuitry.
Figures 7 through 11 depict the architecture and signal processing for a CDMA compatible Integrated Receiver. Note that variations of this example shouLd yield IR designs suitable for TDMA, FD~5A, AM/FM and other communication schemes. The example receiver ( see Figure 7 ) operates at S-band with a 3 MCPS PN code rate and BPSK modulation . The use of f ixed clocks ( thermally controlled crystal oscillatory TCXO) is emphasized in this exAmple so as to reduce synthesizer complexity and to restrict the digital signal processor to a single block to support circuit integ ra t ion ob j ec t ive s .
An overview of the signal processing for the CDMA receiver examples is illustrated in Figure 8. Note that the processing SUBSTITUTE SHEET (RULE 26) , ... . , .. . . , _ _ _ _ _ _ _ _ _ .

WO 9s/24079 t 2 1 8 4 0 6 4 sequence discussed earlier is followed in this example: PN
acquisition, carrier acquisition and f inally signal tracking .
The PN acquisition process is greatly aided by the CCD. In this example (see Figure 9 ), the recovered waveform is sameled at 8 times the PN chip rate. The sample rate is application dependent. Samples rates of twice the chip rate are typical for many applications. The resolution resulting from this sampling yields uncertainty of l/16th of a chip. The samples are collected in a 256 stage accumulation for coherent accumulation over a half 6ymbol duration. The results of coherent accumulation then pass through a squaring operation ( to remove sign) and are then accumulated non-coherently. Finally, the PN
acquisition algorithm selects the largest value of all the correlated states.
Carrier acquisition is initiated following completion of the PN
acquisition process. Inphase (I) and quadrature (Q) samples are collected and squared to remove the data modulation envelope. An FFT of the samples is then taken and the peak of the resulting spectrum is used to identify the location of the carrier. Figure 10 depicts this process.
Once the signal is acquired, signal tracking is initiated.
Figure 11 illustrates this process. Note that the same I, Q
samples used for acquisition are used by all three tracking loops. These samples are first coherently accumulated with the duration of the accumulation determined by the data tracking loop. Output of the accumulator is passed to the complex multiplier where output from a sine/cosine look-up table is used to mix with the samples. This removes the residual carrier and phase components in the recovered signal and yields coherent inphase and quadrature signals. Full symbol accumulation is then performed with the symbol samples distributed to each of the three loops. A Q times sign of I discriminator is used for carrier tracking while a DTTL is used for symbol tracking. The PN tracking loop uses the system~s resolution of 1/16th of a chip to direct its operation. Updates to the local PN clock are made in increments of 1/8th chip duration. The updated local PN clock is used to generate the local code and sample clock which are SUBSTITUTE SHEET (RULE 26) _ _ _ _ _ _ . .. .. _ . _ _ _ , WO 95/24079 ~ 2 1 8 4 ~ 6 4 ~ "~

passed back to the CCD.
Other examples of Integrated Receiver Application are depicted in Figures 12-15. l~ultichannel applications such as GPS (see Figure 12 ) are very appropriate for CCD-based Integrated Receiver designs incorporating the invention. Very simple direct sequence (DS) spread spectrum applications (see Figure 13) are, as discussed in the e~rlier example, well suited for the IR of this invention . Frequency hopped ( FH ) or FH/DS receivers ( see Figure 15 ) may also be developed with the IR approach . Flexible modem design ( see Figure 15 ) can also be handled according to the invention .
Transmitter design can also benefit from the CCD filtering capability. The CCD can filter, modulate, tune, spread, and amplify/attenuate the signal for the purpose of generating a waveform for supplying to a power amplifier and antenna for ~rAncmi fifiiOn .
While preferred ~ flir ts of the invention have been shown and illustrated, it will be appreciated that other embodiments will be readily apparent to those skilled in the art and be t~n~ ~fised by the claims appended hereto.
What Is Claimed Is:

SU~STITUTE Sl IEET (RULE 26)

Claims (12)

11
1. A receiver for receiving and processing communication, sonar, and radar signals, comprising:
means for receiving said signals and producing an analog electrical signal corresponding thereto, a integrated circuit-chip having:
1) a CCD portion connected to receive said analog electrical signals and efficiently reduces and replace selected RF components, selected from mixers, filters, and correlators, (e.g., via MMIC), and efficiently process wide bandwidth signals in a manner not feasible with existing digital technology, and selected of the following functions:
a. demodulate, b. filter, c. store samples, d. decimate, e. despread, f. frequency translation, g. tune, h. amplify/attenuate;
2) an analog-to-digital (A/D) converter portion, and a digital signal processor connected to said A/D converter that integrates all synchronization functions in a single chip with significantly reduced power consumption due to the CCD signal processing.
2. A receiver for receiving and processing communication, sonar, and radar signals, comprising:
means for receiving said signals and producing an analog electrical signal corresponding thereto, a integrated circuit-chip having:
1) a CCD portion connected to receive said analog electrical signals and efficiently reduces a replace selected RF components selected from mixers, filters, and correlators currently employed in conventional receivers (e.g., via MMIC), and efficiently process wide bandwidth signals in a manner not feasible with existing digital technology, and perform at least two of the following functions:
a. demodulate, b. filter, c. store samples, d. decimate, e. despread, f. frequency translation, g. tune, h. amplify/attenuate;
2) an analog-to-digital (A/D) converter, and a utilization device connected to said A/D converter.
3. The receiver defined in claim 2 including a digital signal processor that integrates all synchronization functions in a single chip with significantly reduced power consumption due to the CCD signal processing.
4. A receiver for receiving and processing communication, sonar, and radar signals, comprising:
means for receiving said signals and producing an analog electrical signal corresponding thereto, a single integrated circuit-chip having:
1) a CCD portion connected to receive said analog electrical signals and adapted to perform at least two of the following functions:
a. demodulate, b. filter, c. store samples, d. decimate, e. despread, f. frequency translation, g. tune, h. amplify/attenuate, 2) an analog-to-digital (A/D) converter portion and a utilization device connected to said A/D converter.
5. The receiver defined in claim 4 wherein said CCD portion includes a CCD matched filter to reduce or eliminate RF/IF
circuitry, decimate and provide sample-and-hold, and filtering to said electrical signals.
6. The receiver defined in claim 4 wherein said CCD portion is adapted to perform RF to baseband conversion by sampling at a rate commensurate with the nyquist bandwidth but sub-sampling relative to the RF carrier frequency.
7. The receiver defined in claim 4 wherein said CCD portion is adapted to use a common sample set to achieve signal acquisition and tracking.
8. The receiver defined in claim 4 including a CCD adjustable clock and tap weight update means in conjunction with IF sampling to:
a) achieving PN code alignment, b) achieving carrier alignment, and c) achieving symbol synchronization.
9. The receiver defined in claim 3 wherein said utilization device includes a digital signal processor and said CCD portion includes a matched filter portion and means for IF sampling with the matched filter and programming said digital signal processor to provide an output that can be used for detecting signals of both digital and analog modulation types.
10. The receiver defined in claim 9, adapted for use in a search and rescue application, said CCD portion being adapted to act as a spread spectrum receiver for passing digital messages via satellite during a search operation and then be reconfigured to handle line of sight FM voice communications during the rescue phase, and signaling structures through the course of the search and rescue mission adapted to be very diverse so that much of the same circuitry could be used in all instances so as to realize an extremely efficient and capable design.
11. The receiver defined in claim 4 wherein said CCD portion is adapted for PN tracking by over-sampling relative to the chip rate and updating the tracking loop in fractions of a chip duration thereby eliminating the need for tuning circuitry such as NCOs, VCOs.
12. A transmitter comprised of a single chip having a CCD
portion adapted to filter, modulate, tune, spread, amplify and attenuate a signal and generate a waveform for transmission, and a power amplifier and antennae for receiving said waveform and transmission.
CA002184064A 1994-03-04 1995-02-23 Transmitter and receiver having charge-coupled-device based signal processing Abandoned CA2184064A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/205,496 US5483549A (en) 1994-03-04 1994-03-04 Receiver having for charge-coupled-device based receiver signal processing
US08/205,496 1994-03-04

Publications (1)

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CA2184064A1 true CA2184064A1 (en) 1995-09-08

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EP (1) EP0748539A1 (en)
JP (1) JPH09510055A (en)
AU (1) AU689867B2 (en)
BR (1) BR9506990A (en)
CA (1) CA2184064A1 (en)
FI (1) FI963443A (en)
WO (1) WO1995024079A1 (en)

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US5483549A (en) 1996-01-09
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EP0748539A1 (en) 1996-12-18
AU1968595A (en) 1995-09-18

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