CA2153918A1 - Switch element for fibre channel networks - Google Patents
Switch element for fibre channel networksInfo
- Publication number
- CA2153918A1 CA2153918A1 CA002153918A CA2153918A CA2153918A1 CA 2153918 A1 CA2153918 A1 CA 2153918A1 CA 002153918 A CA002153918 A CA 002153918A CA 2153918 A CA2153918 A CA 2153918A CA 2153918 A1 CA2153918 A1 CA 2153918A1
- Authority
- CA
- Canada
- Prior art keywords
- port
- fabric
- channel
- fiber optic
- switch module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/2852—Metropolitan area networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/44—Star or tree networks
Abstract
A system for facilitating data communications in a fibre channel network is presented. The system comprises a fiber optic switch element which enables implementation of a Fibre Channel network by permitting selective interconnection of a plurality of fiber optic channels. The fiber optic switch element permits both circuit and frame switching. The switch element comprises a switch module which is connected to at least one fabric-port within the fibre channel fabric.
The switch module allocates switching bandwidth. A path allocation system, whichis connected to the switch module, generally directs frames of data between the at least one fabric-port to other fabric-ports located within the fabric. A channel module comprising a port intelligence mechanism is disposed between the switch module and the fabric-ports. An element controller provides centralized fabric management.
The switch module allocates switching bandwidth. A path allocation system, whichis connected to the switch module, generally directs frames of data between the at least one fabric-port to other fabric-ports located within the fabric. A channel module comprising a port intelligence mechanism is disposed between the switch module and the fabric-ports. An element controller provides centralized fabric management.
Description
-SWITCII ELEMENT FOR FlBRE CIIANNEL NETWORKS
CROSS REFERENCE TO RELATED APrLlCATlONS
The following applications of common assignee contain some common disclosure, and are believed to have an effective filing date identical with that of the present invention:
PATH ALLOCATION SYSTEM AND METHOD HAVING
DOUBLE LINK LIST QUEUES IMPLEMENTED WITH A
DIGlTAL SlGNAL PROCESSOR (DSP) FOR A HIGH
PERFORMANCE FIBER OPTIC SWITCH, Serial Number (Attorney Docket Number HP-1094784);
HIGH PERFORMANCE PATH ALLOCATION SYSTEM
AND METHOD FOR A FIBER OPTIC SWITCH FOR A
FIBER OPTIC NETWORK, Serial Number (Attorney Docket Number HP-1094788);
HIGH PERFORMANCE PATH ALLOCATION SYSTEM
AND METHOD WITH FAIRNESS INSURANCE
MECHANISM POR A FIBER OPTIC SWITCH, Serial Number (Attorney Docket Number HP-1094967);
CHANNEL MODULL FOR A FIBER OPTIC SWITCH WlTH
BIT SLICED MEMORY ARCHITECTURE FOR DATA
FRAME STORAGE, Serial Number (Attorney Docket Number HP-1094775);
The disclosures of the above referenced applications are incorporated by reference herein as if set forth in full below.
HP CASE# 1094780 FIELD OF TI~E INVENTION
The present invention relates generally to high speed data communications networks and more particularly to a switch mechanism for controlling the flow of data on a fibre channel network.
s BACKGROUND OF TI~E INVENTION
Mainframes, super computers, mass storage systems, workstations and very high resolution display s~lbsystems are freqllently connected together to facilitate file and print sharing. Common networks and cllannels used for these types of connections oftentimes introduce communications bottlenecking, especially in cases where the data is in a large file format typical of graphically-based applications.
There are two basic types of data communications connections between processors, and between a processor and peripherals. A "channel" provides a direct or switched point-to-point connection between communicating devices. The channel's primary task is merely to transport data at the highest possible data rate with the least amount of delay. Channels typically perform simple error correction in hardware.A "network," by contrast, is an aggregation of distributed nodes (e.g., workstations, mass storage units) with its own protocol that sllpports interaction among these nodes.
Typically, each node contends for the transmission medium, and eacll node must be capable of recognizing error conditions on the network and must provide the error management required to rccover from the error conditions One type of communications inlerconnect that has been developed is Fibre Channel. The Fibre channel protocol was developed and adopted as the American National Standard for Information Systems (ANSI). See Fibre C/7annel r'llysical and Signalling In~e)~ace, Revision 4.2, American National Standard for Information Systems (ANSI) (1993) for a detailed discussion of the fibre channelstandard. Briefly, fibre channel is a switched protocol that allows concurrent communication among workstations, super computers and various peripherals. The total network bandwidth provided by fibre channel is on the order of a terabit per HP CASE~Y 1094780 ~la3~18 -second. ~ibre channel is capable of transmitting data frames at rates exceeding 1 gigabit per second in both directions simultaneously. It is also able to transport existing protocols such as internet protocol (IP), small computer system interface (SCSI), high performance parallel interface (HIPPI) and intelligent peripheral interface (IPI) over both optical flber and copper cable.
Essentially, the ~Ibre channel is a channel-network hybrid, containing enough network features to provide the needed connectivity, distance and protocol multiplexing, and enough channel features to retain simplicity, repeatable performance and reliable delivery. Fibre channel allows for an active, intelligent interconnection scheme, known as a "fabric," to connect devices. A fabric is an entity that intercollllecls various node-ports (N~orts) attached to the fabric. The fabric has the capability of routing data frames based upon information contained within the frames as specified by a class of service. The N port simply manages the simple point-to-point connection between itself and the fabri~. That transmission is isolated from the control protocol so that different topologies (e.g., point-to-point links, rings, multidrop buses, crosspoint switches) can be implemented. The fabric is self-managed so that N ports do not need station management functionality, greatly simplifying system implementation.
SUMMARY OF T~E lNVENTlON
The present invention provides a novel switch element for a fiber optic network. The fiber optic switch element enables implementation of a fibre channel network by permitting selective interconnection of a plurality of fiber optic channels.
The fiber optic switch permits both circuit and frame switclling. Circuit switching enables data transfer on a dedicated connection. In the circuit-switched mode, adedicated path between two N ports is established before data transfer occurs. This dedicated palh is maintained until either of llle two N ports disconnects. I~rame switclling is a connectionless data lransfer mode in which the bandwidth is dynamically allocated on a fMme-by-frame basis.
HP CASE~ 1094780 ~ ~ ~391 ~
The fiber optic switch element comprises a switch module which is connected to a fabric-port (F port) within the flbre channel fabric through a channel control box. The switch module allocates switching bandwidth. A path allocation system, which is connected to the switch module, generally directs frames between F_ports through the switch module. The path allocation system is essentially a specialized multi-processor subsystem for lhe allocation and control of switching and pOn resources. An element controller, which is connected to the path allocation system and switch module, provides centralized fabric management.
A plurality of ports are associated respectively with the plurality of fber optic channels of the network. Each of the ports has a co.les~,onding port intelligence mechanism, which comprises a transmitter and a receiver. The port intelligence mechanisms are located within the channel control box. The channel control box also comprises a memory interface system which has receive memory and is associated witll the plurality of the port intelligence mech~nisms (or ports) for m temporarily storing incoming new data frames from source ports for class 2 data transfers (frame switching). The memory interface system has bypass paths for class I data transfers (circuit switching).
The switch module includes, among other things, a main distribution network (MDN), an intermix distribution network (IDN), and a control distribution network (CDN). The switch module and the data passed through the switch module are controlled by the path allocation system. The path allocation system comprises an arbitrator and a scheduler. The scheduler maintains a d~stin~tion queue corresponding with each of the ports. Each queue is configured to store queue entries specifying data destined for its corresponding port. Each queue entry comprises a source port indicator which identi~les a source channel module and a buffer indicator which identifies a particular buffer within the receive memory of the source channel module, where the data frame can be found. The arbitrator ultimately controls data transfers through the switcll module and commllnicates with the scheduler and the port intelligence mechanisms. The arbitrator determines when the ports are available HP CASE# 1094780 ~5391~
or are busy servicing other data transfer requests. If available, the arbitrator allows communication (class 1 transfer or class 2 transfer) of the data between ports via the MDN or IDN of the switch module.
BRlEF DESCRIPTION OF T~IE DRAWINCS
FIG. la shows a block diagram of a lel)resentative Fibre Channel architecture.
FIG lb shows the frame protocol of the Fibre Channel.
FIG. 2 shows a block diagram of a fiber optic switch element according to the present invention.
FIG. 3 shows a more detailed block diagram of the fiber oplic switch element.
FIG. 4 shows a block diagram of the channel module in FIG. 3.
FIG. 5 shows a more detailed block diagram of the channel module.
FIG. 6 shows a block diagram of the path allocation system in FIG. 3.
DETAILED DESCR~I'TION OF T~E rREFERRED EMI~Or)llVlENT
Briefly, the present invention provides a fiber optic switch element based upon a parallel, non-blocking, cross-point architecture with centralized control.
The switch element supports both circuit- and frame-switched connections for multiple baud rate interfaces.
As used herein, these terms and phrases are defined as follows:
Class 1 service-- a circuit-switched connection;
Class 2 service-- a connectionless, frame-switched link providing guaranteed delivery and receipt noti~lcation;
Class 3 service-- a connectionless service with no con~lrmation;
F~ort-- "fabric" port, the access point of the Fabric for physically connecting N~orts;
HP CASE# 1094780 Fabric-- a Fibre Channel-defined interconnection methodology that handles routing in Fibre Channel networks;
Frame-- a linear set of tMnsmitted bits that deflne a basic transport element;
s Intermix-- a class of service lhat provides functionality of both Class I and 2,Intermix reserves the full channel for a Class 1 conl1ection while allowing Class 2 traffic to pass on unused bandwidth;
Link-- a communications channel;
N_port-- "node" port, a Fibre Channel-defined hardware entity at the node end of a link.
Refer now to FIG. la which shows a block diagram of a rep-~s~nt~tive fibre channel architecture. A fibre channel network 100 is presented. A workstation 120, a mainframe 122 and a super computer 124 are interconnected with various subsystems (e.g., a tape subsystem 126, a disk subsystem 128, and a display subsystem 130) via a fibre channel fabric 110. The fabric 110 is an entity that interconnects various node-ports (N_ports) attached to the fabric 110. The essential function of the fabric 110 is to receive frames of data from a source N_port and, using a first protocol, route the frames to a destination N_port. In a preferredembodiment, the first protocol is thc rlbre channel protocol. Olher protocols, stlch as the asynchronous transfer mode (ATM) could be used without departing from thescope of the present invention.
Each of the various systems and subsystems (e.g., the workstation 120, the tape subsystem 126) connected to the rlbre channel fabric 110 comprises an associated N-port 140. The N port is a hardware entity at ~he node end of a link.
The F-port 142 is the access point of the fabric 110 for physically connecting the various N-ports 140. The fabric 110 has the capability of routing data frames (see FIG. lb below) based upon information contained within the fMmes as specified bya class of service. The N_port simply manages the simple point-to-point connection between itself and the fabric 110. That transmission is isolated from the control HP CASE# 1094780 2~ 918 protocol so that different topologies (e.g., point-to-point links, rings, multidrop buses, crosspoint switches) can be implemented. The fabric 110 is self-managed so that N_ports do not need station management functionality, greatly simplifying systemi mplementation .
FIG lb shows tlle frame protocol of the fibre channel. In a preferred embodiment, the protocol can be up to 2,148 bytes wide, depending llpon the size of the payload. A frame 180 is the smallest indivisible packet of data that is sentthrough a fibre channel network. Addressing of the frame 180 is done within the frame header 182 which is 24 bytes long. Frames are not visible to the upper-level protocols and consist of the following fields:
a start-of-frame delimiter (4 bytes);
a frame header (24 bytes);
optional headers (64 bytes);
a variable-length payload containing user data (from 0 to 2048 bytes);
a cyclic redundancy check error check (4 bytes); and an end-of-frame delimiter (4 bytes).
The frame header 182 can be further defined as shown. The addressing of the frame 180 is accomplished using a source address (SOURCE_ADDR) and destination address (DESTINATION ADDR). Each connected N_port has a unique address identifier. The length of the user data that is encapsulated within the frame 180 is defined within the header 182 under the LENGTH field.
FIG. 2 shows a block diagram of a fber optic switch element according to the present invention. Tlle fber optic switch element 200 enables implementation of a rlbre channel network by permitting selective interconnection of a plurality of fiber optic channels (not shown). The rber optic switch 200 permits both circuit and frame switching. Circuit switching enables data transfer on a dedicated connection. In lhe circuit-swi~che~ mode, a dedicated palh between twoN_ports is established before data transfer occurs. This dedicated palh is maintained unlil eilher of the two N ports disconnects. Prame switching is a connectionless data IIP CASE~ 1094780 ~1~3918 transfer mode in which the bandwidth is dynamically allocated on a frame-by-frame basis.
A switch module 220 is connected to an F_port wi~hin the fibre channel fabric through a channel control box 210. The switch module 220 is responsible for core switching bandwidth. A path allocation system 230, which is connected to the switch module 220, generally directs frames between F_ports (logically located within the channel control box 210) through the switch module 220. The path allocation system 230 is essentially a specialized multi-processor subsystem for the allocation and control of switching and port resources. FMme switclling requires a relatively large amount of buffering while circuit switching requires pre-allocation of switching bandwidth. To accomplisll both, the fiber optic switch element 200 provides local buffering at the cllannel control box 210 with centralized routing hardware in the path allocation system 230. In a preferred embodiment, there are two modes of buffering.
The first mode is known as "cut-tllrougll" mode bufrering. Cut-through mode allows frame data to be read as the frame is being written to lhe buffer. This mode facilitates faster routing of the data frames through tlle switcll element 200. The channel control box 210 typically operates under the cut-through mode. The second mode is known as "store-and-forward" mode buffering. This mode resembles the more standard type of buffering in which the entire frame is written to the buffer before it can be read out. The store-and-forward mode is typically used during intermix operalion, for example.
An element controller 240, which is connected to the path allocation system 230 and switch module 220, provides centralized fabric management. A
feature of the element controller 230 is an embedded port to communicate with N~orts.
FIG. 3 shows a more detailed block diagram of the fiber optic switch element 200. The fiber optic switch 200 has a plurality of channel modules 304 to which the fiber optic channels 302 are connected via respective ports p~ through pj.
In a preferred embodiment, there are 4 channel modules, each providing a 266 HP CASEiY 1094780 21~3~1~
MBaud bi-directional path into the fabric. Other configurations can be implemented without departing from the scope of the present invention. ~or example, two 531 MBaud channel modules or a single 1063 MBaud channel module could be used.
Each channel module 304is connected to one or more of tlle fiber optic channels 302 and provides port intelligence as well as receive memory for temporarily storing data frames. The channel modules 304 are connccted to the switch module 220, which distributes electrical energy from a power supply 306 via connection 308.
In the preferred embodiment, the switch module 220 is implemented as part of a back plane; a number of functional interface elements are disposed upon the back plane.
The switch module 220 has a shlus multiplexer (MUX) 310 which is configured to receive stahls signals from the channel module 304 concerning the fiber optic channels 302. A main distribu~ion network (MDN) 312 selectively interconnects the data paths of the channels 302. In a preferred embodiment, the MDN 312 is a 16xl6 non-blocking crosspoint swilch. A control distribution network (CDN) 314 communicates control signals to the various cllannel modules 304. ~or example the C D N 314 informs channel modules when a data frame may be sent. An intermix distribution network (IDN) 316 selectively interconnects intermix paths between channel modules 304. Intermix paths are a set of alternate data paths which are separate from those data paths associated with lhe MDN 312 and which can permit dah flow between sclected channels 302 while d~ta paths of the MDN 312 are in use.
In a preferred embodiment, both the CDN 314 and the IDN 316 are implemented by a 8x8 crosspoint switch. Finally, a processor (uProc) selector 318 can optionally be provided as part of an auxiliary system for interconnecting processors and controllers distribu~ed throughout the fiber optic switch 200. Additionally, the uProc selector 318 facilihtes "off-line" service of the switch 200.
The path allocation system 230 is connected to the switch module 220 and, particularly, to the status MUX 310, the MDN 312, the CDN 314 and the IDN
316. The path allocation system 230 generally allocates dah interconnect paths between fiber optic cl-annels 302 and determines the priority of lhe connections. The HP CASE# 1094780 9 1 ~
path allocation system 230 is a significant element of the present invention andbecause of its design, results in very desirable performance attributes with minimum hardware requirements (see PIG. 6).
Also connected to the switch module 230 is an element controller (EC) 240. The EC 240 essentially provides servers (e.g., a name server, a time server) for the fiber optic switch element 200. The EC 240 has a data link 340 with the path allocation system 230 for communicating server information and a status/control conneclion 342 for exchanging status/control signals with the path allocation system 230. The EC 240 also exchanges server information with the IDN 316 and the processor selector 318 via respective links 342,344. Data link 342 provides an embedded port into the element controller 240. The embedded port behaves essentially as an N port wl1ich can be addressed as if it were another system connected to the switch 200. The embedded port facilitates operator control of the switch element 200. l~or example, when a system such as a workstation plugs intothe switch for the first time, the system will attempt to communicate with the switch 200 by logging on. The embedded port will send switch configuration information back to the new system and will provide information indicative of the other systems and subsystems that are already connected to lhe switch 200.
The EC 240 comprises a microprocessor and various memory elements including a flash EPROM, RAM and a Boot ROM. The Boot ROM stores a Boot Manager and self-test software for the EC 240. The flask EPROM is used to store an operating system, such as VxWorks, available from Wind River Systems, U.S.A.,and additional firmware for the switch module and path allocation system. In a preferred embodiment, the microprocessor within the EC 240 is a model i960CA, manufactured by Intel.
FIG. 4 shows a block diagram of the channel module in FIC. 3. The channel module 304 comprises a port intelligence system 410 and a memory interface system 420. In a preferred embodiment, the channel module 304 provides a 1063 MBaud bi-directional path into the fabric.
HP CASE~ 1094780 9 1 ~
-The port intelligence system 410 comprises at least one transceiver and a first application-specific integrated circuit (ASIC). Essentially, the port intelligence system 410 provides port intelligence adapted to transmit and receive data according to a specific protocol, preferably ~Ibre cllannel, associated with the fiber optic channel 302. The port intelligence system 410 is interchangeable to accommodate a variety of protocols, such as asynchronous transfer mode (ATM). Additionally, the port intelligence system 410 can be adapted to be hooked up to channels with different bit rates. A conventional optical link card (OLC), such as an OLC266 manufactured byIBM, can be utilized to directly interface the port intelligence system 410 to the fiber optic channel 302. In a preferred embodiment, the first ASIC is configured to support three modes of operation: 266-, 531- and 1063-MBaud data transfer.
The memory interface system 420 comprises at least one frame burfer and a second ASIC which is configured differently from tlle first ASIC in tlle port intelligence system 410. The frame buffer may be random access memory with bit-sliced organization. Additionally, separate receive buffers and transmit buffers may be used. The second ASIC is a bit-sliced chip for memory management and is responsible for connecting the memory interface system 420 to tlle internal switcl data paths via the main link 320 and the intermix link 322.
FIG. 5 shows a more detailed block diagram of the channel module of FlGs. 3 and 4. The port intelligence system 410 has one or more port intelligence mechanisms 502. One port intelligence mechanism 502 is allocated to each fiber optic channel 302. Each port intelligence mechanism 502 has a receiver (RX) 504,a transmitter (TX) 506, an optical link card (OLC) 508, and a status/control (STAT/CNTL) logic 510. The receiver 504 and the transmitter 506 are adapted to receive and transmit data, respectively, through their co~ 1~ sponding input and output fibers 501, 502 (shown collectively in FIG. 3 as channel 302) in accordance with the Fibre Channel industry standard protocol and at the channel's particular bit rate.
The OLC 508 is utilized to directly interface the port intelligence mechanism 502 to the ~Iber optic channel 302. The OLC 508 provides an optical-to-electrical HP CASE# 1094780 39l~
-conversion as well as a serial-to-parallel conversion between the input fiber 501 of the channel 302 and the receiver 504. Furthermore, the OLC 508 provides an electrical-to-optical conversion as well as a parallel-to-serial conversion between the output fiber 502 of the channel 302 and the transmitter 506.
The status/control logic 510 monitors and controls both the receiver 504 and the transmitter 506, as indicated by co~s~onding bidirectional control connec~ions 511,512. Further, the status/control logic 510 exchanges control signals on control connection 324 with the CDN (item 314 in FIG. 3), provides status signals on connection 326 to the status MUX (item 310 in FIG. 3) indicative of, e.g., whether the co~e~lJoIlding port (p, lhrough p~ is available or busy, and forwards control signals to the memory interface system 420 via connection 432. The status/control logic 510 further recognizes when a new frame is received by the receiver 504 and determines the transfer class (either 1 or 2) as well as the length of data pertaining to each new frame. It should be noted that a frame could have no data, as for example, in the case of an SOFcl frame (i.e., a start of frame for class 1 service), which is initially passed through the switch 200 for setting the switch 200 up to reserve a bidirectional path for a class 1 data transfer.
The memory interface system 420 is connected in series, or caccadecl, with the port intelligence system 410, and particularly, with each port intelligence mechanism 502 contained therein. l he men~ory interface system 420 generally provides class 1 bypass data connections 530,532 for class 1 data transfers and provides temporary storage for class 2 dala transfers. For data slorage relative to class 2 data transfers, the memory interface system 420 has a receive memory (RX MEMORY) 520 for source data, a transmit memory (TX MEMORY) 522 for destination data, and memory control logic 524 for conlrolling lhe receive and transmit memories 520,522.
The receive memory 520 and the transmit memory 522 may be partitioned into a number of individual buffers or memory blocks, if desired.
FIG. 6 shows a block diagram of tl-e palh allocation system in FIG. 3.
The path allocation system 230 communicates with the channel module(s) (item 304 HP CASE~ 1094780 ~ ~3918 in FIGs. 3 and 4) and the element conlroller (EC) (item 240 in FIG. 3) via the control distribution network (CDN) (item 314 in FIG. 3). Basically, the path allocation system 230 controls all switching bandwidth wilhin the fiber optic switch element and directs all frame flow. In addition to managing port and switch resources for allocating frame data paths througl1 the fiber optic switch, lhe path allocation system 230 collects frame header infomlation, validatcs each framc based upon the header informalion~ initiales frame-reject (I~RJT) ~lags for discrepant frames, initiates frame-busy (FBSY) flags for frames which cannot be delivered within a predetermined time-out value and collects performance stalistics for lhe elementcontroller.
The path allocation system 230 allocates the data paths through the switch module 220. A sequencer 650 is connected to the CDN (item 314 in ~IG. 3) via a control connection 651. A sentry 610 communicates to the CDN 314 via the control connection 611 and is connected to the sequencer 650. A timer 630 communicates to the sentry 610 and glue logic 660. The glue logic 660 communicates control signals with the sentry 610 via the control connection 661, and communicates control signals to the sequencer 650 via tlle control connection 662.
The scheduler 642 maintains a plurality of destination queues (Qp,-Qp;) 643 which co-le~,ond respectively with each of the ports (pl through p~ in FIG. 3. The scheduler 642 communicates with the glue logic 660.
An arbitrator 640 is connected to the scheduler 642, the glue logic 660, and the sequencer 650. The arbitralor 640 also communicates to the MDN and IDN
(items 312 and 316 in FIG. 3 respectively). A closer 620 monitors the sequencer 650 and receives control signals from the CDN via the control connection 621. The closer 620 also communicates an EC interface (not shown) which in turn communicates to the sentry 610, the arbitrator 640, and the elelllent controller (EC) (item 240 in FIG.
CROSS REFERENCE TO RELATED APrLlCATlONS
The following applications of common assignee contain some common disclosure, and are believed to have an effective filing date identical with that of the present invention:
PATH ALLOCATION SYSTEM AND METHOD HAVING
DOUBLE LINK LIST QUEUES IMPLEMENTED WITH A
DIGlTAL SlGNAL PROCESSOR (DSP) FOR A HIGH
PERFORMANCE FIBER OPTIC SWITCH, Serial Number (Attorney Docket Number HP-1094784);
HIGH PERFORMANCE PATH ALLOCATION SYSTEM
AND METHOD FOR A FIBER OPTIC SWITCH FOR A
FIBER OPTIC NETWORK, Serial Number (Attorney Docket Number HP-1094788);
HIGH PERFORMANCE PATH ALLOCATION SYSTEM
AND METHOD WITH FAIRNESS INSURANCE
MECHANISM POR A FIBER OPTIC SWITCH, Serial Number (Attorney Docket Number HP-1094967);
CHANNEL MODULL FOR A FIBER OPTIC SWITCH WlTH
BIT SLICED MEMORY ARCHITECTURE FOR DATA
FRAME STORAGE, Serial Number (Attorney Docket Number HP-1094775);
The disclosures of the above referenced applications are incorporated by reference herein as if set forth in full below.
HP CASE# 1094780 FIELD OF TI~E INVENTION
The present invention relates generally to high speed data communications networks and more particularly to a switch mechanism for controlling the flow of data on a fibre channel network.
s BACKGROUND OF TI~E INVENTION
Mainframes, super computers, mass storage systems, workstations and very high resolution display s~lbsystems are freqllently connected together to facilitate file and print sharing. Common networks and cllannels used for these types of connections oftentimes introduce communications bottlenecking, especially in cases where the data is in a large file format typical of graphically-based applications.
There are two basic types of data communications connections between processors, and between a processor and peripherals. A "channel" provides a direct or switched point-to-point connection between communicating devices. The channel's primary task is merely to transport data at the highest possible data rate with the least amount of delay. Channels typically perform simple error correction in hardware.A "network," by contrast, is an aggregation of distributed nodes (e.g., workstations, mass storage units) with its own protocol that sllpports interaction among these nodes.
Typically, each node contends for the transmission medium, and eacll node must be capable of recognizing error conditions on the network and must provide the error management required to rccover from the error conditions One type of communications inlerconnect that has been developed is Fibre Channel. The Fibre channel protocol was developed and adopted as the American National Standard for Information Systems (ANSI). See Fibre C/7annel r'llysical and Signalling In~e)~ace, Revision 4.2, American National Standard for Information Systems (ANSI) (1993) for a detailed discussion of the fibre channelstandard. Briefly, fibre channel is a switched protocol that allows concurrent communication among workstations, super computers and various peripherals. The total network bandwidth provided by fibre channel is on the order of a terabit per HP CASE~Y 1094780 ~la3~18 -second. ~ibre channel is capable of transmitting data frames at rates exceeding 1 gigabit per second in both directions simultaneously. It is also able to transport existing protocols such as internet protocol (IP), small computer system interface (SCSI), high performance parallel interface (HIPPI) and intelligent peripheral interface (IPI) over both optical flber and copper cable.
Essentially, the ~Ibre channel is a channel-network hybrid, containing enough network features to provide the needed connectivity, distance and protocol multiplexing, and enough channel features to retain simplicity, repeatable performance and reliable delivery. Fibre channel allows for an active, intelligent interconnection scheme, known as a "fabric," to connect devices. A fabric is an entity that intercollllecls various node-ports (N~orts) attached to the fabric. The fabric has the capability of routing data frames based upon information contained within the frames as specified by a class of service. The N port simply manages the simple point-to-point connection between itself and the fabri~. That transmission is isolated from the control protocol so that different topologies (e.g., point-to-point links, rings, multidrop buses, crosspoint switches) can be implemented. The fabric is self-managed so that N ports do not need station management functionality, greatly simplifying system implementation.
SUMMARY OF T~E lNVENTlON
The present invention provides a novel switch element for a fiber optic network. The fiber optic switch element enables implementation of a fibre channel network by permitting selective interconnection of a plurality of fiber optic channels.
The fiber optic switch permits both circuit and frame switclling. Circuit switching enables data transfer on a dedicated connection. In the circuit-switched mode, adedicated path between two N ports is established before data transfer occurs. This dedicated palh is maintained until either of llle two N ports disconnects. I~rame switclling is a connectionless data lransfer mode in which the bandwidth is dynamically allocated on a fMme-by-frame basis.
HP CASE~ 1094780 ~ ~ ~391 ~
The fiber optic switch element comprises a switch module which is connected to a fabric-port (F port) within the flbre channel fabric through a channel control box. The switch module allocates switching bandwidth. A path allocation system, which is connected to the switch module, generally directs frames between F_ports through the switch module. The path allocation system is essentially a specialized multi-processor subsystem for lhe allocation and control of switching and pOn resources. An element controller, which is connected to the path allocation system and switch module, provides centralized fabric management.
A plurality of ports are associated respectively with the plurality of fber optic channels of the network. Each of the ports has a co.les~,onding port intelligence mechanism, which comprises a transmitter and a receiver. The port intelligence mechanisms are located within the channel control box. The channel control box also comprises a memory interface system which has receive memory and is associated witll the plurality of the port intelligence mech~nisms (or ports) for m temporarily storing incoming new data frames from source ports for class 2 data transfers (frame switching). The memory interface system has bypass paths for class I data transfers (circuit switching).
The switch module includes, among other things, a main distribution network (MDN), an intermix distribution network (IDN), and a control distribution network (CDN). The switch module and the data passed through the switch module are controlled by the path allocation system. The path allocation system comprises an arbitrator and a scheduler. The scheduler maintains a d~stin~tion queue corresponding with each of the ports. Each queue is configured to store queue entries specifying data destined for its corresponding port. Each queue entry comprises a source port indicator which identi~les a source channel module and a buffer indicator which identifies a particular buffer within the receive memory of the source channel module, where the data frame can be found. The arbitrator ultimately controls data transfers through the switcll module and commllnicates with the scheduler and the port intelligence mechanisms. The arbitrator determines when the ports are available HP CASE# 1094780 ~5391~
or are busy servicing other data transfer requests. If available, the arbitrator allows communication (class 1 transfer or class 2 transfer) of the data between ports via the MDN or IDN of the switch module.
BRlEF DESCRIPTION OF T~IE DRAWINCS
FIG. la shows a block diagram of a lel)resentative Fibre Channel architecture.
FIG lb shows the frame protocol of the Fibre Channel.
FIG. 2 shows a block diagram of a fiber optic switch element according to the present invention.
FIG. 3 shows a more detailed block diagram of the fiber oplic switch element.
FIG. 4 shows a block diagram of the channel module in FIG. 3.
FIG. 5 shows a more detailed block diagram of the channel module.
FIG. 6 shows a block diagram of the path allocation system in FIG. 3.
DETAILED DESCR~I'TION OF T~E rREFERRED EMI~Or)llVlENT
Briefly, the present invention provides a fiber optic switch element based upon a parallel, non-blocking, cross-point architecture with centralized control.
The switch element supports both circuit- and frame-switched connections for multiple baud rate interfaces.
As used herein, these terms and phrases are defined as follows:
Class 1 service-- a circuit-switched connection;
Class 2 service-- a connectionless, frame-switched link providing guaranteed delivery and receipt noti~lcation;
Class 3 service-- a connectionless service with no con~lrmation;
F~ort-- "fabric" port, the access point of the Fabric for physically connecting N~orts;
HP CASE# 1094780 Fabric-- a Fibre Channel-defined interconnection methodology that handles routing in Fibre Channel networks;
Frame-- a linear set of tMnsmitted bits that deflne a basic transport element;
s Intermix-- a class of service lhat provides functionality of both Class I and 2,Intermix reserves the full channel for a Class 1 conl1ection while allowing Class 2 traffic to pass on unused bandwidth;
Link-- a communications channel;
N_port-- "node" port, a Fibre Channel-defined hardware entity at the node end of a link.
Refer now to FIG. la which shows a block diagram of a rep-~s~nt~tive fibre channel architecture. A fibre channel network 100 is presented. A workstation 120, a mainframe 122 and a super computer 124 are interconnected with various subsystems (e.g., a tape subsystem 126, a disk subsystem 128, and a display subsystem 130) via a fibre channel fabric 110. The fabric 110 is an entity that interconnects various node-ports (N_ports) attached to the fabric 110. The essential function of the fabric 110 is to receive frames of data from a source N_port and, using a first protocol, route the frames to a destination N_port. In a preferredembodiment, the first protocol is thc rlbre channel protocol. Olher protocols, stlch as the asynchronous transfer mode (ATM) could be used without departing from thescope of the present invention.
Each of the various systems and subsystems (e.g., the workstation 120, the tape subsystem 126) connected to the rlbre channel fabric 110 comprises an associated N-port 140. The N port is a hardware entity at ~he node end of a link.
The F-port 142 is the access point of the fabric 110 for physically connecting the various N-ports 140. The fabric 110 has the capability of routing data frames (see FIG. lb below) based upon information contained within the fMmes as specified bya class of service. The N_port simply manages the simple point-to-point connection between itself and the fabric 110. That transmission is isolated from the control HP CASE# 1094780 2~ 918 protocol so that different topologies (e.g., point-to-point links, rings, multidrop buses, crosspoint switches) can be implemented. The fabric 110 is self-managed so that N_ports do not need station management functionality, greatly simplifying systemi mplementation .
FIG lb shows tlle frame protocol of the fibre channel. In a preferred embodiment, the protocol can be up to 2,148 bytes wide, depending llpon the size of the payload. A frame 180 is the smallest indivisible packet of data that is sentthrough a fibre channel network. Addressing of the frame 180 is done within the frame header 182 which is 24 bytes long. Frames are not visible to the upper-level protocols and consist of the following fields:
a start-of-frame delimiter (4 bytes);
a frame header (24 bytes);
optional headers (64 bytes);
a variable-length payload containing user data (from 0 to 2048 bytes);
a cyclic redundancy check error check (4 bytes); and an end-of-frame delimiter (4 bytes).
The frame header 182 can be further defined as shown. The addressing of the frame 180 is accomplished using a source address (SOURCE_ADDR) and destination address (DESTINATION ADDR). Each connected N_port has a unique address identifier. The length of the user data that is encapsulated within the frame 180 is defined within the header 182 under the LENGTH field.
FIG. 2 shows a block diagram of a fber optic switch element according to the present invention. Tlle fber optic switch element 200 enables implementation of a rlbre channel network by permitting selective interconnection of a plurality of fiber optic channels (not shown). The rber optic switch 200 permits both circuit and frame switching. Circuit switching enables data transfer on a dedicated connection. In lhe circuit-swi~che~ mode, a dedicated palh between twoN_ports is established before data transfer occurs. This dedicated palh is maintained unlil eilher of the two N ports disconnects. Prame switching is a connectionless data IIP CASE~ 1094780 ~1~3918 transfer mode in which the bandwidth is dynamically allocated on a frame-by-frame basis.
A switch module 220 is connected to an F_port wi~hin the fibre channel fabric through a channel control box 210. The switch module 220 is responsible for core switching bandwidth. A path allocation system 230, which is connected to the switch module 220, generally directs frames between F_ports (logically located within the channel control box 210) through the switch module 220. The path allocation system 230 is essentially a specialized multi-processor subsystem for the allocation and control of switching and port resources. FMme switclling requires a relatively large amount of buffering while circuit switching requires pre-allocation of switching bandwidth. To accomplisll both, the fiber optic switch element 200 provides local buffering at the cllannel control box 210 with centralized routing hardware in the path allocation system 230. In a preferred embodiment, there are two modes of buffering.
The first mode is known as "cut-tllrougll" mode bufrering. Cut-through mode allows frame data to be read as the frame is being written to lhe buffer. This mode facilitates faster routing of the data frames through tlle switcll element 200. The channel control box 210 typically operates under the cut-through mode. The second mode is known as "store-and-forward" mode buffering. This mode resembles the more standard type of buffering in which the entire frame is written to the buffer before it can be read out. The store-and-forward mode is typically used during intermix operalion, for example.
An element controller 240, which is connected to the path allocation system 230 and switch module 220, provides centralized fabric management. A
feature of the element controller 230 is an embedded port to communicate with N~orts.
FIG. 3 shows a more detailed block diagram of the fiber optic switch element 200. The fiber optic switch 200 has a plurality of channel modules 304 to which the fiber optic channels 302 are connected via respective ports p~ through pj.
In a preferred embodiment, there are 4 channel modules, each providing a 266 HP CASEiY 1094780 21~3~1~
MBaud bi-directional path into the fabric. Other configurations can be implemented without departing from the scope of the present invention. ~or example, two 531 MBaud channel modules or a single 1063 MBaud channel module could be used.
Each channel module 304is connected to one or more of tlle fiber optic channels 302 and provides port intelligence as well as receive memory for temporarily storing data frames. The channel modules 304 are connccted to the switch module 220, which distributes electrical energy from a power supply 306 via connection 308.
In the preferred embodiment, the switch module 220 is implemented as part of a back plane; a number of functional interface elements are disposed upon the back plane.
The switch module 220 has a shlus multiplexer (MUX) 310 which is configured to receive stahls signals from the channel module 304 concerning the fiber optic channels 302. A main distribu~ion network (MDN) 312 selectively interconnects the data paths of the channels 302. In a preferred embodiment, the MDN 312 is a 16xl6 non-blocking crosspoint swilch. A control distribution network (CDN) 314 communicates control signals to the various cllannel modules 304. ~or example the C D N 314 informs channel modules when a data frame may be sent. An intermix distribution network (IDN) 316 selectively interconnects intermix paths between channel modules 304. Intermix paths are a set of alternate data paths which are separate from those data paths associated with lhe MDN 312 and which can permit dah flow between sclected channels 302 while d~ta paths of the MDN 312 are in use.
In a preferred embodiment, both the CDN 314 and the IDN 316 are implemented by a 8x8 crosspoint switch. Finally, a processor (uProc) selector 318 can optionally be provided as part of an auxiliary system for interconnecting processors and controllers distribu~ed throughout the fiber optic switch 200. Additionally, the uProc selector 318 facilihtes "off-line" service of the switch 200.
The path allocation system 230 is connected to the switch module 220 and, particularly, to the status MUX 310, the MDN 312, the CDN 314 and the IDN
316. The path allocation system 230 generally allocates dah interconnect paths between fiber optic cl-annels 302 and determines the priority of lhe connections. The HP CASE# 1094780 9 1 ~
path allocation system 230 is a significant element of the present invention andbecause of its design, results in very desirable performance attributes with minimum hardware requirements (see PIG. 6).
Also connected to the switch module 230 is an element controller (EC) 240. The EC 240 essentially provides servers (e.g., a name server, a time server) for the fiber optic switch element 200. The EC 240 has a data link 340 with the path allocation system 230 for communicating server information and a status/control conneclion 342 for exchanging status/control signals with the path allocation system 230. The EC 240 also exchanges server information with the IDN 316 and the processor selector 318 via respective links 342,344. Data link 342 provides an embedded port into the element controller 240. The embedded port behaves essentially as an N port wl1ich can be addressed as if it were another system connected to the switch 200. The embedded port facilitates operator control of the switch element 200. l~or example, when a system such as a workstation plugs intothe switch for the first time, the system will attempt to communicate with the switch 200 by logging on. The embedded port will send switch configuration information back to the new system and will provide information indicative of the other systems and subsystems that are already connected to lhe switch 200.
The EC 240 comprises a microprocessor and various memory elements including a flash EPROM, RAM and a Boot ROM. The Boot ROM stores a Boot Manager and self-test software for the EC 240. The flask EPROM is used to store an operating system, such as VxWorks, available from Wind River Systems, U.S.A.,and additional firmware for the switch module and path allocation system. In a preferred embodiment, the microprocessor within the EC 240 is a model i960CA, manufactured by Intel.
FIG. 4 shows a block diagram of the channel module in FIC. 3. The channel module 304 comprises a port intelligence system 410 and a memory interface system 420. In a preferred embodiment, the channel module 304 provides a 1063 MBaud bi-directional path into the fabric.
HP CASE~ 1094780 9 1 ~
-The port intelligence system 410 comprises at least one transceiver and a first application-specific integrated circuit (ASIC). Essentially, the port intelligence system 410 provides port intelligence adapted to transmit and receive data according to a specific protocol, preferably ~Ibre cllannel, associated with the fiber optic channel 302. The port intelligence system 410 is interchangeable to accommodate a variety of protocols, such as asynchronous transfer mode (ATM). Additionally, the port intelligence system 410 can be adapted to be hooked up to channels with different bit rates. A conventional optical link card (OLC), such as an OLC266 manufactured byIBM, can be utilized to directly interface the port intelligence system 410 to the fiber optic channel 302. In a preferred embodiment, the first ASIC is configured to support three modes of operation: 266-, 531- and 1063-MBaud data transfer.
The memory interface system 420 comprises at least one frame burfer and a second ASIC which is configured differently from tlle first ASIC in tlle port intelligence system 410. The frame buffer may be random access memory with bit-sliced organization. Additionally, separate receive buffers and transmit buffers may be used. The second ASIC is a bit-sliced chip for memory management and is responsible for connecting the memory interface system 420 to tlle internal switcl data paths via the main link 320 and the intermix link 322.
FIG. 5 shows a more detailed block diagram of the channel module of FlGs. 3 and 4. The port intelligence system 410 has one or more port intelligence mechanisms 502. One port intelligence mechanism 502 is allocated to each fiber optic channel 302. Each port intelligence mechanism 502 has a receiver (RX) 504,a transmitter (TX) 506, an optical link card (OLC) 508, and a status/control (STAT/CNTL) logic 510. The receiver 504 and the transmitter 506 are adapted to receive and transmit data, respectively, through their co~ 1~ sponding input and output fibers 501, 502 (shown collectively in FIG. 3 as channel 302) in accordance with the Fibre Channel industry standard protocol and at the channel's particular bit rate.
The OLC 508 is utilized to directly interface the port intelligence mechanism 502 to the ~Iber optic channel 302. The OLC 508 provides an optical-to-electrical HP CASE# 1094780 39l~
-conversion as well as a serial-to-parallel conversion between the input fiber 501 of the channel 302 and the receiver 504. Furthermore, the OLC 508 provides an electrical-to-optical conversion as well as a parallel-to-serial conversion between the output fiber 502 of the channel 302 and the transmitter 506.
The status/control logic 510 monitors and controls both the receiver 504 and the transmitter 506, as indicated by co~s~onding bidirectional control connec~ions 511,512. Further, the status/control logic 510 exchanges control signals on control connection 324 with the CDN (item 314 in FIG. 3), provides status signals on connection 326 to the status MUX (item 310 in FIG. 3) indicative of, e.g., whether the co~e~lJoIlding port (p, lhrough p~ is available or busy, and forwards control signals to the memory interface system 420 via connection 432. The status/control logic 510 further recognizes when a new frame is received by the receiver 504 and determines the transfer class (either 1 or 2) as well as the length of data pertaining to each new frame. It should be noted that a frame could have no data, as for example, in the case of an SOFcl frame (i.e., a start of frame for class 1 service), which is initially passed through the switch 200 for setting the switch 200 up to reserve a bidirectional path for a class 1 data transfer.
The memory interface system 420 is connected in series, or caccadecl, with the port intelligence system 410, and particularly, with each port intelligence mechanism 502 contained therein. l he men~ory interface system 420 generally provides class 1 bypass data connections 530,532 for class 1 data transfers and provides temporary storage for class 2 dala transfers. For data slorage relative to class 2 data transfers, the memory interface system 420 has a receive memory (RX MEMORY) 520 for source data, a transmit memory (TX MEMORY) 522 for destination data, and memory control logic 524 for conlrolling lhe receive and transmit memories 520,522.
The receive memory 520 and the transmit memory 522 may be partitioned into a number of individual buffers or memory blocks, if desired.
FIG. 6 shows a block diagram of tl-e palh allocation system in FIG. 3.
The path allocation system 230 communicates with the channel module(s) (item 304 HP CASE~ 1094780 ~ ~3918 in FIGs. 3 and 4) and the element conlroller (EC) (item 240 in FIG. 3) via the control distribution network (CDN) (item 314 in FIG. 3). Basically, the path allocation system 230 controls all switching bandwidth wilhin the fiber optic switch element and directs all frame flow. In addition to managing port and switch resources for allocating frame data paths througl1 the fiber optic switch, lhe path allocation system 230 collects frame header infomlation, validatcs each framc based upon the header informalion~ initiales frame-reject (I~RJT) ~lags for discrepant frames, initiates frame-busy (FBSY) flags for frames which cannot be delivered within a predetermined time-out value and collects performance stalistics for lhe elementcontroller.
The path allocation system 230 allocates the data paths through the switch module 220. A sequencer 650 is connected to the CDN (item 314 in ~IG. 3) via a control connection 651. A sentry 610 communicates to the CDN 314 via the control connection 611 and is connected to the sequencer 650. A timer 630 communicates to the sentry 610 and glue logic 660. The glue logic 660 communicates control signals with the sentry 610 via the control connection 661, and communicates control signals to the sequencer 650 via tlle control connection 662.
The scheduler 642 maintains a plurality of destination queues (Qp,-Qp;) 643 which co-le~,ond respectively with each of the ports (pl through p~ in FIG. 3. The scheduler 642 communicates with the glue logic 660.
An arbitrator 640 is connected to the scheduler 642, the glue logic 660, and the sequencer 650. The arbitralor 640 also communicates to the MDN and IDN
(items 312 and 316 in FIG. 3 respectively). A closer 620 monitors the sequencer 650 and receives control signals from the CDN via the control connection 621. The closer 620 also communicates an EC interface (not shown) which in turn communicates to the sentry 610, the arbitrator 640, and the elelllent controller (EC) (item 240 in FIG.
3) via the connection 622. In a preferred embodiment, the EC interface is a DSP or some similar processor.
HP CASE# 1094780 ~Lr~3918 -The sequencer 650 can be implemented witl1 any suitable logic, for example, as a state machine in a conventional field programmable gate array (FPGA) with the functionality described below. The sequencer 650 serves as the primary interface to the CDN (item 314 in FIG. 3) via the control connection 651. It essentially arbitrates the CDN among the sentry 610, the arbitrator 640, and thecloser 620.
The sentry 610 can be also be constructed wilh any suitable logic, for example, as a state machine in an FPGA. It monitors the new frame status (new frame arrived signal) corresponding with the ports (p, through p;) via the status MUX
(item 310 in FIG. 3) and status/control logic (item 510 in FIG. 5) and determines when a new frame is available for routing tllrough the MDN (item 312 in FIG. 3).In essence, the sentry 610 collects data of validated, buffered frames, maps thedestination port identification (DID) from the frame header of an incoming frame to an appropliate port via a routing table(s), determines the approl)-iateness of a new frame for a destin~tion port (i.e., whelher the frame can be inlermixed onto a class I stream), and determines whether a new frame is proper or in error.
The sentry 610 and timer 630, together, further provide queue command information to the scheduler 642, via the glue logic 660. The queue command information can include an add signal, a frame busy (FBSY) signal, and adelete (DEL) signal. The add signal is sent when a new frame is within the receive memory (item 520 in FIG. 5) of the memory interface system and is ready to be routed through the fiber optic switch 200. When an add signal is sent from the sentry 610 to the scheduler 642, the following information is sent: the add command, the destination port (or queue), a tail pointer, a class indicator, the source port, source buffer number, head pointer.
The FBSY signal is sent when ~he new frame has resided in the receive memory for a predetermined lime period (FBSY time period) which is considered too lengthy for the system. The FBSY signal which is sent by the timer 630 to the scheduler 642 generally includes same information as the add signal.
HP CASE# 10947B0 The delete signal is sent when the frame has resided in the receive memory for another predetermined time period (delete time period), which is longer than the FBSY time period, and which warrants deletion of the frame. A delete signal may also be issued for other error conditions. The delete signals which are sent by ei~her the timer 630, or the sentry 610, to the scheduler 642 includes the following path data: (a) the delete command, (b) the source port, and (c) the source buffer number.
The timer 630 can be implemented with any conventional processing mechanism, for instance, a digilal signal processor (DSP). The limer 630 measures tlle time in which a new frame resides within the receive memory (item 520 in FIG.
5) and determines when an FBSY signal and when a delete signal should be asserted by the sentry 610. For this purpose, the timer 630 maintains internally an FBSY/DEL clock for tracking the FBSY time period and the delete time period for each new frame. The timer 630 receives an initiate (init) signal from the sentry 610 for starting the FBSY/DEL clock when a new frame is ready to be transferred froma port, receives a timer clear (clr) signal from lhe arbitrator 640 via glue logic 660 for the purpose of clearing the FBSY/DEL clock, and outputs the FBSY signal and the delete signal to the sentry 610 after, respectively, an FBSY time period and a delete time period, provided that no timer clear signal has been received from the arbitrator 640. The timer clear signal essentially terminates the FBSY/DEL clock of the timer 630.
The glue logic 660 primarily serves as an interface among the sentry 610, the timer 630, the sequencer 650, the arbitrator 640, and the scheduler 642. In the preferred embodiment, the glue logic 660 is implemented as a statc machine via an ~PGA or o~her suilable logic. The glue logic 660 also perrorms other functionality in the preferred embodiment. The glue logic 660 monitors transmission ready (txready) signals and intermix ready signals through the sequencer 650, which indicate when a port intelligence mechanisll1 (item 502 in FIG. 5) is ready to receive a data frame. The glue logic 660 performs a circular sequence wherein it searches ~IP CASE~ 1094780 ~1~3~1~
-in sequence tllrough those txready and intermix ready signals which are asserted, by masking out those which are deasserted, to determine the next destination port which is to receive data (as well as the next destination queue 643 to service). The glue logic 660 forwards the identity of the next destination port to be serviced to the scheduler 642. In this regard, lhe glue logic 660 forwards a word to the scheduler 642 comprising a base pointer address, whicll identifies the heads of double link list queues, and a destination queue indicator, which identifies a particular destination queue.
The scheduler 642, which can be implemented with any convention processing mechanism, such as a DSr', maintains and manages the destination queues (Qp,-Qp~ 643 and receives the queue management commands, particularly, an add signal, a FBSY signal, and a delete signal, from the sentry 610. The scheduler 642 also receives a next destination port signal from the glue logic 660. The next destination port signal indicates the next port to service (and hence, the next destination queue 643 to service).
The scheduler 642 maintains and updates a destination queue (Qp,-Qp~
643 for each of the fiber optic ports (pl through pi) and is configured to store queue entries associated with each corresponding port. Each queue entry has path data which identifies the following: (a) source port from which dala is to be transferred from, (b) the source buffer number in receive memory (item 520 in FIG. 5) where the frame is located, and (c) ~lags which indicate whetller tlle queue entry is a normal frame entry, a frame for starting a class 1 data transfer ("SOFcln) entry, a Q-Head entry, or a Q-tail entry.
The arbitrator 640 is implemented with any suitable logic, preferably a state machine implemented wi~h an FPGA. The arbitra~or 640 tracks the status of the port intelligence mechanisms (item 502 in FIG. 5), determines when the port intelligence mecllanisms are available for transmitting and receiving data, and arbitrates connections between the port intelligence mechanisms. Specifically, the arbitrator 640 monitors transmission ready (txready), intermix ready, intermix bus HP CASE~ 1094780 ~1~3918 ., ready, and receive ready (rxready) signals generated by the statustcontrol logic (item 510 in FIG. 5) of the port intelligence mechanisms. When the arbitrator 640 receives a transfer request signal from the scheduler 642 to transfer data from a particular source pon to a particular destination port, the arbitrator 640 determines whether the transfer is either class I (circuit swilching), class 2 (rrame swilching) or some olher class of service.
While the present invention has been illustrated and described in connection with the preferred embodiment, it is not to be limited to the particular structure shown. It should be understood by those skilled in the art that various changes and modifications may be made wilhin the purview of the appended claims without departing from the spirit and scope of lhe invention in its broader aspects.
HP CASE~ 1094780
HP CASE# 1094780 ~Lr~3918 -The sequencer 650 can be implemented witl1 any suitable logic, for example, as a state machine in a conventional field programmable gate array (FPGA) with the functionality described below. The sequencer 650 serves as the primary interface to the CDN (item 314 in FIG. 3) via the control connection 651. It essentially arbitrates the CDN among the sentry 610, the arbitrator 640, and thecloser 620.
The sentry 610 can be also be constructed wilh any suitable logic, for example, as a state machine in an FPGA. It monitors the new frame status (new frame arrived signal) corresponding with the ports (p, through p;) via the status MUX
(item 310 in FIG. 3) and status/control logic (item 510 in FIG. 5) and determines when a new frame is available for routing tllrough the MDN (item 312 in FIG. 3).In essence, the sentry 610 collects data of validated, buffered frames, maps thedestination port identification (DID) from the frame header of an incoming frame to an appropliate port via a routing table(s), determines the approl)-iateness of a new frame for a destin~tion port (i.e., whelher the frame can be inlermixed onto a class I stream), and determines whether a new frame is proper or in error.
The sentry 610 and timer 630, together, further provide queue command information to the scheduler 642, via the glue logic 660. The queue command information can include an add signal, a frame busy (FBSY) signal, and adelete (DEL) signal. The add signal is sent when a new frame is within the receive memory (item 520 in FIG. 5) of the memory interface system and is ready to be routed through the fiber optic switch 200. When an add signal is sent from the sentry 610 to the scheduler 642, the following information is sent: the add command, the destination port (or queue), a tail pointer, a class indicator, the source port, source buffer number, head pointer.
The FBSY signal is sent when ~he new frame has resided in the receive memory for a predetermined lime period (FBSY time period) which is considered too lengthy for the system. The FBSY signal which is sent by the timer 630 to the scheduler 642 generally includes same information as the add signal.
HP CASE# 10947B0 The delete signal is sent when the frame has resided in the receive memory for another predetermined time period (delete time period), which is longer than the FBSY time period, and which warrants deletion of the frame. A delete signal may also be issued for other error conditions. The delete signals which are sent by ei~her the timer 630, or the sentry 610, to the scheduler 642 includes the following path data: (a) the delete command, (b) the source port, and (c) the source buffer number.
The timer 630 can be implemented with any conventional processing mechanism, for instance, a digilal signal processor (DSP). The limer 630 measures tlle time in which a new frame resides within the receive memory (item 520 in FIG.
5) and determines when an FBSY signal and when a delete signal should be asserted by the sentry 610. For this purpose, the timer 630 maintains internally an FBSY/DEL clock for tracking the FBSY time period and the delete time period for each new frame. The timer 630 receives an initiate (init) signal from the sentry 610 for starting the FBSY/DEL clock when a new frame is ready to be transferred froma port, receives a timer clear (clr) signal from lhe arbitrator 640 via glue logic 660 for the purpose of clearing the FBSY/DEL clock, and outputs the FBSY signal and the delete signal to the sentry 610 after, respectively, an FBSY time period and a delete time period, provided that no timer clear signal has been received from the arbitrator 640. The timer clear signal essentially terminates the FBSY/DEL clock of the timer 630.
The glue logic 660 primarily serves as an interface among the sentry 610, the timer 630, the sequencer 650, the arbitrator 640, and the scheduler 642. In the preferred embodiment, the glue logic 660 is implemented as a statc machine via an ~PGA or o~her suilable logic. The glue logic 660 also perrorms other functionality in the preferred embodiment. The glue logic 660 monitors transmission ready (txready) signals and intermix ready signals through the sequencer 650, which indicate when a port intelligence mechanisll1 (item 502 in FIG. 5) is ready to receive a data frame. The glue logic 660 performs a circular sequence wherein it searches ~IP CASE~ 1094780 ~1~3~1~
-in sequence tllrough those txready and intermix ready signals which are asserted, by masking out those which are deasserted, to determine the next destination port which is to receive data (as well as the next destination queue 643 to service). The glue logic 660 forwards the identity of the next destination port to be serviced to the scheduler 642. In this regard, lhe glue logic 660 forwards a word to the scheduler 642 comprising a base pointer address, whicll identifies the heads of double link list queues, and a destination queue indicator, which identifies a particular destination queue.
The scheduler 642, which can be implemented with any convention processing mechanism, such as a DSr', maintains and manages the destination queues (Qp,-Qp~ 643 and receives the queue management commands, particularly, an add signal, a FBSY signal, and a delete signal, from the sentry 610. The scheduler 642 also receives a next destination port signal from the glue logic 660. The next destination port signal indicates the next port to service (and hence, the next destination queue 643 to service).
The scheduler 642 maintains and updates a destination queue (Qp,-Qp~
643 for each of the fiber optic ports (pl through pi) and is configured to store queue entries associated with each corresponding port. Each queue entry has path data which identifies the following: (a) source port from which dala is to be transferred from, (b) the source buffer number in receive memory (item 520 in FIG. 5) where the frame is located, and (c) ~lags which indicate whetller tlle queue entry is a normal frame entry, a frame for starting a class 1 data transfer ("SOFcln) entry, a Q-Head entry, or a Q-tail entry.
The arbitrator 640 is implemented with any suitable logic, preferably a state machine implemented wi~h an FPGA. The arbitra~or 640 tracks the status of the port intelligence mechanisms (item 502 in FIG. 5), determines when the port intelligence mecllanisms are available for transmitting and receiving data, and arbitrates connections between the port intelligence mechanisms. Specifically, the arbitrator 640 monitors transmission ready (txready), intermix ready, intermix bus HP CASE~ 1094780 ~1~3918 ., ready, and receive ready (rxready) signals generated by the statustcontrol logic (item 510 in FIG. 5) of the port intelligence mechanisms. When the arbitrator 640 receives a transfer request signal from the scheduler 642 to transfer data from a particular source pon to a particular destination port, the arbitrator 640 determines whether the transfer is either class I (circuit swilching), class 2 (rrame swilching) or some olher class of service.
While the present invention has been illustrated and described in connection with the preferred embodiment, it is not to be limited to the particular structure shown. It should be understood by those skilled in the art that various changes and modifications may be made wilhin the purview of the appended claims without departing from the spirit and scope of lhe invention in its broader aspects.
HP CASE~ 1094780
Claims (8)
1. An apparatus for facilitating data communications in a fibre channel network,the fibre channel having first and second fabric ports, the apparatus comprising:
a switch module connected to the first fabric port;
a channel control box disposed between the switch module and the first fabric port;
an element controller connected to the switch module; and a path allocation system connected to the element controller and the switch module, the path allocation system allocates an interconnect path between the first fabric port and the second fabric port.
a switch module connected to the first fabric port;
a channel control box disposed between the switch module and the first fabric port;
an element controller connected to the switch module; and a path allocation system connected to the element controller and the switch module, the path allocation system allocates an interconnect path between the first fabric port and the second fabric port.
2. The apparatus of claim 1, further comprising first and second fiber optic channels, the first fiber optic channel disposed between the first fabric port and the channel control box, the second fiber optic channel disposed between the second fabric port and the channel control box.
3. The apparatus of claim 2, wherein the switch module comprises:
a status MUX disposed between the channel control box and the path allocation system, the status MUX is configured to receive a plurality of statussignals indicative the first and second fiber optic channels;
a main distribution network disposed between the channel control box and the path allocation system, the main distribution network interconnects the first and second fiber optic channels; and a control distribution network disposed between the channel control box and the path allocation system.
a status MUX disposed between the channel control box and the path allocation system, the status MUX is configured to receive a plurality of statussignals indicative the first and second fiber optic channels;
a main distribution network disposed between the channel control box and the path allocation system, the main distribution network interconnects the first and second fiber optic channels; and a control distribution network disposed between the channel control box and the path allocation system.
4. The apparatus of claim 3, wherein the channel control box comprises:
a port intelligence system connected to the first and second fabric ports, the port intelligence system is configured according to a first protocol;and a memory interface system connected to the port intelligence system, the memory interface system receives and transmits data from the first and second fabric port to the first and second fiber optic channels.
a port intelligence system connected to the first and second fabric ports, the port intelligence system is configured according to a first protocol;and a memory interface system connected to the port intelligence system, the memory interface system receives and transmits data from the first and second fabric port to the first and second fiber optic channels.
5. The apparatus of claim 4, wherein the port intelligence system comprises at least one transceiver and a first application-specific integrated circuit.
6. The apparatus of claim 5, wherein the memory interface system comprises at least one frame buffer and a second application-specific integrated circuit, the second application-specific integrated circuit is connected to the main distribution network.
7. The apparatus of claim 6, wherein the at least one frame buffer is a random access memory configured with a bit-sliced organization.
8. The apparatus of claim 7, wherein the first protocol is Fibre Channel protocol.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/330,155 | 1994-10-27 | ||
| US08/330,155 US5519695A (en) | 1994-10-27 | 1994-10-27 | Switch element for fiber channel networks |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2153918A1 true CA2153918A1 (en) | 1996-04-28 |
Family
ID=23288534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002153918A Abandoned CA2153918A1 (en) | 1994-10-27 | 1995-07-14 | Switch element for fibre channel networks |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5519695A (en) |
| EP (1) | EP0711053A1 (en) |
| JP (1) | JPH08265369A (en) |
| CA (1) | CA2153918A1 (en) |
Families Citing this family (52)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5805924A (en) * | 1994-11-08 | 1998-09-08 | Stoevhase; Bent | Method and apparatus for configuring fabrics within a fibre channel system |
| US5610745A (en) * | 1995-10-26 | 1997-03-11 | Hewlett-Packard Co. | Method and apparatus for tracking buffer availability |
| US5831985A (en) * | 1995-11-09 | 1998-11-03 | Emc Corporation | Method and apparatus for controlling concurrent data transmission from multiple sources in a channel communication system |
| US5959994A (en) * | 1996-08-19 | 1999-09-28 | Ncr Corporation | ATM/SONET network enhanced as a universal computer system interconnect |
| US5894481A (en) * | 1996-09-11 | 1999-04-13 | Mcdata Corporation | Fiber channel switch employing distributed queuing |
| US6031842A (en) | 1996-09-11 | 2000-02-29 | Mcdata Corporation | Low latency shared memory switch architecture |
| US5978379A (en) * | 1997-01-23 | 1999-11-02 | Gadzoox Networks, Inc. | Fiber channel learning bridge, learning half bridge, and protocol |
| US6185203B1 (en) | 1997-02-18 | 2001-02-06 | Vixel Corporation | Fibre channel switching fabric |
| US6118776A (en) * | 1997-02-18 | 2000-09-12 | Vixel Corporation | Methods and apparatus for fiber channel interconnection of private loop devices |
| US6160813A (en) * | 1997-03-21 | 2000-12-12 | Brocade Communications Systems, Inc. | Fibre channel switching system and method |
| US5956723A (en) * | 1997-03-21 | 1999-09-21 | Lsi Logic Corporation | Maintaining identifier information in a memory using unique identifiers as a linked list |
| US6005849A (en) * | 1997-09-24 | 1999-12-21 | Emulex Corporation | Full-duplex communication processor which can be used for fibre channel frames |
| US6144668A (en) * | 1997-11-26 | 2000-11-07 | International Business Machines Corporation | Simultaneous cut through and store-and-forward frame support in a network device |
| US5941972A (en) | 1997-12-31 | 1999-08-24 | Crossroads Systems, Inc. | Storage router and method for providing virtual local storage |
| USRE42761E1 (en) | 1997-12-31 | 2011-09-27 | Crossroads Systems, Inc. | Storage router and method for providing virtual local storage |
| US6185620B1 (en) * | 1998-04-03 | 2001-02-06 | Lsi Logic Corporation | Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion |
| US6064679A (en) * | 1998-05-01 | 2000-05-16 | Emulex Corporation | Hub port without jitter transfer |
| US6157652A (en) * | 1998-05-01 | 2000-12-05 | Emulex Corporation | Hub port with constant phase |
| US6353612B1 (en) * | 1998-06-19 | 2002-03-05 | Brocade Communications Systems, Inc. | Probing device |
| US6401128B1 (en) * | 1998-08-07 | 2002-06-04 | Brocade Communiations Systems, Inc. | System and method for sending and receiving frames between a public device and a private device |
| US6765919B1 (en) * | 1998-10-23 | 2004-07-20 | Brocade Communications Systems, Inc. | Method and system for creating and implementing zones within a fibre channel system |
| US7430171B2 (en) * | 1998-11-19 | 2008-09-30 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
| US7382736B2 (en) * | 1999-01-12 | 2008-06-03 | Mcdata Corporation | Method for scoring queued frames for selective transmission through a switch |
| US6608819B1 (en) * | 1999-01-12 | 2003-08-19 | Mcdata Corporation | Method for scoring queued frames for selective transmission through a switch |
| US6341315B1 (en) * | 1999-02-26 | 2002-01-22 | Crossroads Systems, Inc. | Streaming method and system for fiber channel network devices |
| US6820115B1 (en) * | 1999-04-09 | 2004-11-16 | Nortel Networks Limited | Apparatus and method for mediating message transmission across a network |
| AU4358700A (en) * | 1999-05-24 | 2000-12-12 | Crossroads Systems, Inc. | Method and system for multi-initiator support to streaming devices in a fibre channel network |
| US6205141B1 (en) | 1999-06-30 | 2001-03-20 | Crossroads Systems, Inc. | Method and system for un-tagged command queuing |
| US6965934B1 (en) | 1999-11-12 | 2005-11-15 | Crossroads Systems, Inc. | Encapsulation protocol for linking storage area networks over a packet-based network |
| AU4707001A (en) * | 1999-11-12 | 2001-06-25 | Crossroads Systems, Inc. | Encapsulation protocol for linking storage area networks over a packet-based network |
| US6433903B1 (en) | 1999-12-29 | 2002-08-13 | Sycamore Networks, Inc. | Optical management channel for wavelength division multiplexed systems |
| US6732219B1 (en) * | 2001-02-23 | 2004-05-04 | Hewlett-Packard Development Company, L.P. | Dynamic allocation of devices to host controllers |
| US7366194B2 (en) | 2001-04-18 | 2008-04-29 | Brocade Communications Systems, Inc. | Fibre channel zoning by logical unit number in hardware |
| US20020156924A1 (en) * | 2001-04-23 | 2002-10-24 | Moshe Czeiger | Method for communicating between fibre channel systems |
| US6623186B2 (en) * | 2001-04-26 | 2003-09-23 | Occam Networks | Optical ethernet overlay for loop topology network |
| US7239636B2 (en) | 2001-07-23 | 2007-07-03 | Broadcom Corporation | Multiple virtual channels for use in network devices |
| US6532212B1 (en) * | 2001-09-25 | 2003-03-11 | Mcdata Corporation | Trunking inter-switch links |
| US7295555B2 (en) | 2002-03-08 | 2007-11-13 | Broadcom Corporation | System and method for identifying upper layer protocol message boundaries |
| US7411959B2 (en) | 2002-08-30 | 2008-08-12 | Broadcom Corporation | System and method for handling out-of-order frames |
| US7346701B2 (en) | 2002-08-30 | 2008-03-18 | Broadcom Corporation | System and method for TCP offload |
| US7934021B2 (en) | 2002-08-29 | 2011-04-26 | Broadcom Corporation | System and method for network interfacing |
| US7313623B2 (en) | 2002-08-30 | 2007-12-25 | Broadcom Corporation | System and method for TCP/IP offload independent of bandwidth delay product |
| US8180928B2 (en) | 2002-08-30 | 2012-05-15 | Broadcom Corporation | Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney |
| US7327692B2 (en) * | 2002-09-10 | 2008-02-05 | International Business Machines Corporation | System and method for selecting fibre channel switched fabric frame paths |
| US7600035B2 (en) * | 2003-01-31 | 2009-10-06 | Brocade Communications Systems, Inc. | Dynamic link distance configuration for extended fabric |
| US7352740B2 (en) * | 2003-04-29 | 2008-04-01 | Brocade Communciations Systems, Inc. | Extent-based fibre channel zoning in hardware |
| US7619974B2 (en) * | 2003-10-31 | 2009-11-17 | Brocade Communication Systems, Inc. | Frame traffic balancing across trunk groups |
| US7430203B2 (en) * | 2004-01-29 | 2008-09-30 | Brocade Communications Systems, Inc. | Fibre channel zoning hardware for directing a data packet to an external processing device |
| US7298946B2 (en) * | 2004-12-22 | 2007-11-20 | Hewlett-Packard Development Company, L.P. | Multi-fiber cable for efficient manageability of optical system |
| JP5019936B2 (en) * | 2007-04-13 | 2012-09-05 | 株式会社オートネットワーク技術研究所 | In-vehicle relay connection unit |
| US8223633B2 (en) * | 2008-10-03 | 2012-07-17 | Brocade Communications Systems, Inc. | Port trunking at a fabric boundary |
| US8412831B2 (en) | 2009-08-03 | 2013-04-02 | Brocade Communications Systems, Inc. | Per priority TCP quality of service |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5418779A (en) * | 1994-03-16 | 1995-05-23 | The Trustee Of Columbia University Of New York | High-speed switched network architecture |
-
1994
- 1994-10-27 US US08/330,155 patent/US5519695A/en not_active Expired - Lifetime
-
1995
- 1995-07-14 CA CA002153918A patent/CA2153918A1/en not_active Abandoned
- 1995-08-14 EP EP95112796A patent/EP0711053A1/en not_active Withdrawn
- 1995-10-26 JP JP27936295A patent/JPH08265369A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US5519695A (en) | 1996-05-21 |
| JPH08265369A (en) | 1996-10-11 |
| EP0711053A1 (en) | 1996-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5519695A (en) | Switch element for fiber channel networks | |
| US5828475A (en) | Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch using a bypass bus and buffer | |
| US5490007A (en) | Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch | |
| US5502719A (en) | Path allocation system and method having double link list queues implemented with a digital signal processor (DSP) for a high performance fiber optic switch | |
| US5610745A (en) | Method and apparatus for tracking buffer availability | |
| EP1454440B1 (en) | Method and apparatus for providing optimized high speed link utilization | |
| US6240096B1 (en) | Fibre channel switch employing distributed queuing | |
| US5592472A (en) | High performance path allocation system and method for a fiber optic switch for a fiber optic network | |
| US6031842A (en) | Low latency shared memory switch architecture | |
| US5528584A (en) | High performance path allocation system and method with fairness insurance mechanism for a fiber optic switch | |
| US5844887A (en) | ATM switching fabric | |
| US7394814B2 (en) | Method and apparatus for rendering a cell-based switch useful for frame based application protocols | |
| US7296093B1 (en) | Network processor interface system | |
| US7042842B2 (en) | Fiber channel switch | |
| US5724348A (en) | Efficient hardware/software interface for a data switch | |
| US5943338A (en) | Redundant ATM interconnect mechanism | |
| EP0709986A2 (en) | Channel module for a fiber optic switch with a bit sliced memory architecture for data frame storage | |
| GB2314723A (en) | ATM network | |
| JPH0918515A (en) | Variable band communication equipment | |
| EP0766429A2 (en) | Method and apparatus for buffer management |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |