CA2130369A1 - Method and facility for temporarily storing data packets, and exchange with such a facility - Google Patents
Method and facility for temporarily storing data packets, and exchange with such a facilityInfo
- Publication number
- CA2130369A1 CA2130369A1 CA002130369A CA2130369A CA2130369A1 CA 2130369 A1 CA2130369 A1 CA 2130369A1 CA 002130369 A CA002130369 A CA 002130369A CA 2130369 A CA2130369 A CA 2130369A CA 2130369 A1 CA2130369 A1 CA 2130369A1
- Authority
- CA
- Canada
- Prior art keywords
- data packets
- logic
- queues
- data
- facility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
- H04J3/247—ATM or packet multiplexing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5647—Cell loss
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5651—Priority, marking, classes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
Abstract
Abstract Method and Facility for Temporarily Storing Data Packets, and Exchange with such a Facility Prior Art: Data packets (D4 - D8) are temporarily stored in two or more logic queues (QU1, QU2) to which the locations of a shared buffer memory (MEM) are dynamically allo-cated.
Technical Problem: In overload situations, the loss proba-bility for data packets (D4 - D8) is approximately equal in all queues (QU1, QU2).
The loss probability cannot be graduated.
Basic Idea: The unavoidable loss of data packets is systemized by selective rejection of data packets.
Solution: A data packet (D6 - D8) stored in a low-priority queue (QU2) is deleted if an in-coming data packet (D1) is assigned to a higher-priority queue (QU1) and if the over-all length of the queues has exceeded a predetermined value.
Advantages: - Buffer with different, adjustable accep-tance or service methods is easy to implement.
- Fast solution, suitable for ATM.
Figure: 1
Technical Problem: In overload situations, the loss proba-bility for data packets (D4 - D8) is approximately equal in all queues (QU1, QU2).
The loss probability cannot be graduated.
Basic Idea: The unavoidable loss of data packets is systemized by selective rejection of data packets.
Solution: A data packet (D6 - D8) stored in a low-priority queue (QU2) is deleted if an in-coming data packet (D1) is assigned to a higher-priority queue (QU1) and if the over-all length of the queues has exceeded a predetermined value.
Advantages: - Buffer with different, adjustable accep-tance or service methods is easy to implement.
- Fast solution, suitable for ATM.
Figure: 1
Description
`` '~` Z13~9 Method and Facility for Temporarily Storing Data Packets, and Exchange with such a Facility The present invention relates to a method for tem-porarily storing data packets as set forth in the pre-amble of claim 1, to a facility for temporarily storing data packets as set forth in the preamble of claim 7, and to an exchange with such a facility as set forth in the preamble of claim 11.
In ATM switching facilities (ATM = Asynchronous Trans-fer Mode) it is frequently necessary to switch data packets (also referred to as "cells") from several input lines to one and the same output line. This is one of the reasons why data packets are temporarily stored -there before, during, or after the switching process.
The temporary storaye may be in the form of several -~
parallel queues. The queues are treated differently, so that the data packets are served differently according to which queue they belong to.
: ' The invention is based on a facility as is described on pages 162 and 163 of an article entitled "Das ATM-Koppelfeld von Alcatel und seine Eigenschaften", which was published in "Elektrisches Nachrichtenwesen", Vol. ~;
64, No. 2/3, 1990, a technical journal of Alcatel.
- ' ;':, f`` ~3~3~ :
In ATM switching facilities (ATM = Asynchronous Trans-fer Mode) it is frequently necessary to switch data packets (also referred to as "cells") from several input lines to one and the same output line. This is one of the reasons why data packets are temporarily stored -there before, during, or after the switching process.
The temporary storaye may be in the form of several -~
parallel queues. The queues are treated differently, so that the data packets are served differently according to which queue they belong to.
: ' The invention is based on a facility as is described on pages 162 and 163 of an article entitled "Das ATM-Koppelfeld von Alcatel und seine Eigenschaften", which was published in "Elektrisches Nachrichtenwesen", Vol. ~;
64, No. 2/3, 1990, a technical journal of Alcatel.
- ' ;':, f`` ~3~3~ :
This facility forms part of an integrated switching ele-ment for AT~ data packets (referred to as "ATM cells" or "cells"). In this facility, data packets which come from different inlets are allocated to several queues and temporarily stored there.
The facility comprises a memory device, a routing logic, and a memory management device.
The memory device contains several logic queues. "Logic"
in this connection means that the assignment of memory cells to a queue is not permanent, but variable.
The routing logic allocates incoming data packets to one of the logic queues on the basis of routing information contained in the data packets.
The memory management device manages the locations of the memory device. It ensures the queue discipline in the logic queues and allocates vacant locations to the data packets to be inserted into the queues.
~" , This results in the following mode of operation: A
stream of data packets arrives at the memory device, is distributed to the logic queues on the basis of the routing information, and is temporarily stored there.
Such a facility has the advantage that the data packets are temporarily stored in different queues which can be served in different ways, and that storage utilization is better than with separate queues with fixed memory allocation. This results from the fact that all locations of the memory device can be used by all queues. -~-` 213~)369 Under overload conditions, the loss proability of data packets is, as a rule, independent of their affiliation with a logic queue. In many cases, however, it is neces-sary for the loss pro~ability of the data packets in a given queue to be as low as possible. For data packets of another queue which is of less importance, a slightly higher loss probability would be toleratedO
It is, therefore, the object of the invention to achieve different qualitative treatments for data packets tem-porarily stored in different logic queues.
The object is attained by a method according to theteaching of claim 1 and by a facility according to the teaching of claim 7. An advantageous use is set forth in claim 11.
The basic idea of the invention is to systemize the un-avoidable loss of data packets by selective rejection of data packets. Data packets of queues which are not so important are deliberately rejected within given limits in order to make room for data packets of greater im-portance.
Further advantageous features of the invention are de-fined in the subclaims.
In particular, data packets are allocated to the queues on the basis of a priority class designated in the data packets so that each queue contains data packets of another priority class. The queues are served with dif-ferent frequency. Thus, a temporary storage with priority-dependent loss and delay probabilities is im-pl~mented in an advantageous manner.
-- - , :
~ ~L31~)3~.~
The special advantage of the invention is that the con-figuration of few parameters makes it possible to switch between several methods which bring about different loss or delay probabilities. This pxovides a universally applicable temporary storage which is adjusted to the respective task by the configuration of few parameters.
Another advantage of the invention is that it meets high speed requirements, so that it is also suitable for ATM.
The invention will become more apparent from the follow-ing description of an embodiment taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a symbolic representation of a novel facility for temporarily storing data packets which uses the method according to the invention;
Fig. 2 is a symbolic representation of a portion of a write device for the facility of Fig. 1, and Fig. 3 is a symbolic representation of a server and of a portion of a buffer memory for the facility of Fig. 1.
First the use of the novel method in a novel facility for temporarily storing data packets will be described, wherein it is possible to switch between several operat- -~
ing modes of the servers and the access control devices. -The incoming data packets have been assigned ~ -r~
2~3~36~
to one of two priority classes and are allocated to one of two queues according to their priority class.
It is also possible to allocate the incoming data packets to the queues in accordance with another cri-terion. For example, the data packets could be distri-buted to the queues in accordance with routing informa-tion contained therein, in which case each queue could also be assigned a different output.
Fig. 1 shows a write device WR, a buffer memory MEM, a server SER, and a memory management device MCoNTR. At the write device WR, three data packets Dl, D2, and D3 ::
are arriving.
-The data packets Dl, D2, and D3 are data packets as are used to exchange information in a communication network.
They carry an indicator that indicates the priority they are assigned to. The data packet D1 is assigned to pri-ority class P1, and the data packets D2 and D3 are assigned to priority classes P2, where P1 corresponds to th~ higher priority class and P2 to the lower one.
The data packets Dl, D2, and D3 may also have another form or another use. Such a data packet could represent, for example, th~ process context of a waiting process in a data processing system.
The write device WR receives incoming data packets to enter them into the buffer memory MEM. In addition, it decides on the rejection of data packets and, to this extent, exchanges signals with the memory management de-vice MCONTR.
~ 2~3G136~
In the buffer memory MEM, two logic queues QU1 and QU2 have been formed. mhe queue QU1 contains two data packets D4 and D5, and the queue QU2 three data packets D6, D7, and Ds. Each of these da~a packets is provided with a time stamp TS, which gives information on the order of arrival of the data packets. The queues QU1 and QU2 are organized as FIFo queues (FIFO = first-in-first-out~.
It is also possible to organize the queues differently, i.e., so that shorter data packets are read out first.
The server SER reads data packets from the buffer memory MEM following a given algorithm, and passes them on, e.g., to a transmitting device.
The memory management device MCONTR is responsible for ~-~
the management of storage in the buffer memory MEM. It holds a list of those locations of the buffer memory MEM
which are vacant, and allocates locations from this list to data packets when the latter are entered by the write device into one of the two queues QU1 and QU2. In addi-tion, the memory management device MCONTR organizes the logic queues QV1 and QU2 and stores information on their current lengths and the overall length of the two queues QU1 and QU2 in a register. The data of this register is communicated to the write device WR.
When a data packet is read by the server from one of the logic queues QU1 and QU2, the memory locations occupied by it are entered in the list of vacant memory loca-tions. In this e}~ample it is also possible that the memory locations of a data packet are entered in the list of vacant memory locations by the memory manage~ent 2~3~36~31 device MCONTR in response to a signal from the write device WR . This data p~cket is thus deleted from the queue.
The write device WR contains a clock CLOCK, a distrib~t-ing device DIV, and an access control device ZUG with two inputs IN1 and IN2 and two outputs OUT1 and OUT2.
The distributing device DIV receives the incoming data packets D1, D2 and D3, and passes them to the input IN1 of the access control device ZUG if they belong to pri-ority class P1, and to the input IN2 if they belong to priority class P2.
Furthermore, the distributing device DIV provides the incoming data packets with a time stamp TS. This time stamp TS indicates the arrival time of a data packet.
The arrival time is determined by means of the clock CLOCK.
Other methods of recording the order of arrival of the data packets in the time stamp TS are also possible. For instance, the count of a counter which is incremented by one on each incoming data packet could be stored in the time stamp TS. The time stamp could also be associated with a data packet in a different manner. For example, it could be stored separately and be combined with the respective data packet by the memory management device MCO~TR.
It is also possible to do without a time stamp TS
associated with a data packet. Then, however, the information on the order of arrival would no longer be available to the server SER.
2~ )3~
The access control device ZUG inserts the data packets applied at the inputs IN1 and IN2 into the queues QU1 and QU2, respectively, if necessary. In addition, the access control device ZUG makes the decisions on the re~
jection of data packets and carries out or initiates the rejection. To this end, it exchanges signals with the ~ -memory management device MCONTR.
The operation of the access control device ZUG is illu-strated in more detail in Fig. 2.
. .
Fig. 2 shows the access control device ZUG with the in-puts IN1 and IN2 and the outputs OUT1 and OUT2. It con-tains two controllers CONTR1 and CONTR2. The controller CONTR1 is responsible for the data packets allocated to the queue QU1, and the controller CONTR2 for those allocated to the queue QU2.
The controller CONTR1 has two comparators CMP1 and CMP2, two AND gates AND1 and AND2, a NOT gate NOT, and a write device El. The controller CONTR2 has two comparators CMP3 and CMP4, an AND gate AND3, and a write device E2.
Two signals n and n2 are received from the memory management device MCONTR, and a signal DOP02 is trans-mitted to the memory management device MCONTR. By means of a signal POEN, the operating mode of the access con-trol device ZUG is set. The signal POEN is received, for example, from a mode selector switch or a higher-level controller.
~3~3t~3 The value of the signal n2 corresponds to the number of data packets in the queue QU2, and the value of the sig-nal n corresponds to the total number of data packets in both queues QU1 and QU2. The signals DOP02 and POEN are binary signals, whose value is either a logic 1 or a logic O.
The write device E1 either inserts a data packet ar-riving at the input IN1 into the queue QU1 via the out-put OUT1 or rejects it. The write device E2 is connect-ed to the input IN2 and the output OUT2 and handles the data packets in the same manner. The AND gates ANDl, AND2, and AND3 each have two inputs and one output.
The signal n is applied to the comparators CMPl, CMP2, and CMP3, the signal n2 to the comparator CMP4, and the signal POEN to the first input of the AND gate AND3.
The comparator CMP3 compares the value of the signal n with a threshold value S2. If the value of the signal n is greater than or equal to the threshold value S2, the write device E2 will be instructed to reject the arriving data packets. If that is not the case, the write device will insert these data packets into the queue QU2 via the output OUT2.
The comparator CMP4 compares the value of the signal n7 with zero. If the value is greater than zero, a logic 1 will be applied to the second input of the AND gate AND3; if not, a logic O will be applied. The output of the AND gate AND3 (signal PA) is coupled to the first input of the AND gate AND2 and, through the NOT gate NOT, to the second input of the AND gate ANDl.
-2~303G9 - 1 0 - , " ~ ~
:. `::
The value of the signal n is compared with the theshold value Sl in the comparator CMP1 and with a threshold value N in the comparator CMP2. I f t:he value of the sig-nal n is greater than or equal to the threshold value S1, a logic 1 will be applied to the first input of the AND gate ANDl; if not, a logic 0 will be applied. If the value is greater than or equal to the threshold value N, a logic 1 will be applied to the second input of the AND
gate AND2; if not, a logic o will be applied.
If a logic 1 is applied at both inputs of the AND gate ANDl, the write device E1 will be instructed to reject the incoming data packets. If that is not the case, the write device E1 will insert these packets into the queue QU1 via the output OUT1. With a logic 1 applied at both inputs of the AND gate AND2, the memory management de-vice MCONTR Will be instructed via the signal DOP02 to delete the data packet located at the end of the queue QU2 from the buffer memory MEM.
The thresholds S1 and N are set to a value equal to the maximum number of data packets that can be stored in the buffer memory MEM. If the access control device ZUG were -extended to more than two priority classes, the threshold S1 would have to be set to a lower value.
: - ~
The above-described connection of the components makes it possible to switch between two different operating modes:
If the value of the signal POEN is set to logic O, then, starting from a given overall length of the two queues QU1 and QU2, only data packets intended for the queue Z~3C1369 : -.
. .
QU1 of the high priority class P1 will be entered into the buffer memory MEM. The data packets intended for the queue QU2 will be rejected. This threshold of the over-all length is set via the thresholcl value S2.
If the value of the signal POEN is set to logic 1, and the threshold S2 is set to the same values as the thresholds N and Sl, and if the overall length of the two queues QUl and QU2 has reached the limit of the capacity of the buffer memory MEM, and data packets are still stored in the queue QU2 of the lower priority class P2, one data packet will be deleted from the queue QUl and the vacated location will be used for storing a data packet of the high priority class P1.
It is also possible to do without the switching between two operating modes and implement only one of the two modes.
Also, other methods which selectively reject data packets by means of the data from the memory management device MCONTR and the allocation of the data packets to a queue may be used. Such methods could be implemented, for example, by setting the thresholds N, S1, or S2 or ~ ~ -the signal POEN to suitable other values. It is also possible to switch between more than two operating modes.
The operation of the server SER is illustrated in more detail in Fig. 3.
' ~:
Fig. 3 shows a portion of the buffer memory MEM and the server SER. The buffer memory MEM has two logic queues 13a33~ :
QUl and QU2 and contains two data packets D4 and D6 which are stored at the beginnings of the queues QU1 and QU2, respectively. The server SER contains a read device AE, a switching device SW, and three controllers SERVE1, SERVE2, and SERVE3.
The read device AE takes a data packet from the begin-ning of either the queue QU1 or the queue QU2 and passes it on. Which queue a data packet is taken from is de-cided by one oE the three controllers SERVE1, SERVE2, and SERVE3. By selecting one of these three controllers by means of the switching device SW, one of three operating modes is set. Each mode corresponds to a dif-ferent service method.
In the first mode, the controller SERVEl reads the time stamp TS of the data packet D4 via a data input TS1, and that of the data packet D6 via an input TS2. By means of this data, the controller SERVEl then causes that of the two data packets D4 and D6 to be read by the read device AE which arrived earlier at the write device WR. In this manner, FIFO serving of all data packets is implement-ed.
In the second mode, the controller SERVE2 checks via two inputs DAl and DA2 whether at least one data packet is contained in the queues QUl and QU2, respectively. By means of this data, the controller SERVE2 then causes data packets to be read from the queue QU2 only if no data packets are present in the queue QU1. In this manner, a delay priority of the data packets of the higher priority class Pl is implemented.
2~33~
In the third mode, the controller SERVE3 instructs the read device AE to read from each queue for a given period of time. In this manner, cyclic serving of the two queues is achieved.
It is also possible to dispense with the switching capa-bility between several modes of the server SER and use only one mode, or to employ service methods other than those described above.
In the example described, a novel facility for tempor-arily storing data packets belonging to one of two priority classes is shown. This facility could also be expanded to permit the temporary storage of data packets which are assigned to one of more than two priority classes. To do this, for each additional priority class, one additional queue would have to be formed in the buffer memory MEM and one additional controller would have to be provided in the access control device. This additional controller would then be of the same construction as the controller CONTRl and would be assigned to a higher priority class than class P1. An additional circuit would have to be added which generates a signal corresponding to the signal PA for the additional controller and derives from the signals POEN and n~ a signal for the controller CONTRl whose value indicates the length of the queue QU1.
.
The following describes an advantageous use of the in-vention in an ATM exchange.
,, . . . . . ., .. . ~ . . , , ~ , .. . .
The facility comprises a memory device, a routing logic, and a memory management device.
The memory device contains several logic queues. "Logic"
in this connection means that the assignment of memory cells to a queue is not permanent, but variable.
The routing logic allocates incoming data packets to one of the logic queues on the basis of routing information contained in the data packets.
The memory management device manages the locations of the memory device. It ensures the queue discipline in the logic queues and allocates vacant locations to the data packets to be inserted into the queues.
~" , This results in the following mode of operation: A
stream of data packets arrives at the memory device, is distributed to the logic queues on the basis of the routing information, and is temporarily stored there.
Such a facility has the advantage that the data packets are temporarily stored in different queues which can be served in different ways, and that storage utilization is better than with separate queues with fixed memory allocation. This results from the fact that all locations of the memory device can be used by all queues. -~-` 213~)369 Under overload conditions, the loss proability of data packets is, as a rule, independent of their affiliation with a logic queue. In many cases, however, it is neces-sary for the loss pro~ability of the data packets in a given queue to be as low as possible. For data packets of another queue which is of less importance, a slightly higher loss probability would be toleratedO
It is, therefore, the object of the invention to achieve different qualitative treatments for data packets tem-porarily stored in different logic queues.
The object is attained by a method according to theteaching of claim 1 and by a facility according to the teaching of claim 7. An advantageous use is set forth in claim 11.
The basic idea of the invention is to systemize the un-avoidable loss of data packets by selective rejection of data packets. Data packets of queues which are not so important are deliberately rejected within given limits in order to make room for data packets of greater im-portance.
Further advantageous features of the invention are de-fined in the subclaims.
In particular, data packets are allocated to the queues on the basis of a priority class designated in the data packets so that each queue contains data packets of another priority class. The queues are served with dif-ferent frequency. Thus, a temporary storage with priority-dependent loss and delay probabilities is im-pl~mented in an advantageous manner.
-- - , :
~ ~L31~)3~.~
The special advantage of the invention is that the con-figuration of few parameters makes it possible to switch between several methods which bring about different loss or delay probabilities. This pxovides a universally applicable temporary storage which is adjusted to the respective task by the configuration of few parameters.
Another advantage of the invention is that it meets high speed requirements, so that it is also suitable for ATM.
The invention will become more apparent from the follow-ing description of an embodiment taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a symbolic representation of a novel facility for temporarily storing data packets which uses the method according to the invention;
Fig. 2 is a symbolic representation of a portion of a write device for the facility of Fig. 1, and Fig. 3 is a symbolic representation of a server and of a portion of a buffer memory for the facility of Fig. 1.
First the use of the novel method in a novel facility for temporarily storing data packets will be described, wherein it is possible to switch between several operat- -~
ing modes of the servers and the access control devices. -The incoming data packets have been assigned ~ -r~
2~3~36~
to one of two priority classes and are allocated to one of two queues according to their priority class.
It is also possible to allocate the incoming data packets to the queues in accordance with another cri-terion. For example, the data packets could be distri-buted to the queues in accordance with routing informa-tion contained therein, in which case each queue could also be assigned a different output.
Fig. 1 shows a write device WR, a buffer memory MEM, a server SER, and a memory management device MCoNTR. At the write device WR, three data packets Dl, D2, and D3 ::
are arriving.
-The data packets Dl, D2, and D3 are data packets as are used to exchange information in a communication network.
They carry an indicator that indicates the priority they are assigned to. The data packet D1 is assigned to pri-ority class P1, and the data packets D2 and D3 are assigned to priority classes P2, where P1 corresponds to th~ higher priority class and P2 to the lower one.
The data packets Dl, D2, and D3 may also have another form or another use. Such a data packet could represent, for example, th~ process context of a waiting process in a data processing system.
The write device WR receives incoming data packets to enter them into the buffer memory MEM. In addition, it decides on the rejection of data packets and, to this extent, exchanges signals with the memory management de-vice MCONTR.
~ 2~3G136~
In the buffer memory MEM, two logic queues QU1 and QU2 have been formed. mhe queue QU1 contains two data packets D4 and D5, and the queue QU2 three data packets D6, D7, and Ds. Each of these da~a packets is provided with a time stamp TS, which gives information on the order of arrival of the data packets. The queues QU1 and QU2 are organized as FIFo queues (FIFO = first-in-first-out~.
It is also possible to organize the queues differently, i.e., so that shorter data packets are read out first.
The server SER reads data packets from the buffer memory MEM following a given algorithm, and passes them on, e.g., to a transmitting device.
The memory management device MCONTR is responsible for ~-~
the management of storage in the buffer memory MEM. It holds a list of those locations of the buffer memory MEM
which are vacant, and allocates locations from this list to data packets when the latter are entered by the write device into one of the two queues QU1 and QU2. In addi-tion, the memory management device MCONTR organizes the logic queues QV1 and QU2 and stores information on their current lengths and the overall length of the two queues QU1 and QU2 in a register. The data of this register is communicated to the write device WR.
When a data packet is read by the server from one of the logic queues QU1 and QU2, the memory locations occupied by it are entered in the list of vacant memory loca-tions. In this e}~ample it is also possible that the memory locations of a data packet are entered in the list of vacant memory locations by the memory manage~ent 2~3~36~31 device MCONTR in response to a signal from the write device WR . This data p~cket is thus deleted from the queue.
The write device WR contains a clock CLOCK, a distrib~t-ing device DIV, and an access control device ZUG with two inputs IN1 and IN2 and two outputs OUT1 and OUT2.
The distributing device DIV receives the incoming data packets D1, D2 and D3, and passes them to the input IN1 of the access control device ZUG if they belong to pri-ority class P1, and to the input IN2 if they belong to priority class P2.
Furthermore, the distributing device DIV provides the incoming data packets with a time stamp TS. This time stamp TS indicates the arrival time of a data packet.
The arrival time is determined by means of the clock CLOCK.
Other methods of recording the order of arrival of the data packets in the time stamp TS are also possible. For instance, the count of a counter which is incremented by one on each incoming data packet could be stored in the time stamp TS. The time stamp could also be associated with a data packet in a different manner. For example, it could be stored separately and be combined with the respective data packet by the memory management device MCO~TR.
It is also possible to do without a time stamp TS
associated with a data packet. Then, however, the information on the order of arrival would no longer be available to the server SER.
2~ )3~
The access control device ZUG inserts the data packets applied at the inputs IN1 and IN2 into the queues QU1 and QU2, respectively, if necessary. In addition, the access control device ZUG makes the decisions on the re~
jection of data packets and carries out or initiates the rejection. To this end, it exchanges signals with the ~ -memory management device MCONTR.
The operation of the access control device ZUG is illu-strated in more detail in Fig. 2.
. .
Fig. 2 shows the access control device ZUG with the in-puts IN1 and IN2 and the outputs OUT1 and OUT2. It con-tains two controllers CONTR1 and CONTR2. The controller CONTR1 is responsible for the data packets allocated to the queue QU1, and the controller CONTR2 for those allocated to the queue QU2.
The controller CONTR1 has two comparators CMP1 and CMP2, two AND gates AND1 and AND2, a NOT gate NOT, and a write device El. The controller CONTR2 has two comparators CMP3 and CMP4, an AND gate AND3, and a write device E2.
Two signals n and n2 are received from the memory management device MCONTR, and a signal DOP02 is trans-mitted to the memory management device MCONTR. By means of a signal POEN, the operating mode of the access con-trol device ZUG is set. The signal POEN is received, for example, from a mode selector switch or a higher-level controller.
~3~3t~3 The value of the signal n2 corresponds to the number of data packets in the queue QU2, and the value of the sig-nal n corresponds to the total number of data packets in both queues QU1 and QU2. The signals DOP02 and POEN are binary signals, whose value is either a logic 1 or a logic O.
The write device E1 either inserts a data packet ar-riving at the input IN1 into the queue QU1 via the out-put OUT1 or rejects it. The write device E2 is connect-ed to the input IN2 and the output OUT2 and handles the data packets in the same manner. The AND gates ANDl, AND2, and AND3 each have two inputs and one output.
The signal n is applied to the comparators CMPl, CMP2, and CMP3, the signal n2 to the comparator CMP4, and the signal POEN to the first input of the AND gate AND3.
The comparator CMP3 compares the value of the signal n with a threshold value S2. If the value of the signal n is greater than or equal to the threshold value S2, the write device E2 will be instructed to reject the arriving data packets. If that is not the case, the write device will insert these data packets into the queue QU2 via the output OUT2.
The comparator CMP4 compares the value of the signal n7 with zero. If the value is greater than zero, a logic 1 will be applied to the second input of the AND gate AND3; if not, a logic O will be applied. The output of the AND gate AND3 (signal PA) is coupled to the first input of the AND gate AND2 and, through the NOT gate NOT, to the second input of the AND gate ANDl.
-2~303G9 - 1 0 - , " ~ ~
:. `::
The value of the signal n is compared with the theshold value Sl in the comparator CMP1 and with a threshold value N in the comparator CMP2. I f t:he value of the sig-nal n is greater than or equal to the threshold value S1, a logic 1 will be applied to the first input of the AND gate ANDl; if not, a logic 0 will be applied. If the value is greater than or equal to the threshold value N, a logic 1 will be applied to the second input of the AND
gate AND2; if not, a logic o will be applied.
If a logic 1 is applied at both inputs of the AND gate ANDl, the write device E1 will be instructed to reject the incoming data packets. If that is not the case, the write device E1 will insert these packets into the queue QU1 via the output OUT1. With a logic 1 applied at both inputs of the AND gate AND2, the memory management de-vice MCONTR Will be instructed via the signal DOP02 to delete the data packet located at the end of the queue QU2 from the buffer memory MEM.
The thresholds S1 and N are set to a value equal to the maximum number of data packets that can be stored in the buffer memory MEM. If the access control device ZUG were -extended to more than two priority classes, the threshold S1 would have to be set to a lower value.
: - ~
The above-described connection of the components makes it possible to switch between two different operating modes:
If the value of the signal POEN is set to logic O, then, starting from a given overall length of the two queues QU1 and QU2, only data packets intended for the queue Z~3C1369 : -.
. .
QU1 of the high priority class P1 will be entered into the buffer memory MEM. The data packets intended for the queue QU2 will be rejected. This threshold of the over-all length is set via the thresholcl value S2.
If the value of the signal POEN is set to logic 1, and the threshold S2 is set to the same values as the thresholds N and Sl, and if the overall length of the two queues QUl and QU2 has reached the limit of the capacity of the buffer memory MEM, and data packets are still stored in the queue QU2 of the lower priority class P2, one data packet will be deleted from the queue QUl and the vacated location will be used for storing a data packet of the high priority class P1.
It is also possible to do without the switching between two operating modes and implement only one of the two modes.
Also, other methods which selectively reject data packets by means of the data from the memory management device MCONTR and the allocation of the data packets to a queue may be used. Such methods could be implemented, for example, by setting the thresholds N, S1, or S2 or ~ ~ -the signal POEN to suitable other values. It is also possible to switch between more than two operating modes.
The operation of the server SER is illustrated in more detail in Fig. 3.
' ~:
Fig. 3 shows a portion of the buffer memory MEM and the server SER. The buffer memory MEM has two logic queues 13a33~ :
QUl and QU2 and contains two data packets D4 and D6 which are stored at the beginnings of the queues QU1 and QU2, respectively. The server SER contains a read device AE, a switching device SW, and three controllers SERVE1, SERVE2, and SERVE3.
The read device AE takes a data packet from the begin-ning of either the queue QU1 or the queue QU2 and passes it on. Which queue a data packet is taken from is de-cided by one oE the three controllers SERVE1, SERVE2, and SERVE3. By selecting one of these three controllers by means of the switching device SW, one of three operating modes is set. Each mode corresponds to a dif-ferent service method.
In the first mode, the controller SERVEl reads the time stamp TS of the data packet D4 via a data input TS1, and that of the data packet D6 via an input TS2. By means of this data, the controller SERVEl then causes that of the two data packets D4 and D6 to be read by the read device AE which arrived earlier at the write device WR. In this manner, FIFO serving of all data packets is implement-ed.
In the second mode, the controller SERVE2 checks via two inputs DAl and DA2 whether at least one data packet is contained in the queues QUl and QU2, respectively. By means of this data, the controller SERVE2 then causes data packets to be read from the queue QU2 only if no data packets are present in the queue QU1. In this manner, a delay priority of the data packets of the higher priority class Pl is implemented.
2~33~
In the third mode, the controller SERVE3 instructs the read device AE to read from each queue for a given period of time. In this manner, cyclic serving of the two queues is achieved.
It is also possible to dispense with the switching capa-bility between several modes of the server SER and use only one mode, or to employ service methods other than those described above.
In the example described, a novel facility for tempor-arily storing data packets belonging to one of two priority classes is shown. This facility could also be expanded to permit the temporary storage of data packets which are assigned to one of more than two priority classes. To do this, for each additional priority class, one additional queue would have to be formed in the buffer memory MEM and one additional controller would have to be provided in the access control device. This additional controller would then be of the same construction as the controller CONTRl and would be assigned to a higher priority class than class P1. An additional circuit would have to be added which generates a signal corresponding to the signal PA for the additional controller and derives from the signals POEN and n~ a signal for the controller CONTRl whose value indicates the length of the queue QU1.
.
The following describes an advantageous use of the in-vention in an ATM exchange.
,, . . . . . ., .. . ~ . . , , ~ , .. . .
3~3~369 In such an exchange, the incoming data packets are tem-porarily stored before, while, or after being switched by a switching network. Thus, for each line carrying in-coming or outgoing data packets or for the switching process, one temporary storage :is needed. At those -points, facilities for temporarily storing data packets in accordance with the invention are used.
.
.
Claims (11)
1. A method for temporarily storing data packets wherein the incoming data packets (D1, D2, D3) are distributed to and temporarily stored in two or more logic queues (QU1, QU2) on the basis of data (P1, P2) contained in said data packets, and wherein all of said logic queues (QU1, QU2) share a common buffer memory (MEM) whose locations are dynamically allocated to the individual logic queues (QU1, QU2) only when required, c h a r a c t e r i z e d i n that individual data packets are rejected if proper treatment is not ensured for all data packets, that data on the lengths of the logic queues (QU1, QU2) is determined, that data on which logic queue an incoming data packet (D1, D2, D3) will be allocated to is determined, and that the data packets to be rejected are selected on the basis of said determined data.
2. A method as claimed in claim 1, characterized in that data packets to be rejected are rejected before they are inserted into a logic queue (QU1, QU2).
3. A method as claimed in claim 1, characterized in that data packets to be rejected are removed from a logic queue (QU1, QU2).
4. A method as claimed in claim 1, characterized in that each data packet contains data (P1, P2) which assigns a priority class to said data packet, and that for each priority class, a separate logic queue (QU1, QU2) is provided in which the data packets (D5, D4; D8, D7, D6) assigned to said priority class are temporarily stored.
5. A method as claimed in claims 2 and 4, characterized in that the overall length (n) of the logic queues (QU1, QU2) is determined, that at least one priority class is assigned a reference value (S1, S2), and that the incoming data packets (D1, D2, D3) of such a priority class are rejected if the overall length (n) of the logic queues (QU1, QU2) exceeds the reference value (S1, S2).
6. A method as claimed in claims 3 and 4, characterized in that a data packet (D6, D7, D8) of a lower priority class will be removed from the buffer memory (MEM) if no memory location is available in the buffer memory (MEM) for an incoming data packet (D1, D2) of a higher priority class.
7. A facility for temporarily storing data packets, comprising a buffer memory (MEM) in which two or more logic queues (QU1, QU2) are provided for temporarily storing the data packets, a memory management device (MCONTR) for managing the logic queues (QU1, QU2) which is designed to dynamically allocate memory locations to the individual logic queues (QU1, QU2) only when required, a write device (WR) designed to insert an incoming data packet (D1, D2, D3) into one of the logic queues (QU1, QU2) on the basis of data (P1, P2) contained in said data packet, and a server (SER) for reading data packets from the logic queues (QU1, QU2), c h a r a c t e r i z e d i n that the memory management device (MCONTR) is provided with a device for determining data on the lengths (n, n2) of the logic queues (QU1, QU2), and that the write device (WR) is provided with an access control device (ZUG) for re-jecting data packets which is designed to combine data giving information on lengths (n, n2) of logic queues (QU1, QU2) and information on which logic queue (QU1, QU2) an incoming data packet (D1, D2, D3) will be allocated to, in order to make the decision on the rejection of data packets.
8. A facility as claimed in claim 7, characterized in that the write unit (WR) is provided with a device (DIV) for assigning a time stamp (TS) to each incoming data packet (D1, D2, D3), and that the server (SER) is designed so that the order in which the logic queues (QU1, QU2) are served during readout can be influenced by the time stamps (TS).
9. A facility as claimed in claim 7, characterized in that the server (SER) is designed so that it is possible to switch between two or more modes of operation which determine the order in which the individual queues are served.
10. A facility as claimed in claim 7, characterized in that the access control device (ZUG) is designed so that it is possible to switch between at least two modes of operation which relate to the rejection of data packets.
11. An exchange for a communications network for trans-porting data packets, comprising at least one facility for temporarily storing data packets which is provided with a buffer memory (MEM) in which two or more logic queues (QU1, QU2) are provided for temporarily storing the data packets, a memory management device (MCONTR) for managing the logic queues (QU1, QU2) which is designed to dynamically allocate memory locations to the individual logic queues (QU1, QU2) only when required, a write device (WR) designed to insert an incoming data packet (D1, D2, D3) into one of the logic queues (QU1, QU2) on the basis of data (P1, P2) contained in said data packet, and a server (SER) for reading data packets from the logic queues (QU1, QU2), c h a r a c t e r i z e d i n that the memory management device (MCONTR) is provided with a device for determining data on the lengths (n, n2) of the logic queues (QU1, QU2), and that the write device (WR) is provided with an access control device (ZUG) for re-jecting data packets which is designed to combine data giving information on lengths (n, n2) of logic queues (QU1, QU2) and information on which logic queue (QU1, QU2) an incoming data packet (D1, D2, D3) will be allocated to, in order to make the decision on the rejection of data packets.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4328862A DE4328862A1 (en) | 1993-08-27 | 1993-08-27 | Method and device for buffering data packets and switching center with such a device |
| DEP4328862.6 | 1993-08-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2130369A1 true CA2130369A1 (en) | 1995-02-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002130369A Abandoned CA2130369A1 (en) | 1993-08-27 | 1994-08-18 | Method and facility for temporarily storing data packets, and exchange with such a facility |
Country Status (9)
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| US (1) | US5521923A (en) |
| EP (1) | EP0641099B1 (en) |
| JP (1) | JP3575628B2 (en) |
| CN (1) | CN1064500C (en) |
| AT (1) | ATE213369T1 (en) |
| AU (1) | AU679758B2 (en) |
| CA (1) | CA2130369A1 (en) |
| DE (2) | DE4328862A1 (en) |
| ES (1) | ES2172521T3 (en) |
Families Citing this family (83)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FI94814C (en) * | 1993-11-30 | 1995-10-25 | Nokia Telecommunications Oy | Procedure for managing congestion situations in a frame switching network and a subscriber node in a frame switching network |
| JP3458469B2 (en) * | 1994-07-15 | 2003-10-20 | ソニー株式会社 | Signal receiving apparatus and communication method |
| TW252248B (en) * | 1994-08-23 | 1995-07-21 | Ibm | A semiconductor memory based server for providing multimedia information on demand over wide area networks |
| DE19507569C2 (en) * | 1995-03-03 | 1997-02-13 | Siemens Ag | Circuit arrangement for receiving and forwarding message cells through an ATM communication device |
| JP3311234B2 (en) * | 1995-04-24 | 2002-08-05 | キヤノン株式会社 | Network system, node device, and transmission control method |
| EP0748086A1 (en) * | 1995-06-09 | 1996-12-11 | Siemens Aktiengesellschaft | Method for scheduling message cells leaving an ATM node |
| US5809024A (en) * | 1995-07-12 | 1998-09-15 | Bay Networks, Inc. | Memory architecture for a local area network module in an ATM switch |
| US5867663A (en) | 1995-07-19 | 1999-02-02 | Fujitsu Network Communications, Inc. | Method and system for controlling network service parameters in a cell based communications network |
| JP2000501902A (en) * | 1995-07-19 | 2000-02-15 | フジツウ ネットワーク コミュニケーションズ，インコーポレイテッド | Multipoint-to-point arbitration in a network switch |
| JPH0983535A (en) * | 1995-09-14 | 1997-03-28 | Toshiba Corp | Cell data exchange method/device |
| WO1997010656A1 (en) | 1995-09-14 | 1997-03-20 | Fujitsu Network Communications, Inc. | Transmitter controlled flow control for buffer allocation in wide area atm networks |
| DE69635880T2 (en) | 1995-09-18 | 2006-10-05 | Kabushiki Kaisha Toshiba, Kawasaki | System and method for the transmission of parcels, suitable for a large number of entrance gates |
| CA2237869A1 (en) * | 1995-11-17 | 1997-05-29 | Next Level Communications | Cell grant mechanism |
| DK176242B1 (en) * | 1995-11-24 | 2007-04-16 | Tellabs Denmark As | Receiving unit for a data transmission system |
| AU1697697A (en) | 1996-01-16 | 1997-08-11 | Fujitsu Limited | A reliable and flexible multicast mechanism for atm networks |
| EP0810808B1 (en) * | 1996-05-29 | 2009-08-12 | Nippon Telegraph And Telephone Corporation | ATM cell transport equipment |
| US5748905A (en) * | 1996-08-30 | 1998-05-05 | Fujitsu Network Communications, Inc. | Frame classification using classification keys |
| US6222840B1 (en) * | 1996-12-30 | 2001-04-24 | Compaq Computer Corporation | Method and system for performing concurrent read and write cycles in network switch |
| US6201789B1 (en) * | 1996-12-30 | 2001-03-13 | Compaq Computer Corporation | Network switch with dynamic backpressure per port |
| US5926458A (en) * | 1997-01-31 | 1999-07-20 | Bay Networks | Method and apparatus for servicing multiple queues |
| US5914956A (en) * | 1997-02-03 | 1999-06-22 | Williams; Joel R. | Cache for improving the connection capacity of a communications switch |
| DE19705789A1 (en) | 1997-02-14 | 1998-09-03 | Siemens Ag | Method and circuit arrangement for transmitting message cells in the course of virtual connections of different priorities |
| US6041059A (en) * | 1997-04-25 | 2000-03-21 | Mmc Networks, Inc. | Time-wheel ATM cell scheduling |
| KR100247022B1 (en) | 1997-06-11 | 2000-04-01 | 윤종용 | A single switch element of atm switching system and buffer thresholds value decision method |
| KR100216368B1 (en) | 1997-06-11 | 1999-08-16 | 윤종용 | The input buffer controller and logical buffer size decision algorithm |
| NO309918B1 (en) | 1997-08-18 | 2001-04-17 | Ericsson Telefon Ab L M | Procedure related to a data communication system |
| US6643293B1 (en) * | 1997-09-05 | 2003-11-04 | Alcatel Canada Inc. | Virtual connection shaping with hierarchial arbitration |
| US6370144B1 (en) * | 1997-11-05 | 2002-04-09 | Polytechnic University | Methods and apparatus for shaping queued packets using a two-dimensional RAM-based search engine |
| US6389031B1 (en) | 1997-11-05 | 2002-05-14 | Polytechnic University | Methods and apparatus for fairly scheduling queued packets using a ram-based search engine |
| JPH11167560A (en) * | 1997-12-03 | 1999-06-22 | Nec Corp | Data transfer system, switching circuit used to the transfer system, adapter, integrated circuit having the transfer system and data transfer method |
| US7012896B1 (en) | 1998-04-20 | 2006-03-14 | Alcatel | Dedicated bandwidth data communication switch backplane |
| US6314106B1 (en) * | 1998-04-20 | 2001-11-06 | Alcatel Internetworking, Inc. | Receive processing for dedicated bandwidth data communication switch backplane |
| DE19817789C2 (en) | 1998-04-21 | 2001-05-10 | Siemens Ag | Method for controlling packet-oriented data transmission over a switching matrix |
| US6470017B1 (en) * | 1998-04-21 | 2002-10-22 | Nippon Telegraph And Telephone Corporation | Packet multiplexing apparatus |
| FR2778257B1 (en) * | 1998-04-30 | 2000-06-09 | Sgs Thomson Microelectronics | OCCUPANCY BIT FOR EXTERNAL MEMORY INTERFACE OUTPUT BUFFER CIRCUIT |
| JPH11331196A (en) | 1998-05-19 | 1999-11-30 | Nec Corp | Multiservice class definition type atm exchanger |
| US6247061B1 (en) * | 1998-06-09 | 2001-06-12 | Microsoft Corporation | Method and computer program product for scheduling network communication packets originating from different flows having unique service requirements |
| US6807667B1 (en) | 1998-09-21 | 2004-10-19 | Microsoft Corporation | Method and system of an application program interface for abstracting network traffic control components to application programs |
| GB2344031B (en) * | 1998-11-19 | 2004-03-10 | Nds Ltd | Improvements in or relating to processing digital signals |
| US7382736B2 (en) | 1999-01-12 | 2008-06-03 | Mcdata Corporation | Method for scoring queued frames for selective transmission through a switch |
| US6424658B1 (en) | 1999-01-29 | 2002-07-23 | Neomagic Corp. | Store-and-forward network switch using an embedded DRAM |
| US7584472B1 (en) * | 1999-02-08 | 2009-09-01 | Alcatel-Lucent Canada Inc. | Method and apparatus for processing call signaling messages |
| US6421756B1 (en) * | 1999-05-06 | 2002-07-16 | International Business Machines Corporation | Buffer assignment for bridges |
| US6728265B1 (en) * | 1999-07-30 | 2004-04-27 | Intel Corporation | Controlling frame transmission |
| AU2001249545A1 (en) * | 2000-03-31 | 2001-10-15 | Dataplay, Inc. | Asynchronous input/output interface protocol |
| GB2408368B (en) * | 2000-08-18 | 2005-07-06 | Smart Media Ltd | Apparatus, system and method for enhancing data security |
| US7356030B2 (en) * | 2000-11-17 | 2008-04-08 | Foundry Networks, Inc. | Network switch cross point |
| US7236490B2 (en) | 2000-11-17 | 2007-06-26 | Foundry Networks, Inc. | Backplane interface adapter |
| US7596139B2 (en) | 2000-11-17 | 2009-09-29 | Foundry Networks, Inc. | Backplane interface adapter with error control and redundant fabric |
| US7002980B1 (en) * | 2000-12-19 | 2006-02-21 | Chiaro Networks, Ltd. | System and method for router queue and congestion management |
| US20050071545A1 (en) * | 2001-01-11 | 2005-03-31 | Yottayotta, Inc. | Method for embedding a server into a storage subsystem |
| WO2002060132A1 (en) * | 2001-01-25 | 2002-08-01 | Crescent Networks, Inc. | Operation of a multiplicity of time sorted queues with reduced memory |
| US20020169863A1 (en) * | 2001-05-08 | 2002-11-14 | Robert Beckwith | Multi-client to multi-server simulation environment control system (JULEP) |
| US6937607B2 (en) * | 2001-06-21 | 2005-08-30 | Alcatel | Random early discard for cell-switched data switch |
| US20030016625A1 (en) * | 2001-07-23 | 2003-01-23 | Anees Narsinh | Preclassifying traffic during periods of oversubscription |
| US6865388B2 (en) * | 2001-08-09 | 2005-03-08 | Hughes Electronics Corporation | Dynamic queue depth management in a satellite terminal for bandwidth allocations in a broadband satellite communications system |
| US20030067874A1 (en) * | 2001-10-10 | 2003-04-10 | See Michael B. | Central policy based traffic management |
| GB2381407B (en) * | 2001-10-24 | 2004-06-30 | Zarlink Semiconductor Ltd | Dynamic buffering in packet systems |
| US6967951B2 (en) * | 2002-01-11 | 2005-11-22 | Internet Machines Corp. | System for reordering sequenced based packets in a switching network |
| DE10209787B4 (en) * | 2002-02-27 | 2005-10-13 | Technische Universität Dresden | Method for lossless transmission of messages in a switched transmission network |
| US7468975B1 (en) | 2002-05-06 | 2008-12-23 | Foundry Networks, Inc. | Flexible method for processing data packets in a network routing system for enhanced efficiency and monitoring capability |
| US20120155466A1 (en) | 2002-05-06 | 2012-06-21 | Ian Edward Davis | Method and apparatus for efficiently processing data packets in a computer network |
| US7266117B1 (en) | 2002-05-06 | 2007-09-04 | Foundry Networks, Inc. | System architecture for very fast ethernet blade |
| US7649885B1 (en) | 2002-05-06 | 2010-01-19 | Foundry Networks, Inc. | Network routing system for enhanced efficiency and monitoring capability |
| US7187687B1 (en) | 2002-05-06 | 2007-03-06 | Foundry Networks, Inc. | Pipeline method and system for switching packets |
| US6901072B1 (en) * | 2003-05-15 | 2005-05-31 | Foundry Networks, Inc. | System and method for high speed packet transmission implementing dual transmit and receive pipelines |
| WO2005015349A2 (en) * | 2003-08-08 | 2005-02-17 | Yottayotta, Inc. | Method for embedding a server into a storage subsystem |
| US7817659B2 (en) | 2004-03-26 | 2010-10-19 | Foundry Networks, Llc | Method and apparatus for aggregating input data streams |
| US8730961B1 (en) | 2004-04-26 | 2014-05-20 | Foundry Networks, Llc | System and method for optimizing router lookup |
| US7657703B1 (en) | 2004-10-29 | 2010-02-02 | Foundry Networks, Inc. | Double density content addressable memory (CAM) lookup scheme |
| US8448162B2 (en) | 2005-12-28 | 2013-05-21 | Foundry Networks, Llc | Hitless software upgrades |
| US7903654B2 (en) | 2006-08-22 | 2011-03-08 | Foundry Networks, Llc | System and method for ECMP load sharing |
| US8238255B2 (en) | 2006-11-22 | 2012-08-07 | Foundry Networks, Llc | Recovering from failures without impact on data traffic in a shared bus architecture |
| US8395996B2 (en) | 2007-01-11 | 2013-03-12 | Foundry Networks, Llc | Techniques for processing incoming failure detection protocol packets |
| US8037399B2 (en) | 2007-07-18 | 2011-10-11 | Foundry Networks, Llc | Techniques for segmented CRC design in high speed networks |
| US8271859B2 (en) | 2007-07-18 | 2012-09-18 | Foundry Networks Llc | Segmented CRC design in high speed networks |
| US8149839B1 (en) | 2007-09-26 | 2012-04-03 | Foundry Networks, Llc | Selection of trunk ports and paths using rotation |
| US8190881B2 (en) * | 2007-10-15 | 2012-05-29 | Foundry Networks Llc | Scalable distributed web-based authentication |
| US8090901B2 (en) | 2009-05-14 | 2012-01-03 | Brocade Communications Systems, Inc. | TCAM management approach that minimize movements |
| US8599850B2 (en) | 2009-09-21 | 2013-12-03 | Brocade Communications Systems, Inc. | Provisioning single or multistage networks using ethernet service instances (ESIs) |
| US9077586B2 (en) * | 2010-11-03 | 2015-07-07 | Broadcom Corporation | Unified vehicle network frame protocol |
| US9674086B2 (en) * | 2013-11-05 | 2017-06-06 | Cisco Technology, Inc. | Work conserving schedular based on ranking |
| KR20220102160A (en) * | 2021-01-11 | 2022-07-20 | 삼성전자주식회사 | Switch for transmitting packet, network on chip having the same, and operating method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4630261A (en) * | 1984-07-30 | 1986-12-16 | International Business Machines Corp. | Integrated buffer management and signaling technique |
| US5222085A (en) * | 1987-10-15 | 1993-06-22 | Peter Newman | Self-routing switching element and fast packet switch |
| US5157654A (en) * | 1990-12-18 | 1992-10-20 | Bell Communications Research, Inc. | Technique for resolving output port contention in a high speed packet switch |
| US5367643A (en) * | 1991-02-06 | 1994-11-22 | International Business Machines Corporation | Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets |
| US5361372A (en) * | 1991-12-27 | 1994-11-01 | Digital Equipment Corporation | Memory management for data transmission networks |
| US5381413A (en) * | 1992-12-28 | 1995-01-10 | Starlight Networks | Data throttling system for a communications network |
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1993
- 1993-08-27 DE DE4328862A patent/DE4328862A1/en not_active Withdrawn
-
1994
- 1994-08-18 AU AU70348/94A patent/AU679758B2/en not_active Expired
- 1994-08-18 CA CA002130369A patent/CA2130369A1/en not_active Abandoned
- 1994-08-23 EP EP94113129A patent/EP0641099B1/en not_active Expired - Lifetime
- 1994-08-23 AT AT94113129T patent/ATE213369T1/en active
- 1994-08-23 DE DE59410045T patent/DE59410045D1/en not_active Expired - Lifetime
- 1994-08-23 ES ES94113129T patent/ES2172521T3/en not_active Expired - Lifetime
- 1994-08-24 US US08/295,521 patent/US5521923A/en not_active Expired - Lifetime
- 1994-08-26 CN CN94115722A patent/CN1064500C/en not_active Expired - Lifetime
- 1994-08-29 JP JP20383194A patent/JP3575628B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| ES2172521T3 (en) | 2002-10-01 |
| AU7034894A (en) | 1995-03-09 |
| JP3575628B2 (en) | 2004-10-13 |
| DE4328862A1 (en) | 1995-03-02 |
| CN1064500C (en) | 2001-04-11 |
| ATE213369T1 (en) | 2002-02-15 |
| US5521923A (en) | 1996-05-28 |
| EP0641099B1 (en) | 2002-02-13 |
| JPH07154424A (en) | 1995-06-16 |
| CN1109231A (en) | 1995-09-27 |
| AU679758B2 (en) | 1997-07-10 |
| EP0641099A1 (en) | 1995-03-01 |
| DE59410045D1 (en) | 2002-03-21 |
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| Date | Code | Title | Description |
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| FZDE | Discontinued |