CA2093439A1 - Thermal control for laser diode used in outside plant communications terminal - Google Patents
Thermal control for laser diode used in outside plant communications terminalInfo
- Publication number
- CA2093439A1 CA2093439A1 CA002093439A CA2093439A CA2093439A1 CA 2093439 A1 CA2093439 A1 CA 2093439A1 CA 002093439 A CA002093439 A CA 002093439A CA 2093439 A CA2093439 A CA 2093439A CA 2093439 A1 CA2093439 A1 CA 2093439A1
- Authority
- CA
- Canada
- Prior art keywords
- laser diode
- signal
- set forth
- burst mode
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
- H01S5/068—Stabilisation of laser output parameters
- H01S5/0683—Stabilisation of laser output parameters by monitoring the optical output parameters
- H01S5/06835—Stabilising during pulse modulation or generation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/501—Structural aspects
- H04B10/503—Laser transmitters
- H04B10/504—Laser transmitters using direct modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/564—Power control
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
- H01S5/068—Stabilisation of laser output parameters
- H01S5/06812—Stabilisation of laser output parameters by monitoring or fixing the threshold current or other specific points of the L-I or V-I characteristics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
- H01S5/068—Stabilisation of laser output parameters
- H01S5/06825—Protecting the laser, e.g. during switch-on/off, detection of malfunctioning or degradation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
- H01S5/4025—Array arrangements, e.g. constituted by discrete laser diodes or laser bar
- H01S5/4031—Edge-emitting structures
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Lasers (AREA)
- Optical Communication System (AREA)
- Optical Couplings Of Light Guides (AREA)
Abstract
A method and apparatus implementing the method are provided for controlling optical power output level of a laser diode (18) modulated during a burst mode interval by digital data transitions within a shared logical bus (16) optical communications network (10) and over a predetermined thermal gradient. The method comprises the steps of: optically monitoring a component of the optical output power of the laser diode (18) during each burst mode interval and converting the component into a control signal, establishing a reference signal and comparing the control signal with the established reference signal and for providing a logical condition from said comparison, generating a strobe signal from information related in time to the burst mode interval, storing the logical condition upon receipt of the strobe signal, integrating the stored logical condition over a time period to provide an integrated control signal, and regulating current flow through the laser diode in accordance with the integrated control signal.
Description
WO 91/15886 PCI/US91/~2304 , 2093439 THERMAL CONTROL FOR LASER DIODE USED IN
OUTSIDE PLANT COMMUNICATIONS TERMIN~4L
The present invention relates to control circuitry for automatically s regulating optical output power of a laser diode over a thermal gradient.
Communications systems employing optical fiber cables are proliferating, due to the many advantages associat~ d with the optical filber medium. While optical fiber long distance trunks between central of fice 10 switching points are well established, optical fi~er paths have not yet been extended on a widespread basis to service subscriber locations. Central office locations provide a controlled environment for the optical transmission and reception apparatus associated with the cable. For instance, power supply levels are sufflcient at the central office to provide 15 needed heating and/or cooling to maintain temperature control of light emitting elements used in the optical communications path. While laser diodes are known to be useful for light beam comrnunications over optical fibers, such laser diodes are not well suited for use at subscriber locations unless they are located in a house or building having a controlled 20 temperature.
It is known that optical output power of a laser diode varies with temperature. The prior art has addressed this characteristlc in several ways. One approach has been to control the environment in which the 2 5 laser diode is operative. Heating and cooling devices have been employed to achieve a regulated temperature environment for the laser diode. One practical cooling mechanism for cooling a laser diode has been to employ junction devices implementing the Peltier effect at a junction of dissimilar materials~ Joule heating has also been employed to provide heating to the 30 laser diode.
One drawback of Peltier effect junctions and heating devices is that they are not efficient and typically require considerable operating power to achieve relatively modest heating and cooling effects. While laser 3 5 diodes which are located at central offlce or head end interface units of an WO 91/15886 PCr/lJS91/02304 -2- ~93~39 optical fiber cornmunicalions network may be maintained within very close thermal tolerances, laser diodes of subscriber interface units remotely located from the office interface unit are typically subjected to much harsher thermal gradients, especially if located outdoors. Outdoor 5 subscriber interface units are typically small weather-resistant enclosures which are located within about 200 feet of a subscriber's premises. Such units are typically exposed to ~e ambient environment. In some climates, the ambient environment may present a thermal gradient from -40 degrees Centigrade to +70 degrees Centigrade. Also, the power at each 10 subscriber interface unit is very limited, and power is not available to provide Joule heating or Peltier cell cooling for the laser diode transmitter.
Optical fiber communications networks have typically been 5 configured in a variety of architectures, including point-to-point, star, ring and bus. One advantage of a logical bus architecture is that it works particularly well within the conventional outside plant environment between the central offlce and subscriber premises.
With the lo"ical bus architecture, time division multiple~
techniques have been adopted to provide each subscriber interface unit with necessary access to the office interface unit at the central office or head end of the bus. Time division mul~iplex allots time slots to each of the subscriber inter~ace units, and only one subscriber interface unit will 2 s send or receive data during its tirne slot in any given time frame. When laser diodes are operated only during a narrow time slot of an overall duty cycle, conventional power control techniques will not work since the laser diode is dark most of the time. Also, with subscriber interface units distributed along a logical bus, differing optical path losses require that a mechanism be provided to enable dynamic adjustment of the optical power level of each laser diode of the subscriber interf~ce unit, so that those units most distant from the office interface unit put out the greatest optical power.
WO 91/15886 PCriUS91/02304 3_ 2093~39 Thus, a hitherto unsolved need has arisen for a power control circui~ for regulating optical power output of a laser diode operating in a time division multiplex mode and over a wide range the~nal gradient.
A general object of the present invention is to provide a power control circuit and power regulation method for a laser diode operating in a time division multipIex burst mode across a thermaI gradient in a manner which overcomes limitations and drawbacks of ~e pnor art.
A more specific object of dle present invention is to generate a feedbaclc control signal based upon detection of a component of actual peak optical E~ower output.
Another more specific object of the present invention is to generate a feedback control signal based upon detection of an optical power threshold or turn-on knee characteristic as detected dunng a pedestal interval occurring during a beginning of a data packet time slot.
A fur~er more specific object of the present invention is to provide 20 a power control circuit which establishes peak power in response to externally controlled bias level cornmands, and which generates a power regulation control signal based upon optical feedback from the laser diode and the particular bias level cornmand.
One more specific object of the present invention is to provide circuitry and methods for regulating optical power of a laser diode over a remotely controllable dynamic range with circuitry which is available, inexpensive and reliable in use over a severe thermal gradient, such as from ~0 degrees C to + 70 degrees C.
Yet another specific object of the present invention is to provide circuitry and methods for regulating optical power of a laser diode used within outside plant communications terminal equipment, particuiarly equipment using a laser powered bus having a maxirnum voltage less than WO 91/lS886 PCl'/US91/02304 4_ 2093~39 20V, specifically less ~han 15V, optirnally less than 10V, particularly less than 8V, more specifically less than 6V, especially one which supplies 5 volts or less voltage.
One more specific object of the present invent;on is to provide an inexpensive circuit for regulating optical power of a laser diode used within outside plant communications terminal equipment and which also provides a con~rol strobe signal which indicates to the terminal equipment and in turn to head end equipment the relative humidity at the terminal 10 equipment.
In accordance with a facet of the present invention, a control circuit is provided for controlling the output power level of a laser diode operating periodically in a burst mode interval within a time division 15 multiplex optical communications network. In this particular arrangement, preferably the laser diode includes a reverse facet photodetector or other circuitry for monitoling a component of the optical output power of the laser diode during each burst mode ~nterval.
Ths con~r~l cirçuit includes a transimpedance amplifier for converting a current signal from the photodetector into an optical le-rel voltage representative of sensed optical power during dle burst mode interval; a comparator for comparing the optical level voltage with an established reference voltage and for providing a signal representing a 25 logical condition from said comparison; a clocked storage device for storing the signal representing the logical condition upon receipt of a strobe signal; an integrator for integrating the stored logica} condition over a time period to provide a contro} signal; a current control circuit in series with the laser diode and responsive to the control signal to regulate 30 current flow through the laser diode; and, a s~obe generator for generating the strobe signal from information related in time to ~e burst mode interval.
WO 91/15886 PCI'/~JS91/02304 -5- 2~93~39 In one aspect of this facet of the invention, an optical power control circuit is provided for responding to externally supplied logical signals by controlling bias current through the laser diode during each said burst mode interval.
In another aspect of this facet of the invention, an altemating current (AC) coupling device is provided between the ~nsimpedance amplifier and an inpu~ of the eomparator, and a voltage clamp is connected to said input of the comparator for cl~nping the voltage at said 10 input to approximately zero volts in the absence of an output of the optical level voltage from ~e transimpedance amplifier and wherein the reference voltage is adjusted to maintain optical power of the laser diode in relation to peak optical power level thereof.
In one more aspect of this facet of the invention, the reference voltage is established in relation to the setting of the optical power control c}rcuit.
In yet another aspect of this facet of the invention, the control circui~ receives and responds to a transmit enable con~ol signal mar~ing in time the boundaries of the burst mode interval and ~e control circuit fur~er receives and modulates a bias current through the laser diode wi~h digital data transitions representing cornmunications information.
In still one more aspect of this facet of the invention, ~e strobe generation circuit is responsive to a transition of the transmit control signal marking the end bouuldary of the burst mode interval.
In yet one more aspect of this facet of the invention, the digital data transitions are presented to the laser diode after a predetelmined pedestal interval, and the strobe generation circuit is responsive to the beginning of the digital data transition within the interval.
WO 91/15886 PCr/US91/02304 -6- 2~3~39 Ln another aspect of this facet of ~e invention, ~e transimpedance amplifier is directly coupled to an input of the comparator, and a resistor-capacitor network is connected eo a voltage reference input of the comparator and to the direct coupled input of ~e comparator, the time 5 constant of the resis~or-capacitor network being longer than the pedestal interval thereby to supply as a dynamic reference voltage to the comp~rator the voltage present at the directly coupled input before the occurrence of the burst mode interval. This aspect preferably further includes a biasing circuit for presetting the state of ~le comparator to a 10 known logical condition before the burst interval. ~1 one implementation a bias resistor may apply positive preset bias to the plus input of the comparator. In another implementation, a bias resistor may apply negative preset bias to the minus input of the comparator.
In one more aspect of this facet of the invention, an optical power biasing circuit is provided for responding to externally supplied logical signals by controlling bias current through the laser diode during each burst mode interval.
2 0 In another facet of the present invention, a methQd is provided ~r controlling optical power output level of a laser diode modulated during a burst mode interval by digital data transitions within a shared bus optical communications network and over a thelmal gradient. The method of this facet comprises the steps of:
optically monitoring a component of the optical output power of the laser diode during each burst mode interval and converting the component into a control signal, establishing a reference signal and comparing the control signal, with the established reference signal and for providing a signal representing a logical condition ~rom said comparison, WO 91/15886 PCl'~US91/02304 storing the signal representing the logical condition upon receipt of a strobe signal, integrating the stored signal representing the logical condition over - 5 a time period to provide an integrated contro;L signal, regulating current flow ~rough the laser diode in accordance with the integrated control signal, and generating the strobe signal from infolmatiorl related in time to the burst mode interval.
In one aspect of this facet of the invention, a further step is provided for responding ~o extemally supplied logical condition signals by controlling current flow through the laser diode during each said burst mode interval.
In another aspect of this facet of the invention, the step of converting the component into a control signal comprises the steps of ?.0 converting tbe component in~o a current with a photocliode and translatingthe current into a control voltage with transimpedance amplifier means, and wherein the step of comparing the control signal with a reference signal comprises comparing the control voltage with a reference voltage.
In a further aspect of ~is facet of the invention, a further step is provided for coupling ~e control voltage to a comparator ~or carrying out the comparing step with an alternating current coupling and including the further step of clamping the altemating current coupled control voltage to approximately zero volts in the absence of an ou~put of said optical component and including the fur~er step of adjusting said reference voltage to maintain optical power of the laser diode in relation to peak optical power leveI thereof.
WO 91/t5886 PCI/US91/0231)4 -8- 20~343~
In one more aspect of this facet of the invention, the step of establishing the reference signal is carned out in relation to a further step of controlling current flow through the laser diode dunng each burst mode interYal in response to externally supplied logical signals.
In yet another aspect of this facet of the invention, the burst mode interval is established by an externally supplied transmit enable control signal and the digital data transitions are t~anslated to optical output power during the inteIval mar~ed by ~e transmit enable con~ol signal.
In still another aspect of this facet of the invention, the step of generating the strobe is carried out in response to a transition of the transmit enable control signal marlcing the end boundary of the burst mode interval.
In one more aspect of this facet of the invention, the digital data transitions are presented to the laser diode after a predetermined pedestal interval within the burst mode interval, and the step of generating the strobe occurs after the pedestal interval has passed and the beginning of 20 ~he digital data transition has occurred within the interval.
In still another aspect of this facet of the invention, fur~er steps are provided ~or directly coupling the control signal to an input of a 2 5 comparator for car~ing out the comparing step and providing a signal storage device at another input of the comparator coupled to the one input and having a predetermined time constant, and wherein the time constant of the signal storage device is made lor~lger than the pedestal inten~al so that the step of establishing the reference signal is carried out by 3 o supplying to the another input the signal stored in the signal storage device.
WO 91/15886 PCl`/~S91/02304 9 20~3~39 In one more aspect of this facet of the invention, a further step is provided for controlling the operating power through said laser diode in response to extemally supplied logical signals.
In one more aspect of this facet of the invention, the method includes a further step of generating a signal indicative of relative humidity at the vicinity of the laser diode. In this as]pect, a preferred implementation generates the signal indicative of reLative humidity by by pulsewidth-modula~ion of the strobe signal.
These and other objects, advantages, aspects, facets and features of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of the following preferred embodiments, presented in conjunction with the accompanying drawing.
Fig. 1 is a block diagram of a bus optical fiber communications network in which an office mterface unit (OIU) supports a plurality of subscriber interface units (SIUs) via transmit and receive shared optical filber paths.
Fig. 2 is a representative family of curves graphing optical power output as a function of laser current over a temperature range of 40 C to +70 C.
Figs. 3A and 3B represent a single schematic diagram of one presently preferred form of control circuit for controlling optical output power of a laser diode in accordance with principles of the present invention. Fig. 3A forms the left half, and Fig. 3B the right half, of the schematic diagram.
Fig. 4 is a graph of wave-forms illustrating pertinent operational characteristics of the Fig. 3 circuit.
-lO- 20~3~39 Figs. SA and SB represent a single schematic circuit diagram of another presen~ly pre~erred form of control circui~ for controlling optical output power of a laser diode in accordance with principles of the present invention. Fig. 5A forrns the left half, and Fig. SB the right half, 5 of the schematic diag~m.
Fig. 6 is a graph of wave-forms illustrating pertinent operational characteristics of the Fig. S circuit;
~igs. 7A-7B and 8A-8B are similar respective to Figs. 3A 3B and SA-SB except for the substitution of a digital counter/integrator for the RC integrators utilized in Figs. 3A-3B and SA-SB, the digital counter/integrator allowing feedback control to be implemented less frequented than RC integrators.
Fig. 8C is an alternative embodLment of the comparator circuit illustrating a pull-down resistor rather than a pull-up resistor.
Fig. 8D is a waveform graph illustrating an excessive bias condition 20 so as to illus~ate one mode of operation of t~e Figs. gC and 8D circuits.
An optical fiber communications network 10 includes an off~ce interface unit ("OIU") 12 and a plurality of subscriber interface units ("SIU") 14a, 14b, . . .14n-1, and 14n. Twen~ four SIlJs 14 are presently 25 preferred. The OIU 12 communicates with each SIU 14 in its time slot via an optical fiber bus 16. A transmit fiber 16T enables ~e OIU 12 to transmit to each SIU 14, and a receive fiber 16R enables each SIU 14 to transmit in its turn to the OIU 12. Time division multiple~ing techniques are preferably employed. For exarnple, in one overall operational cycle 30 or frame of 125 microseconds, each SIU 14 is allotted a time slot of about 4 microseconds with the time slots being separated by dead spacings. l~is means that the optical laser diode of a particular SIU 14 is on for 4 microseconds, and is off for the balance of each cycle or frame.
WO 91/15886 PCI/US~1/02304 2 0 ~ 9 The OIU 1~, sometimes referred to as a head-end unit, has a very sensitive reGeiver and a suf~lciently powerful transmitter to be able to receive and send signals, preferably digital, to ~e most distant SIU 14n on the bus 16. The OIU 12 and each SIU 14 include application specific 5 microcontrollers' which communicate with each other over the optical fiber bus 16, so that the OTU 12 can control operations at each SIU 14, and so that the status of-each SIU 14 may be reported bacl; to the O[U 12.
The OIU 12 is typically contained in a controlled environment, 10 such as a central office switching center, or other caLI concen~ation and forwarding location of a telecommunications network~ while each SIU 14 is part of an outside plant installation and is located ideally not more than about 200 feet from each subscriber's premises. Wire pairs or coaxial cable extend from the SIU 14 to the subscriber's premises to provide 15 telecommunications service access to ~e subscriber. A single SIU 14 may accomrnodate a number of subscriber service lines. While the OIU 12 is located in an environment in which the power supply is not an issue, and where temperature of transmit laser diodes may be carefully regulated by conventional means, each SIU located in the outside plant has a very ~o ]imi~ed p~wer supply. Conventional temperature compensation techniques for a Iaser diode transmitter at the SIU 14 are not available.
Fig. 2 presents a family of characteristic curves for a laser diode 18 of the type employed in each SIU 14. The laser diode 18 (Fig. 3) may be a 25 type PU-llSLD-N made by Mitsubishi, or equivalent. The laser diode 1$
has a forward direction optical facet, Md has a reverse facet in proximity with a photodiode 20 which enables indirect sensing of the optical power put out in the forward direction. Light energy at the reverse facet closely approximates the light energy at the forward facet.
According to Fig. 2, the current passing through the laser diode, for a given optical power, varies considerably with temperature. The lef~nost curve represents the current vs. optical power output at a diode temperature of -40 C, while the rightmost curve represents laser current WO 91/158~6 PCr/US9t/OX304 -12- 2093~3~
vs. optical power output at the other temperature extreme, such as +70 C.
At the lowest temperature the laser diode 18 manifests a turn-on threshold or knee at approximately S milliamperes, whereas at the highest temperature, the tum-on curlent is about 30 milliamperes. Since ~e SIU
5 14 (and its laser diode 18) is located in the extemal ambient, in some clisnates the temperature range shown in Fig. 2 may be present as the seasons change.
Turning now to Figs. 3A-3B, a control circuit 22 is proYided for 10 controlling two aspects of the operation of the laser diode 18. The first control aspect is one for adjusting dynamically the power output level, so that the OIU }2 can command that the power level be increased for more distantly located SIUs 14 and reduced for the SIUs located nearby. The second control aspect is one which tracks and compensates for variations in optical output otherwise caused by various variables, particularly temperature changes. The implementation of these two control aspects will now be considered.
Digital data (BAR TxD) enters the circuit 22 on a line 24 and a time 20 slo~ control signal (BAR TxEN) enters the ~ircuit on a line 26. The digital data passes through gates 28, 30 and 32 to a subcircuit 34 which enables the power level of the laser diode 18 to be set dynamically, e.g. the first control aspect. Ultima~ely, the data signal BAR TxD is combined wi~ a bias current from control t~nsistor 44 and appears at a node 36 leading to 25 the cathode of the laser diode 18. The power level set by the subcircuit 34 is set by digital values suppiied over a control bus 38 from an ASIC
controller (not shown) included within the SIU 14. The SIU controller establishes the power level at the SIU in accordance with ins~uctions it receives from its counterpart at the OIU 12.
The time slot control signal BAR TxEN passes through a gate 40 and through one input of the AND gate 30 to block the data signal BAR
TxD except during the ~ne that the time slot control signal is active.
Simultaneously, the time slot control signal passes through a Schottky - WO 91/15886 PCI'/US9t/02304 -13- 2~93~39 junction diode 42 to the control transistor 44 in series with a resistor 46 and the cathode of the laser diode 18. The transistor 44 provides a proportional adjustment of bias current for the laser diode and acts to control the bias current over a wide temperature range in accordance with 5 a further control signal, the generation of which will be e~pIained hereinafter, e.g. the second control aspect. The anode of the laser diode 18 leads to a +5 volt digital electrical power bus 48. A choke 50 also connects to ~e bus 48 and separates the digital side thereof from an analog side 52 dlereof. Filter capacitors are on both the digital and analog sides o of the ~5 volt supply bus. The reverse facet photodetector diode 20 is cormected to a transimpedance amplifier 54 which converts the current developed through the diode 20 into a voltage which is proportional to the instantaneous peak optical power ou~tput of the laser diode 18 which is detected during the time sIot fixed by the time slot control signal BAR
TxEN. The proportional voltage put out by the amplifler 54 leads ~rough a coupling capacitor 56 to a node 62 to which two reverse-connected Schottky diodes 58 and 60 which are biased to clamp ~he node 62 (at roughly zero volts) during the peak negative excursion of a signal passing through the capacitor 56. The node 62 provides one input (Vo) to 2 Q a comparator 64. More speci~lcally, the capasitor 56 and diodes 58, 6n function to clamp onto the peak negative voltage generated by ~e diode 20 throughout the time slot, which peak vol~ge Vo is inputted into the comparator 64 via the node 62. Dunng a da~ period of the frame, the voltage Vo is drained by resistor 17.
A predetermined reference voltage is provided at the other input to the comparator 64 from a potentiometer 66 which permits adjustment of the regulated power output of the laser diode 1 B. The wiper of the potentiometer 66 leads through an operational amplifier 68 which puts 30 out a VREF signal on a line 70 leading to a resistor-capacitor parallel network at the reference voltage input of the comparator 64. An output node 76 of the comparator 64 provides a binary value indica~ing whether the voltage, Vo, on the node 62 is above or below ~e reference voltage VREF on the line 70. The binary value is ~en strobed into a latch 78 in -14- 209~33 accordance with a cloc~cing signal developed fro m ~he rising edge of ~e tirne slot control signal BAR TxEN (Fig. 4). l~is rising edge clocking signal passes through the gate 40 and a gate 80 to ma,inta~n i~s original logical condition as an inverted control signal. The gate ~0 leads via a line 5 82 to a clocking input of a flip-flop 84 configured as a one shot. The duration of the pulse put out by the flip-flop 84 over a clock line 90 is established by the time constant of a series RC nehvork including a capacitor 86 and a resistor 88.
Advantageously, the capacitor 86 is one having a characteristic which varies in a known way with changes in relative humidity. Thus, the width (w) (Fig. 4) of the clocking pulse put out on the line 90 is related to the relative humidity within the SIU 14. If excess moisture intrudes into the interior space of the SIU 14, the width of the clocking pulse on the line 15 90 will change. The pulse width of this signal is monitored by the ASIC
controller of the SIU 14, and if it exceeds a predeterrnined acceptable range, a warning signal is sent by the controller to the OIU 12 so that an alarrn may be generated and service personnel dispatched to the particular SIU. The dotted line 53 in Fig. 4 repre~ents an alternative possible width 20 nf the clocking pulse, the ac~ual width (w) encountered in practic~
depending on the hurnidity as sensed by ~e capacitor 86, as explained.
The clocking signal on the line 90 clocks the binary value into the latch 78. An inverted output of the latch 78 leads to an input of an 2s operational amplifier 92 configured as an integrator by virtue of a feedback capacitor 94. An output line 96 from the integrator 92 leads through a series resistor 98 to the base of the control transistor 44.
Another resistor 100 also connects the base of the control transistor 44 to ground. The signal on the line 96 controls the arnount of current passing 30 through the transistor 44 and in turn the amount of current passing through the laser diode 18.
It should be noted that the voltage appearing across the power adjustrnent potentiorneter 66 is dynamically adjusted to track the power ~ WO 91/15886 PCI/US91/Q2304 -15- 2~93.~9 setting commanded by the OIU over the control bus 38. To this end, a gate 102 and resistor 104 provide an adjustment when one bit line of the bus 38 is enabled. Similarly, a gate 106 and a resistor 108 make a fur~er dynarnic adjustment when another bit line of the bus 38 is enabled. The 5 resistors 104 and 108 are within a voltage divider net~vork leading from the analog +5 voltbus 52 and also including series r~sistors 110 and 112 leading to the potentiometer 66.
Operation of ~e circuit 22 will now be explained in conjunction 10 with Fig. 4. Therein in graph A the time slot control signaI BAR TxEN is shown to be a negative going pulse of approximat~ly four microseconds duration within an overall recurrent operational cycle or ~rame of 125 microseconds, for example. The particular SIU 14 is only able to transmit during its 4 microsecond time slot in the overall cycle. In graph B the BAR TxD data signal, more specifically node 62 and Vo, is shown for two BAR TxEN time slots. In the left tirne slot data burst, the peak negative excursion is shown to be less than a value fixed by the VREF
value on the line 70. When the peak negative exclusion is converted to a voltage and compared with VREF in the comparator 64, the binary output 20 is a logical HIGH. At thé clock time, which coincides with ~e rising edge of the BAR TxEN time slot control signal (at the end of ~is pulse), ~e logical HIGH binary value is strobed into ~e flip-flop 78, and its inverted -output is then LOW for the remainder of dle 125 microsecond overall operational cycle. This logical LOW value causes the integrator 94 to 25 increase the voltage level on the line 96 during dle remainder of the operational cycle, with the rate of increase fixed by the time constant formed by the integration feedback capacitor 94 and a low value seAes resistor 95. The increasing voltage is presented to the control transistor 44, and duAng the next BAR TxEN time slot, more current will flow 30 through the control transistor 44, and more current will consequentIy flow through the laser diode 18.
At the Aght side of Graph B of Fig. 4, the peak amplitude of optical power put out by the laser 18 is greater than the VREF value. In this ~ - WO 91/15886 P(~T/US91/02304 -16- 2~93~9 situation, the opposite condition results a~ ~e output of the comparator 64, and a LOW level is latched into the flip-flop 78 by the strobe pulse on the line 90. The inverted output of d~e flip-flop 78 is now HIGH, causing the integrator 94 to lower the voltage put out on the line 96 leading back 5 to the base of the control transistor 44.
During operation of the circuit 22, the binary value put out by the comparator 64 will dither about the VREF setpoint, which is preset to be at the desired ma~imum peak optical power output level for the particular 10 laser diode 18. As the temperature changes, the bina~y value put out by the comparator will correspond to the direction of temperature change, and either successively raise or lower the base voltage to the transistor so that the peak negative excursion continues to dither about the VREF
setpoint. Since the circuit 22 monitors peak optical power output of the laser diode 18, and dynamically corrects that power output level, it remains substantially constant over a ~ery wide temperature range and compensates for other variables as well, such as laser diode aging.
Graph C of Fig. 4 illustrates the strobe pulse on the line 90 as being 2 o of variable duration, based on the humidity within the SIU as sensed by the capacitor 86. As humidity varies, pulse width varies as designated by the dashed lines in Graph C of Fig. 4.. Advantageously, the flip-flop 78 is edge-triggered, and is therefore insensitive to actual duration of the pulse, whereas the duration may be counted by a counter of the ASIC con~oller 25 of the SIU and used to indicate an alarm if excessive moisture colleets or is present within the housing of ~e SIU 14.
While the circuit 22 of Figs. 3A-3B operates very satisfactorily to detect peak optical power output from the laser diode 18 during the time 3 o slot when light energy is being detected by the photodetector diode 20 and thereby regulate optical power over thermal gradient, the circuit 22 has some slight drawbacks.
WO 91/15886 PCl'/US91/02304 -17- 2093~39 For one thing, the circuit measures and controls ~e peak optical power by controlling the DC bias current in the laser. The precise DC
operating point of the laser is not accurately determined. Therefore, because of the extreme nonlinear nature of the laser charac~eristics as 5 shown in Fig. 2, the range of the programmable optical power is limited to about 6 dB in a practical case. Furthe~ore, the analog voltage bus is limited to +S volts because of power constraints at the remo~ely sihlated SIU 14. 1 he +5 volt bus effectively limits the linear range of ~e integrator 94 to about l.S vol~s which has ~e consequence of limiting the 10 dynamic range of the circuit 22. If a 10 dB adjustment range were desired, such as one volt to 100 millivolts at the lower level the diodes 58 and 60 are inoperative to clarnp the node 62.
The circuit 122 in Figs. SA-5B operates upon the same premise of 15 permitting the laser diode 18 to operate in accordance with its particular characteristics over the thermal gradient, but tracks optical power differently. The Fig. SA-SB circuit monitors the turn-on knee of the laser diode and sets the dynamic range from that point, rather than from maximum peak power as is done with the circuit 22 thereby insuring that 20 the laser o~erates in the linear region. In the circuit l 22 like re~erence numerals are used for elements that correspond generally wi~ like elements in the circuit 22, while different numerals are given to those elements of the Fig. SA-SB circuit 122 which differ from the Fig. 3A-3B
circuit 22.
The Fig. SA-SB circuit 122 detects the location of the turn-on threshold or knee of the optical laser diode 18 over the operating temperature range. As noted, this approach has some advantage over ~he circuit 22 by providing a greater dynamic range for commanding optical 30 power output levels. Whereas about 6 dB of power tuning is available with the circuit 22 using a ~SV bus, the circuit 122 provides a power tuning control bus 38 having a greater power tuning range above the tum-on knee of the characteristic curve at a particular ambient operating temperature.
' WO 91/15886 PCltlJS~1/023Q4 -18- 2~93~39 In the circuit 122, the BAR TxEN signal is generated slightly ahead of the beginning of data. For example, Fig. 6 shows the BAR TxEN burst enable signal having a falling edge at tl, and the beginning of the data burst 5 BAR TxD occurring at a later time t2. According to a pre~elTed em~odiment, t~ne t2 occurs about 400 nanoseconds after time tl. When the BAR TxEN signal goes LOW, the dio~de 42 becomes reverse biased, and the laser diode 18 begins to lase at its turn-on knee of its characterIstic culve. Since data is not yet present, the photodiode 20 puts out what 10 amounts to a pedestal current above the diode dark current level.
The transimpedance ampli~ler 54 changes the dark current to a voltage 123 and the pedestal current to a lower pedestal voltage 124, as graphed in Fig. 6E. The pedestal voltage 124 is supplied to the non-inverting input of the comparator, while a predetermined reference voltage 126 held by a storage capacitor 128 is supplied to the inverting input of the comparator 64.
A resistor 130 ~rom the ~S volt analog bus 52 and the bias current 20 flowing through the tr~nsimpedance ampli~er 54 prÇsent nomir a!
voltage to the non-inverting input of the comparator 64 such as about 3 volts in the absence of a change in voltage from the transimpedance amplifier 54 due to the pedestal 124. Since the inverting input is also connected to this input bias point, the same dark current voltage is present 25 to the inverting input after the capacitor 128 charges. The dark current voltage present at the inverting input, e.g. node 126, corresponds to a predetermined reference voltage which establishes the desired point for the tum-on knee for the laser diode.
When the BAR TxEN signal goes LOW, the dark current voltage 123 falls rapidly (e.g. wi~in about 400 nsec) to the pedestal voltage 124 as supplied to the non-inverting input of the comparator whereas the dark current voltage 126 supplied to the inverting input is held by the capacitor 128 and thereby becomes a dynamic reference voltage. Accordingly, if WO 91/15886 PCI/US91/023~4 -19- 2~9~39 the comparator is strobed about 400 nsec after the falling edge of the BAR TxEN signal, a comparison of the voltages at nodes 124 and 126 results in the comparator 64 and flip flop 78. If the strobed pedestal voltage 124 is ~elow the voltage present at the inveIting input of node 126 5 as held by the capacitor 128, the output of the comparator 64 is LOW
(indicating too much light), and this causes ~e latch 78 to put out a LOW
logic level at its BAR Q output to the integrator 92. The integrator 92 then ramps down the control voltage on the line 96 to adjust the bias on the control transistor 44 and cause the pedestal currene iin the laser diode to 10 increase. ~ the pedestal voltage 124 is above the reference voltage 126 as held by the capacitor 128, the integrator 92 ramps up the pedestal current of the laser diode 18.
The logical value put out by the comparator 64 is latched into the 15 flip-flop 78 at the beginning of the data burst at time t2. A flip-flop 132 is clocked by the leading edge of the data burst, and it is reset by the falling edge of a TxEN control signal (Fig. 6B) which is an inversion of the incoming BAR TxEN control signal at the input 26. The flip-flop 132 puts out a strobe pulse over a control line 134 leading to the flip-flop 78.
2 o The capacitor l 28 forms an ~C network having a time constan~ in microseconds, rather than nanoseconds, and so is effective to maintain ~e voltage at the inverting input of dle comparator at approximately the same value during ~e tl to t2 400 nanosecond interval when data arrives and the comparator logical output level is strobed into the ~ip-flop 78.
In practice the integrator 92 ramps the pedestal current up or down in the frame succeeding the frame when the time slot is strobed so that this feedback information is utilized in a time slot following the relatively short strobed time slot.
The embodirnents of Figs. 3A-3B and 5A-SB operate to adjust a data signal voltage, e.g. either a peak voltage or a pedestal voltage, in a time slot in a time frame subsequent to the actual ~rne slot whe~ein comparison to a reference voltage is made. This has the advantage of not . .
WO 91/15886 PCI`/US91/02304 -20- 2~93~9 requiring ultrahigh speed electronics which is re~uired if a comparison and integration function is desired in the same time slot that the comparison occurs. According to both the embodiments of Figs. 3A-3B
and SA-SB, the comparison is made for each data paclcet and hence for 5 each frame in which data is sent. ~ the Fig. 5A-SB embodiment, this has a disadvantage in that it consumes a predeterrnined amount of overhead since the pedestal is measured during the data transm;ssion packet tirne during a period, in the embodiment specified 400 nsec, in which actual data cannot be sent. Since the circuit is intended to simply adjust dle o pedestal current so as to dither a~out a reference pedestal current, and since temperature chan,,es and laser diode aging occur relatively slow, it is apparent that an output from the integrator 92 does not have to be utilized for each and every data packet, which in the case of telephone voice signals occurs 8000 times a second. Accordingly, as illustrated in S Figs. 7A-7B and 8A-8B, the integrator 92 could be replaced with a digital counter/integrator 192 which could hold the output from the comparator 64 and latch 78 for a predetermined period of time, for example one superframe which corresponds to 24 frames, so as to decrease the arnount of overhead associated with the circuit of the invention. Accord~ngly, it 2 o will be ~ppre~ia~ed that one need only ~etermine the maximum expec~ed temperature change over time and the amount of voltage increment to be generated by the digital counter~mtegrator 192 so as to determine an optimum or minimum repetition frequency ~or sampling an OlltpUt of the laser diode 18 so as to generate the requisite feedback control so that the 2s laser diode 18 is functional as intended over the desired ambient operating temperature range.
With reference to Fig. 8C, node A represents a voltage which can vary over a limited range such as 1-3 volts, for example. Node B at ~e 30 positive input of the comparator 64 represents an instantaneous level which follows the level at node A without any inertia. Node C at the negative input of the comparator 64 represents a reference level which floats very closely to the level appearing at node A, but is subject to a tirne constant established by the capacitor 128 and the lK resistor and the 220 WO 91/15886 PCl/US91/02304 -21- 2~93~3 ohrn resistor. As shown in Fig. 8D, the voltage at node B represents a real tirne delta or change value occurring at node A. The condition graphed in Fig. 8D is one in which the output of the comparator 64 will become positive, and will result in a negative or decrement logical condition being 5 put out by the latch 78 to the counter 19~.
If node A, and node B go a~ove the level at nocle C by some amount, denoted as delta V in Fig. 8D, during the illumination interval when the Iaser diode 18 is operating, this condi~ion means ~at too much bias 10 current is being supplied to the laser diode ~8, and the counter 192 will be decremented as a result of this condition. However, if the delta V voltage does not go above the level A, there is insufflcient bias being supplied to the laser diode 18, and the counter 192 is incremented for this burst interval.
Node A represents a very low impedance and operates at a quiescent point of about 3.5 volts. When light is detected in the reverse facet diode 20, current flows through the 3.9K resistor and is amplified by the transistor Darlington pair, causing the voltage at node A to come 20 do~,vn slight]y. In the circuit ex~nple given in Fig. 8B, ~e resistor 13Q
provides a slight positive bias to the positive input of the compa~ator 64 (node B). In the circuit exarnple given in Fig. 8C, the resistor 130' provides a slight negative bias to the negative input of the comparator 64 (node C). Thus, the resistors 130, 130' operate to preset the logical state 25 of the comparator 64 and establish the delta V step height occurring during the burst interval. The negative bias provided by`the resistor 130 (Fig. 8C) provides a simpler, more convenient arrangement with sligh~y improved dynamic range than the circuit shown in Fig. 8B. Both circuits work well.
To those skilled in the art to which the present invention pertains many widely differing embodiments will be suggested by the foregoing without departing from the spirit and scope of the present invention. The descriptions and disclosures herein are intended solely for purposes of WO 91/i5886 - P~/US91/02304 illustration and should not be construed as l~ni~ing the scope of the present invention which is more particul~rly pointed out by the following claims.
OUTSIDE PLANT COMMUNICATIONS TERMIN~4L
The present invention relates to control circuitry for automatically s regulating optical output power of a laser diode over a thermal gradient.
Communications systems employing optical fiber cables are proliferating, due to the many advantages associat~ d with the optical filber medium. While optical fiber long distance trunks between central of fice 10 switching points are well established, optical fi~er paths have not yet been extended on a widespread basis to service subscriber locations. Central office locations provide a controlled environment for the optical transmission and reception apparatus associated with the cable. For instance, power supply levels are sufflcient at the central office to provide 15 needed heating and/or cooling to maintain temperature control of light emitting elements used in the optical communications path. While laser diodes are known to be useful for light beam comrnunications over optical fibers, such laser diodes are not well suited for use at subscriber locations unless they are located in a house or building having a controlled 20 temperature.
It is known that optical output power of a laser diode varies with temperature. The prior art has addressed this characteristlc in several ways. One approach has been to control the environment in which the 2 5 laser diode is operative. Heating and cooling devices have been employed to achieve a regulated temperature environment for the laser diode. One practical cooling mechanism for cooling a laser diode has been to employ junction devices implementing the Peltier effect at a junction of dissimilar materials~ Joule heating has also been employed to provide heating to the 30 laser diode.
One drawback of Peltier effect junctions and heating devices is that they are not efficient and typically require considerable operating power to achieve relatively modest heating and cooling effects. While laser 3 5 diodes which are located at central offlce or head end interface units of an WO 91/15886 PCr/lJS91/02304 -2- ~93~39 optical fiber cornmunicalions network may be maintained within very close thermal tolerances, laser diodes of subscriber interface units remotely located from the office interface unit are typically subjected to much harsher thermal gradients, especially if located outdoors. Outdoor 5 subscriber interface units are typically small weather-resistant enclosures which are located within about 200 feet of a subscriber's premises. Such units are typically exposed to ~e ambient environment. In some climates, the ambient environment may present a thermal gradient from -40 degrees Centigrade to +70 degrees Centigrade. Also, the power at each 10 subscriber interface unit is very limited, and power is not available to provide Joule heating or Peltier cell cooling for the laser diode transmitter.
Optical fiber communications networks have typically been 5 configured in a variety of architectures, including point-to-point, star, ring and bus. One advantage of a logical bus architecture is that it works particularly well within the conventional outside plant environment between the central offlce and subscriber premises.
With the lo"ical bus architecture, time division multiple~
techniques have been adopted to provide each subscriber interface unit with necessary access to the office interface unit at the central office or head end of the bus. Time division mul~iplex allots time slots to each of the subscriber inter~ace units, and only one subscriber interface unit will 2 s send or receive data during its tirne slot in any given time frame. When laser diodes are operated only during a narrow time slot of an overall duty cycle, conventional power control techniques will not work since the laser diode is dark most of the time. Also, with subscriber interface units distributed along a logical bus, differing optical path losses require that a mechanism be provided to enable dynamic adjustment of the optical power level of each laser diode of the subscriber interf~ce unit, so that those units most distant from the office interface unit put out the greatest optical power.
WO 91/15886 PCriUS91/02304 3_ 2093~39 Thus, a hitherto unsolved need has arisen for a power control circui~ for regulating optical power output of a laser diode operating in a time division multiplex mode and over a wide range the~nal gradient.
A general object of the present invention is to provide a power control circuit and power regulation method for a laser diode operating in a time division multipIex burst mode across a thermaI gradient in a manner which overcomes limitations and drawbacks of ~e pnor art.
A more specific object of dle present invention is to generate a feedbaclc control signal based upon detection of a component of actual peak optical E~ower output.
Another more specific object of the present invention is to generate a feedback control signal based upon detection of an optical power threshold or turn-on knee characteristic as detected dunng a pedestal interval occurring during a beginning of a data packet time slot.
A fur~er more specific object of the present invention is to provide 20 a power control circuit which establishes peak power in response to externally controlled bias level cornmands, and which generates a power regulation control signal based upon optical feedback from the laser diode and the particular bias level cornmand.
One more specific object of the present invention is to provide circuitry and methods for regulating optical power of a laser diode over a remotely controllable dynamic range with circuitry which is available, inexpensive and reliable in use over a severe thermal gradient, such as from ~0 degrees C to + 70 degrees C.
Yet another specific object of the present invention is to provide circuitry and methods for regulating optical power of a laser diode used within outside plant communications terminal equipment, particuiarly equipment using a laser powered bus having a maxirnum voltage less than WO 91/lS886 PCl'/US91/02304 4_ 2093~39 20V, specifically less ~han 15V, optirnally less than 10V, particularly less than 8V, more specifically less than 6V, especially one which supplies 5 volts or less voltage.
One more specific object of the present invent;on is to provide an inexpensive circuit for regulating optical power of a laser diode used within outside plant communications terminal equipment and which also provides a con~rol strobe signal which indicates to the terminal equipment and in turn to head end equipment the relative humidity at the terminal 10 equipment.
In accordance with a facet of the present invention, a control circuit is provided for controlling the output power level of a laser diode operating periodically in a burst mode interval within a time division 15 multiplex optical communications network. In this particular arrangement, preferably the laser diode includes a reverse facet photodetector or other circuitry for monitoling a component of the optical output power of the laser diode during each burst mode ~nterval.
Ths con~r~l cirçuit includes a transimpedance amplifier for converting a current signal from the photodetector into an optical le-rel voltage representative of sensed optical power during dle burst mode interval; a comparator for comparing the optical level voltage with an established reference voltage and for providing a signal representing a 25 logical condition from said comparison; a clocked storage device for storing the signal representing the logical condition upon receipt of a strobe signal; an integrator for integrating the stored logica} condition over a time period to provide a contro} signal; a current control circuit in series with the laser diode and responsive to the control signal to regulate 30 current flow through the laser diode; and, a s~obe generator for generating the strobe signal from information related in time to ~e burst mode interval.
WO 91/15886 PCI'/~JS91/02304 -5- 2~93~39 In one aspect of this facet of the invention, an optical power control circuit is provided for responding to externally supplied logical signals by controlling bias current through the laser diode during each said burst mode interval.
In another aspect of this facet of the invention, an altemating current (AC) coupling device is provided between the ~nsimpedance amplifier and an inpu~ of the eomparator, and a voltage clamp is connected to said input of the comparator for cl~nping the voltage at said 10 input to approximately zero volts in the absence of an output of the optical level voltage from ~e transimpedance amplifier and wherein the reference voltage is adjusted to maintain optical power of the laser diode in relation to peak optical power level thereof.
In one more aspect of this facet of the invention, the reference voltage is established in relation to the setting of the optical power control c}rcuit.
In yet another aspect of this facet of the invention, the control circui~ receives and responds to a transmit enable con~ol signal mar~ing in time the boundaries of the burst mode interval and ~e control circuit fur~er receives and modulates a bias current through the laser diode wi~h digital data transitions representing cornmunications information.
In still one more aspect of this facet of the invention, ~e strobe generation circuit is responsive to a transition of the transmit control signal marking the end bouuldary of the burst mode interval.
In yet one more aspect of this facet of the invention, the digital data transitions are presented to the laser diode after a predetelmined pedestal interval, and the strobe generation circuit is responsive to the beginning of the digital data transition within the interval.
WO 91/15886 PCr/US91/02304 -6- 2~3~39 Ln another aspect of this facet of ~e invention, ~e transimpedance amplifier is directly coupled to an input of the comparator, and a resistor-capacitor network is connected eo a voltage reference input of the comparator and to the direct coupled input of ~e comparator, the time 5 constant of the resis~or-capacitor network being longer than the pedestal interval thereby to supply as a dynamic reference voltage to the comp~rator the voltage present at the directly coupled input before the occurrence of the burst mode interval. This aspect preferably further includes a biasing circuit for presetting the state of ~le comparator to a 10 known logical condition before the burst interval. ~1 one implementation a bias resistor may apply positive preset bias to the plus input of the comparator. In another implementation, a bias resistor may apply negative preset bias to the minus input of the comparator.
In one more aspect of this facet of the invention, an optical power biasing circuit is provided for responding to externally supplied logical signals by controlling bias current through the laser diode during each burst mode interval.
2 0 In another facet of the present invention, a methQd is provided ~r controlling optical power output level of a laser diode modulated during a burst mode interval by digital data transitions within a shared bus optical communications network and over a thelmal gradient. The method of this facet comprises the steps of:
optically monitoring a component of the optical output power of the laser diode during each burst mode interval and converting the component into a control signal, establishing a reference signal and comparing the control signal, with the established reference signal and for providing a signal representing a logical condition ~rom said comparison, WO 91/15886 PCl'~US91/02304 storing the signal representing the logical condition upon receipt of a strobe signal, integrating the stored signal representing the logical condition over - 5 a time period to provide an integrated contro;L signal, regulating current flow ~rough the laser diode in accordance with the integrated control signal, and generating the strobe signal from infolmatiorl related in time to the burst mode interval.
In one aspect of this facet of the invention, a further step is provided for responding ~o extemally supplied logical condition signals by controlling current flow through the laser diode during each said burst mode interval.
In another aspect of this facet of the invention, the step of converting the component into a control signal comprises the steps of ?.0 converting tbe component in~o a current with a photocliode and translatingthe current into a control voltage with transimpedance amplifier means, and wherein the step of comparing the control signal with a reference signal comprises comparing the control voltage with a reference voltage.
In a further aspect of ~is facet of the invention, a further step is provided for coupling ~e control voltage to a comparator ~or carrying out the comparing step with an alternating current coupling and including the further step of clamping the altemating current coupled control voltage to approximately zero volts in the absence of an ou~put of said optical component and including the fur~er step of adjusting said reference voltage to maintain optical power of the laser diode in relation to peak optical power leveI thereof.
WO 91/t5886 PCI/US91/0231)4 -8- 20~343~
In one more aspect of this facet of the invention, the step of establishing the reference signal is carned out in relation to a further step of controlling current flow through the laser diode dunng each burst mode interYal in response to externally supplied logical signals.
In yet another aspect of this facet of the invention, the burst mode interval is established by an externally supplied transmit enable control signal and the digital data transitions are t~anslated to optical output power during the inteIval mar~ed by ~e transmit enable con~ol signal.
In still another aspect of this facet of the invention, the step of generating the strobe is carried out in response to a transition of the transmit enable control signal marlcing the end boundary of the burst mode interval.
In one more aspect of this facet of the invention, the digital data transitions are presented to the laser diode after a predetermined pedestal interval within the burst mode interval, and the step of generating the strobe occurs after the pedestal interval has passed and the beginning of 20 ~he digital data transition has occurred within the interval.
In still another aspect of this facet of the invention, fur~er steps are provided ~or directly coupling the control signal to an input of a 2 5 comparator for car~ing out the comparing step and providing a signal storage device at another input of the comparator coupled to the one input and having a predetermined time constant, and wherein the time constant of the signal storage device is made lor~lger than the pedestal inten~al so that the step of establishing the reference signal is carried out by 3 o supplying to the another input the signal stored in the signal storage device.
WO 91/15886 PCl`/~S91/02304 9 20~3~39 In one more aspect of this facet of the invention, a further step is provided for controlling the operating power through said laser diode in response to extemally supplied logical signals.
In one more aspect of this facet of the invention, the method includes a further step of generating a signal indicative of relative humidity at the vicinity of the laser diode. In this as]pect, a preferred implementation generates the signal indicative of reLative humidity by by pulsewidth-modula~ion of the strobe signal.
These and other objects, advantages, aspects, facets and features of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of the following preferred embodiments, presented in conjunction with the accompanying drawing.
Fig. 1 is a block diagram of a bus optical fiber communications network in which an office mterface unit (OIU) supports a plurality of subscriber interface units (SIUs) via transmit and receive shared optical filber paths.
Fig. 2 is a representative family of curves graphing optical power output as a function of laser current over a temperature range of 40 C to +70 C.
Figs. 3A and 3B represent a single schematic diagram of one presently preferred form of control circuit for controlling optical output power of a laser diode in accordance with principles of the present invention. Fig. 3A forms the left half, and Fig. 3B the right half, of the schematic diagram.
Fig. 4 is a graph of wave-forms illustrating pertinent operational characteristics of the Fig. 3 circuit.
-lO- 20~3~39 Figs. SA and SB represent a single schematic circuit diagram of another presen~ly pre~erred form of control circui~ for controlling optical output power of a laser diode in accordance with principles of the present invention. Fig. 5A forrns the left half, and Fig. SB the right half, 5 of the schematic diag~m.
Fig. 6 is a graph of wave-forms illustrating pertinent operational characteristics of the Fig. S circuit;
~igs. 7A-7B and 8A-8B are similar respective to Figs. 3A 3B and SA-SB except for the substitution of a digital counter/integrator for the RC integrators utilized in Figs. 3A-3B and SA-SB, the digital counter/integrator allowing feedback control to be implemented less frequented than RC integrators.
Fig. 8C is an alternative embodLment of the comparator circuit illustrating a pull-down resistor rather than a pull-up resistor.
Fig. 8D is a waveform graph illustrating an excessive bias condition 20 so as to illus~ate one mode of operation of t~e Figs. gC and 8D circuits.
An optical fiber communications network 10 includes an off~ce interface unit ("OIU") 12 and a plurality of subscriber interface units ("SIU") 14a, 14b, . . .14n-1, and 14n. Twen~ four SIlJs 14 are presently 25 preferred. The OIU 12 communicates with each SIU 14 in its time slot via an optical fiber bus 16. A transmit fiber 16T enables ~e OIU 12 to transmit to each SIU 14, and a receive fiber 16R enables each SIU 14 to transmit in its turn to the OIU 12. Time division multiple~ing techniques are preferably employed. For exarnple, in one overall operational cycle 30 or frame of 125 microseconds, each SIU 14 is allotted a time slot of about 4 microseconds with the time slots being separated by dead spacings. l~is means that the optical laser diode of a particular SIU 14 is on for 4 microseconds, and is off for the balance of each cycle or frame.
WO 91/15886 PCI/US~1/02304 2 0 ~ 9 The OIU 1~, sometimes referred to as a head-end unit, has a very sensitive reGeiver and a suf~lciently powerful transmitter to be able to receive and send signals, preferably digital, to ~e most distant SIU 14n on the bus 16. The OIU 12 and each SIU 14 include application specific 5 microcontrollers' which communicate with each other over the optical fiber bus 16, so that the OTU 12 can control operations at each SIU 14, and so that the status of-each SIU 14 may be reported bacl; to the O[U 12.
The OIU 12 is typically contained in a controlled environment, 10 such as a central office switching center, or other caLI concen~ation and forwarding location of a telecommunications network~ while each SIU 14 is part of an outside plant installation and is located ideally not more than about 200 feet from each subscriber's premises. Wire pairs or coaxial cable extend from the SIU 14 to the subscriber's premises to provide 15 telecommunications service access to ~e subscriber. A single SIU 14 may accomrnodate a number of subscriber service lines. While the OIU 12 is located in an environment in which the power supply is not an issue, and where temperature of transmit laser diodes may be carefully regulated by conventional means, each SIU located in the outside plant has a very ~o ]imi~ed p~wer supply. Conventional temperature compensation techniques for a Iaser diode transmitter at the SIU 14 are not available.
Fig. 2 presents a family of characteristic curves for a laser diode 18 of the type employed in each SIU 14. The laser diode 18 (Fig. 3) may be a 25 type PU-llSLD-N made by Mitsubishi, or equivalent. The laser diode 1$
has a forward direction optical facet, Md has a reverse facet in proximity with a photodiode 20 which enables indirect sensing of the optical power put out in the forward direction. Light energy at the reverse facet closely approximates the light energy at the forward facet.
According to Fig. 2, the current passing through the laser diode, for a given optical power, varies considerably with temperature. The lef~nost curve represents the current vs. optical power output at a diode temperature of -40 C, while the rightmost curve represents laser current WO 91/158~6 PCr/US9t/OX304 -12- 2093~3~
vs. optical power output at the other temperature extreme, such as +70 C.
At the lowest temperature the laser diode 18 manifests a turn-on threshold or knee at approximately S milliamperes, whereas at the highest temperature, the tum-on curlent is about 30 milliamperes. Since ~e SIU
5 14 (and its laser diode 18) is located in the extemal ambient, in some clisnates the temperature range shown in Fig. 2 may be present as the seasons change.
Turning now to Figs. 3A-3B, a control circuit 22 is proYided for 10 controlling two aspects of the operation of the laser diode 18. The first control aspect is one for adjusting dynamically the power output level, so that the OIU }2 can command that the power level be increased for more distantly located SIUs 14 and reduced for the SIUs located nearby. The second control aspect is one which tracks and compensates for variations in optical output otherwise caused by various variables, particularly temperature changes. The implementation of these two control aspects will now be considered.
Digital data (BAR TxD) enters the circuit 22 on a line 24 and a time 20 slo~ control signal (BAR TxEN) enters the ~ircuit on a line 26. The digital data passes through gates 28, 30 and 32 to a subcircuit 34 which enables the power level of the laser diode 18 to be set dynamically, e.g. the first control aspect. Ultima~ely, the data signal BAR TxD is combined wi~ a bias current from control t~nsistor 44 and appears at a node 36 leading to 25 the cathode of the laser diode 18. The power level set by the subcircuit 34 is set by digital values suppiied over a control bus 38 from an ASIC
controller (not shown) included within the SIU 14. The SIU controller establishes the power level at the SIU in accordance with ins~uctions it receives from its counterpart at the OIU 12.
The time slot control signal BAR TxEN passes through a gate 40 and through one input of the AND gate 30 to block the data signal BAR
TxD except during the ~ne that the time slot control signal is active.
Simultaneously, the time slot control signal passes through a Schottky - WO 91/15886 PCI'/US9t/02304 -13- 2~93~39 junction diode 42 to the control transistor 44 in series with a resistor 46 and the cathode of the laser diode 18. The transistor 44 provides a proportional adjustment of bias current for the laser diode and acts to control the bias current over a wide temperature range in accordance with 5 a further control signal, the generation of which will be e~pIained hereinafter, e.g. the second control aspect. The anode of the laser diode 18 leads to a +5 volt digital electrical power bus 48. A choke 50 also connects to ~e bus 48 and separates the digital side thereof from an analog side 52 dlereof. Filter capacitors are on both the digital and analog sides o of the ~5 volt supply bus. The reverse facet photodetector diode 20 is cormected to a transimpedance amplifier 54 which converts the current developed through the diode 20 into a voltage which is proportional to the instantaneous peak optical power ou~tput of the laser diode 18 which is detected during the time sIot fixed by the time slot control signal BAR
TxEN. The proportional voltage put out by the amplifler 54 leads ~rough a coupling capacitor 56 to a node 62 to which two reverse-connected Schottky diodes 58 and 60 which are biased to clamp ~he node 62 (at roughly zero volts) during the peak negative excursion of a signal passing through the capacitor 56. The node 62 provides one input (Vo) to 2 Q a comparator 64. More speci~lcally, the capasitor 56 and diodes 58, 6n function to clamp onto the peak negative voltage generated by ~e diode 20 throughout the time slot, which peak vol~ge Vo is inputted into the comparator 64 via the node 62. Dunng a da~ period of the frame, the voltage Vo is drained by resistor 17.
A predetermined reference voltage is provided at the other input to the comparator 64 from a potentiometer 66 which permits adjustment of the regulated power output of the laser diode 1 B. The wiper of the potentiometer 66 leads through an operational amplifier 68 which puts 30 out a VREF signal on a line 70 leading to a resistor-capacitor parallel network at the reference voltage input of the comparator 64. An output node 76 of the comparator 64 provides a binary value indica~ing whether the voltage, Vo, on the node 62 is above or below ~e reference voltage VREF on the line 70. The binary value is ~en strobed into a latch 78 in -14- 209~33 accordance with a cloc~cing signal developed fro m ~he rising edge of ~e tirne slot control signal BAR TxEN (Fig. 4). l~is rising edge clocking signal passes through the gate 40 and a gate 80 to ma,inta~n i~s original logical condition as an inverted control signal. The gate ~0 leads via a line 5 82 to a clocking input of a flip-flop 84 configured as a one shot. The duration of the pulse put out by the flip-flop 84 over a clock line 90 is established by the time constant of a series RC nehvork including a capacitor 86 and a resistor 88.
Advantageously, the capacitor 86 is one having a characteristic which varies in a known way with changes in relative humidity. Thus, the width (w) (Fig. 4) of the clocking pulse put out on the line 90 is related to the relative humidity within the SIU 14. If excess moisture intrudes into the interior space of the SIU 14, the width of the clocking pulse on the line 15 90 will change. The pulse width of this signal is monitored by the ASIC
controller of the SIU 14, and if it exceeds a predeterrnined acceptable range, a warning signal is sent by the controller to the OIU 12 so that an alarrn may be generated and service personnel dispatched to the particular SIU. The dotted line 53 in Fig. 4 repre~ents an alternative possible width 20 nf the clocking pulse, the ac~ual width (w) encountered in practic~
depending on the hurnidity as sensed by ~e capacitor 86, as explained.
The clocking signal on the line 90 clocks the binary value into the latch 78. An inverted output of the latch 78 leads to an input of an 2s operational amplifier 92 configured as an integrator by virtue of a feedback capacitor 94. An output line 96 from the integrator 92 leads through a series resistor 98 to the base of the control transistor 44.
Another resistor 100 also connects the base of the control transistor 44 to ground. The signal on the line 96 controls the arnount of current passing 30 through the transistor 44 and in turn the amount of current passing through the laser diode 18.
It should be noted that the voltage appearing across the power adjustrnent potentiorneter 66 is dynamically adjusted to track the power ~ WO 91/15886 PCI/US91/Q2304 -15- 2~93.~9 setting commanded by the OIU over the control bus 38. To this end, a gate 102 and resistor 104 provide an adjustment when one bit line of the bus 38 is enabled. Similarly, a gate 106 and a resistor 108 make a fur~er dynarnic adjustment when another bit line of the bus 38 is enabled. The 5 resistors 104 and 108 are within a voltage divider net~vork leading from the analog +5 voltbus 52 and also including series r~sistors 110 and 112 leading to the potentiometer 66.
Operation of ~e circuit 22 will now be explained in conjunction 10 with Fig. 4. Therein in graph A the time slot control signaI BAR TxEN is shown to be a negative going pulse of approximat~ly four microseconds duration within an overall recurrent operational cycle or ~rame of 125 microseconds, for example. The particular SIU 14 is only able to transmit during its 4 microsecond time slot in the overall cycle. In graph B the BAR TxD data signal, more specifically node 62 and Vo, is shown for two BAR TxEN time slots. In the left tirne slot data burst, the peak negative excursion is shown to be less than a value fixed by the VREF
value on the line 70. When the peak negative exclusion is converted to a voltage and compared with VREF in the comparator 64, the binary output 20 is a logical HIGH. At thé clock time, which coincides with ~e rising edge of the BAR TxEN time slot control signal (at the end of ~is pulse), ~e logical HIGH binary value is strobed into ~e flip-flop 78, and its inverted -output is then LOW for the remainder of dle 125 microsecond overall operational cycle. This logical LOW value causes the integrator 94 to 25 increase the voltage level on the line 96 during dle remainder of the operational cycle, with the rate of increase fixed by the time constant formed by the integration feedback capacitor 94 and a low value seAes resistor 95. The increasing voltage is presented to the control transistor 44, and duAng the next BAR TxEN time slot, more current will flow 30 through the control transistor 44, and more current will consequentIy flow through the laser diode 18.
At the Aght side of Graph B of Fig. 4, the peak amplitude of optical power put out by the laser 18 is greater than the VREF value. In this ~ - WO 91/15886 P(~T/US91/02304 -16- 2~93~9 situation, the opposite condition results a~ ~e output of the comparator 64, and a LOW level is latched into the flip-flop 78 by the strobe pulse on the line 90. The inverted output of d~e flip-flop 78 is now HIGH, causing the integrator 94 to lower the voltage put out on the line 96 leading back 5 to the base of the control transistor 44.
During operation of the circuit 22, the binary value put out by the comparator 64 will dither about the VREF setpoint, which is preset to be at the desired ma~imum peak optical power output level for the particular 10 laser diode 18. As the temperature changes, the bina~y value put out by the comparator will correspond to the direction of temperature change, and either successively raise or lower the base voltage to the transistor so that the peak negative excursion continues to dither about the VREF
setpoint. Since the circuit 22 monitors peak optical power output of the laser diode 18, and dynamically corrects that power output level, it remains substantially constant over a ~ery wide temperature range and compensates for other variables as well, such as laser diode aging.
Graph C of Fig. 4 illustrates the strobe pulse on the line 90 as being 2 o of variable duration, based on the humidity within the SIU as sensed by the capacitor 86. As humidity varies, pulse width varies as designated by the dashed lines in Graph C of Fig. 4.. Advantageously, the flip-flop 78 is edge-triggered, and is therefore insensitive to actual duration of the pulse, whereas the duration may be counted by a counter of the ASIC con~oller 25 of the SIU and used to indicate an alarm if excessive moisture colleets or is present within the housing of ~e SIU 14.
While the circuit 22 of Figs. 3A-3B operates very satisfactorily to detect peak optical power output from the laser diode 18 during the time 3 o slot when light energy is being detected by the photodetector diode 20 and thereby regulate optical power over thermal gradient, the circuit 22 has some slight drawbacks.
WO 91/15886 PCl'/US91/02304 -17- 2093~39 For one thing, the circuit measures and controls ~e peak optical power by controlling the DC bias current in the laser. The precise DC
operating point of the laser is not accurately determined. Therefore, because of the extreme nonlinear nature of the laser charac~eristics as 5 shown in Fig. 2, the range of the programmable optical power is limited to about 6 dB in a practical case. Furthe~ore, the analog voltage bus is limited to +S volts because of power constraints at the remo~ely sihlated SIU 14. 1 he +5 volt bus effectively limits the linear range of ~e integrator 94 to about l.S vol~s which has ~e consequence of limiting the 10 dynamic range of the circuit 22. If a 10 dB adjustment range were desired, such as one volt to 100 millivolts at the lower level the diodes 58 and 60 are inoperative to clarnp the node 62.
The circuit 122 in Figs. SA-5B operates upon the same premise of 15 permitting the laser diode 18 to operate in accordance with its particular characteristics over the thermal gradient, but tracks optical power differently. The Fig. SA-SB circuit monitors the turn-on knee of the laser diode and sets the dynamic range from that point, rather than from maximum peak power as is done with the circuit 22 thereby insuring that 20 the laser o~erates in the linear region. In the circuit l 22 like re~erence numerals are used for elements that correspond generally wi~ like elements in the circuit 22, while different numerals are given to those elements of the Fig. SA-SB circuit 122 which differ from the Fig. 3A-3B
circuit 22.
The Fig. SA-SB circuit 122 detects the location of the turn-on threshold or knee of the optical laser diode 18 over the operating temperature range. As noted, this approach has some advantage over ~he circuit 22 by providing a greater dynamic range for commanding optical 30 power output levels. Whereas about 6 dB of power tuning is available with the circuit 22 using a ~SV bus, the circuit 122 provides a power tuning control bus 38 having a greater power tuning range above the tum-on knee of the characteristic curve at a particular ambient operating temperature.
' WO 91/15886 PCltlJS~1/023Q4 -18- 2~93~39 In the circuit 122, the BAR TxEN signal is generated slightly ahead of the beginning of data. For example, Fig. 6 shows the BAR TxEN burst enable signal having a falling edge at tl, and the beginning of the data burst 5 BAR TxD occurring at a later time t2. According to a pre~elTed em~odiment, t~ne t2 occurs about 400 nanoseconds after time tl. When the BAR TxEN signal goes LOW, the dio~de 42 becomes reverse biased, and the laser diode 18 begins to lase at its turn-on knee of its characterIstic culve. Since data is not yet present, the photodiode 20 puts out what 10 amounts to a pedestal current above the diode dark current level.
The transimpedance ampli~ler 54 changes the dark current to a voltage 123 and the pedestal current to a lower pedestal voltage 124, as graphed in Fig. 6E. The pedestal voltage 124 is supplied to the non-inverting input of the comparator, while a predetermined reference voltage 126 held by a storage capacitor 128 is supplied to the inverting input of the comparator 64.
A resistor 130 ~rom the ~S volt analog bus 52 and the bias current 20 flowing through the tr~nsimpedance ampli~er 54 prÇsent nomir a!
voltage to the non-inverting input of the comparator 64 such as about 3 volts in the absence of a change in voltage from the transimpedance amplifier 54 due to the pedestal 124. Since the inverting input is also connected to this input bias point, the same dark current voltage is present 25 to the inverting input after the capacitor 128 charges. The dark current voltage present at the inverting input, e.g. node 126, corresponds to a predetermined reference voltage which establishes the desired point for the tum-on knee for the laser diode.
When the BAR TxEN signal goes LOW, the dark current voltage 123 falls rapidly (e.g. wi~in about 400 nsec) to the pedestal voltage 124 as supplied to the non-inverting input of the comparator whereas the dark current voltage 126 supplied to the inverting input is held by the capacitor 128 and thereby becomes a dynamic reference voltage. Accordingly, if WO 91/15886 PCI/US91/023~4 -19- 2~9~39 the comparator is strobed about 400 nsec after the falling edge of the BAR TxEN signal, a comparison of the voltages at nodes 124 and 126 results in the comparator 64 and flip flop 78. If the strobed pedestal voltage 124 is ~elow the voltage present at the inveIting input of node 126 5 as held by the capacitor 128, the output of the comparator 64 is LOW
(indicating too much light), and this causes ~e latch 78 to put out a LOW
logic level at its BAR Q output to the integrator 92. The integrator 92 then ramps down the control voltage on the line 96 to adjust the bias on the control transistor 44 and cause the pedestal currene iin the laser diode to 10 increase. ~ the pedestal voltage 124 is above the reference voltage 126 as held by the capacitor 128, the integrator 92 ramps up the pedestal current of the laser diode 18.
The logical value put out by the comparator 64 is latched into the 15 flip-flop 78 at the beginning of the data burst at time t2. A flip-flop 132 is clocked by the leading edge of the data burst, and it is reset by the falling edge of a TxEN control signal (Fig. 6B) which is an inversion of the incoming BAR TxEN control signal at the input 26. The flip-flop 132 puts out a strobe pulse over a control line 134 leading to the flip-flop 78.
2 o The capacitor l 28 forms an ~C network having a time constan~ in microseconds, rather than nanoseconds, and so is effective to maintain ~e voltage at the inverting input of dle comparator at approximately the same value during ~e tl to t2 400 nanosecond interval when data arrives and the comparator logical output level is strobed into the ~ip-flop 78.
In practice the integrator 92 ramps the pedestal current up or down in the frame succeeding the frame when the time slot is strobed so that this feedback information is utilized in a time slot following the relatively short strobed time slot.
The embodirnents of Figs. 3A-3B and 5A-SB operate to adjust a data signal voltage, e.g. either a peak voltage or a pedestal voltage, in a time slot in a time frame subsequent to the actual ~rne slot whe~ein comparison to a reference voltage is made. This has the advantage of not . .
WO 91/15886 PCI`/US91/02304 -20- 2~93~9 requiring ultrahigh speed electronics which is re~uired if a comparison and integration function is desired in the same time slot that the comparison occurs. According to both the embodiments of Figs. 3A-3B
and SA-SB, the comparison is made for each data paclcet and hence for 5 each frame in which data is sent. ~ the Fig. 5A-SB embodiment, this has a disadvantage in that it consumes a predeterrnined amount of overhead since the pedestal is measured during the data transm;ssion packet tirne during a period, in the embodiment specified 400 nsec, in which actual data cannot be sent. Since the circuit is intended to simply adjust dle o pedestal current so as to dither a~out a reference pedestal current, and since temperature chan,,es and laser diode aging occur relatively slow, it is apparent that an output from the integrator 92 does not have to be utilized for each and every data packet, which in the case of telephone voice signals occurs 8000 times a second. Accordingly, as illustrated in S Figs. 7A-7B and 8A-8B, the integrator 92 could be replaced with a digital counter/integrator 192 which could hold the output from the comparator 64 and latch 78 for a predetermined period of time, for example one superframe which corresponds to 24 frames, so as to decrease the arnount of overhead associated with the circuit of the invention. Accord~ngly, it 2 o will be ~ppre~ia~ed that one need only ~etermine the maximum expec~ed temperature change over time and the amount of voltage increment to be generated by the digital counter~mtegrator 192 so as to determine an optimum or minimum repetition frequency ~or sampling an OlltpUt of the laser diode 18 so as to generate the requisite feedback control so that the 2s laser diode 18 is functional as intended over the desired ambient operating temperature range.
With reference to Fig. 8C, node A represents a voltage which can vary over a limited range such as 1-3 volts, for example. Node B at ~e 30 positive input of the comparator 64 represents an instantaneous level which follows the level at node A without any inertia. Node C at the negative input of the comparator 64 represents a reference level which floats very closely to the level appearing at node A, but is subject to a tirne constant established by the capacitor 128 and the lK resistor and the 220 WO 91/15886 PCl/US91/02304 -21- 2~93~3 ohrn resistor. As shown in Fig. 8D, the voltage at node B represents a real tirne delta or change value occurring at node A. The condition graphed in Fig. 8D is one in which the output of the comparator 64 will become positive, and will result in a negative or decrement logical condition being 5 put out by the latch 78 to the counter 19~.
If node A, and node B go a~ove the level at nocle C by some amount, denoted as delta V in Fig. 8D, during the illumination interval when the Iaser diode 18 is operating, this condi~ion means ~at too much bias 10 current is being supplied to the laser diode ~8, and the counter 192 will be decremented as a result of this condition. However, if the delta V voltage does not go above the level A, there is insufflcient bias being supplied to the laser diode 18, and the counter 192 is incremented for this burst interval.
Node A represents a very low impedance and operates at a quiescent point of about 3.5 volts. When light is detected in the reverse facet diode 20, current flows through the 3.9K resistor and is amplified by the transistor Darlington pair, causing the voltage at node A to come 20 do~,vn slight]y. In the circuit ex~nple given in Fig. 8B, ~e resistor 13Q
provides a slight positive bias to the positive input of the compa~ator 64 (node B). In the circuit exarnple given in Fig. 8C, the resistor 130' provides a slight negative bias to the negative input of the comparator 64 (node C). Thus, the resistors 130, 130' operate to preset the logical state 25 of the comparator 64 and establish the delta V step height occurring during the burst interval. The negative bias provided by`the resistor 130 (Fig. 8C) provides a simpler, more convenient arrangement with sligh~y improved dynamic range than the circuit shown in Fig. 8B. Both circuits work well.
To those skilled in the art to which the present invention pertains many widely differing embodiments will be suggested by the foregoing without departing from the spirit and scope of the present invention. The descriptions and disclosures herein are intended solely for purposes of WO 91/i5886 - P~/US91/02304 illustration and should not be construed as l~ni~ing the scope of the present invention which is more particul~rly pointed out by the following claims.
Claims (35)
1. A circuit for controlling an output power level of a laser diode operating over a thermal gradient, said laser diode emitting optical energy at a remotely commanded optical power level periodically in a burst mode interval of a recurrent frame within a time division multiplex optical communications network, comprising:
monitoring means for monitoring a peak output optical power of the laser diode during a said burst mode interval thereof, transimpedance amplifier means for converting a current signal from the monitoring means into a peak optical level voltage representative of sensed peak optical power during the burst mode interval, comparator means for comparing the peak optical level voltage with a reference voltage derived in response to remotely commanded optical output level and for providing a signal representative of a logical condition from said comparison, adjusting means for adjusting the peak optical power based on the signal and the remotely commanded optical output level.
monitoring means for monitoring a peak output optical power of the laser diode during a said burst mode interval thereof, transimpedance amplifier means for converting a current signal from the monitoring means into a peak optical level voltage representative of sensed peak optical power during the burst mode interval, comparator means for comparing the peak optical level voltage with a reference voltage derived in response to remotely commanded optical output level and for providing a signal representative of a logical condition from said comparison, adjusting means for adjusting the peak optical power based on the signal and the remotely commanded optical output level.
2. The circuit of claim 1, the adjusting means comprising:
strobe generation means for generating a strobe signal from information related in time to the burst mode interval;
clocked storage means for storing the signal representative of the logical condition upon receipt of the strobe signal so as to provide a control signal, current control means in series with the laser diode and responsive to the control signal to regulate current flow through the laser diode.
strobe generation means for generating a strobe signal from information related in time to the burst mode interval;
clocked storage means for storing the signal representative of the logical condition upon receipt of the strobe signal so as to provide a control signal, current control means in series with the laser diode and responsive to the control signal to regulate current flow through the laser diode.
3. The circuit set forth in claim 2 wherein the strobe generation means generates the strobes signal at an end of a data burst occurring during a said burst mode interval, the current control means adjusting the current flow through the laser diode in response to the control signal in a subsequent burst mode interval.
4. The circuit set forth in claim 3 wherein the clocked storage means includes an integrator means for integrating the stored logical condition over a time period to provide the signal control.
5. The circuit set forth in claim 4 wherein the integrator means includes either a digital counter or an RC circuit.
6. The circuit set forth in claim 4 wherein the current control means increases the current flow through the laser diode when the peak optical level voltage is less than the reference voltage and decreases the current flow through the laser diode when the peak voltage is greater than the reference voltage.
7. The circuit set forth in claim 2 further comprising a power bus for powering the monitoring means, the transimpedance amplifier means, the comparator means, and the clock storage means, the power bus having a voltage less than 10 volts.
8. The circuit set forth in claim 5 wherein the adjusting means includes a digital counter whereby the logical condition used for adjusting the peak optical power is generated less frequently than once a frame.
9. The circuit set forth in claim 1 wherein the adjusting means includes power tuning optical power control means for responding to logical signals relating to the remotely commanded optical power level by controlling bias current through said laser diode during each said burst mode interval to adjust its peak optical power to the commanded level.
10. The circuit set forth in claim 1 further comprising alternating current coupling means between the transimpedance amplifier means and an input of the comparator means, and voltage clamp means connected to said input of the comparator means for clamping the peak voltage at said input to a value between 0.1 volts and 4.0 volts.
11. The circuit set forth in claim 2 wherein the circuit receives and responds to a transmit enable control signal marking in time the boundaries of the burst mode interval, an edge of the transmit enable control signal marking an end of the burst mode interval being used for generating the strobe signal, the circuit receiving and modulating a bias current through the laser diode with digital data transitions representing communications information.
12. The circuit set forth in claim 2 wherein the strobe generation means includes means for characterizing the strobe with information relating to relative humidity at the circuit and further comprising alarm means responsive to the strobe for generating an alarm when the relative humidity exceeds a predetermined level.
13. A circuit for controlling the output power level of a digital data modulated laser diode operating periodically in a burst mode interval of a recurrent frame within a time division multiplex optical communications network, comprising:
enabling means for generating a transmit enable signal denoting a beginning boundary of the burst mode interval, monitoring means for monitoring an output optical power of a LOW pedestal signal of the laser diode during a beginning portion of the burst mode when digital data modulation is not being sent by the laser diode;
transimpedance amplifier means for converting a current signal from the monitoring means into an optical level voltage representative of sensed optical power during the beginning portion of the burst mode interval, comparator means for comparing a maximum value of the optical level voltage with a dynamic reference voltage and for providing a signal representative of a logical condition from said comparison, adjusting means for adjusting the pedestal signal based on a value of the signal.
enabling means for generating a transmit enable signal denoting a beginning boundary of the burst mode interval, monitoring means for monitoring an output optical power of a LOW pedestal signal of the laser diode during a beginning portion of the burst mode when digital data modulation is not being sent by the laser diode;
transimpedance amplifier means for converting a current signal from the monitoring means into an optical level voltage representative of sensed optical power during the beginning portion of the burst mode interval, comparator means for comparing a maximum value of the optical level voltage with a dynamic reference voltage and for providing a signal representative of a logical condition from said comparison, adjusting means for adjusting the pedestal signal based on a value of the signal.
14. The circuit of claim 13, the adjusting means comprising:
strobe generation means for generating a strobe signal from information related in time to the burst mode interval;
clocked storage means for storing the signal representative of the logical condition upon receipt of the strobe signal so as to provide a control signal, current control means in series with the laser diode and responsive to the control signal to regulate current flow through the laser diode.
strobe generation means for generating a strobe signal from information related in time to the burst mode interval;
clocked storage means for storing the signal representative of the logical condition upon receipt of the strobe signal so as to provide a control signal, current control means in series with the laser diode and responsive to the control signal to regulate current flow through the laser diode.
15. The circuit set forth in claim 14 wherein the strobe generation means generates the strobe signal in a transmit enable time interval prior to transmitting digital data, the current control means adjusting the current flow through the laser in response to the control signal in a subsequent transmit enable time interval.
16. The circuit set forth in claim 15 wherein the clock storage means includes an integrator means for integrating the stored logical condition over a time period to provide the control signal.
17. The circuit set forth in claim 16 wherein the integrator means includes at least one of a digital counter and an RC circuit.
18. The circuit set forth in claim 17 wherein the adjusting means includes a digital counter whereby the signal representative of the logical condition used for adjusting the LOW pedestal signal is generated less frequently than once a frame.
19. The circuit set forth in claim 16 wherein the current control means increases the current flow through the laser diode when the pedestal voltage is less than the dynamic reference voltage and decreases the current flow through the laser diode when the dynamic LOW pedestal signal is greater than the reference voltage.
20. The circuit set forth in claim 13 further comprising power tuning optical power control means for responding to externally supplied logical signals by controlling bias current through said laser diode during each said burst mode interval.
21. The circuit set forth in claim 13 wherein the digital data transitions are presented to the laser diode after a predetermined pedestal interval, and the strobe generation means is responsive to the beginning of the digital data transition within the interval.
22. The circuit set forth in claim 21 wherein the transimpedance amplifier means is directly coupled to an input of the comparator means, and further comprising a resistor-capacitor network means connected to a voltage reference input of the comparator means and to the direct coupled input of the comparator means, the time constant of the resistor-capacitor network being longer than the pedestal interval thereby to supply as the dynamic reference voltage to the comparator means the voltage present at the directly coupled input before the occurrence of the digital data.
23. A circuit for controlling the output power level of a digital data modulated laser diode operating periodically in a burst mode interval of a recurrent frame within a time division multiplex optical communications network, the laser diode including a reverse facet photodetector for monitoring the optical output power of the laser diode during each burst mode interval, the circuit comprising:
transimpedance amplifier means for converting a current signal from the photodetector into an optical level voltage representative of sensed optical power during the burst mode interval, comparator means for comparing the optical level voltage with a dynamic reference voltage and for providing a signal representative of a logical condition from said comparison, clocked storage means for storing the signal representative of the logical condition upon receipt of a strobe signal, integrator means for integrating the stored signal representative of the logical condition over a time period to provide a control signal, current control means in series with the laser diode and responsive to the control signal to regulate current flow through the laser diode, and strobe generation means for generating the strobe signal from information related in time to the burst mode interval.
transimpedance amplifier means for converting a current signal from the photodetector into an optical level voltage representative of sensed optical power during the burst mode interval, comparator means for comparing the optical level voltage with a dynamic reference voltage and for providing a signal representative of a logical condition from said comparison, clocked storage means for storing the signal representative of the logical condition upon receipt of a strobe signal, integrator means for integrating the stored signal representative of the logical condition over a time period to provide a control signal, current control means in series with the laser diode and responsive to the control signal to regulate current flow through the laser diode, and strobe generation means for generating the strobe signal from information related in time to the burst mode interval.
24. The circuit set forth in claim 23 wherein the current control means further comprises optical power control means for responding to externally supplied logical signals by controlling bias current through said laser diode during each said burst mode interval and further comprising dynamic reference voltage generating means for generating the dynamic reference voltage in function of the externally supplied logical signals and applying the dynamic reference voltage to the comparator means.
25. The circuit set forth in claim 23 wherein the circuit receives and responds to a transmit enable control signal marking in time the boundaries of the burst mode interval and wherein the circuit receives and modulates a bias current through the laser diode with digital data transitions representing communications information.
26. The circuit set forth in claim 25 wherein the strobe generation means is responsive to a transition of the transmit control signal marking the end boundary of the burst mode interval.
27. The circuit set forth in claim 25 wherein the digital data transitions are presented to the laser diode after a predetermined pedestal interval, and the strobe generation means is responsive to the beginning of the digital data modulation within the interval.
28. The circuit set forth in claim 27 wherein the transimpedance amplifier means is directly coupled to an input of the comparator means, and further comprising a resistor-capacitor network means connected to a voltage reference input of the comparator means and to the direct coupled input of the comparator means, the time constant of the resistor-capacitor network being longer than the pedestal interval thereby to supply as the reference voltage to the comparator means the voltage present at the directly coupled input before the occurrence of the burst mode interval.
29. The circuit set forth in claim 28 wherein the current control means further comprises optical power control means for responding to externally supplied logical signals by controlling bias current through said laser diode during each said burst mode interval.
30. A method for controlling optical power output level of a laser diode modulated during a burst mode interval by digital data transitions within a logical bus optical communications network; and over a thermal gradient, the method comprising the steps of:
optically monitoring a component of the optical output power of the laser diode during each burst mode interval and converting the component into a control signal, generating a dynamic reference signal and comparing the control signal with the dynamic reference signal and providing a signal representative of a logical condition from said comparison, storing the signal representative of the logical condition upon receipt of a strobe signal, regulating current flow through the laser diode in accordance with the integrated control signal.
optically monitoring a component of the optical output power of the laser diode during each burst mode interval and converting the component into a control signal, generating a dynamic reference signal and comparing the control signal with the dynamic reference signal and providing a signal representative of a logical condition from said comparison, storing the signal representative of the logical condition upon receipt of a strobe signal, regulating current flow through the laser diode in accordance with the integrated control signal.
31. The method set forth in claim 30 wherein the step of converting the component into a control signal comprises the steps of converting the component into a current with a photodiode and translating the current into a control voltage with transimpedance amplifier means, and wherein the step of comparing the control signal with a dynamic reference signal comprises comparing the control voltage with a dynamic reference voltage.
32. The method set forth in claim 30, wherein the dynamic reference voltage is dynamically established during operation of the optical communications network in function of at least one of externally supplied optical power level control signals and internally generated reference voltages related to dynamic detection of low pedestal knee characteristics of the laser diode across said thermal gradient.
33. The circuit set forth in claim 22 further comprising bias resistor means for presetting the logical condition of the comparator means.
34. The circuit set forth in claim 33 wherein the bias resistor means applies a positive bias to a positive input of the comparator means.
35. The circuit set forth in claim 33 wherein the bias resistor means applies a negative bias to a negative input of the comparator means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/504,167 US5036189A (en) | 1990-04-03 | 1990-04-03 | Thermal control for laser diode used in outside plant communications terminal |
| US504,167 | 1990-04-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2093439A1 true CA2093439A1 (en) | 1991-10-04 |
Family
ID=24005136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002093439A Abandoned CA2093439A1 (en) | 1990-04-03 | 1991-04-03 | Thermal control for laser diode used in outside plant communications terminal |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US5036189A (en) |
| EP (1) | EP0523188B1 (en) |
| JP (1) | JPH05507176A (en) |
| AT (1) | ATE143182T1 (en) |
| CA (1) | CA2093439A1 (en) |
| DE (1) | DE69122239T2 (en) |
| DK (1) | DK0523188T3 (en) |
| ES (1) | ES2094222T3 (en) |
| WO (1) | WO1991015886A1 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69224534T2 (en) * | 1991-12-20 | 1998-09-17 | Ericsson Raynet A Delaware Gen | DEVICE AND METHOD FOR CONTROLLING THE TEMPERATURE DEPENDENCY OF THE ON / OFF RATIO OF A LASER DIODE |
| WO1993013577A1 (en) * | 1991-12-20 | 1993-07-08 | Raynet Corporation | Apparatus and method for controlling an extinction ratio of a laser diode over temperature |
| US5278404A (en) * | 1992-07-20 | 1994-01-11 | At&T Bell Laboratories | Optical sub-system utilizing an embedded micro-controller |
| US5502298A (en) * | 1992-12-21 | 1996-03-26 | Ericsson Raynet | Apparatus and method for controlling an extinction ratio of a laser diode over temperature |
| IT1268058B1 (en) * | 1994-05-20 | 1997-02-20 | Cselt Centro Studi Lab Telec O | PROCEDURE AND DEVICE FOR CHECKING THE PEAK POWER OF A LASER TRANSMITTER IN DISCONTINUOUS OPTICAL TRANSMISSION SYSTEMS. |
| EP0766080A1 (en) * | 1995-09-29 | 1997-04-02 | FINMECCANICA S.p.A. AZIENDA ANSALDO | System and method for monitoring combustion and pollutants by means of laser diodes |
| US5610709A (en) * | 1996-02-02 | 1997-03-11 | Eastman Kodak Company | Automatic ranging optical power monitoring system |
| US5764667A (en) * | 1996-12-09 | 1998-06-09 | Hewlett-Packard Company | Current steering circuit |
| US6327546B1 (en) * | 1998-12-14 | 2001-12-04 | Adac Laboratories | Method and apparatus for independently calibrating event detectors |
| JP3593646B2 (en) * | 1999-03-19 | 2004-11-24 | 富士通株式会社 | Burst light transmission circuit |
| US7215891B1 (en) | 2003-06-06 | 2007-05-08 | Jds Uniphase Corporation | Integrated driving, receiving, controlling, and monitoring for optical transceivers |
| US7925291B2 (en) * | 2003-08-13 | 2011-04-12 | Qualcomm Incorporated | User specific downlink power control channel Q-bit |
| US7505692B2 (en) * | 2004-08-31 | 2009-03-17 | Cisco Technology, Inc. | System and method for optical transmission |
| US8585213B2 (en) * | 2009-05-28 | 2013-11-19 | Transpacific Image, Llc | Projection-type display and control thereof |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2476945A1 (en) * | 1980-02-22 | 1981-08-28 | Lignes Telegraph Telephon | DEVICE FOR AUTOMATICALLY CONTROLLING OUTPUT POWER OF TRANSMITTER MODULE FOR OPTICAL FIBER TRANSMISSION SYSTEM |
| US4592057A (en) * | 1981-03-23 | 1986-05-27 | International Business Machines Corporation | Versatile digital controller for light emitting semiconductor devices |
| DE3325420A1 (en) * | 1983-07-14 | 1985-01-31 | Telefunken electronic GmbH, 7100 Heilbronn | CIRCUIT ARRANGEMENT FOR CONTROLLING SEMICONDUCTOR LASERS |
| US4689795A (en) * | 1984-04-27 | 1987-08-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor laser controller |
| JPS6190540A (en) * | 1984-10-09 | 1986-05-08 | Olympus Optical Co Ltd | Optical output stabilizer |
| US4698817A (en) * | 1985-02-28 | 1987-10-06 | Northern Telecom Limited | Peak optical power control circuit for laser driver |
| US4709416A (en) * | 1986-02-24 | 1987-11-24 | Rca Corporation | Laser bias current stabilization for burst mode fiber optic communication system |
| US4718118A (en) * | 1986-02-24 | 1988-01-05 | Rca Corporation | Transparent laser drive current update for burst mode fiber optic communication system |
| US4837787A (en) * | 1986-06-04 | 1989-06-06 | Konishiroku Photo Industry Co., Ltd. | Semiconductor laser device with light emission inhibiting means |
| JPS63193582A (en) * | 1987-02-06 | 1988-08-10 | Ando Electric Co Ltd | Laser-diode driving circuit |
| JP2778967B2 (en) * | 1987-05-06 | 1998-07-23 | ブリテツシユ・テレコミユニケイシヨンズ・パブリツク・リミテツド・カンパニー | Control of optical system |
| JPH06103765B2 (en) * | 1987-10-30 | 1994-12-14 | 日本電気株式会社 | Semiconductor laser bias current control method |
| JPH0273682A (en) * | 1988-09-08 | 1990-03-13 | Nippon Digital Equip Kk | Laser diode driving method and device |
-
1990
- 1990-04-03 US US07/504,167 patent/US5036189A/en not_active Expired - Lifetime
-
1991
- 1991-04-03 DE DE69122239T patent/DE69122239T2/en not_active Expired - Lifetime
- 1991-04-03 US US07/927,383 patent/US5319656A/en not_active Expired - Lifetime
- 1991-04-03 DK DK91908752.8T patent/DK0523188T3/en active
- 1991-04-03 JP JP91508317A patent/JPH05507176A/en active Pending
- 1991-04-03 WO PCT/US1991/002304 patent/WO1991015886A1/en active IP Right Grant
- 1991-04-03 EP EP91908752A patent/EP0523188B1/en not_active Expired - Lifetime
- 1991-04-03 AT AT91908752T patent/ATE143182T1/en not_active IP Right Cessation
- 1991-04-03 ES ES91908752T patent/ES2094222T3/en not_active Expired - Lifetime
- 1991-04-03 CA CA002093439A patent/CA2093439A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP0523188A1 (en) | 1993-01-20 |
| WO1991015886A1 (en) | 1991-10-17 |
| DE69122239T2 (en) | 1997-02-06 |
| AU644169B2 (en) | 1993-12-02 |
| ATE143182T1 (en) | 1996-10-15 |
| JPH05507176A (en) | 1993-10-14 |
| DE69122239D1 (en) | 1996-10-24 |
| US5319656A (en) | 1994-06-07 |
| AU7757891A (en) | 1991-10-30 |
| EP0523188B1 (en) | 1996-09-18 |
| US5036189A (en) | 1991-07-30 |
| DK0523188T3 (en) | 1996-10-07 |
| ES2094222T3 (en) | 1997-01-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |