CA2059920A1 - Multiprocessor system and message passing controller thereof - Google Patents
Multiprocessor system and message passing controller thereofInfo
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- CA2059920A1 CA2059920A1 CA002059920A CA2059920A CA2059920A1 CA 2059920 A1 CA2059920 A1 CA 2059920A1 CA 002059920 A CA002059920 A CA 002059920A CA 2059920 A CA2059920 A CA 2059920A CA 2059920 A1 CA2059920 A1 CA 2059920A1
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- Prior art keywords
- processors
- message passing
- message
- bus
- request signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Abstract
MULTIPROCESSOR SYSTEM AND MESSAGE PASSING
CONTROLLER THEREOF
ABSTRACT
Upon requesting message passing, a processor notifies the request to another processor by designating identifiers of candidate destination processors and the upper limit UNR
and the lower limit LNR of the number of destination processors. A counter counts acknowledge signals from the candidate destination processors. A comparator compares the count value with the lower and higher limit values. If the count value is not less than the lower limit value, the sending processor determines that it can perform message passing and selects processors, as many as the upper limit number, from the candidate destination processors according to a rule; then initiates the message passing to the processor thus selected.
CONTROLLER THEREOF
ABSTRACT
Upon requesting message passing, a processor notifies the request to another processor by designating identifiers of candidate destination processors and the upper limit UNR
and the lower limit LNR of the number of destination processors. A counter counts acknowledge signals from the candidate destination processors. A comparator compares the count value with the lower and higher limit values. If the count value is not less than the lower limit value, the sending processor determines that it can perform message passing and selects processors, as many as the upper limit number, from the candidate destination processors according to a rule; then initiates the message passing to the processor thus selected.
Description
JA9-90-525 1 2~S9920 MULTIPROCESSOR SYSTEM AND MESSA OE PASSING
CONTROLLER T~EREOF
This invention relates to multiprocessor systems having a plurality of processors interconnected through a shared bus, and more particularly, to a message passing technique which enables the processors to perform asynchronous communication.
Prior Art Tightly coupled multiprocessor systems having a plurality of processor modules interconnected through a shared bus have been proposed and are being used in practice. In such tightly coupled multiprocessor systems, a plurality of processors proceed their processing by reading from and writing to the shared memory. In order for the system to perform parallel processing, a mechanism for synchronization among processors is indispensable, and the synchronization me~hanism has a significant effect on the efficiency of the entire system.
A multiprocessor system of a shared memory type, in general, maintains synchronization among the processors by using a shared variable in the shared memory. Since events asynchronously generated can not be efficiently communicated among the processors only by means of the shared variable, a mechanism for permitting the processors to asynchronously interrupt one another is re~uired.
A multiprocessor workstation proposed by the present inventors et al. ("High-performance Multiprocessor Work Station TOP-l", Shimizu, Ohba, Moriwaki, Nakada and Obara, Symposium of Parallel Processing JSPP 89, pp. 155-162) is e~uipped with message passing hardware that permits processors to perform event-driven communication and request interruption among them. This workstation has two kinds of message passing schemes which are different from each other in terms of how to operate depending on whether a receiving or destination processor has actually received the message or not. Hereinbelow, they are referred to as "Every~ody JA9-90-525 2 20~9920 Message (Message to all destination)" and "Anybody Message (Message to desired destination)".
In the "Everybody Message" scheme, message passing is successfully performed if all of the processors designated as destinations are ready for receipt of a message. If the reception buffer is not vacant even in one of the destination processors and cannot receive the message, the message passing results in failure, and the transmitting processor can know it. This method is effective for interruption of all processors desired for coherency control of TLB (Translation Look-aside Buffer or the like).
In "Anybody Message" scheme, message passing results in success if at least one of the destination processors is ready for reception of a message. Message passing results in failure only when none of the processors is ready for ~eception. This method is effective for dispatching a given process to an arbitrary processor.
There are, however, other destination operations that have not been realized by these two kinds of message methods. Consider, for example, a system in which eight processors send messages to one another. Neither of the above methods could achieve a destination operation by which one of the processors can send a message to an arbitrary one of the other seven processors to interrupt it (although it have been possible to designate a particular processor as a designation). Also, it has not been possible to instruct that "message passing should result in success only when the message has been sent to four or more of the other seven processors". Therefore~ it has been impossi~le to make for example, two arbitrary processors stop the current processes and assign them new processes with hardware alone.
JA PUPA 1-2511~4 is prior art relevant to the present invention, and discloses a method for sending message to processors of a designated class. IBM~ Technical Disclosure Bulletin, V. 31, No. 6, p 438 discloses a method of sending message together with IDs of processors.
JA9-90-525 3 2~s99~a An object of the present invention is to provide a generalized asynchronous message passing method for a multiprocessor system coupled through a shared bus. In particular, the greatest advantage of the invention lies in flexible, specific control of designation of destination processors. More specifically, the invention makes it possible to designate m arbitrary processors from all, i.e., n processors (1 =< m =< n) and to pass a message to p to q processors among the designated processors (1 =< p =< q =< m =< n). This fully includes functions of "Everybody Message"
and "Anybody Message" referred to in the description on the prior art and enables more powerful the designation of destination.
In a multiprocessor system according to the invention, in order to attain the object, each processor comprises a means for generating a message passing request signal, a means for generating acknowledge signals to messa~e passing request signals from other processors, a means for counting acknowledge signals issued from other processors in response to its own message passing request signal, a means for defining the range of the number of message passing destination processors, and a means responsive to the count value of the acknowledge signals for determining whether message can be sent to a such number of processors as to be included within the range.
In this arrangement, the following types of message passing are possible. Suppose a system includes eight processors, processor 1 to processor 8 coupled through a shared bus. One processor sending a message designates three pieces of information, first on ID or IDs of one or more message passing destination processors, second for the lower limit number of receiving processors, and third for the upper limit number of the receiving processors. The lower limit number of the receiving processors indicates "how many processors, at the minimum, must be ready for receiving a message", and the upper limit number of receiving processor indicates "how many, at the maximum, of the processors are selected as destinations from the processor ready for receiving the message".
JA9-90-525 4 20~992~
Example 1 When the processor 1 is requested to send a message to all the seven processors, the processors 2 to 8 (corresponding to Everybody Message), the destination ID are the processors 2, 3, 4, ..., and 8, the upper and lower limit processor numbers are both 7. Message passing is successful onl~ when all of the seven processors 2 to 8 are ready for reception and a message are sent to these seven processors. When the processor 1 is requested to send message to one or more of the seven processors 2 to 8 (corresponding to Anybody Message), the lower limit processor number is 1 and the upper limit processor number is 7.
Example 2 When the processor 1 is requested to send a message to only one of the five processors, the processor 2 to 6, the destination IDs are the processors 2, 3, ..., and 6 and the lower and upper limit processor numbers are both 1.
Example 3 When the processor 1 is requested to send a message to two or more of the four processors, the processors 5 to 8, the destination IDs are the processors 5, 6, 7, and 8, the lower limit processor number is 2, and the upper limit processor number is 4.
Example 4 When the processor 1 is requested to send a message to three to five processors of the seven processors, the processors 2 to 8, the destination IDs are the processors 2, 3, 4, ..., and 8, the lower limit processor number are 3, and the upper limit processor number is 5.
As shown in the foregoing examples, the invention enables very flexible, specific designation of destination processors.
JA9-90-S25 5 205992a An embodiment of the invention is described below with reference to the drawings, wherein:
Fig. 1 is a block diagram showing the entirety of a multiprocessor system to which an embodiment of the invention is applicable;
Fig. 2 is a block diagram showing the entirety of a single processor involved in the embodiment of the invention;
Fig. 3 is a block diagram showing an integral portion (regarding transmission of a massage) of Fig. 2;
Fig. 4 is a block diagram showing another integral portion (regarding reception of a message) of Fig. 2;
Fig. 5 is a time chart for explanation of the operation of the embodiment of Fig. 2;
Fig. 6 is a diagram showing exchanges of signals for e~planation of the operation of the embodiment of Fig. 2.
Fig. 1 shows the entirety of the embodiment of the invention. A plurality of processors P1, P2 ... Pn are connected to shared memory 2 via a shared bus 1. The shared bus 1 consists of a message exchange bus (Fig. 2~ to which the invention is related, and a memory access bus and so forth. The processors exchange message with each other through the message exchange bus.
Fig. 2 shows an arrangement of message pa~sing hardware, a message bus (address bus and data bus), and an arbitration bus according to the invention. In Fig. 2, a processor P has an MPU (microprocessing unit) 3, a message passing controller 4, and so forth. Although the processor P further has a memory access controller and other elements, such elements do not have direct relevancy to the present in~ention and are not shown in Fig. 2. The shared bus 1 includes message address bus la, message data bus lb, arbitration bus lc. The message passing controller 4 is JA9-90-525 6 ~ 0 5 ~
coupled directly to the MPU 3 and receives instructions.
Practically, MPU 3 gives instructions for message passing to a register referred to later (Figs. 3 and 4) by executing I/O read/write. The message passing controller 4 exchanges messages with the message passing controllers 4 which are implemented in the same way, of the other processors via three buses, i.e., the message address bus la, the message data bus lb, and the arbitration bus lc.
The message address bus la is a control bus for designating a destination of a message and includes as many signal lines as the processor. If the total number of the processors is n, the message address bus includes n lines, ADSl to ADSn, corresponding to the respective processors.
The message data bus lb is for sending a message itself. If m bits of a message are sent at one time, the bus lb includes m signal lines.
The arbitration bus lc is used for the arbitration of bus acquisition when message transmission requests are issued simultaneously from a plurality of message passing controllers 4, and is also used for response indicating whether the processor is ready for reception or not when the processor is a message passing destination. The arbitration bus lc includes as many lines ARB1 to ARBn, as the processors. Various kinds of arbitration methods may be used. For example, the method used in the shared bus in the publication "High-Performance Multiprocessor Work Station TOP-1" referred to the above.
Next refer to Figs. 3 and 4 for detailed description of the message passing controller 4. Fig. 3 shows a part of the message passing controller 4 for transmission of a message whereas Fig. 4 shows a part of the message passing controller 4 for reception of a message.
In Fig. 3, blocks operative upon transmission of a message are a destination control register (DCR) 5, a message data register (MDR) 6, a lower limit receiving processor number register (LNR) 7~ and a upper limit JA9-90-525 7 20~9~2~
receiving processor register (UNR) 8, a parallel counter 9, and a parallel comparator 10.
The DCR 5 is a register that designates destination of a message. Suppose the system includes eight processors;
then the DCR consists of eight bits. Each bit corresponds to a respective processor, and processors whose bits are 1 are selected to be destinations. For example, a message is desired to be sent from the processor 1 to the processors 2, 5, 6, 7, the DCR bits corresponding to the destination processors are set to 1 as follows:
Processor 1 2 3 4 5 6 7 8 DCR bit 0 1 0 0 1 1 1 0 In a more precise e~pression, processors for which the bits of the DCR 5 are set to 1 are only candidates of destinations of the message, and whether the message is actually sent to them depends on the content of the UNR 8 and the LNR 7 explained below. Each bit of the DCR 5 is connected directly to the message address bus la, and the signal lines of the message address bus la are statically assigned to the respective processors beforehand upon initialization of the system, such as signal line ADS 1 to processor 1, signal line ADS 2 to processor 2.
The MDR 6 is used for writing in the content of a message to be sent. When message passing successes, the content of the MDR 6 flow onto the message bus lb and reach one or more destination processors.
The LNR 7 is a register for designating how many processors must be ready for receiving message for successful massage passing. If message passing is requested to success when one or more of destination processors are capable of message reception, the LNR 7 should be set at 1.
If message passing is requested to success when four or more processors are ready for reception, the LNR is set at 4.
This is the register for setting p explained above.
205~2~
The UNR 8 is a register for determining how many processors, in maximum, the message should be sent to, when message passing is possible. By combining it with the LNR 7 referred to the above, specific designation of destination is possible. For example, a message is requested to be sent only one processor, both the LNR 7 and the UNR 8 should be set at 1. This is the register for setting q explained above.
The parallel counter 9 counts how many processors sent back their affirmative acknowledges ACKs. As described before the arbitration bus lc includes n signal lines each corresponding to the respective processor. When a message command is sent, ACK or ACKs return from one or more processors ready for receiving a message among the destination processors. The parallel counter 9 counts these ACKs.
The parallel comparator 10 compares the content of the parallel counter 9 (the count indicating how many processors among the destination processors sent back ACKs) with the content of the LNR 7. When not less ACKs than the value set in the LNR 7 have been sent back, as many processors as the value of the UNR 8 are selected in the order priorities from higher to lower, and the bits corresponding to the processor thus selected are set to 1 in the D~R S.
Fig. 4 shows other blocks of the message passing controller 4, operative upon reception. In Fiq. 4, the bloc~s operative upon reception are a processor ID register (PID) 11, a message reception register (MRR) 12, and an arbitration priority register (APR) 13.
The PID 11 is a register for holding ID of the processor for which the message passing controller 4 serves, and the ID is compared with destination addresses issued on the message address bus la.
The MRR 12 is a buffer for message data.
JA9-90-525 9 2 ~ 5 9 ~ 2 ~
The APR 13 is a register for holding a priority for arbitration. Every time bus arbitration is executed, the priority increases by one, and returns to zero when it overflows. The system is designed so that the processors have different priorities from one another at any time.
Next refer to Figs. 5 and 6 for explanation of how the embodiment operates.
Fig. 5 shows a time chart of message passing, and Fig. 6 shows an example of information exchanges among processors.
A plurality of processors may simultaneously request a bus. Therefore, bus arbitration is first executed at a timing i in a cycle 1. This is a normal arbitration for acquiring the bus. A processor that has won the arbitration can start its massage passing processing. During the following message passing operation, the message passing controllers 4 that has won the bus keeps a busy signal active so that new bus arbitration does not occur.
The processor that won the bus issues message command (timing ii) and message data (timing iii), respectively, on the message address bus and the message data bus in a cycle 2. The message command is for designating on or more destination processors. In Fig. 6(a), the processor 1 sends message command to the processors 2, 3, and 4. Each processor designated as the destination checks its own condition for receiving message in a cycle 3, and, only when it is ready for reception, it sends back ACK to the arbitration bus in a cycle 4 (a timing iv in the cycle 4 is for a message ACK and not for a normal bus arbitration. In Fig. 6(b), processor 3 alone is ready for receiving message, and sends back ACK. In a cycle 5, the message passing controller of the sending processor observes ACK signals to determine which destination processors are ready for receiving the message. When more ACKs than the minimum receiving processor number have been sent back, which means that message passing will result in success, the processor 1 sends command again to as many processors as the maximum receiving processor number ~cycle 5, timing v), and actually sends them the message. In Fig. 6(c), the processor 1 sends a message data to the processor 3. The processor designated as a destination by the command finally receives the message.
As described in the above, the invention performs message passing by designating the range for the number of destination processors, and thus enables flexible, specific message passing. Its effects are discussed below with reference to some examples.
Suppose now that some processors permit the reception of a process and that a certain process is desired to be assigned to one of them. An interruption request is sent to one processor to make the processor switch from the current process to the desired process.
When the conventional message passing method (Anybody Message) is used, a message is sent all processors that permit the reception of a process. A plurality of processors having received message and interrupted must exclusively acquire the process ~y using a semaphore or the like in the shared memory. One processor that has won the semaphore initiates the processing for the assigned process.
The remaining processors restore their conditions before the interruption.
In contrast, when the message passing method according to the invention is used, a message is sent to destination processors which permit the reception of a process. Then, one of the processors is automatically selected, the selected processor alone is interrupted, and processing of the process is initiated. Specifically, the use of the method according to the invention gives two advantages. One is that no interruption request is sent to processors that need not be interrupted. Interruption processing is serious one ~or processors. For example, a typical 32-bit microprocessor, 80386, (produced by Intel, U.
S. A.) takes only several to tens of cycles for addition, subtraction, multiplication, or subtraction, but requires JA9-90-525 11 2~5~2~
200 cycles or more for interruption. The other of the advantages is that it does not require quasi-software exclusive control such as semaphore. Exclusive control using a shared variable causes memory access which in turn causes access to the shared bus, and increases traffic of the shared bus. Unnecessary access to the shared bus adversely affects the performance of the system.
As a next example, suppose that processes A, B, and C
are waiting for processors to become available and that execution of these processes A, B, and C require two processors, four processors, and five processors respectively. In this case, only if a message with the minimum receiving processor number being 2 and the maximum receiving processor number being 5 of receiver processors being 5 is sent by means of the message passing mechanism according to the invention, the process A, B, or C can be selectively initiated depending on the number of the processors that have received the message, i.e., that have been acquired for execution of processes. More specifically, when two or three processors have received the message, then the process A will be initiated, when four processors have, then the process B will be initiated, and when five processors, then the process C will be initiated.
CONTROLLER T~EREOF
This invention relates to multiprocessor systems having a plurality of processors interconnected through a shared bus, and more particularly, to a message passing technique which enables the processors to perform asynchronous communication.
Prior Art Tightly coupled multiprocessor systems having a plurality of processor modules interconnected through a shared bus have been proposed and are being used in practice. In such tightly coupled multiprocessor systems, a plurality of processors proceed their processing by reading from and writing to the shared memory. In order for the system to perform parallel processing, a mechanism for synchronization among processors is indispensable, and the synchronization me~hanism has a significant effect on the efficiency of the entire system.
A multiprocessor system of a shared memory type, in general, maintains synchronization among the processors by using a shared variable in the shared memory. Since events asynchronously generated can not be efficiently communicated among the processors only by means of the shared variable, a mechanism for permitting the processors to asynchronously interrupt one another is re~uired.
A multiprocessor workstation proposed by the present inventors et al. ("High-performance Multiprocessor Work Station TOP-l", Shimizu, Ohba, Moriwaki, Nakada and Obara, Symposium of Parallel Processing JSPP 89, pp. 155-162) is e~uipped with message passing hardware that permits processors to perform event-driven communication and request interruption among them. This workstation has two kinds of message passing schemes which are different from each other in terms of how to operate depending on whether a receiving or destination processor has actually received the message or not. Hereinbelow, they are referred to as "Every~ody JA9-90-525 2 20~9920 Message (Message to all destination)" and "Anybody Message (Message to desired destination)".
In the "Everybody Message" scheme, message passing is successfully performed if all of the processors designated as destinations are ready for receipt of a message. If the reception buffer is not vacant even in one of the destination processors and cannot receive the message, the message passing results in failure, and the transmitting processor can know it. This method is effective for interruption of all processors desired for coherency control of TLB (Translation Look-aside Buffer or the like).
In "Anybody Message" scheme, message passing results in success if at least one of the destination processors is ready for reception of a message. Message passing results in failure only when none of the processors is ready for ~eception. This method is effective for dispatching a given process to an arbitrary processor.
There are, however, other destination operations that have not been realized by these two kinds of message methods. Consider, for example, a system in which eight processors send messages to one another. Neither of the above methods could achieve a destination operation by which one of the processors can send a message to an arbitrary one of the other seven processors to interrupt it (although it have been possible to designate a particular processor as a designation). Also, it has not been possible to instruct that "message passing should result in success only when the message has been sent to four or more of the other seven processors". Therefore~ it has been impossi~le to make for example, two arbitrary processors stop the current processes and assign them new processes with hardware alone.
JA PUPA 1-2511~4 is prior art relevant to the present invention, and discloses a method for sending message to processors of a designated class. IBM~ Technical Disclosure Bulletin, V. 31, No. 6, p 438 discloses a method of sending message together with IDs of processors.
JA9-90-525 3 2~s99~a An object of the present invention is to provide a generalized asynchronous message passing method for a multiprocessor system coupled through a shared bus. In particular, the greatest advantage of the invention lies in flexible, specific control of designation of destination processors. More specifically, the invention makes it possible to designate m arbitrary processors from all, i.e., n processors (1 =< m =< n) and to pass a message to p to q processors among the designated processors (1 =< p =< q =< m =< n). This fully includes functions of "Everybody Message"
and "Anybody Message" referred to in the description on the prior art and enables more powerful the designation of destination.
In a multiprocessor system according to the invention, in order to attain the object, each processor comprises a means for generating a message passing request signal, a means for generating acknowledge signals to messa~e passing request signals from other processors, a means for counting acknowledge signals issued from other processors in response to its own message passing request signal, a means for defining the range of the number of message passing destination processors, and a means responsive to the count value of the acknowledge signals for determining whether message can be sent to a such number of processors as to be included within the range.
In this arrangement, the following types of message passing are possible. Suppose a system includes eight processors, processor 1 to processor 8 coupled through a shared bus. One processor sending a message designates three pieces of information, first on ID or IDs of one or more message passing destination processors, second for the lower limit number of receiving processors, and third for the upper limit number of the receiving processors. The lower limit number of the receiving processors indicates "how many processors, at the minimum, must be ready for receiving a message", and the upper limit number of receiving processor indicates "how many, at the maximum, of the processors are selected as destinations from the processor ready for receiving the message".
JA9-90-525 4 20~992~
Example 1 When the processor 1 is requested to send a message to all the seven processors, the processors 2 to 8 (corresponding to Everybody Message), the destination ID are the processors 2, 3, 4, ..., and 8, the upper and lower limit processor numbers are both 7. Message passing is successful onl~ when all of the seven processors 2 to 8 are ready for reception and a message are sent to these seven processors. When the processor 1 is requested to send message to one or more of the seven processors 2 to 8 (corresponding to Anybody Message), the lower limit processor number is 1 and the upper limit processor number is 7.
Example 2 When the processor 1 is requested to send a message to only one of the five processors, the processor 2 to 6, the destination IDs are the processors 2, 3, ..., and 6 and the lower and upper limit processor numbers are both 1.
Example 3 When the processor 1 is requested to send a message to two or more of the four processors, the processors 5 to 8, the destination IDs are the processors 5, 6, 7, and 8, the lower limit processor number is 2, and the upper limit processor number is 4.
Example 4 When the processor 1 is requested to send a message to three to five processors of the seven processors, the processors 2 to 8, the destination IDs are the processors 2, 3, 4, ..., and 8, the lower limit processor number are 3, and the upper limit processor number is 5.
As shown in the foregoing examples, the invention enables very flexible, specific designation of destination processors.
JA9-90-S25 5 205992a An embodiment of the invention is described below with reference to the drawings, wherein:
Fig. 1 is a block diagram showing the entirety of a multiprocessor system to which an embodiment of the invention is applicable;
Fig. 2 is a block diagram showing the entirety of a single processor involved in the embodiment of the invention;
Fig. 3 is a block diagram showing an integral portion (regarding transmission of a massage) of Fig. 2;
Fig. 4 is a block diagram showing another integral portion (regarding reception of a message) of Fig. 2;
Fig. 5 is a time chart for explanation of the operation of the embodiment of Fig. 2;
Fig. 6 is a diagram showing exchanges of signals for e~planation of the operation of the embodiment of Fig. 2.
Fig. 1 shows the entirety of the embodiment of the invention. A plurality of processors P1, P2 ... Pn are connected to shared memory 2 via a shared bus 1. The shared bus 1 consists of a message exchange bus (Fig. 2~ to which the invention is related, and a memory access bus and so forth. The processors exchange message with each other through the message exchange bus.
Fig. 2 shows an arrangement of message pa~sing hardware, a message bus (address bus and data bus), and an arbitration bus according to the invention. In Fig. 2, a processor P has an MPU (microprocessing unit) 3, a message passing controller 4, and so forth. Although the processor P further has a memory access controller and other elements, such elements do not have direct relevancy to the present in~ention and are not shown in Fig. 2. The shared bus 1 includes message address bus la, message data bus lb, arbitration bus lc. The message passing controller 4 is JA9-90-525 6 ~ 0 5 ~
coupled directly to the MPU 3 and receives instructions.
Practically, MPU 3 gives instructions for message passing to a register referred to later (Figs. 3 and 4) by executing I/O read/write. The message passing controller 4 exchanges messages with the message passing controllers 4 which are implemented in the same way, of the other processors via three buses, i.e., the message address bus la, the message data bus lb, and the arbitration bus lc.
The message address bus la is a control bus for designating a destination of a message and includes as many signal lines as the processor. If the total number of the processors is n, the message address bus includes n lines, ADSl to ADSn, corresponding to the respective processors.
The message data bus lb is for sending a message itself. If m bits of a message are sent at one time, the bus lb includes m signal lines.
The arbitration bus lc is used for the arbitration of bus acquisition when message transmission requests are issued simultaneously from a plurality of message passing controllers 4, and is also used for response indicating whether the processor is ready for reception or not when the processor is a message passing destination. The arbitration bus lc includes as many lines ARB1 to ARBn, as the processors. Various kinds of arbitration methods may be used. For example, the method used in the shared bus in the publication "High-Performance Multiprocessor Work Station TOP-1" referred to the above.
Next refer to Figs. 3 and 4 for detailed description of the message passing controller 4. Fig. 3 shows a part of the message passing controller 4 for transmission of a message whereas Fig. 4 shows a part of the message passing controller 4 for reception of a message.
In Fig. 3, blocks operative upon transmission of a message are a destination control register (DCR) 5, a message data register (MDR) 6, a lower limit receiving processor number register (LNR) 7~ and a upper limit JA9-90-525 7 20~9~2~
receiving processor register (UNR) 8, a parallel counter 9, and a parallel comparator 10.
The DCR 5 is a register that designates destination of a message. Suppose the system includes eight processors;
then the DCR consists of eight bits. Each bit corresponds to a respective processor, and processors whose bits are 1 are selected to be destinations. For example, a message is desired to be sent from the processor 1 to the processors 2, 5, 6, 7, the DCR bits corresponding to the destination processors are set to 1 as follows:
Processor 1 2 3 4 5 6 7 8 DCR bit 0 1 0 0 1 1 1 0 In a more precise e~pression, processors for which the bits of the DCR 5 are set to 1 are only candidates of destinations of the message, and whether the message is actually sent to them depends on the content of the UNR 8 and the LNR 7 explained below. Each bit of the DCR 5 is connected directly to the message address bus la, and the signal lines of the message address bus la are statically assigned to the respective processors beforehand upon initialization of the system, such as signal line ADS 1 to processor 1, signal line ADS 2 to processor 2.
The MDR 6 is used for writing in the content of a message to be sent. When message passing successes, the content of the MDR 6 flow onto the message bus lb and reach one or more destination processors.
The LNR 7 is a register for designating how many processors must be ready for receiving message for successful massage passing. If message passing is requested to success when one or more of destination processors are capable of message reception, the LNR 7 should be set at 1.
If message passing is requested to success when four or more processors are ready for reception, the LNR is set at 4.
This is the register for setting p explained above.
205~2~
The UNR 8 is a register for determining how many processors, in maximum, the message should be sent to, when message passing is possible. By combining it with the LNR 7 referred to the above, specific designation of destination is possible. For example, a message is requested to be sent only one processor, both the LNR 7 and the UNR 8 should be set at 1. This is the register for setting q explained above.
The parallel counter 9 counts how many processors sent back their affirmative acknowledges ACKs. As described before the arbitration bus lc includes n signal lines each corresponding to the respective processor. When a message command is sent, ACK or ACKs return from one or more processors ready for receiving a message among the destination processors. The parallel counter 9 counts these ACKs.
The parallel comparator 10 compares the content of the parallel counter 9 (the count indicating how many processors among the destination processors sent back ACKs) with the content of the LNR 7. When not less ACKs than the value set in the LNR 7 have been sent back, as many processors as the value of the UNR 8 are selected in the order priorities from higher to lower, and the bits corresponding to the processor thus selected are set to 1 in the D~R S.
Fig. 4 shows other blocks of the message passing controller 4, operative upon reception. In Fiq. 4, the bloc~s operative upon reception are a processor ID register (PID) 11, a message reception register (MRR) 12, and an arbitration priority register (APR) 13.
The PID 11 is a register for holding ID of the processor for which the message passing controller 4 serves, and the ID is compared with destination addresses issued on the message address bus la.
The MRR 12 is a buffer for message data.
JA9-90-525 9 2 ~ 5 9 ~ 2 ~
The APR 13 is a register for holding a priority for arbitration. Every time bus arbitration is executed, the priority increases by one, and returns to zero when it overflows. The system is designed so that the processors have different priorities from one another at any time.
Next refer to Figs. 5 and 6 for explanation of how the embodiment operates.
Fig. 5 shows a time chart of message passing, and Fig. 6 shows an example of information exchanges among processors.
A plurality of processors may simultaneously request a bus. Therefore, bus arbitration is first executed at a timing i in a cycle 1. This is a normal arbitration for acquiring the bus. A processor that has won the arbitration can start its massage passing processing. During the following message passing operation, the message passing controllers 4 that has won the bus keeps a busy signal active so that new bus arbitration does not occur.
The processor that won the bus issues message command (timing ii) and message data (timing iii), respectively, on the message address bus and the message data bus in a cycle 2. The message command is for designating on or more destination processors. In Fig. 6(a), the processor 1 sends message command to the processors 2, 3, and 4. Each processor designated as the destination checks its own condition for receiving message in a cycle 3, and, only when it is ready for reception, it sends back ACK to the arbitration bus in a cycle 4 (a timing iv in the cycle 4 is for a message ACK and not for a normal bus arbitration. In Fig. 6(b), processor 3 alone is ready for receiving message, and sends back ACK. In a cycle 5, the message passing controller of the sending processor observes ACK signals to determine which destination processors are ready for receiving the message. When more ACKs than the minimum receiving processor number have been sent back, which means that message passing will result in success, the processor 1 sends command again to as many processors as the maximum receiving processor number ~cycle 5, timing v), and actually sends them the message. In Fig. 6(c), the processor 1 sends a message data to the processor 3. The processor designated as a destination by the command finally receives the message.
As described in the above, the invention performs message passing by designating the range for the number of destination processors, and thus enables flexible, specific message passing. Its effects are discussed below with reference to some examples.
Suppose now that some processors permit the reception of a process and that a certain process is desired to be assigned to one of them. An interruption request is sent to one processor to make the processor switch from the current process to the desired process.
When the conventional message passing method (Anybody Message) is used, a message is sent all processors that permit the reception of a process. A plurality of processors having received message and interrupted must exclusively acquire the process ~y using a semaphore or the like in the shared memory. One processor that has won the semaphore initiates the processing for the assigned process.
The remaining processors restore their conditions before the interruption.
In contrast, when the message passing method according to the invention is used, a message is sent to destination processors which permit the reception of a process. Then, one of the processors is automatically selected, the selected processor alone is interrupted, and processing of the process is initiated. Specifically, the use of the method according to the invention gives two advantages. One is that no interruption request is sent to processors that need not be interrupted. Interruption processing is serious one ~or processors. For example, a typical 32-bit microprocessor, 80386, (produced by Intel, U.
S. A.) takes only several to tens of cycles for addition, subtraction, multiplication, or subtraction, but requires JA9-90-525 11 2~5~2~
200 cycles or more for interruption. The other of the advantages is that it does not require quasi-software exclusive control such as semaphore. Exclusive control using a shared variable causes memory access which in turn causes access to the shared bus, and increases traffic of the shared bus. Unnecessary access to the shared bus adversely affects the performance of the system.
As a next example, suppose that processes A, B, and C
are waiting for processors to become available and that execution of these processes A, B, and C require two processors, four processors, and five processors respectively. In this case, only if a message with the minimum receiving processor number being 2 and the maximum receiving processor number being 5 of receiver processors being 5 is sent by means of the message passing mechanism according to the invention, the process A, B, or C can be selectively initiated depending on the number of the processors that have received the message, i.e., that have been acquired for execution of processes. More specifically, when two or three processors have received the message, then the process A will be initiated, when four processors have, then the process B will be initiated, and when five processors, then the process C will be initiated.
Claims
The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
(1) A multiprocessor system having a plurality of processors connected through a bus wherein each of said processors comprising:
means for sending a message passing request signal;
means for sending an acknowledge signal when responding to a message passing request signal from another of said processors;
means for counting acknowledge signals issued from other one or ones of said processors in response to said message passing request signal;
means for defining the range of the number of message passing destination processors; and means responsive to the count value of said acknowledge signals for determining whether a message can be transmitted to such a number of processors as to be included within said range.
(2) The multiprocessor system according to claim 1 wherein said bus has an arbitration bus and wherein each of said processors further comprises:
means for sending the priority of said processor concerned to said arbitration bus; and means responsive to said priority of said processor concerned and one or more priorities from other one or ones of said processors sent on said arbitration bus for determining whether said message passing request signal can be sent or not.
(3) The multiprocessor system according to claim 2 wherein said message passing request signal includes one or more identifiers of one or more candidates for said message passing destination processors.
(4) The multiprocessor system according to claim 3 wherein said means for defining the range for the number of said message passing destination processors includes means for defining the upper limit of said number and means for defining the lower limit of said number.
(5) The multiprocessor system according to claim 4 wherein when said count value of said acknowledge signals is larger than said upper limit, said upper limit number of processors are selected as said message passing destination processors among said processors having responded to said message passing request signal based on a predetermined rule and a message is sent to said processors thus selected.
(6) The multiprocessor system according to claim 5 wherein said rule is that said processors should be selected based on said priorities.
(7) A multiprocessor system having a plurality of processors connected through a bus, wherein said bus comprises:
a message address bus for transferring one or more message passing destinations;
a message data bus for transferring the content of a message; and an arbitration bus for transferring one or more priorities for the arbitration among a plurality of message passing request signals, and further wherein each of said processors comprising:
means for sending the priority of said processor concerned to said arbitration bus;
means responsive to priorities sent onto said arbitration bus from said processor concerned and other one or ones of said processors for determining whether a message passing request signal can be sent or not;
means for sending said message passing request signal including one or more identifier of one or more message passing destination processors;
means for sending an acknowledge signal when responding to a message passing request signal from another of said processors;
means for counting acknowledge signals issued from other one or ones of said processors in response to said message passing request signal;
means for defining the upper limit of said number of said message passing destination processors; and means for defining the lower limit of said number of said message passing destination processors;
means for initiating message passing when the count value of said acknowledge signals is not less than said lower limit; and means for selecting as many processors as said upper limit as said message passing destination processors among said processors having responded to said message passing request signal based on a predetermined rule when a count value of said acknowledge signals is larger than said upper limit.
(8) A message transmission and reception control apparatus used in each processor for transmission and reception of messages among processors in a multiprocessor system, said processors being connected through a bus, comprising:
means for sending a message passing request signal;
means for generating an acknowledge signal when responding to a message passing request signal received;
means for counting acknowledge signals in response to said message passing request signal thus sent;
means for storing the range of the number of message passing destination processors; and means responsive to the count value of said acknowledge signals for determining whether a message can be transmitted to such a number of processors as to be included in said range.
(1) A multiprocessor system having a plurality of processors connected through a bus wherein each of said processors comprising:
means for sending a message passing request signal;
means for sending an acknowledge signal when responding to a message passing request signal from another of said processors;
means for counting acknowledge signals issued from other one or ones of said processors in response to said message passing request signal;
means for defining the range of the number of message passing destination processors; and means responsive to the count value of said acknowledge signals for determining whether a message can be transmitted to such a number of processors as to be included within said range.
(2) The multiprocessor system according to claim 1 wherein said bus has an arbitration bus and wherein each of said processors further comprises:
means for sending the priority of said processor concerned to said arbitration bus; and means responsive to said priority of said processor concerned and one or more priorities from other one or ones of said processors sent on said arbitration bus for determining whether said message passing request signal can be sent or not.
(3) The multiprocessor system according to claim 2 wherein said message passing request signal includes one or more identifiers of one or more candidates for said message passing destination processors.
(4) The multiprocessor system according to claim 3 wherein said means for defining the range for the number of said message passing destination processors includes means for defining the upper limit of said number and means for defining the lower limit of said number.
(5) The multiprocessor system according to claim 4 wherein when said count value of said acknowledge signals is larger than said upper limit, said upper limit number of processors are selected as said message passing destination processors among said processors having responded to said message passing request signal based on a predetermined rule and a message is sent to said processors thus selected.
(6) The multiprocessor system according to claim 5 wherein said rule is that said processors should be selected based on said priorities.
(7) A multiprocessor system having a plurality of processors connected through a bus, wherein said bus comprises:
a message address bus for transferring one or more message passing destinations;
a message data bus for transferring the content of a message; and an arbitration bus for transferring one or more priorities for the arbitration among a plurality of message passing request signals, and further wherein each of said processors comprising:
means for sending the priority of said processor concerned to said arbitration bus;
means responsive to priorities sent onto said arbitration bus from said processor concerned and other one or ones of said processors for determining whether a message passing request signal can be sent or not;
means for sending said message passing request signal including one or more identifier of one or more message passing destination processors;
means for sending an acknowledge signal when responding to a message passing request signal from another of said processors;
means for counting acknowledge signals issued from other one or ones of said processors in response to said message passing request signal;
means for defining the upper limit of said number of said message passing destination processors; and means for defining the lower limit of said number of said message passing destination processors;
means for initiating message passing when the count value of said acknowledge signals is not less than said lower limit; and means for selecting as many processors as said upper limit as said message passing destination processors among said processors having responded to said message passing request signal based on a predetermined rule when a count value of said acknowledge signals is larger than said upper limit.
(8) A message transmission and reception control apparatus used in each processor for transmission and reception of messages among processors in a multiprocessor system, said processors being connected through a bus, comprising:
means for sending a message passing request signal;
means for generating an acknowledge signal when responding to a message passing request signal received;
means for counting acknowledge signals in response to said message passing request signal thus sent;
means for storing the range of the number of message passing destination processors; and means responsive to the count value of said acknowledge signals for determining whether a message can be transmitted to such a number of processors as to be included in said range.
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| JP3089004A JP2561759B2 (en) | 1991-03-29 | 1991-03-29 | Multiprocessor system and message transmission / reception control device thereof |
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| JPH0887341A (en) * | 1994-09-16 | 1996-04-02 | Fujitsu Ltd | Computer system with automatic degeneratively starting-up function |
| JP3674720B2 (en) * | 1995-10-23 | 2005-07-20 | 富士通株式会社 | Data transfer method in parallel computer |
| US5933598A (en) * | 1996-07-17 | 1999-08-03 | Digital Equipment Corporation | Method for sharing variable-grained memory of workstations by sending particular block including line and size of the block to exchange shared data structures |
| US5802585A (en) * | 1996-07-17 | 1998-09-01 | Digital Equipment Corporation | Batched checking of shared memory accesses |
| US5758183A (en) * | 1996-07-17 | 1998-05-26 | Digital Equipment Corporation | Method of reducing the number of overhead instructions by modifying the program to locate instructions that access shared data stored at target addresses before program execution |
| US5761729A (en) * | 1996-07-17 | 1998-06-02 | Digital Equipment Corporation | Validation checking of shared memory accesses |
| US5787480A (en) * | 1996-07-17 | 1998-07-28 | Digital Equipment Corporation | Lock-up free data sharing |
| US6412056B1 (en) | 1997-10-01 | 2002-06-25 | Compac Information Technologies Group, Lp | Extended translation lookaside buffer with fine-grain state bits |
| US6789256B1 (en) | 1999-06-21 | 2004-09-07 | Sun Microsystems, Inc. | System and method for allocating and using arrays in a shared-memory digital computer system |
| US6718398B1 (en) | 1999-06-21 | 2004-04-06 | Sun Microsystems, Inc. | Robust communications connection system and method for shared memory |
| WO2001022335A2 (en) * | 1999-09-23 | 2001-03-29 | Raymond Leonard G | Notification and alert processing using a plurality of communication media |
| US6782537B1 (en) * | 1999-09-23 | 2004-08-24 | International Business Machines Corporation | Establishing a communicator across multiple processes in a multithreaded computing environment |
| US7447777B1 (en) | 2002-02-11 | 2008-11-04 | Extreme Networks | Switching system |
| US7152124B1 (en) * | 2002-02-11 | 2006-12-19 | Extreme Networks | Method and system for maintaining temporal consistency of resources and data in a multiple-processor packet switch |
| US7814204B1 (en) | 2002-02-11 | 2010-10-12 | Extreme Networks, Inc. | Method of and system for analyzing the content of resource requests |
| US7584262B1 (en) | 2002-02-11 | 2009-09-01 | Extreme Networks | Method of and system for allocating resources to resource requests based on application of persistence policies |
| US7321926B1 (en) | 2002-02-11 | 2008-01-22 | Extreme Networks | Method of and system for allocating resources to resource requests |
| US7298746B1 (en) | 2002-02-11 | 2007-11-20 | Extreme Networks | Method and system for reassembling and parsing packets in a network environment |
| US7447794B1 (en) * | 2002-12-04 | 2008-11-04 | Silicon Graphics, Inc. | System and method for conveying information |
| GB2409303B (en) * | 2003-12-18 | 2006-10-18 | Advanced Risc Mach Ltd | Inter-processor communication mechanism |
| CN103186491B (en) * | 2011-12-30 | 2017-11-07 | 中兴通讯股份有限公司 | The implementation method and device of a kind of end-to-end hardware message transmission |
| JP6176166B2 (en) | 2014-03-25 | 2017-08-09 | 株式会社デンソー | Data processing device |
| FR3052890B1 (en) | 2016-06-21 | 2018-07-13 | Thales Sa | METHOD OF RECEIVING GUARANTEE OF COMMON SIGNALS IN AN AVIONIC SYSTEM COMPRISING A PLURALITY OF ELECTRONIC COMPUTERS |
| JP7155727B2 (en) * | 2018-08-07 | 2022-10-19 | 富士通株式会社 | Information processing device, control method for information processing device, and control program for information processing device |
Family Cites Families (17)
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| US3840859A (en) * | 1972-07-03 | 1974-10-08 | Burroughs Corp | Method and apparatus for regulating input/output traffic of a data processing system |
| US3810110A (en) * | 1973-05-01 | 1974-05-07 | Digital Equipment Corp | Computer system overlap of memory operation |
| US4320452A (en) * | 1978-06-29 | 1982-03-16 | Standard Oil Company (Indiana) | Digital bus and control circuitry for data routing and transmission |
| US4307454A (en) * | 1978-12-21 | 1981-12-22 | Bell Telephone Laboratories, Incorporated | Arrangement preventing multiple connections to peripheral circuits |
| US4430639A (en) * | 1981-05-21 | 1984-02-07 | Benvar Associates, C/O Dale Bennett | Visual message intercommunication unit and system |
| US4622550A (en) * | 1982-04-28 | 1986-11-11 | International Computers Limited | Data communication system |
| US4718005A (en) * | 1984-05-03 | 1988-01-05 | International Business Machines Corporation | Distributed control of alias name usage in networks |
| US4941143A (en) * | 1987-11-10 | 1990-07-10 | Echelon Systems Corp. | Protocol for network having a plurality of intelligent cells |
| US4920486A (en) * | 1987-11-23 | 1990-04-24 | Digital Equipment Corporation | Distributed arbitration apparatus and method for shared bus |
| US4998245A (en) * | 1987-12-17 | 1991-03-05 | Matsushita Electric Industrial Co., Ltd. | Information transmission system having collective data transmission and collection devices |
| JPH01251154A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Message transfer control system |
| JPH077375B2 (en) * | 1988-06-17 | 1995-01-30 | 日本電気株式会社 | Bus control method |
| US4866609A (en) * | 1988-06-22 | 1989-09-12 | International Business Machines Corporation | Byte count handling in serial channel extender with buffering for data pre-fetch |
| US4864559A (en) * | 1988-09-27 | 1989-09-05 | Digital Equipment Corporation | Method of multicast message distribution |
| US4947317A (en) * | 1988-10-12 | 1990-08-07 | Pitney Bowes Inc. | Communication protocol for a three nodes system having dedicated connections and bit indicating function of exchanged message |
| JPH02140860A (en) * | 1988-11-22 | 1990-05-30 | Fujitsu Ltd | Control system for communicating instruction between central processing units |
| FR2662830B1 (en) * | 1990-06-05 | 1992-08-28 | Bull Sa | PROCESS FOR DIALOGUE BETWEEN PROCESSORS OF A SYSTEM, SYSTEM FOR ITS IMPLEMENTATION AND USE FOR THE DISTRIBUTION OF PROCESSES TO PROCESSORS. |
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| US5528761A (en) | 1996-06-18 |
| EP0511731A2 (en) | 1992-11-04 |
| EP0511731A3 (en) | 1992-11-19 |
| JP2561759B2 (en) | 1996-12-11 |
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