CA2051147C - Echo canceller using impulse response estimating method - Google Patents
Echo canceller using impulse response estimating methodInfo
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- CA2051147C CA2051147C CA002051147A CA2051147A CA2051147C CA 2051147 C CA2051147 C CA 2051147C CA 002051147 A CA002051147 A CA 002051147A CA 2051147 A CA2051147 A CA 2051147A CA 2051147 C CA2051147 C CA 2051147C
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- echo
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- correction amount
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M9/00—Arrangements for interconnection not involving centralised switching
- H04M9/08—Two-way loud-speaking telephone systems with means for conditioning the signal, e.g. for suppressing echoes for one or both directions of traffic
- H04M9/082—Two-way loud-speaking telephone systems with means for conditioning the signal, e.g. for suppressing echoes for one or both directions of traffic using echo cancellers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other
- H04B3/23—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
Abstract
An echo canceller uses a Finite-Impulse-Response (FIR) filter to remove an echo from a transmission input signal, the echo resulting from a reflection of a received signal through an echo path. An echo-cancelled signal is thereby output. The echo canceller includes impulse response estimating means for estimating the impulse response of the echo path at a time t from the received signal, the echo-cancelled signal, and the estimated impulse response signal. The estimated impulse response is output as the estimated impulse response signal.
An echo signal estimating means determines a predicted signal of the echo signal from the estimated impulse response signal and the received signal, and outputs the predicted signal as an estimated echo signal. Subtractor means subtracts the estimated echo signal from the transmission signal to produce the echo cancelled signal, and the impulse response estimating means estimates the impulse response of the echo path by using the received signal and the echo cancelled signal at the time t, and the received signal and the echo cancelled signal at a time (t-M) (M being a natural number).
An echo signal estimating means determines a predicted signal of the echo signal from the estimated impulse response signal and the received signal, and outputs the predicted signal as an estimated echo signal. Subtractor means subtracts the estimated echo signal from the transmission signal to produce the echo cancelled signal, and the impulse response estimating means estimates the impulse response of the echo path by using the received signal and the echo cancelled signal at the time t, and the received signal and the echo cancelled signal at a time (t-M) (M being a natural number).
Description
~ ECHO CANCELLER USING IMPULSE RESPONSE ESTIMATING METHOD
The present invention relates to an echo canceller using a Finite-Impulse-Response (FIR) filter and, more particularly, to an echo canceller which increases the convergence speed of a FIR filter.
A typical application of an echo canceller is in a hybrid transformer which implements the 2-4 conversion of a telephone line or satellite communication, and generates an echo due to the impedance mismatching thereof. Another typical application is in a TV conference system or a voice conference system, in which a loudspeaker and a microphone are acoustically coupled to generate an echo. In an echo canceller, a FIR filter estimates the impulse response of an echo path from a received input signal and then generates an estimated echo signal. The estimation of an impulse response cannot be done unless multiplication and addition are repeated a number of times within a short period of time. The number of such arithmetic operations increases with the duration of the impulse response. For example, the multiplication and addition have to be repeated several hundred times within about 100 milliseconds in the case of the estimation of an echo ascribable to the hybrid transformer of a telephone line or even several thousand times when it comes to the estimation of an echo ascribable to the turn-around of the speaker output to a microphone.
To promote efficient echo estimation, there have been proposed various kinds of methods such as a normalized LMS
(Least Mean Square) method and a RLS (Recursive Least Square) method.
The normalized LMS method may be denoted as follows:
y(j) = H(j)' X(j) .... (1) e(j) = y(j) - y(j) .... (2) H(j+1) = H(j) + ~e(j) X(j)/tX(j)t X(j)] --- (3) where y(j), y(j), e(j) and x(j) are respectively the estimated echo signal, transmission input signal, ,. *
transmission output signal (difference output signal), and received input signal at a particular time j.
A received input vector X(j) and an estimated impulse response vector H(j) at a time j are defined as:
X(j) = [x(j), x(j-l), ... , x(j-N+1) ]t H(j) = [ho(j)~ hl(j), ..., hN1(j)]
where hj(j) is the estimated impulse response at a tap position i and at a time j. Further, ~ is constant, and is greater than zero and smaller than 2; the convergence speed is highest when ~ is 1.
An echo canceller of the type estimating an echo by the normalized LMS method is disclosed by, for example, YING G. TAO in "A Cascadable VLSI Echo Canceller", IEEE
JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. SAC-2, March 1984, pp. 297-303. Since the normalized LMS method is based on a statistical procedure, convergence occurs most rapidly with an input signal having no correlation, i.e.
white noise. The maximum convergence speed depends on the estimation order of the filter, and the convergence is completed by a repetition which is about twenty times as great as the estimation order (about 30 dB in terms of the amount of echo cancellation). Assuming an acoustic echo canceller, the estimation order (number of taps) of the filter should be as high as about 2,000, even when the sampling frequency is 8 kilohertz, i.e., more than five seconds is necessary for the convergence. It follows that when the initial convergence of the path is changed, the echo is noticeably increased to degrade the conversation quality.
In light of the above, an echo canceller using the RLS method has also been proposed which solves simultaneous equations to thereby produce an impulse response sequence H(j) uniformly. However, the RLS method is not practicable without requiring a prohibitive number of arithmetic operations, although it promotes rapid convergence and copes with the initial convergence and path change compared to the normalized LMS method.
It is, therefore, an object of the present invention to provide a FIR-type echo canceller capable of promoting rapid conversion while reducing the ratio of increase in the amount of calculations.
In accordance with the present invention, an echo canceller uses a FIR filter for removing an echo from a transmission input signal, the echo resulting from a reflection of a received signal through an echo path. The echo canceller comprises a first memory for storing N latest samples of the received signal, and a second memory for storing an N-th order impulse response of the echo path. It further comprises a first delay circuit for delaying the received signal by M samples, and a third memory for storing N samples of an output of the first delay circuit. It also comprises a second delay circuit for delaying the transmission input signal by M samples, and first and second convolution circuits. The first convolution circuit multiplies and adds the outputs of the first and second memories, and the second convolution circuit multiplies and adds the outputs of the second and third memories. The echo canceller also comprises first and second subtractors. The first subtractor subtracts the output of the first convolution circuit from the transmission input signal to prouduce a transmission output signal, and the second subtractor subtracts the output of the second convolution circuit from the output of the second delay circuit. A
first correction amount calculating circuit of the echo canceller determines a first correction amount on the basis of the transmission output signal from the first subtractor and the received signal. A first multiplier of the echo canceller multiplies the first correction amount by the output of the first memory. The echo canceller further has a first adder, a second correction amount calculating circuit, a second multiplier, and a second adder. The first adder adds the output of the first multiplier to the impulse response from the second memory. The second correction amount calculating circuit determines a second correction amount on the basis of the output of the second subtractor and the output of the first delay circuit. The second multiplier multiplies the second correction amount by the output of the third memory. The second adder adds the output of the second multiplier to the output of the first adder, and feeds back the resulting sum to the second memory.
The first correction amount calculating circuit may comprise a first power circuit for determining the power of N samples of the received signal, and also comprise a first divider for dividing the output of the first lS subtractor by the output of the first power circuit to produce the first correction amount. In this arrangement, the second correction amount calculating circuit comprises a second power circuit for determining the power of N
samples of the output of the first delay circuit, and also comprise a second divider for dividing the output of the second subtractor by the output of the second power circuit to produce the second correction amount.
The first correction amount calculating circuit may comprise a third multiplier for multiplying the output of the first subtractor by a predetermined value ~ to produce the first correction amount. In this arrangement, the second correction amount calculating circuit comprises a fourth multiplier for multiplying the output of the second subtractor by a predetermined value ~ to produce the second correction amount.
M may be smaller than or equal to N, and the first delay circuit may consist of a portion of the first memory which delays the received signal by M samples.
The above and other objects, features and advantages of the present invention will become more , -,, apparent from the following detailed description taken with the accompanying drawings, in which:
Figure 1 is a block diagram schematically showing an echo canceller embodying the present invention;
Figure 2 is a circuit diagram showing a specific construction of a correction coefficient calculating circuit included in the embodiment and implemented with the normalized LMS method;
Figure 3 is a circuit diagram similar to Figure 2, showing another specific construction of the correction coefficient calculating circuit implemented with the LMS
method; and, Figure 4 is a block diagram schematically showing an alternative embodiment of the present invention.
The principle of impulse response estimation particular to an echo canceller of the present invention will first be described. The normalized LMS method estimates the impulse response of an echo path on the assumption that the received input vector appears randomly in the statistical aspect. However, since the received input signal vector is shifted in the direction of the time axis, the estimation of an impulse response is not practicable unless sampling is repeated ten to twenty times as often as the number of taps. On the other hand, to increase the convergence speed, it is necessary to reduce the number of samples necessary for the estimation to be completed. Therefore, if estimation is effected twice in a single sampling period, the number of repetitions will be apparently increased and the number of samples will be reduced. This kind of scheme, however, slows down the estimation when it comes to samples having strong correlation with each other, e.g., two consecutive samples.
To eliminate this problem, a received input signal and a transmission input signal are each provided with a delay sufficient to remove the correlation between sampled signals before parallel processing. When the present invention is implemented with the normalized LMS method, it may be denoted as follows:
y(j) = H(j)' X(j) .... (4) Y(j-M) = H(j)t X(j_M) e(j) = y(j) - y(j) .... (6) e(j-M) = y(j-M) - y(j-M) --- (7) H(j+l) = H(j) + ~h(j) X(j) +~h(j-M) X(j-M) ... (8) where ~e(j) ~e(j-M) ~h(j) = , ~h(j-M) =
X(j)t X(j) X(j-M)' X(j-M) Referring to Figure 1, an echo canceller is shown embodying the present invention to which the normalized LMS
method is applied. As shown, the echo canceller has first to third N-sample memories 1-3, first and second M-sample delay circuits 20 and 21, first and second correction coefficient calculating circuits 30 and 31, first and second convolution circuits 10 and 11, first and second subtractors 40 and 41, first and second adders 50 and 51, and first and second multipliers 60 and 61.
A received input signal x(j) is applied to the first N-sample memory 1 and M-sample delay circuit 20. In response, the N-sample memory 1 stores N latest-received input signals at a time, i.e., it removes the oldest signal x(j-N) on receiving signal x(j). The M-sample delay circuit 20 delays the received input signal x(j) by M samples to output a delayed received input signal x(j-M). Further, the received input signal x(j) is applied to the first correction coefficient calculating circuit 30 and is used to produce a first correction coefficient ~h(j) which will be further described. The delayed received input signal x(j-M) is fed to the third N-sample memory 3 and to the second correction coefficient calculating circuit 31. The third N-sample memory 3, which may have the same construction as the -first N-sample memory 1, stores N latest-delayed received input signals at a time. Having the same construction as the first correction coefficient calculating circuit 30, the second correction coefficient calculating circuit 31 produces a second correction coefficient Ah(j-M) from a first echo cancelled signal e(j-M) fed from the second subtractor 41 and the first delayed received input signal x(j-M). The second N-sample memory 2 stores corrected impulse response hj(j) (i = O, 1, ..., (N-1)) fed from the second adder 51 while sequentially feeding them out. The received input signal vector X(j) and the impulse response vector H(j) from the first and second N-sample memories 1 and 2, respectively, are applied to the first convolution circuit 10, the vectors X(j) and H(j) having N elements each. In response, the convolution circuit 10 determines an estimated echo y associated with a transmission input signal y(j) according to the equation (4). Likewise, the second convolution circuit 11 receives the M-samples-delayed received input signal vector X(j-M) from the third N-sample memory 3, and receives the impulse response vector H(j) from the third and second N-sample memories 3 and 2, respectively, and determines an estimated echo y(j-M) associated with a M-samples-delayed transmission input signal y(j-M) according to the equation (5). The first subtractor 40 subtracts the estimated echo y(j) outputted by the first convolution circuit 10 from the transmission input signal y(j), outputting the resulting difference as a transmission output signal e(j). The transmission output signal e(j) is also applied to the first correction coefficient calculating circuit 30. The second M-sample delay circuit 21 delays the transmission input signal y(j) by M samples to produce a delayed transmission input signal y(j-M). The second subtractor 41 subtracts the estimated echo y(j-M) outputted by the second convolution circuit 11 from the delayed transmission input singal Y(j-M), feeding the resulting difference signal e(j-M) to the second 205 ~ I ~ 7 correction coefficient calculating circuit 31. The first multiplier 60 multiplies the first correction coefficient ~h(j) and the corresponding element of the received input signal vector X(j) to produce ~h(j) X(j). The first adder 50 adds H(j) to L~h(j) X(j) to output H(j) + ~h(j) X(j).
Likewise, the second multiplier 61 produces ~h(j-M) X(J-M).
As a result, the second adder 51 outputs H(j+1), and feeds it to the second N-sample memory 2. The construction described above executes parallel processing for estimating the impulse responses of two samples which are M samples remote from each other in a single sampling period, thereby increasing the convergence speed. Since the embodiment uses a FIR filter having N taps, the estimated echo y(j) and the vectors including the impulse response vector H(j) have to be calculated with each of N elements. For example, ~h(j) X(j) is calculated by ~h(j) xj(j) (i = 0, 1, ..., N). In Figure 1, the control over the write-in and read-out of the first to third N-sample memories 1-3 and the output of the first and second correction coefficients can be readily implemented by a microprocessor, counter, etc., although not shown in the figure.
Figure 2 shows a specific construction of the first correction coefficient calculating circuit 30 in Figure 1. As shown, the correction coefficient calculating circuit 30 is made up of a power calculating circuit 71 having a N-sample memory, and a dividing circuit 70. Figure 2 represents a case wherein the speed coefficient ~ is 1.
The received input signal x(j) is written to the N-sample memory of the power calculating circuit 71 and, at the same time, used to calculate the power of N samples ~x2(j), i.e.
X(j).X(j), together with the past (N-1) samples. The dividing circuit 70 divides the transmission output signal e(j) from the first subtractor 40 by the power ~x2(j) to produce e(j)/(X(j).X(j)) as ~h(j). When ~ is not 1, a multiplier for multiplying the output of the dividing circuit 70 by ~ may be used. The second correction 9 205 1 1 ~7 coefficient calculating circuit 31 may have the same construction as the circuit 30.
Figure 3 shows another specific construction of the correction coefficient calculating circuit 30 which is applicable to the LMS scheme, wherein the normalization by the received input signal x(j) is not effected. As shown, instead of dividing by the power ~x2(j), the circuit 30 multiplies the transmission output signal e(j) by a predetermined scaling factor ~ using a multiplier 62. The resulting product ~e(j) is outputted as ~h(j). The circuit shown in Figure 3 can be implemented with the arrangement shown in Figure 1, except that it is not necessary to supply the received input signal x(j) and delayed received input signal x(j-M). The scaling factor ~ is determined after considering the dynamic range of the received input signal.
Figure 4 shows an alternative embodiment of the present invention which is practicable if M is smaller than or equal to N. Specifically, this embodiment omits the first M-sample delay circuit 20, Figure 1, by using the fact that if M is smaller than or equal to N, the M-sample delayed received input signal x(j-M) is obtainable from the N sample memory. The rest of the construction is identical with the embodiment shown in Figure 1.
In any of the embodiments shown and described, N
may be determined on the basis of the impulse response to be estimated. N increases with the duration of the impulse response to be estimated, as stated earlier. On the other hand, while any value other than 0 may be selected for M, small M's would increase the correlation between two samples to be processed in parallel, and would thereby decrease the convergence speed. Specifically, when the present invention was implemented with the normalized LMS method, the convergence speed was measured to be about 1.9 times as high as the conventional convergence speed when N = M = 256 and ~ or about 1.7 times as high as the latter when N = 256 and M = 128. Although the embodiments have concentrated on particular estimation algorithms, i.e. normalized LMS method and LMS method, the present invention is similarly practicable with an affine projection method or similar algorithm, so long as it is based on LMS.
In summary, it will be seen that the present invention increases the convergence speed by simultaneously estimating the impulse responses of two samples that are M
samples removed from each other.
The present invention relates to an echo canceller using a Finite-Impulse-Response (FIR) filter and, more particularly, to an echo canceller which increases the convergence speed of a FIR filter.
A typical application of an echo canceller is in a hybrid transformer which implements the 2-4 conversion of a telephone line or satellite communication, and generates an echo due to the impedance mismatching thereof. Another typical application is in a TV conference system or a voice conference system, in which a loudspeaker and a microphone are acoustically coupled to generate an echo. In an echo canceller, a FIR filter estimates the impulse response of an echo path from a received input signal and then generates an estimated echo signal. The estimation of an impulse response cannot be done unless multiplication and addition are repeated a number of times within a short period of time. The number of such arithmetic operations increases with the duration of the impulse response. For example, the multiplication and addition have to be repeated several hundred times within about 100 milliseconds in the case of the estimation of an echo ascribable to the hybrid transformer of a telephone line or even several thousand times when it comes to the estimation of an echo ascribable to the turn-around of the speaker output to a microphone.
To promote efficient echo estimation, there have been proposed various kinds of methods such as a normalized LMS
(Least Mean Square) method and a RLS (Recursive Least Square) method.
The normalized LMS method may be denoted as follows:
y(j) = H(j)' X(j) .... (1) e(j) = y(j) - y(j) .... (2) H(j+1) = H(j) + ~e(j) X(j)/tX(j)t X(j)] --- (3) where y(j), y(j), e(j) and x(j) are respectively the estimated echo signal, transmission input signal, ,. *
transmission output signal (difference output signal), and received input signal at a particular time j.
A received input vector X(j) and an estimated impulse response vector H(j) at a time j are defined as:
X(j) = [x(j), x(j-l), ... , x(j-N+1) ]t H(j) = [ho(j)~ hl(j), ..., hN1(j)]
where hj(j) is the estimated impulse response at a tap position i and at a time j. Further, ~ is constant, and is greater than zero and smaller than 2; the convergence speed is highest when ~ is 1.
An echo canceller of the type estimating an echo by the normalized LMS method is disclosed by, for example, YING G. TAO in "A Cascadable VLSI Echo Canceller", IEEE
JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. SAC-2, March 1984, pp. 297-303. Since the normalized LMS method is based on a statistical procedure, convergence occurs most rapidly with an input signal having no correlation, i.e.
white noise. The maximum convergence speed depends on the estimation order of the filter, and the convergence is completed by a repetition which is about twenty times as great as the estimation order (about 30 dB in terms of the amount of echo cancellation). Assuming an acoustic echo canceller, the estimation order (number of taps) of the filter should be as high as about 2,000, even when the sampling frequency is 8 kilohertz, i.e., more than five seconds is necessary for the convergence. It follows that when the initial convergence of the path is changed, the echo is noticeably increased to degrade the conversation quality.
In light of the above, an echo canceller using the RLS method has also been proposed which solves simultaneous equations to thereby produce an impulse response sequence H(j) uniformly. However, the RLS method is not practicable without requiring a prohibitive number of arithmetic operations, although it promotes rapid convergence and copes with the initial convergence and path change compared to the normalized LMS method.
It is, therefore, an object of the present invention to provide a FIR-type echo canceller capable of promoting rapid conversion while reducing the ratio of increase in the amount of calculations.
In accordance with the present invention, an echo canceller uses a FIR filter for removing an echo from a transmission input signal, the echo resulting from a reflection of a received signal through an echo path. The echo canceller comprises a first memory for storing N latest samples of the received signal, and a second memory for storing an N-th order impulse response of the echo path. It further comprises a first delay circuit for delaying the received signal by M samples, and a third memory for storing N samples of an output of the first delay circuit. It also comprises a second delay circuit for delaying the transmission input signal by M samples, and first and second convolution circuits. The first convolution circuit multiplies and adds the outputs of the first and second memories, and the second convolution circuit multiplies and adds the outputs of the second and third memories. The echo canceller also comprises first and second subtractors. The first subtractor subtracts the output of the first convolution circuit from the transmission input signal to prouduce a transmission output signal, and the second subtractor subtracts the output of the second convolution circuit from the output of the second delay circuit. A
first correction amount calculating circuit of the echo canceller determines a first correction amount on the basis of the transmission output signal from the first subtractor and the received signal. A first multiplier of the echo canceller multiplies the first correction amount by the output of the first memory. The echo canceller further has a first adder, a second correction amount calculating circuit, a second multiplier, and a second adder. The first adder adds the output of the first multiplier to the impulse response from the second memory. The second correction amount calculating circuit determines a second correction amount on the basis of the output of the second subtractor and the output of the first delay circuit. The second multiplier multiplies the second correction amount by the output of the third memory. The second adder adds the output of the second multiplier to the output of the first adder, and feeds back the resulting sum to the second memory.
The first correction amount calculating circuit may comprise a first power circuit for determining the power of N samples of the received signal, and also comprise a first divider for dividing the output of the first lS subtractor by the output of the first power circuit to produce the first correction amount. In this arrangement, the second correction amount calculating circuit comprises a second power circuit for determining the power of N
samples of the output of the first delay circuit, and also comprise a second divider for dividing the output of the second subtractor by the output of the second power circuit to produce the second correction amount.
The first correction amount calculating circuit may comprise a third multiplier for multiplying the output of the first subtractor by a predetermined value ~ to produce the first correction amount. In this arrangement, the second correction amount calculating circuit comprises a fourth multiplier for multiplying the output of the second subtractor by a predetermined value ~ to produce the second correction amount.
M may be smaller than or equal to N, and the first delay circuit may consist of a portion of the first memory which delays the received signal by M samples.
The above and other objects, features and advantages of the present invention will become more , -,, apparent from the following detailed description taken with the accompanying drawings, in which:
Figure 1 is a block diagram schematically showing an echo canceller embodying the present invention;
Figure 2 is a circuit diagram showing a specific construction of a correction coefficient calculating circuit included in the embodiment and implemented with the normalized LMS method;
Figure 3 is a circuit diagram similar to Figure 2, showing another specific construction of the correction coefficient calculating circuit implemented with the LMS
method; and, Figure 4 is a block diagram schematically showing an alternative embodiment of the present invention.
The principle of impulse response estimation particular to an echo canceller of the present invention will first be described. The normalized LMS method estimates the impulse response of an echo path on the assumption that the received input vector appears randomly in the statistical aspect. However, since the received input signal vector is shifted in the direction of the time axis, the estimation of an impulse response is not practicable unless sampling is repeated ten to twenty times as often as the number of taps. On the other hand, to increase the convergence speed, it is necessary to reduce the number of samples necessary for the estimation to be completed. Therefore, if estimation is effected twice in a single sampling period, the number of repetitions will be apparently increased and the number of samples will be reduced. This kind of scheme, however, slows down the estimation when it comes to samples having strong correlation with each other, e.g., two consecutive samples.
To eliminate this problem, a received input signal and a transmission input signal are each provided with a delay sufficient to remove the correlation between sampled signals before parallel processing. When the present invention is implemented with the normalized LMS method, it may be denoted as follows:
y(j) = H(j)' X(j) .... (4) Y(j-M) = H(j)t X(j_M) e(j) = y(j) - y(j) .... (6) e(j-M) = y(j-M) - y(j-M) --- (7) H(j+l) = H(j) + ~h(j) X(j) +~h(j-M) X(j-M) ... (8) where ~e(j) ~e(j-M) ~h(j) = , ~h(j-M) =
X(j)t X(j) X(j-M)' X(j-M) Referring to Figure 1, an echo canceller is shown embodying the present invention to which the normalized LMS
method is applied. As shown, the echo canceller has first to third N-sample memories 1-3, first and second M-sample delay circuits 20 and 21, first and second correction coefficient calculating circuits 30 and 31, first and second convolution circuits 10 and 11, first and second subtractors 40 and 41, first and second adders 50 and 51, and first and second multipliers 60 and 61.
A received input signal x(j) is applied to the first N-sample memory 1 and M-sample delay circuit 20. In response, the N-sample memory 1 stores N latest-received input signals at a time, i.e., it removes the oldest signal x(j-N) on receiving signal x(j). The M-sample delay circuit 20 delays the received input signal x(j) by M samples to output a delayed received input signal x(j-M). Further, the received input signal x(j) is applied to the first correction coefficient calculating circuit 30 and is used to produce a first correction coefficient ~h(j) which will be further described. The delayed received input signal x(j-M) is fed to the third N-sample memory 3 and to the second correction coefficient calculating circuit 31. The third N-sample memory 3, which may have the same construction as the -first N-sample memory 1, stores N latest-delayed received input signals at a time. Having the same construction as the first correction coefficient calculating circuit 30, the second correction coefficient calculating circuit 31 produces a second correction coefficient Ah(j-M) from a first echo cancelled signal e(j-M) fed from the second subtractor 41 and the first delayed received input signal x(j-M). The second N-sample memory 2 stores corrected impulse response hj(j) (i = O, 1, ..., (N-1)) fed from the second adder 51 while sequentially feeding them out. The received input signal vector X(j) and the impulse response vector H(j) from the first and second N-sample memories 1 and 2, respectively, are applied to the first convolution circuit 10, the vectors X(j) and H(j) having N elements each. In response, the convolution circuit 10 determines an estimated echo y associated with a transmission input signal y(j) according to the equation (4). Likewise, the second convolution circuit 11 receives the M-samples-delayed received input signal vector X(j-M) from the third N-sample memory 3, and receives the impulse response vector H(j) from the third and second N-sample memories 3 and 2, respectively, and determines an estimated echo y(j-M) associated with a M-samples-delayed transmission input signal y(j-M) according to the equation (5). The first subtractor 40 subtracts the estimated echo y(j) outputted by the first convolution circuit 10 from the transmission input signal y(j), outputting the resulting difference as a transmission output signal e(j). The transmission output signal e(j) is also applied to the first correction coefficient calculating circuit 30. The second M-sample delay circuit 21 delays the transmission input signal y(j) by M samples to produce a delayed transmission input signal y(j-M). The second subtractor 41 subtracts the estimated echo y(j-M) outputted by the second convolution circuit 11 from the delayed transmission input singal Y(j-M), feeding the resulting difference signal e(j-M) to the second 205 ~ I ~ 7 correction coefficient calculating circuit 31. The first multiplier 60 multiplies the first correction coefficient ~h(j) and the corresponding element of the received input signal vector X(j) to produce ~h(j) X(j). The first adder 50 adds H(j) to L~h(j) X(j) to output H(j) + ~h(j) X(j).
Likewise, the second multiplier 61 produces ~h(j-M) X(J-M).
As a result, the second adder 51 outputs H(j+1), and feeds it to the second N-sample memory 2. The construction described above executes parallel processing for estimating the impulse responses of two samples which are M samples remote from each other in a single sampling period, thereby increasing the convergence speed. Since the embodiment uses a FIR filter having N taps, the estimated echo y(j) and the vectors including the impulse response vector H(j) have to be calculated with each of N elements. For example, ~h(j) X(j) is calculated by ~h(j) xj(j) (i = 0, 1, ..., N). In Figure 1, the control over the write-in and read-out of the first to third N-sample memories 1-3 and the output of the first and second correction coefficients can be readily implemented by a microprocessor, counter, etc., although not shown in the figure.
Figure 2 shows a specific construction of the first correction coefficient calculating circuit 30 in Figure 1. As shown, the correction coefficient calculating circuit 30 is made up of a power calculating circuit 71 having a N-sample memory, and a dividing circuit 70. Figure 2 represents a case wherein the speed coefficient ~ is 1.
The received input signal x(j) is written to the N-sample memory of the power calculating circuit 71 and, at the same time, used to calculate the power of N samples ~x2(j), i.e.
X(j).X(j), together with the past (N-1) samples. The dividing circuit 70 divides the transmission output signal e(j) from the first subtractor 40 by the power ~x2(j) to produce e(j)/(X(j).X(j)) as ~h(j). When ~ is not 1, a multiplier for multiplying the output of the dividing circuit 70 by ~ may be used. The second correction 9 205 1 1 ~7 coefficient calculating circuit 31 may have the same construction as the circuit 30.
Figure 3 shows another specific construction of the correction coefficient calculating circuit 30 which is applicable to the LMS scheme, wherein the normalization by the received input signal x(j) is not effected. As shown, instead of dividing by the power ~x2(j), the circuit 30 multiplies the transmission output signal e(j) by a predetermined scaling factor ~ using a multiplier 62. The resulting product ~e(j) is outputted as ~h(j). The circuit shown in Figure 3 can be implemented with the arrangement shown in Figure 1, except that it is not necessary to supply the received input signal x(j) and delayed received input signal x(j-M). The scaling factor ~ is determined after considering the dynamic range of the received input signal.
Figure 4 shows an alternative embodiment of the present invention which is practicable if M is smaller than or equal to N. Specifically, this embodiment omits the first M-sample delay circuit 20, Figure 1, by using the fact that if M is smaller than or equal to N, the M-sample delayed received input signal x(j-M) is obtainable from the N sample memory. The rest of the construction is identical with the embodiment shown in Figure 1.
In any of the embodiments shown and described, N
may be determined on the basis of the impulse response to be estimated. N increases with the duration of the impulse response to be estimated, as stated earlier. On the other hand, while any value other than 0 may be selected for M, small M's would increase the correlation between two samples to be processed in parallel, and would thereby decrease the convergence speed. Specifically, when the present invention was implemented with the normalized LMS method, the convergence speed was measured to be about 1.9 times as high as the conventional convergence speed when N = M = 256 and ~ or about 1.7 times as high as the latter when N = 256 and M = 128. Although the embodiments have concentrated on particular estimation algorithms, i.e. normalized LMS method and LMS method, the present invention is similarly practicable with an affine projection method or similar algorithm, so long as it is based on LMS.
In summary, it will be seen that the present invention increases the convergence speed by simultaneously estimating the impulse responses of two samples that are M
samples removed from each other.
Claims (4)
1. An echo canceller using a Finite-Impulse-Response (FIR) filter for removing an echo from a transmission input signal, the echo resulting from a reflection of a received signal through an echo path, the echo canceller comprising:
a first memory for storing N latest samples of the received signal;
a second memory for storing a N-th order impulse response of the echo path;
a first delay circuit for delaying the received signal by M samples;
a third memory for storing N samples of an output of said first delay circuit;
a second delay circuit for delaying the transmission input signal by M samples;
a first convolution circuit for multiplying and adding the outputs of said first and second memories;
a second convolution circuit for multiplying and adding the outputs of said second and third memories;
a first subtractor for subtracting the output of said first convolution circuit from the transmission input signal to produce a transmission output signal;
a second subtractor for subtracting the output of said second convolution circuit from the output of said second delay circuit;
a first correction amount calculating circuit for determining a first correction amount on the basis of the transmission output signal from said first subtractor and said received signal;
a first multiplier for multiplying said first correction amount by the output of said first memory;
a first adder for adding the output of said first multiplier to the impulse response from said second memory;
a second correction amount calculating circuit for determining a second correction amount on the basis of the output of said second subtractor and the output of said first delay circuit;
a second multiplier for multiplying said second correction amount by the output of said third memory; and, a second adder for adding the output of said second multiplier to the output of said first adder and feeding back the resulting sum to said second memory.
a first memory for storing N latest samples of the received signal;
a second memory for storing a N-th order impulse response of the echo path;
a first delay circuit for delaying the received signal by M samples;
a third memory for storing N samples of an output of said first delay circuit;
a second delay circuit for delaying the transmission input signal by M samples;
a first convolution circuit for multiplying and adding the outputs of said first and second memories;
a second convolution circuit for multiplying and adding the outputs of said second and third memories;
a first subtractor for subtracting the output of said first convolution circuit from the transmission input signal to produce a transmission output signal;
a second subtractor for subtracting the output of said second convolution circuit from the output of said second delay circuit;
a first correction amount calculating circuit for determining a first correction amount on the basis of the transmission output signal from said first subtractor and said received signal;
a first multiplier for multiplying said first correction amount by the output of said first memory;
a first adder for adding the output of said first multiplier to the impulse response from said second memory;
a second correction amount calculating circuit for determining a second correction amount on the basis of the output of said second subtractor and the output of said first delay circuit;
a second multiplier for multiplying said second correction amount by the output of said third memory; and, a second adder for adding the output of said second multiplier to the output of said first adder and feeding back the resulting sum to said second memory.
2. An echo canceller as in claim 1, wherein said first correction amount calculating circuit comprises:
a first power circuit for determining the power of N samples of the received signal; and, a first divider for dividing the output of said first subtractor by the output of said first power circuit to produce said first correction amount;
and wherein said second correction amount calculating circuit comprises:
a second power circuit for determining the power of N samples of the output of said first delay circuit; and, a second divider for dividing the output of said second subtractor by the output of said second power circuit to produce said second correction amount.
a first power circuit for determining the power of N samples of the received signal; and, a first divider for dividing the output of said first subtractor by the output of said first power circuit to produce said first correction amount;
and wherein said second correction amount calculating circuit comprises:
a second power circuit for determining the power of N samples of the output of said first delay circuit; and, a second divider for dividing the output of said second subtractor by the output of said second power circuit to produce said second correction amount.
3. An echo canceller as in claim 1, wherein said first correction amount calculating circuit comprises:
a third multiplier for multiplying the output of said first subtractor by a predetermined value µ to produce said first correction amount;
and wherein said second correction amount calculating circuit comprises:
a fourth multiplier for multiplying the output of said second subtractor by a predetermined value µ to produce said second correction amount.
a third multiplier for multiplying the output of said first subtractor by a predetermined value µ to produce said first correction amount;
and wherein said second correction amount calculating circuit comprises:
a fourth multiplier for multiplying the output of said second subtractor by a predetermined value µ to produce said second correction amount.
4. An echo canceller as in claim 1, wherein M is smaller than or equal to N, and wherein the first delay circuit consists of a portion of said first memory which delays the received signal by M samples.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP239938/1990 | 1990-09-12 | ||
| JP2239938A JP2503747B2 (en) | 1990-09-12 | 1990-09-12 | FIR type eco-canceller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2051147A1 CA2051147A1 (en) | 1992-03-13 |
| CA2051147C true CA2051147C (en) | 1996-10-01 |
Family
ID=17052055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002051147A Expired - Fee Related CA2051147C (en) | 1990-09-12 | 1991-09-11 | Echo canceller using impulse response estimating method |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5289539A (en) |
| JP (1) | JP2503747B2 (en) |
| CA (1) | CA2051147C (en) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5754589A (en) | 1993-01-08 | 1998-05-19 | Multi-Tech Systems, Inc. | Noncompressed voice and data communication over modem for a computer-based multifunction personal communications system |
| US5617423A (en) | 1993-01-08 | 1997-04-01 | Multi-Tech Systems, Inc. | Voice over data modem with selectable voice compression |
| US6009082A (en) | 1993-01-08 | 1999-12-28 | Multi-Tech Systems, Inc. | Computer-based multifunction personal communication system with caller ID |
| US5864560A (en) | 1993-01-08 | 1999-01-26 | Multi-Tech Systems, Inc. | Method and apparatus for mode switching in a voice over data computer-based personal communications system |
| US7082106B2 (en) * | 1993-01-08 | 2006-07-25 | Multi-Tech Systems, Inc. | Computer-based multi-media communications system and method |
| US5535204A (en) | 1993-01-08 | 1996-07-09 | Multi-Tech Systems, Inc. | Ringdown and ringback signalling for a computer-based multifunction personal communications system |
| US5812534A (en) | 1993-01-08 | 1998-09-22 | Multi-Tech Systems, Inc. | Voice over data conferencing for a computer-based personal communications system |
| US5546395A (en) | 1993-01-08 | 1996-08-13 | Multi-Tech Systems, Inc. | Dynamic selection of compression rate for a voice compression algorithm in a voice over data modem |
| US5452289A (en) * | 1993-01-08 | 1995-09-19 | Multi-Tech Systems, Inc. | Computer-based multifunction personal communications system |
| US5453986A (en) | 1993-01-08 | 1995-09-26 | Multi-Tech Systems, Inc. | Dual port interface for a computer-based multifunction personal communication system |
| US5477534A (en) * | 1993-07-30 | 1995-12-19 | Kyocera Corporation | Acoustic echo canceller |
| JP2576767B2 (en) * | 1993-09-10 | 1997-01-29 | 日本電気株式会社 | Echo cancellation method and echo canceller |
| US5757801A (en) | 1994-04-19 | 1998-05-26 | Multi-Tech Systems, Inc. | Advanced priority statistical multiplexer |
| US5682386A (en) | 1994-04-19 | 1997-10-28 | Multi-Tech Systems, Inc. | Data/voice/fax compression multiplexer |
| US5502717A (en) * | 1994-08-01 | 1996-03-26 | Motorola Inc. | Method and apparatus for estimating echo cancellation time |
| JP3395388B2 (en) * | 1994-08-16 | 2003-04-14 | ソニー株式会社 | Signal adaptive processing device and echo suppression device |
| US5561668A (en) * | 1995-07-06 | 1996-10-01 | Coherent Communications Systems Corp. | Echo canceler with subband attenuation and noise injection control |
| DE19525381B4 (en) * | 1995-07-12 | 2006-01-05 | Deutsche Telekom Ag | Method for controlling the step size of an adaptive-filter echo canceller |
| DE19525382B4 (en) * | 1995-07-12 | 2005-12-22 | Deutsche Telekom Ag | Method for controlling the step size of an adaptive-filter echo canceller |
| US5909426A (en) * | 1997-03-31 | 1999-06-01 | Rockwell Science Center, Inc. | Orthogonal LMS algorithms for fast line echo canceler training |
| US7512149B2 (en) * | 2003-04-23 | 2009-03-31 | At & T Intellectual Property Ii, L.P. | Bit and power allocation scheme for full-duplex transmission with echo cancellation in multicarrier-based modems |
| US6671374B1 (en) | 2000-08-03 | 2003-12-30 | Globespanvirata, Inc. | Adaptive filter for echo cancellation, method for operating an adaptive filter for echo cancellation, an article of manufacture for determining tap weights and a length for an adaptive filter for echo cancellation and a computer implemented control system for determining tap weights and a length for an adaptive filter for echo cancellation |
| US7151803B1 (en) | 2002-04-01 | 2006-12-19 | At&T Corp. | Multiuser allocation method for maximizing transmission capacity |
| US7480367B2 (en) * | 2002-12-12 | 2009-01-20 | Adc Dsl Systems, Inc. | Fault characterization using information indicative of echo |
| US7254217B2 (en) * | 2002-12-12 | 2007-08-07 | Adc Dsl Systems, Inc. | Fault characterization using information indicative of echo |
| US8238817B1 (en) | 2006-04-12 | 2012-08-07 | Emc Satcom Technologies, Llc | Noise reduction system and method thereof |
| US7907977B2 (en) * | 2007-10-02 | 2011-03-15 | Agere Systems Inc. | Echo canceller with correlation using pre-whitened data values received by downlink codec |
| US7522877B1 (en) * | 2008-08-01 | 2009-04-21 | Emc Satcom Technologies, Inc. | Noise reduction system and method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56153850A (en) * | 1980-04-28 | 1981-11-28 | Kokusai Denshin Denwa Co Ltd <Kdd> | Echo control system |
| JP2842607B2 (en) * | 1989-03-13 | 1999-01-06 | 株式会社日立製作所 | Echo canceller, communication device including the same, and signal processing method |
-
1990
- 1990-09-12 JP JP2239938A patent/JP2503747B2/en not_active Expired - Lifetime
-
1991
- 1991-09-11 CA CA002051147A patent/CA2051147C/en not_active Expired - Fee Related
- 1991-09-12 US US07/757,951 patent/US5289539A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2051147A1 (en) | 1992-03-13 |
| JPH04120812A (en) | 1992-04-21 |
| JP2503747B2 (en) | 1996-06-05 |
| US5289539A (en) | 1994-02-22 |
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