CA2036545A1 - Method and apparatus for detecting a frame alignment word in a data stream - Google Patents
Method and apparatus for detecting a frame alignment word in a data streamInfo
- Publication number
- CA2036545A1 CA2036545A1 CA002036545A CA2036545A CA2036545A1 CA 2036545 A1 CA2036545 A1 CA 2036545A1 CA 002036545 A CA002036545 A CA 002036545A CA 2036545 A CA2036545 A CA 2036545A CA 2036545 A1 CA2036545 A1 CA 2036545A1
- Authority
- CA
- Canada
- Prior art keywords
- frame alignment
- data stream
- template pattern
- bit groups
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0608—Detectors therefor, e.g. correlators, state machines
Abstract
ABSTRACT
METHOD AND APPARATUS FOR DETECTING A FRAME
ALIGNMENT WORD IN A DATA STREAM
A method and apparatus is provided for detecting a frame alignment word in a data stream. The apparatus comprises a storage means (9) arranged to receive a data stream and pass each bit of the data stream serially through each location of the storage means. A template pattern means (10), arranged to generate a template pattern, is connected to the storage means (9) and arranged in bit groups, each group generating an output signal when it identifies a group of bits corresponding to its template pattern. A decoder circuit (B) is arranged to receive the output signals from the groups and generate a decoder output signal when a specified number of groups match the template pattern indicating that the frame alignment word has been detected.
METHOD AND APPARATUS FOR DETECTING A FRAME
ALIGNMENT WORD IN A DATA STREAM
A method and apparatus is provided for detecting a frame alignment word in a data stream. The apparatus comprises a storage means (9) arranged to receive a data stream and pass each bit of the data stream serially through each location of the storage means. A template pattern means (10), arranged to generate a template pattern, is connected to the storage means (9) and arranged in bit groups, each group generating an output signal when it identifies a group of bits corresponding to its template pattern. A decoder circuit (B) is arranged to receive the output signals from the groups and generate a decoder output signal when a specified number of groups match the template pattern indicating that the frame alignment word has been detected.
Description
~ 4~ ~4 C~
ME~lOD AND APPARATUS FC)R DETECIING A F~A.ME
LIGNMENT WORD IN A DATA STREAM
The present invention relates to a method and apparatus for detecting a ~rame alignment wor~ in a data stream.
The invention finds utility in digital multiplex systems, and is generally applicable to digital communication systems where the detection of specific, recurring binary sequences is required under condition of medium to high binary error ratios.
In digital multiplex systems several independent tributary data streams are combined to a higher rate aggregate bit sequence. A
specific set of characters, known as the Frame A3ignment Word (FAW), is then inserted at regular inlervals into the bit sequence of the aggregate signal prior to transmission. The FAW together with the subsequent bit sequence up to the start of the next FAW constitutes a digital frame.
At the demultiplexer, the received binary data is initially examined on a bit-by-bit basis until a FAW has been correctly detected. This process is known as Frame Search. When the frame search is complete a new digital frame is constructed which is a replica of the originally lransmitted digital frame, the transmitted and recei~ved digital frames are then said to be in alignment. When the demultiplexer frame is in alignment the inverse of the multiplex procedures can be applied to reconstitute the original data streams.
~~ ~ In order to maintain correct operation of the demultiplexer it is necessary to conlinuously check the occurrence of a FAW in the expected position in the digital sequence to confirm that frame 2~3~L5 I
alignment is being maintained. When the check procedure indicates loss of alignment a new frame search is initiated.
In practical digital transmission systems binary errors cause the corruption of the FAWs resulting in failure to recognise the FAW
during frame a]ignment procedures and spurious detection of misalignment when the digital frame is already aligned. The probability of a corrupted FAW is dependent on the binary error ratio and the number of bits which constitute the FAW. The larger the error ratio and the number of bits in the FAW the greater the probability of corrupti on .
In many app]ications the FAW is constructed to give a sufficiently long binary sequence so that the probability of its pattern being simulated by a combination of data bits within the digital frame is negligibly small. Therefore a demultiplexer can readily identify a FAW
within the received signal, using a template matching technique. By this technique the incoming data stream is compared, on a bit-by-bit basis, against a template pattern of the FAW; if there is a ma~ch between the incoming stream and the template pattern, then a FAW is declared as recognised.
If the detection of the FAW ;s based on an exact match between the incoming data stream and the FAW template pattern, it cannot recognise valid FAWs if they have been corrupted by digital errors.
Under such condi~ions, the demultiplexer cannot achieve rapid frame alignment or, in the case of higher error rates, may be subject to frequent spurious realignment thus greatly increasing the impairment of the received digital signal.
203~
It is an object of ~he invention to significantly enhance the frame alignment performance of demultiplexers in conditions of high error rates by applying specific error tolerant FAW detection procedures.
According to the present invention there is provided apparatus for detecting a frame alignment word in a data stream, comprising a storage means arranged to receive a data stream and pass each bit of the data stream serially through each location of the s~orage means, template pattern means, arranged to generate a template pattern, connected to the storage means and arranged in bit groups, each group generating an output signal when it identifies a group of bits corresponding to its template pattern, a decoder circuit arranged to receive the output signals from the groups and generate a decoder output signal when a specif;ed number of groups, which may be less than the total number in the template pattern, match the template pattern indicating that the frame alignment word has been detected.
According to the present invention there is provided, a method of detecting a frame alignment word in a data stream, comprising the steps of:
passing the data stream through each bit location of a serial storage means, checking gIOUpS of bits against a template pattern,`
determining when a predetermined number of groups match the template pattern~ and, generating an output signal indicating that the frame alignment word has been detected.
An embodiment of the present invention will now be described with reference to the accompanying drawing wherein:
2 0 3 ~
Figure 1 shows a FAW detection template pattern, Figure 2 shows a reduced FAW detection template pattern, Figure 3 show~ a block diagram of the circuits which implemen~
the invention, and, Figure 4 shows a block circuit diagram of a decoder.
Referring to Figure 1, a FAW detection template pattern is shown divided into groups 1 to 8.
A FAW is considered as correctly recognised and valid if any seven out of the eight groups are unambiguously detected and free of error. This FAW detection algorithm can be represented in the form of a trnth table as shown in Table 1.
Table 1:
-Groups 1 1 ¦ 2 3 4 5 6 7 8 FAW detected _ M M M M M M M M YES
D M M M M M ~ M YE~
M D M M M M M M YES
M M D M M M M M ~
M M M D M M M M YES
M M M M D M M M YES
M M M M M D M M YES
M M M M M M D M YES
M M M M M M M D YES
~ ~11 oth ,r combinations ~O
M - all bits matched:- group matched D - one or more bits do not match:- group not match~d 2 0 ~
When the demultiplexer has previously achieved frame alignment the FAW detection template pattern is reduced to only the middle four groups, 3, 4, 5 and 6 as shown in Figure 2.
During the check plocedure in the alignment mode the PAW is considered to be valid if any three out of four grcups are unambiguously recognised and ~ree of error. The states of groups 1, 2, 7 and 8 are not taken into account. This l~AW checking algorithm can be represented in a truth table as shown in Ta~le 2.
Table 2:
Groups 1 2 3 4 5 6 7 8 FAW detected _ _ , _ _ _ .
X X M M M M X X ~TS
X X D M M M X X YES
X X M D M M X X ~ES
X X M M D M X X YES
X X M M M D X X YES
All other combinations ~_ M = all ~oits matched:- group matched D = one or more bits do not match:- group not matched X = irre1evant A block schematie for a specific implementation of the present invention is shown in Figure 3, and its operation is dcscribed as ~ollows:
The incoming data is shifted on a bit-by-bit basis through a serial shift register 9. The contents of the shift register 9 is continuously .
~031~S4~
compared with the template pattern, a preset data pattern, by eight 'AND' functions 10, where each of the 'AND' functions relates to a particular group of digits in the template pattern. When the incoming data and the corresponding group in the template pattern match the 'AND' function indicates 'TRUE'. In the Search Mode outputs of the 'AND' functions are evaluated according to the truth table as given in Table 1 by using the DECODER B 12. When a FAW has been detected 12 generates a 'TRUE' signal which is output to the FRAME SEARCH selector 13.
In the Aligned Mode the outputs of the appropriate 'AND' functions aIe evaluated accoIding to the truth ~able as given in Table 2 by using the DECODE~R A 11. When a FAW has ~een detected 11 generates a 'TRUE' signal which is output to 13.
The output of 13 is selected according to the current state of the demultiplexer i.e, alignment or search mode, RefelTing to Figure 4, a block circuit diagram is shown of the decoder A, depicted in Figure 3, It will be appreciated that the decoder B is composed of similar elements except it will comprise eight inpu~s in all. The decoder A comprises four inputs A, B, C and D, each of which is directly applied to a respective AND-gate, Each input is also inverted by a Tespective inverter 14 to 17, Input A is applied directly to AND-gates lB to 21, and the inverse input is applied to AND-gate 22. Input B is applied directly to AND-gates 18 to ~0 and 22 and the inverse input applied to AND-gate 21, Input C is applied directly to AND-gate lg, 19, 21 and 22 and the inverse input is applied to AND-gate 20, Input D is applied to AND-gate 18, 20 to 22 and the inverse input is applied to AND-gate 19, The outputs from the AND-gates 18 to 22 are 2Q3~
applied to an OR-gate 23 which provides the output signal Q. The truth table for decoder A is shown below:
A B C _D O
other combinations û
The truth table for decoder B is shown below:
A B C D E~ F G H O
1 1 1 1 1 1 1 ~ 1 oeher combinations O
The above description has been of one ernbodiment of the present invention and is not intended to ~e limited thereto. It will ~3~
readily be appreciated by those skilled in ~he art that alternative applications are possible, such as in the recognition of specific binary bit sequences required when the digital signal is subject to binary errors.
,
ME~lOD AND APPARATUS FC)R DETECIING A F~A.ME
LIGNMENT WORD IN A DATA STREAM
The present invention relates to a method and apparatus for detecting a ~rame alignment wor~ in a data stream.
The invention finds utility in digital multiplex systems, and is generally applicable to digital communication systems where the detection of specific, recurring binary sequences is required under condition of medium to high binary error ratios.
In digital multiplex systems several independent tributary data streams are combined to a higher rate aggregate bit sequence. A
specific set of characters, known as the Frame A3ignment Word (FAW), is then inserted at regular inlervals into the bit sequence of the aggregate signal prior to transmission. The FAW together with the subsequent bit sequence up to the start of the next FAW constitutes a digital frame.
At the demultiplexer, the received binary data is initially examined on a bit-by-bit basis until a FAW has been correctly detected. This process is known as Frame Search. When the frame search is complete a new digital frame is constructed which is a replica of the originally lransmitted digital frame, the transmitted and recei~ved digital frames are then said to be in alignment. When the demultiplexer frame is in alignment the inverse of the multiplex procedures can be applied to reconstitute the original data streams.
~~ ~ In order to maintain correct operation of the demultiplexer it is necessary to conlinuously check the occurrence of a FAW in the expected position in the digital sequence to confirm that frame 2~3~L5 I
alignment is being maintained. When the check procedure indicates loss of alignment a new frame search is initiated.
In practical digital transmission systems binary errors cause the corruption of the FAWs resulting in failure to recognise the FAW
during frame a]ignment procedures and spurious detection of misalignment when the digital frame is already aligned. The probability of a corrupted FAW is dependent on the binary error ratio and the number of bits which constitute the FAW. The larger the error ratio and the number of bits in the FAW the greater the probability of corrupti on .
In many app]ications the FAW is constructed to give a sufficiently long binary sequence so that the probability of its pattern being simulated by a combination of data bits within the digital frame is negligibly small. Therefore a demultiplexer can readily identify a FAW
within the received signal, using a template matching technique. By this technique the incoming data stream is compared, on a bit-by-bit basis, against a template pattern of the FAW; if there is a ma~ch between the incoming stream and the template pattern, then a FAW is declared as recognised.
If the detection of the FAW ;s based on an exact match between the incoming data stream and the FAW template pattern, it cannot recognise valid FAWs if they have been corrupted by digital errors.
Under such condi~ions, the demultiplexer cannot achieve rapid frame alignment or, in the case of higher error rates, may be subject to frequent spurious realignment thus greatly increasing the impairment of the received digital signal.
203~
It is an object of ~he invention to significantly enhance the frame alignment performance of demultiplexers in conditions of high error rates by applying specific error tolerant FAW detection procedures.
According to the present invention there is provided apparatus for detecting a frame alignment word in a data stream, comprising a storage means arranged to receive a data stream and pass each bit of the data stream serially through each location of the s~orage means, template pattern means, arranged to generate a template pattern, connected to the storage means and arranged in bit groups, each group generating an output signal when it identifies a group of bits corresponding to its template pattern, a decoder circuit arranged to receive the output signals from the groups and generate a decoder output signal when a specif;ed number of groups, which may be less than the total number in the template pattern, match the template pattern indicating that the frame alignment word has been detected.
According to the present invention there is provided, a method of detecting a frame alignment word in a data stream, comprising the steps of:
passing the data stream through each bit location of a serial storage means, checking gIOUpS of bits against a template pattern,`
determining when a predetermined number of groups match the template pattern~ and, generating an output signal indicating that the frame alignment word has been detected.
An embodiment of the present invention will now be described with reference to the accompanying drawing wherein:
2 0 3 ~
Figure 1 shows a FAW detection template pattern, Figure 2 shows a reduced FAW detection template pattern, Figure 3 show~ a block diagram of the circuits which implemen~
the invention, and, Figure 4 shows a block circuit diagram of a decoder.
Referring to Figure 1, a FAW detection template pattern is shown divided into groups 1 to 8.
A FAW is considered as correctly recognised and valid if any seven out of the eight groups are unambiguously detected and free of error. This FAW detection algorithm can be represented in the form of a trnth table as shown in Table 1.
Table 1:
-Groups 1 1 ¦ 2 3 4 5 6 7 8 FAW detected _ M M M M M M M M YES
D M M M M M ~ M YE~
M D M M M M M M YES
M M D M M M M M ~
M M M D M M M M YES
M M M M D M M M YES
M M M M M D M M YES
M M M M M M D M YES
M M M M M M M D YES
~ ~11 oth ,r combinations ~O
M - all bits matched:- group matched D - one or more bits do not match:- group not match~d 2 0 ~
When the demultiplexer has previously achieved frame alignment the FAW detection template pattern is reduced to only the middle four groups, 3, 4, 5 and 6 as shown in Figure 2.
During the check plocedure in the alignment mode the PAW is considered to be valid if any three out of four grcups are unambiguously recognised and ~ree of error. The states of groups 1, 2, 7 and 8 are not taken into account. This l~AW checking algorithm can be represented in a truth table as shown in Ta~le 2.
Table 2:
Groups 1 2 3 4 5 6 7 8 FAW detected _ _ , _ _ _ .
X X M M M M X X ~TS
X X D M M M X X YES
X X M D M M X X ~ES
X X M M D M X X YES
X X M M M D X X YES
All other combinations ~_ M = all ~oits matched:- group matched D = one or more bits do not match:- group not matched X = irre1evant A block schematie for a specific implementation of the present invention is shown in Figure 3, and its operation is dcscribed as ~ollows:
The incoming data is shifted on a bit-by-bit basis through a serial shift register 9. The contents of the shift register 9 is continuously .
~031~S4~
compared with the template pattern, a preset data pattern, by eight 'AND' functions 10, where each of the 'AND' functions relates to a particular group of digits in the template pattern. When the incoming data and the corresponding group in the template pattern match the 'AND' function indicates 'TRUE'. In the Search Mode outputs of the 'AND' functions are evaluated according to the truth table as given in Table 1 by using the DECODER B 12. When a FAW has been detected 12 generates a 'TRUE' signal which is output to the FRAME SEARCH selector 13.
In the Aligned Mode the outputs of the appropriate 'AND' functions aIe evaluated accoIding to the truth ~able as given in Table 2 by using the DECODE~R A 11. When a FAW has ~een detected 11 generates a 'TRUE' signal which is output to 13.
The output of 13 is selected according to the current state of the demultiplexer i.e, alignment or search mode, RefelTing to Figure 4, a block circuit diagram is shown of the decoder A, depicted in Figure 3, It will be appreciated that the decoder B is composed of similar elements except it will comprise eight inpu~s in all. The decoder A comprises four inputs A, B, C and D, each of which is directly applied to a respective AND-gate, Each input is also inverted by a Tespective inverter 14 to 17, Input A is applied directly to AND-gates lB to 21, and the inverse input is applied to AND-gate 22. Input B is applied directly to AND-gates 18 to ~0 and 22 and the inverse input applied to AND-gate 21, Input C is applied directly to AND-gate lg, 19, 21 and 22 and the inverse input is applied to AND-gate 20, Input D is applied to AND-gate 18, 20 to 22 and the inverse input is applied to AND-gate 19, The outputs from the AND-gates 18 to 22 are 2Q3~
applied to an OR-gate 23 which provides the output signal Q. The truth table for decoder A is shown below:
A B C _D O
other combinations û
The truth table for decoder B is shown below:
A B C D E~ F G H O
1 1 1 1 1 1 1 ~ 1 oeher combinations O
The above description has been of one ernbodiment of the present invention and is not intended to ~e limited thereto. It will ~3~
readily be appreciated by those skilled in ~he art that alternative applications are possible, such as in the recognition of specific binary bit sequences required when the digital signal is subject to binary errors.
,
Claims (8)
1. Apparatus for detecting a frame alignment word in a time division multiplex data stream comprising storage means having a plurality of serial locations arranged to receive an ATDM data stream and pass each bit of the data stream serially through each location, and template pattern means connected to said storage means and arranged to provide a template pattern corresponding to a frame alignment word, and wherein said template pattern means is arranged in a plurality of bit groups, each bit group generating an output signal when it identifies a group of bits corresponding to its portion of the whole template pattern, a decoder circuit being connected to the bit groups to receive the output signals from the bit groups and generate a decoder output signal indicating frame alignment when a specified number of bit groups, which may be less than the total number of bit groups, give output signals indicating that they have identified the groups of bits associated with them.
2. Apparatus as claimed in Claim 1, wherein once a frame alignment word has been detected and frame alignment has been confirmed, the number of template pattern groups used to monitor said storage means is reduced in number whereby a defined lesser part of the total storage means is monitored by the template pattern means.
3. Apparatus as claimed in Claim 2 wherein first and second decoder circuits are provided, said first decoder circuit being connected to those template bit groups connected to the defined lesser part of said storage means and said second decoder circuit being connected to all of said template bit groups.
4. Apparatus as claimed in Claim 3 wherein the outputs of said first and second decoder circuits are connected to a selector circuit which indicates that a frame alignment word has been detected.
5. Apparatus as claimed in Claim 4 wherein the selector circuit comprises first and second AND-gates connected to an OR-gate, the output of said first decoder circuit being connected to first said AND-gate and the output of said second decoder circuit being connected to said second AND-gate circuit.
6. Apparatus as claimed in Claim 5 wherein an enabling signal is connected to an additional input of each of said first and second AND-gates, the input of said first AND-gate to which said enabling signal is applied being an inverting input.
7. A method of detecting a frame alignment word in a time division multiplex data stream, the method comprising the steps of passing the data stream through each bit location of a serial storage means, and checking the bits against a template pattern, the method being further characterised in that the template pattern is split into a predetermined number of bit groups and the detection of the frame alignment word is confirmed when a predetermined number of the bit groups indicate that they have detected a match in the data stream.
8. A method as claimed in Claim 7 wherein when detection of a frame alignment word has been confirmed, reaffirmation of frame alignment is provided by confirmatory outputs of a reduced number of the bit groups.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB909004188A GB9004188D0 (en) | 1990-02-23 | 1990-02-23 | Method and apparatus for detecting a frame alignment word in a data stream |
| GB9004188.0 | 1990-02-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2036545A1 true CA2036545A1 (en) | 1991-08-24 |
Family
ID=10671558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002036545A Abandoned CA2036545A1 (en) | 1990-02-23 | 1991-02-18 | Method and apparatus for detecting a frame alignment word in a data stream |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US5204859A (en) |
| EP (1) | EP0443754A3 (en) |
| JP (1) | JPH04216230A (en) |
| CN (1) | CN1025267C (en) |
| AU (1) | AU635112B2 (en) |
| CA (1) | CA2036545A1 (en) |
| FI (1) | FI910865A (en) |
| GB (2) | GB9004188D0 (en) |
| PT (1) | PT96866A (en) |
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| US6470009B1 (en) | 1990-11-22 | 2002-10-22 | Sprint Communications Company L.P. | Broadband telecommunications system interface |
| FR2676879B1 (en) * | 1991-05-24 | 1994-02-11 | Telecommunicat Radioelect Teleph | WEFT LOCK LOSS MONITORING DEVICE. |
| US5544180A (en) * | 1992-06-08 | 1996-08-06 | Qlogic Corporation | Error-tolerant byte synchronization recovery scheme |
| SE501884C2 (en) * | 1993-10-12 | 1995-06-12 | Ellemtel Utvecklings Ab | Synchronous circuit arrangements determine the boundary between consecutive packets |
| KR970003024B1 (en) * | 1994-02-28 | 1997-03-13 | 한국전기통신공사 | Fast re-synchronizing method using parallel-processing pattern matching in variable length codes |
| WO1995031057A1 (en) | 1994-05-05 | 1995-11-16 | Sprint Communications Company, L.P. | Method, system and apparatus for telecommunications control |
| GB2293949B (en) * | 1994-10-08 | 1999-05-26 | Plessey Telecomm | Fast serial pattern recognition |
| GB2302967B (en) * | 1995-07-03 | 1998-11-11 | Behavior Tech Computer Corp | Switch for computer peripheral device |
| GB2320662B (en) * | 1996-12-18 | 2001-06-20 | Dsc Telecom Lp | Apparatus and method of frame aligning information in a wireless telecommunications system |
| SE511389C2 (en) * | 1997-01-21 | 1999-09-20 | Ericsson Telefon Ab L M | Framelocking |
| US6741594B1 (en) * | 2000-06-15 | 2004-05-25 | Advanced Micro Devices, Inc. | Arrangement for identifying data packet types from multiple protocol formats on a network switch port |
| US7111228B1 (en) | 2002-05-07 | 2006-09-19 | Marvell International Ltd. | System and method for performing parity checks in disk storage system |
| US7007114B1 (en) | 2003-01-31 | 2006-02-28 | Qlogic Corporation | System and method for padding data blocks and/or removing padding from data blocks in storage controllers |
| US7287102B1 (en) | 2003-01-31 | 2007-10-23 | Marvell International Ltd. | System and method for concatenating data |
| US7039771B1 (en) | 2003-03-10 | 2006-05-02 | Marvell International Ltd. | Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers |
| US7870346B2 (en) * | 2003-03-10 | 2011-01-11 | Marvell International Ltd. | Servo controller interface module for embedded disk controllers |
| US7064915B1 (en) | 2003-03-10 | 2006-06-20 | Marvell International Ltd. | Method and system for collecting servo field data from programmable devices in embedded disk controllers |
| US7457903B2 (en) * | 2003-03-10 | 2008-11-25 | Marvell International Ltd. | Interrupt controller for processing fast and regular interrupts |
| US7099963B2 (en) * | 2003-03-10 | 2006-08-29 | Qlogic Corporation | Method and system for monitoring embedded disk controller components |
| US7492545B1 (en) | 2003-03-10 | 2009-02-17 | Marvell International Ltd. | Method and system for automatic time base adjustment for disk drive servo controllers |
| US7526691B1 (en) | 2003-10-15 | 2009-04-28 | Marvell International Ltd. | System and method for using TAP controllers |
| US7139150B2 (en) * | 2004-02-10 | 2006-11-21 | Marvell International Ltd. | Method and system for head position control in embedded disk drive controllers |
| US7120084B2 (en) | 2004-06-14 | 2006-10-10 | Marvell International Ltd. | Integrated memory controller |
| US8166217B2 (en) * | 2004-06-28 | 2012-04-24 | Marvell International Ltd. | System and method for reading and writing data using storage controllers |
| US9201599B2 (en) * | 2004-07-19 | 2015-12-01 | Marvell International Ltd. | System and method for transmitting data in storage controllers |
| US8032674B2 (en) * | 2004-07-19 | 2011-10-04 | Marvell International Ltd. | System and method for controlling buffer memory overflow and underflow conditions in storage controllers |
| US7757009B2 (en) | 2004-07-19 | 2010-07-13 | Marvell International Ltd. | Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device |
| US7386661B2 (en) | 2004-10-13 | 2008-06-10 | Marvell International Ltd. | Power save module for storage controllers |
| US7240267B2 (en) * | 2004-11-08 | 2007-07-03 | Marvell International Ltd. | System and method for conducting BIST operations |
| US7802026B2 (en) * | 2004-11-15 | 2010-09-21 | Marvell International Ltd. | Method and system for processing frames in storage controllers |
| US7609468B2 (en) | 2005-04-06 | 2009-10-27 | Marvell International Ltd. | Method and system for read gate timing control for storage controllers |
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| DE1183119B (en) * | 1963-10-15 | 1964-12-10 | Telefunken Patent | Method for data transmission in which the information is transmitted in individual blocks, the beginning of which is identified by synchronization signals arriving at the receiving location before the block begins |
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| US4358845A (en) * | 1980-03-05 | 1982-11-09 | Societe Anonyme de Telecommunications Company | Process for the compression of signalling data or the like transmitted in a train of multiplexed PCM information |
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| FR2631762B1 (en) * | 1988-05-18 | 1991-02-15 | Cit Alcatel | FRAME SYNCHRONIZATION DEVICE FOR A SYNCHRONOUS DIGITAL BLOCK SHARED TRAIN USING A BLOCK CODE AND FRAME STRUCTURE |
| US4979169A (en) * | 1989-02-14 | 1990-12-18 | Data General Corporation | Method and apparatus for performing format conversion between bit streams |
-
1990
- 1990-02-23 GB GB909004188A patent/GB9004188D0/en active Pending
-
1991
- 1991-02-11 GB GB9102844A patent/GB2241413B/en not_active Expired - Fee Related
- 1991-02-11 EP EP19910301061 patent/EP0443754A3/en not_active Withdrawn
- 1991-02-13 US US07/654,949 patent/US5204859A/en not_active Expired - Fee Related
- 1991-02-18 CA CA002036545A patent/CA2036545A1/en not_active Abandoned
- 1991-02-20 AU AU71240/91A patent/AU635112B2/en not_active Ceased
- 1991-02-21 JP JP3049058A patent/JPH04216230A/en active Pending
- 1991-02-22 FI FI910865A patent/FI910865A/en not_active Application Discontinuation
- 1991-02-23 CN CN91101196A patent/CN1025267C/en not_active Expired - Fee Related
- 1991-02-25 PT PT96866A patent/PT96866A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| AU7124091A (en) | 1991-08-29 |
| CN1025267C (en) | 1994-06-29 |
| GB2241413A (en) | 1991-08-28 |
| AU635112B2 (en) | 1993-03-11 |
| EP0443754A2 (en) | 1991-08-28 |
| GB9102844D0 (en) | 1991-03-27 |
| JPH04216230A (en) | 1992-08-06 |
| PT96866A (en) | 1993-01-29 |
| GB2241413B (en) | 1994-10-05 |
| EP0443754A3 (en) | 1992-04-01 |
| US5204859A (en) | 1993-04-20 |
| CN1054344A (en) | 1991-09-04 |
| FI910865A0 (en) | 1991-02-22 |
| FI910865A (en) | 1991-08-24 |
| GB9004188D0 (en) | 1990-04-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |