CA2034911C - Integrated data link controller with autonomous logical elements - Google Patents

Abstract

INTEGRATED DATA LINK CONTROLLER WITH
AUTONOMOUS LOGICAL ELEMENTS

ABSTRACT OF THE DISCLOSURE

A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device handles multiple channels of mixed voice and data traffic concurrently, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications.
Synchronous and asynchronous sections in the device respectively interface with the network and host system.
Special purpose autonomous logic elements in the synchronous section form plural stage receive and transmit processing pipelines between the network and host interfaces. Such pipelines perform OSI Layer 2 processing tasks on data in HDLC channels. Each autonomous element comprises one or more state machine circuits having functional autonomy and reduced time dependence relative to other elements. A
"resource manager" element (RSM) and time swap (TS) RAM
memory operate to dynamically swap states of pipeline elements in synchronism with channel time slots at the network interface, whereby the pipeline stages operate as data buffering stages which perform multiple tasks during any slot. The device contains integrated memory queues in which communication data and channel event status information are stacked for asynchronous transfer.
Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while minimizing critical time dependencies between the device and host system. Device elements provide first and second non-interfering information transfer paths between the device and host system; one for exchanges of control/status information between the device and host, and the other for direct memory access transfers of communication data between the device and an external memory associated with the host.

Description

~ BC9-90-001 1 2 ~ 3 ~

INTEGRATED DATA_LINK CONTROLLER WITH
AUTONOMOUS LOGICAL__LEMENTS

CROSS-REFERENCES TO RELATED PATENT_~PPLICATIONS

1. Canadian Application Serial Number 2,035,673, filed February 5, 1991, by J. Farrell et al, entitled "Integrated Data Link Controller With Synchronous Link Interface And Asynchronous Host Processor Interface", concerns organization of the sub~ect data link control device into synchronous and asynchronous sections providing pipelining effects for more efficient operation.

2. Canadian Application Serial Number 2,034,031, filed January 11, 1991, 1990, by J. Farrell et al, entitled "Burst Time Division Multiplex Interface For Integrated Data Link Controller", concerns a connection interface between a sub~ect device and line control circuits (also called "level 1 circuits"), allowing the device to operate efficiently relative to diverse line speed~, protocols, modem characteristics, etc.

3. Canadian Application Serial Number 2,035,696, filed February ~, 1991, by J. Farrell et al, entitled "Integrated Data Link Control With Dynamic Hyperchannel Mapping", concerns a feature of the sub~ect device relating to its capability for dynamically and variably configuring time channels on ISDN (Integrated Systems Data Networks) links into higher throughput channels called "hyperchannels".

BACKGROUND OF THE IN ENTION
,, , This invention relates to data link control devices for high speed telecommunication networks, particularly devices for performing link control functi.ons relative to diversely configured network channel~ and for transferrin8 information at high speeds between network links and data processing systems. More specifically, the invention relates to devices of this kind having greater versatility and throughput speed than comparable contemporary devices, with particular applicability for use in networks carrying both voice and data signal~ at very high speeds; specifically, but not exclusively, networks operating under international . ~

~C9-90-001 2 2~9 specifications for Integrated Services Digital Network (ISDN) protocols.
The invention relates further to devices of the foregoing kind which can be conveniently and efficiently packaged on a single densely integrated semiconductor chip with contemporary CMOS technology. Based on this last characteristic, and certain capabilities for integrating functions, such devices are presently called "Integrated Data Link Control" (or IDLC) devices.

PRIOR ART
Comparable communication data link control devices --as disclosed in US Patents 4,493,051 and 4,504,901, assigned to the assignee of the present application -- provide flexible modular interfaces between lines in a teleprocessing network and host processors; with ability to selectively support varied transmission rates, modem interfaces and communication protocols (e.g. SDLC, BSC, etc.) on each line. Each such device is intended to replace a variety of different devices or part numbers which otherwise would be required to support such different transmission rates, modem interfaces and protocols.
An aspect of the sub~ect invention is a present recognition that such comparable devices have unapparent and avoidable limitations or dependencies, both external and internal, tending to limit or restrict their performance. As signalling speeds on networks continue to increase progressively (and this trend appears to show little sign of ending), devices of the type presently contemplated will have to satisfy throughput and performance requirements which can not be met by comparable contemporary devices.
External dependencies alluded to above result from real time busing requirements ~elative to external microprocessors, and appear to have developed as a result of the architecture then used; including the nature of functional distribution between the device and external ~y~tems, and the depth or capacity of buffer storage available locally to the device (for queuing information in transit between the device and external systems).

,. .

~C9-90-001 3 203491~

Internal dependencies mentioned above result from the functional organization of internal logic in such prior art devices as a single coherent processing entity, having its fundamental clock cycles of operation tightly coordinated with line or channel scanning periods at the network interface. Typically, such logic can execute only a single discrete function in any clock cycle of operation, and in any one channel scan period (extending over many basic cycles) the same logic is confined to processing functions associated with reception or transmission of a single bit of data relative to the channel being scanned. Furthermore, after having initiated external requests for action relative to a given network channel, such logic must complete related information transfers (of communication data as well as interrupt event status information) during the respective scan period for transferring signals to and from that channel. Such constraints have tended to unduly lengthen required scan period durations, thereby restricting maximum signal throughput rates sustainable by such devices relative to network~ and functions which such devices can perform (e.g. relative to mixed voice and data channels).
,, .
SUMMARY OF THE INVENTION

By eliminating and/or greatly reducing such dependencies, the present invention seeks to provide support , for future ISDN and other networks operating at speeds beyond capabilities of contemporary devices. Thus, where such contemporary devices contemplate support of network connections with line or channel scanning speeds not greater than 350,000 received or transmitted bits per second, the sub~ect device would accommodate connections requiring 8canning speed8 in excess of 2 million received and tran~mitted bits per second.
Furthermore, it is clear that such contemporary devices would have very limited capability for supporting ; transmission of digitized voice; since each full duplex ;, voice channel, running at a maximum rate of 64,000 bits per second, w0-11d consume as much as 20 percent of the throughput capacity of the device. The sub~ect device .

BC9-90-001 4 2~3~911 however would easily accommodate a mix of multiple voice channels and high speed digital data channels.
The sub~ect device i9 organized into synchronous and asynchronous sections (refer to Canadian application no.
2,035,673 mentioned above), each containing multiple partitions of special purpose logic circuits and memory facilities. The foregoing ob~ectives are achieved by organizing the partitions into modular autonomous units, hereafter called "autonomous logic elements", forming distributed logical pipelines relative to the handling of communication data between network and host interfaces.
These distributed pipeline configurations provide advantages relative to contemporary systems, in respect to numbers of logical functions which can be performed in parallel simultaneously relative to any network channel, and also in respect to design adaptiveness ~any element can be replaced by a functionally different element, e.g. for supporting future links requiring new functions, without affecting designs of other elements in the same pipeline), and the pipeline organizatlon adapts efficiently to interpolation of additional elements in tandem into any pipeline.
Each autonomous element has a high degree of functional autonomy and information queueing capacity relative to other elements, including elements within the same pipeline, tending to reduce the time criticality of inter-element data transfers within pipelines. The synchronous section operates in synchronism with appearances of channel time slots at the network interface, whereas operations in the asynchronous section are relatively asynchronous to such appearances.
Autonomous elements in these sections provide distributed processing of communication data per channel within respective pipelines, with a degree of autonomy such that time tependencies relative to information transfers between consecutive pipeline stages are comparatively reduced. Thus, an element in the synchronous section may suspend an action request initiated by it relative to a channel associated wlth a network time slot imminently ending, and reissue the request at the next appearance of the same channel time slot.
. .

~C9-90-001 5 20~491 Channel state information is transferred in a "swapping" exchange between elements in the synchronous section and a "time swap" (TS) RAM (random access memory) in synchronism with appearances of respective channel time slots at the network interface. The saved state information of each exchange is used for establishing the initial state of the respective element in the next scan of the same channel time slot.
A unisue aspect of thi~ "state swapping" process is that the state information stored includes sufficient information relative to states of pending requests for information transfer action originated by one element relative to other elements to allow the one element to withdraw or suspend its request if the slot ends before the action requested begins, and to unambiguously reactivate the ; request during the next appearance of the same channel time ; slot. Another unique aspect of this process is that data queueing capacity in both sections is sufficient to allow the foregoing request suspension and reinstatement actions to be carried out without overrun or underrun of information transfer continuity at external interfaces of the device and yet with efficient distributed integration of queueing facilities in the device such that the size, power consumption and cost of the device are not adversely affected.
. Another aspect of the device is that it contains interrupt handling partition~ and a DMA (direct memory access) control partition, the latter having direct access to memory in the host proces~ing system, characterized in their autonomy relative to host system elements and their offloading of operations ordinarily performed at a higher ,' proces8ing level.
j Another feature is that the DMA control partition acts through a Master I/0 partition in accessing the bus through which acce9s to ho8t system memory is obtained. The Master I/0 partition performs the arbitration function8 required to access the bus, and provides a small body of logic as a focal point for adapting the subJect device design for lnterfacing to a variety of different bus structures.
Another feature of the device is that communication between the partitions which synchronously process data and ~C9-90-001 6 203~9~.
the DMA controls are handled through a DMA Request Queue partition which has synchronous and asynchronous interfaces, and which receives requests from the synchronous partitions and presents them to the DMA control partition on an asynchronous basis.
One of the interrupt handling partitions (INT) monitors events within the device and at the interface between the device and the network (including hardware conditions and activities relative to link channels), collects relevant status details in local memory within the device and sets alerting indications in the other partition (SIO).
Processing elements in the host system monitor the SIO for such indications and operate through the SIO to directly access local memory in the device to collect the stored status details. This eases the time criticality of reportage of time related events.
Through a programming interface between it and the device (also considered unique), the host system stores information in several local memories for initiating device i operations (both generally and relative to individual network channels). Included in such information are DCB's (device control block arrays) for initiating data transmission operations relative to network channels and other control information for directing the placement of received information in host system memory address spaces.
These DCB's and other control information are stored in a - local DMA RAM in the sub~ect device.
A unique aspect of the usage of the above-mentioned other control information in reception processing, is that the DMA control partition uses that information to place received data in endless circular buffers located in directly acce8sible IOP/host memory spaces, and to manage the contalnment of that data within programmable boundary addresses. The advantage of this is that the IOP/host system is relieved of responsibility for dynamically relocating the , data during its reception handling and for monitoring the i data transfer process for boundary overrun conditions.
A unique aspect of the usage of DCB's mentioned above is that in transmission processes the DMA control partition responds to chaining indications in DCB's to fetch additional DCB's, from directly accessed spaces in IOP/host ~C9-90-001 7 203491 memory, thereby offloading from the IOP/host system responsibility for the loading of such additional DCB'g into the device's local DMA RAM. It also allows the IOP/host system to efficiently use its memory by scattering chained DCB's in that memory. With this feature, the subject device may act automatically to retrieve such scattered DCB's and continuously perform processes linked by said DCB'S.
Furthermore, the data transmitted by such processes can also be scattered in IOP/host memory. In addition, combining this feature with autonomously performed protocol framing functions (insertion/removal of protocol related framing information on transmission/reception), enables the subject device to further relieve the host system of functional responsibilities normally assumed at a higher level within the host system.
Another aspect of the invention relative to interrupt handling is that status queues are provided relative to each of a plurality of channels, each queue having plural status storage spaces for storing a plurality of status functions relative to process events in the respective channel occurring and detected at different times by the IDLC (e.g.
frame received, abort signal received, end of transmit chain detected, etc.). These status functions are accessible asynchronously by the IOP, and in one access to any queue it is possible for the IOP to retrieve a plurality of entries relating to different events. This eases the requirements imposed on the IOP for processing interruption status, as well as reducing the real time processing restrictions which otherwise would be needed for maintaininB coordination between the IOP and the IDLC.
An advantageou8 application of transmit DCB chalning by the DMAC partition, and multi-status queueing as noted above, is that it enables the IDLC to eliminate otherwise needed interruptions of the IOP system relative to reportage of receive frame end events (completion of individual frame receptions). However, the IDLC presently does interrupt the IOP to report individual receive frame end events, and the InLC furnishes transmit count information in a dedicated portion of the status word associated with each received frame end; the transmit count indicating the number of frames sent by the IDLC to the source of the received frame.

D c 9--9 0--o 01 20349~Ll Since certain received frames contain information indicating the number of frames received from the IDLC node, as determined by the remote source of the received frames, the IOP can compare the transmit count status to the number indicated by the remote source as a means of maintaining integrity of its transmissions in duplex channels (e.g. by retransmitting frames if there is a discrepancy between the compared parameters). To summarize then, in lieu of providing transmit frame end status to the IOP via (time and bandwidth consuming) interruptions, relative to duplex communication channels the IDLC uses the more efficient expedient presently of inserting transmitted frame count information into an allotted portion of the status which is provided on receive frame end interrupts.

OBJECTS OF THE INVENTION

~ n ob~ect of the present invention is to provide a data link control device, for use between data communication link8 and data proce9sing systems, having fewer limitation9 and time constraints than comparable prior art devices, and consequent greater functional flexibility and speed of operation than comparable devices.
Another ob~ect is to provide a multi-use data link control device, for use between telecommunication links and data processing systems, having a broader range of functional responsibilities as well as a higher degree of functional autonomy relative to external processing systems than comparable prior art devices.
Another obJect is to provide a tevice as above having interconnected autonomous logical circuit partitions forming pipelines through which data is transferred between the processing and network interfaces, which partitions are characterized by having reduced critical time dependencies relative to each other and external interfaces of the device. Such pipelines are characterized herein as having multitasking and multiprocessing responsibilities; inasmuch ag they perform diverse tasks relative to diversely configured channels in time multiplex, and each pipeline has plural discrete processing stages which at any instant of ~C9-90-001 9 2~349~

time are or can be performing plural functions relative to a single channel in parallel and simultaneously.
Another object is to provide a multi-use data link control device, for transferring data between multiple telecommunication channels scanned in a time division multiplex mode and a data processing system, while performing multiple data processing functions on data being transferred relative to each of said channels, in which said functions are performed in a pipelined manner by multiple autonomous logical elements. A related object is to provide a device as just stated wherein said channels are diversely configurable to handle data at varied rates and in accordance with a plurality of different communication protocols, and each of a plurality of said autonomous elements is configured logically as a multitasking unit for processing data relative to said channels in accordance with configurations of respective channels.
Another related ob~ect is to provide a device as just stated wherein one or more of said autonomous elements is capable of performing a plurality of functions relative to data in transit to and from any one of said channels.
Another related ob~ect is to provide a device as just stated having a locally associated random access "time swap" memory including memory spaces pre-allocated for storing state information associated with data being processed by each of a plurality of said autonomous elements relative to each of said channels, and including a resource managing element interfacing with said memory and said plurality of elements for dynamically directing exchanges of state information between said memory and said plurality of elements in time slots associated with said channels, whereby each of said plurality of elements conducts its processing tasks relative to each of 8aid channels in said associated time slots.
Another related ob~ect is to provide a device as ~ust stated wherein said memory contains sufficient storage space allocated relative to each of said channels and 8aid plurality of elements to hold a pipeline of mu1tiple bytes of data relative to each of said elements. A related ob~ect is to configure said plurality of elements individually as one or more logical state machine units having sufficient logical intelligence when signalled by said resource ~C9-90-001 10 203491~

managing element to prepare for an exchange of state information with said memory to sequence to a stable logical state such that any action begun by an element so signalled relative to a channel currently being processed can be unambiguously suspended and continued in the next period of processing allocated to the same channel.
Another object is to provide a modular data link control device, for use between data processing systems and communication network links, in which various different functions associated with reception of information from a single network data communication channel are performed in parallel by a plurality of autonomous logical elements (see definition of "autonomous logical elements" infra) for receive processing, in such fashion that performance of such functions requires less time per channel than would be required if the same functions were performed by a single technologically equivalent element.
Another ob~ect is to provide a modular data link control device, for use between data processing systems and - communication network links, in which various different functions associated with transmission of information to a single network data channel are performed in parallel by a plurality of autonomous logical elements for transmit processing in such fashion that performance of such functions requires less time per channel than would be required if the same functions were performed by a single technologically equivalent element.
Yet another ob~ect i8 to provide a modular data link control device, for use between data processing systems and communication network9, in which various functions relating to transfer of lnformation signals between the device and each of a plurality of channels in said network are performed concurrently and in parallel by a plurality of autonomous loglcal elements for receive and transmit processing, and wherein functions required to dynamically initialize said elements relative to different ones of said channels are directed by an autonomous logical element for re80urce management. A related ob~ect is to provide a data link control system, using a device as ~ust characterized, which includes a local random access "time 9wap" memory organized to retain initial state information relative to ~C9-90-001 11 2034911`

each channel currently being served by said device, and which is immediately accessible to said resource management element of said device. Yet another object is to provide a device as characterized above containing a plurality of autonomous logical elements for interrupt processing; such elements cooperating to receive and process status indications from other autonomous elements and to pass associated interruption request signals to external processing systems. A related object is to provide such a device with autonomously functioning interrupt processing elements incorporating queueing facilities for temporarily storing interrupt status information in transit between said device and external processing system on a per network channel basis. A related object is to operate such queueing facilities on a first in first out (FIFO) basis.
Another ob~ect is to provide a device as just characterized in which at least one of said interrupt processing elements is operable on a multi-tasking basis to direct entries of status information into said queueing facillties, to monitor indicators set by said external processing system to denote retrieval of entries from said queueing facilities, and to manage updating of control parameters indicating the number of outstanding interrupt requests as a function of said monitored indicators. A
related ob~ect is to provide sufficient information to said external processing systems to enable said systems to operate on an efficient multi-tasking basis in handling interrupt requests from said device, retrieving status entries Prom said queueing facilities, and setting said inticators of retrieval.
A relatet ob~ect is to provide a device as ~ust characterized with capability of entering status information into said queuelng facilities representing status relative to indivitual communication frames ~ust received in a duplex communicatlon channel, and of including with said status information "transmit count" information denoting the cumulative number of frames transmitted by said device in the same channel; said transmit count bein8 useful in said external processinR 8ystem to ascertain integrity of said device's transmissions and eliminating otherwise needed transfers of interruption reque~ts from said device and ~C9-90-001 12 20349~1 associated status relative to transmissions of individual frames from said device.
Another object is to provide a device as characterized previously in which states of autonomous transmit and receive elements are varied in synchronism with appearances of channel time slots at an external communication interface of the device to perform processing operations relative to respective channels, said states being varied in accordance with per-channel state information stored in said time swap RAM relative to each of said elements, and in which said stored state information is sufficient to permit said transmit and receive elements to conditionally defer and reinstate requests initiated by them for information transfer action relative to other elements; whereby each such element may suspend a request associated with a given channel if the respective channel time slot ends before the requested action i9 taken, and reinstate the request in the next appearance of the same channel time slot. A unique aspect of this "state swapping" process is that the state information stored includes sufficient information relative to the state of pending exchanges between the respective element and its external interfaces to allow the element to accomplish the foregoing request suspension and reinstatement operations without loss of information and with assured continuity of operation relative to each channel.
Another ob~ect is to provide a device as characterized previously, wherein signal exchanges at a downlink external interface of the device relative to any duplex network channel are time staggered within a scan period allotted to the respective channel -- in the order of "interrupt event 8ampling" first, "tran8mit 8ignalling" second, and "receive sampling" last -- and wherein state determining variables re8pectively unique to interruption, transmission and reception processing functions are applied to autonomous elements of the device at correspondingly time staggered intervals during that scan period, and wherein global state determining variables common to all of said processing functions are transferred to commonly accessible registers in said device at another phase point in said scan period;
whereby usage of said time swap RAM may be optimized.

sC9-90-001 13 20349~

Yet another ob~ect is to provide a device as characterized above containing one or more autonomous elements for managing the flow of data and control information between the device and said external processing system. A related object is to provide a queuing facility relative to such flow, and to operate the storing function of said facility on a FIF0 ba~is. Another related object is to integrate said facility in the device. Another related ob~ect is to partially distribute said integrated queueing facility among a plurality of autonomous elements for efficient topological integration of said facility.
Another related object is to provide as one of the autonomous elements for flow management a direct memory access (DMA) control element which is operative to control transfers of data between said queueing facility and memory associated with said external processing system. A related ob~ect is to adapt such DMA control autonomous element for automatically transferring received data relative to circular buffer spaces in said external memory, and to manage containment of said data within programmably determined boundary locations in said external memory.
Another related ob~ect i9 to adapt said DMA control element to use DCB arrays for locating data to be transmitted to network channels in said external memory, and to respond to chaining indications in said DCB'g to automatically retrieve additional DCB'g from said external memory, thereby allowing for location of said chained DCB' 9 and the data to be transmitted in scattered spaces in said external memory.
Another ob~ect is to provide a communication controller, u~ing a device as characterized above, having an autonomou9 interrupt handling partition and local memory operative to collect status information for delayed communication to the ho5t system.
Another ob~ect is to provide a communication controller, using a device as characterized above, having an autonomous DMA control partition for directly accessing memory in an external host processing system, and an a~sociated local RAM for storing DCB control block information supplied by said system for use in transmitting data from said host system to ~aid network channels, wherein said partition is responsive to chaining indications in said ~C9-90-001 14 203491~

DCB ' s to retrieve additional DCB ' s from scattered spaces in said host system memory and said device is operative further to determine network framing and formatting of transmitted data for varied protocol channels in accordance with control information in said additional DCB ' s .
Another object is to provide a device as characterized above which can be entirely packaged in a single LSI chip ; using contemporary chip design technology.
; These and other objects, features, benefits and advantages of the sub~ect invention will be more fully understood and appreciated from the following detailed description.

DESCRIPTION OF DRAWINGS

. Fig. ~, a block diagram of a typical data communication network using sub~ect devices, illustrates positions of sub~ect devices in the network. The particular network system illustrated is for primary rate ISDN voice and data telecommunication applications, although the sub~ect device is deemed useful for many other network applications.
Fig. 2 is a block diagram of a data processing node in a network as exemplified in Fig. 1, illustrating the conPiguration withi~ the node of the sub~ect IDLC device and its associated local TS ("time swap") RAM memory.
Fig. 3 i9 a high level block diagram of the internal logical organization of the sub~ect device illustrating its ma~or logical partitions and associated RAM memory units including TS RAM. Fig. 4 is a time chart of functions performed within the synchronous section of the sub~ect device, under direction of a resource manager logic element withln the device, for dynamically configuring states of other autonomou8 logic elements in that section in synchronism with level 1 link signalling processes external to the device.
Fig. 5 is an intermediate level block diagram of the IDLC, indicatin8 logical elements and sub-elements as well a~ principal registers in each element and sub-element.
Figure 6 is a block diagram of TS RAM, indicating its ~ize and per channel space allotments.

. .

,, , . . - , , ~C9-90-001 15 2034911 Figure 7 is a block diagram of FIF0 RAM, indicating its size and per channel space allotments.
Figure 8 is a block diagram of DMA RAM, indicating its size and per channel space allotments.
Figure 9 is a block diagram illustrating the logical and physical organization of TS RAM.
Figure 10 is a block diagram of the RSM (resource manager) partition.
Figures 11 and 12 respectively illustrate bit allocations within CCR (channel configuration register) and HPCR (HDLC protocol configuration register) words, which are associated with dedicated registers in the RSM partition and stored in dedicated per channel word spaces in TS RAM.
Figures 13 - 15 contain timing diagrams for explaining the BTDM interface between subject IDLC device and Ll circuits .
Figure 16 is a block diagram of the logical organization of the receive layer l (RLl) circuit element in the IDLC.
~ Figure 17 illustrate~ the layout of the status indication register in RLl.
Figure 18 illu~trate~ the format of the "channelized"
time swap status word, RLl_TSOl, exchanged between RLl and TS RAM via RSM relative to each active communication channel at the BTDM interface.
Figure l9 is a block diagram of the receive validate (RV) circuit element in the IDLC.
Figures 20 and 21 illustrate formats of the two time 9wap ~tatu9 words, RV_TSOl and RV_TS02, exchanged between RV
and TS RAM via RSM.
Figure 22 is a block diagram of the transmit layer 1 (TLl) circuit element in the IDLC.
Figure 23 illustrates the layout of the TLl status indication register.
Figure 24 illustrates the format of the time 9wap status word, TLl_TS01, exchanged between TLl and TS RAM via RSM
Figure 25 i9 a block diagram of the tran8mit validation element (TV) in the IDLC.
Figure 26 illu9trates the format of the time swap word, TV_TS01, exchanged between TV and TS RAM via RSM.

~C9-90-001 16 203491~

Figure 27 i9 a block diagram of the FIFO RAM section of the IDLC.
Figure 28 is a block diagram of the receive FIFO
manager element RFM in the IDLC.
Figures 29 and 30 illustrate the formats of the two time swap status words, RFM_TSOl and RFM_TS02, exchanged between RFM and TS RAM via RSM.
Figure 31 i9 a block diagram of the transmit FIFO
manager element TFM in the IDLC.
Figure 32 illustrates the format of the time swap status word, TFM_TSOl, exchanged between TFM and TS RAM
Figures 33 and 34 illustrate layouts of the word spaces in FIFO RAM reserved for the two receive DMA configuration registers per channel, RDCRl and RDCR2.
Figures 35 and 36 illustrate layouts of the word spaces in FIFO RAM reserved for the two transmit DMA configuration registers per channel, TDCRl and TDCR2.
Figure 37 i9 a block diagram of the interrupt partition INT in the IDLC.
Figure 38 illustrates the form of the status function IHEISR (IDLC Hardware Error Interrupt Status Register) generated in INT.
Figures 39 and 40 illustrate forms of status words CEISR (Channelized Error Interrupt Status Register) and EOPISR (End Of Process Interrupt Status Register) generated in INT and stored relative to each active communication channel in TS RAM.
Figure 41 illustrates the queue in TS RAM relative to each communication channel of (up to 16) status terms EOPISR.
Figure 42 is a chart of IDLC interrupt vector levels and priorities relative to IOP.
Figure 43 is a block diagram of the slave I/O partition SIO in the IDLC.
Figures 44 and 45 illustrate the forms of configuration definlng flmctions ICR (IDLC configuration register) and HCR
(HyperChannel configuration register) registered in SIO.
Figure 46 illustrates the form of the VHR (vector holding register) status function registered in SIO.
Figure 47 is a block diagram of the DMARQ (DMA request queue) partition in the IDLC.

BC9-90-001 17 2 ~ 3 ~ 9 1 1 Figure 48 is a block diagram of the DMAR (DMA RAM) partition in the IDLC.
Figure 49 is a block diagram of the DMAC (DMA control) partition in the IDLC.
Figures 50 and 51 illustrate the forms of terms RDCR3 and RDCR4 stored in DMAR relative to each active channel, and used by DMAC to control its transfer operations relative to data being received in respective communication channels.
Figures 52 and 53 illustrate the forms of terms TDCR3 and TDCR4 stored in DMAR relative to each active channel, and used by DMAC to control its transfer operations relative to data being transmitted to respective communication channels.
Figure 54 (shown with Figures 20 and 21) is a block diagram of the M~O (master I/O) element in the IDLC.
Figure 55 contains a schematic illustration of the circuits within the sub~ect IDLC which participate in the establishment and usage of HyperChannel configurations.

DETAILED DESCRIPTION

1. TERMS. DEFINITIONS A_D CONCEPTS

Terms used herein have the following intended meanings.

Autonomous Logical Element As used presently, means a special purpose logical circuit arrangement having data inputs and outputs and a finite repertoire of logical states, typically a set of logic circuits containing one or more logical state machine circuits, and which upon being set to one of it8 states sequences to other 9tate~ as a function of external conditions or events, and while so sequencing performs logical functlons relative to said data inputs and outputs in a manner such that its operations relative to other elements to which it connects either for exchanging data or receiving external state control are performable in parallel and simultaneous with operations of such other elements.
CCITT

BC9-90-001 18 2~3491~

The International Telegraph and Telephone ConsultatiYe Committee; an organization formed originally under the International Telecommunications Union (ITU) treaty of 1865, and now a specialized agency o~ the Unite~
Nations. The organization generates publications referred to elsewhere herein defining international standards for telecommunication protocols. Participants include telecommunications carriers such as AT&T and GTE Telenet.
CMOS
Complementary Metallic Oxide Silicon as used in contemporary integrated semiconductor devices.

A particular form of CMOS technology accommodating line spacings of 1 micron and providing circuit switching speeds of 1 ns for a 2 input AND gate [refer to: (1) IEEE J. Solid State Circuits, V. 23, N. 5 Oct. 1988, Pp. 1095-11, Won8, D. T. et al, "ll-ns 8K x 18 CMOS
Static RAM With 0.5-mu m Devices"; (2) Proc. Of The Custom Integrated Circuits Conf. 1987, by IEEE, Pp.
248-252, Aldridge, A. W. et al, "40K Equivalent Gate CMOS Standard Cell Chip"; (3) Proc. Of The Custom Integrated Circuits Conf. 1987, by IEEE, Pp. 2~5-247, Hornung, F et al, "A Versatile VLSI Design System For Combining Gate Array And Standard Cell Circuits On The Same Chip"]
Host System A main data processing unit or sy~tem in a data processing network.
H-channel (Hereafter termed HyperChannel) A form of high speed time divi8ion channel defined by the CCITT in its I.412 definitions ~refer to: CCITT Red Book, Vol. III, Fascicle III.5, "Integrated Services Digital Network (ISDN), Recommendations of the Series I, Geneva 1985~.
HDLC (High Level Data Link Control) Generic term encompassing LapB, LapD and SDLC protocol~
defined herein.
HyperChannel See H-channel above.
IOI System /

~C9-90-001 19 20349~1 An input-output processor operating under control of a main (or host) processor.
ISDN
Integrated Services Digital Network, as defined by CCITT [Refer to: CCITT Red Book, VIII, Fascicle III.5 above].
ISDN Layers 1 and 2 (Ll, L2) Respectively, the physical and data link control layers of logical signal handling in ISDN networks; the physical layer attending to transmission and reception of signals on network lines and activation and deactivation of network connections on such lines; the link control layer concerned with error checking and other higher level functions relative to the physical layer [refer to: CCITT Red Book, VIII, Fascicle III.5 above, Part IV, Sections 3 and 4].
LAPB
A particular data link protocol for X.25 networks, defined by CCITT X.25 Recommendation [refer to: CCITT
Fascicle VIII.3 - Recommendation X.25, "Interface Between Data Terminal Equipment (DTE) And Data Circuit-Terminating Equipment (DCE) For Terminals Operating In The Packet Mode And Connected To Public Data Networks By Dedicated Circuit, Geneva 1976, Amended 1980 and 1984].
LAPD
A particular link access protocol for D channels as defined by CCITT Recommendation Q.920 [Refer to: CCITT
Fascicle III.5 above, Part IV, Section 4.]
Motorola 68000 bus Bus used by Motorola 68000 microprocessors to attach to memory and other peripherals [refer to: M68000 8-/16-/32 Bit Microprocessors User's Manual, sixth ed., Prentice Hall, 1989, Section 5 (Signal And Bus Operation Description)].
Network Nodes ~ Points at which terminal equipments attach to a ; network.
Physical Interface Layer 1 interface [see ISDN Layers 1 and 2 above].
RAM

. . .

~C9-90-001 20 2034gl~1 Random Access Memory SDLC
Synchronous Data Link Control; the link control protocol used in SNA [refer to: IBM Publications GA27-3093-3, "Synchronous Data Link Control Concepts", 1979, 1986]
SNA
Systems Network Architecture [refer to: IBM Publication GC30-3072-3, "Systems Network Architecture - Concepts And Products",1981, 1986]
Finite State Machine A logical circuit having a finite repertoire of possible stable operating positions or stages, each position or stage yielding a characteristic action or output, and undergoing transitions between such positions or stages as a function of external stimuli.

2. NETWORK OVERVIEW

Figure 1 illustrates a network 1 having data processing nodes 2, connected by digital communication link 3, in which sub~ect IDLC devices 4 may be advantageously employed.
Although only two nodes are shown it will be understood that such networks may include many nodes. Each device 4 may be part of an I/O processing system 5 associated with a host processing system, 6 or 7. Typically, such networks may comprise a common carrier switching node 8, linking individual voice and data user terminals 9, 10 with data proces~ing services provited in the illustrated configuration by proces8ing system 6. Although only one of each type of terminal 9, 10 is shown it should be understood that many such terminals may be connected to any node.
Data processing 8ervices provided to such terminals and their users may include so-called "voice-mail" services (centralized storage and forwarding of voice messages for telephone users) and access to public or private databases (law libraries, patent libraries, etc.). In the presently contemplated environment, link 3 comprises a high speed Tl or T3 digital signal communication line sustaining multiple time division channels. Although not required for effective use of present devices 4, the network may be structured in ~, ., ~C9-90-001 21 Z0~491~

conformance with ISDN requirements, and the channels of link 3 may be allocated dynamically to digitized voice and data signal traffic throughout.
In such networks, signalling speeds could reach rates of 4.096 Mbits (megabits) per second full duplex on T-l lines, and considerably higher rates on T-3 lines.
Accordingly, a data link control device suitable for serving such lines should be able to operate at speeds in excess of 5 Mbits per second full duplex. The present IDLC device architecture, as implemented in state of the art 1 Micron CMOS technology, is capable of supporting highest full duplex rates presently contemplated for any fully occupied T-l or T-3 line within a single LSI chip structure.
A comparable prior art device -- refer to column 6 in patent 4,493,051 cited above -- has a maximum signal rate of 350,0~0 received or transmitted bits per second (suggesting half duplex) and could not as disclosed service a full T-l line or accommodate mixed voice and data channels. Thus, such device~ would not be suited for ISDN applications in particular, or even higher speed data only applications, and hence the need for devices of the present form.

3. SYSTEM OVERVIEW

Refesring to Fig. 2, sub~ect IDLC device 20 generally forms all or part of a communications controller system 21 interfacing between line control circuits 22 and a host data proce8sing system 23. The expression "all or part" as ~ust used refers to applications discussed below; which either permit packaging of all elements of the controller system within the device chip or require separate packaging of one of the local RAM memories used in the system. The line control circuits operate at the physical signalling level of respective network lines (also termed level 1 or abbreviated Ll) 8uch as 24 (typically, as mentioned, time multiplexed T-l or T-3 line9) corresponding to link 3 shown in Figure 1.
Controller system 21 generally include~ a local RAM
memory 25 (called "time 9wap" RAM or TSR) which is used to store lnformation immediately accessible to the IDLC device for state swapping purposes described later. As mentioned above, the IDLC device can be implemented in a single LSI

~C9-90-001 22 20349~
chip structure using conventional 1 micron CMOS technology.
Depending upon intended usage (number of channels to be served, range of service provided in each channel, etc.) the device may be implemented in two different chip forms; one in which TSR 25 is included within the chip structure and one in which it is not.
In the preferred embGdiment to be described, the IDLC
and Ll circuits are connected at a "Burst Time Division Multiplex" (BTDM) interface (IF) 27 which is paced by signals originating from the Ll circuits. Such signals are arranged to ensure that the average signal transfer rate between the IDLC and Ll circuits relative to any time division channel on line 24 is slightly higher than the average signal transfer rate in the respective channel, so that under normal operating conditions signalling processes between the line channels and systems 21, 23 can not overrun in reception from the line or underrun in transmission to the line, regardless of any slippage or drift between the internal clock of circuits 22 and the clocks at other network nodes. This action, termed "positive slip" operation herein, and its implementation, are fully described in the above cross-referenced application entitled "Burst Time Division Multiplex Interface For Integrated Data Link Controller". Accordingly, attributes and operations of IF 27 are discussed here only in general terms.
The host system may include both an I/O processing subsystem 28 and a main processing subsystem 29 as shown, thereby providing further autonomy between processing activities associated with controlling network usage and activities associated with information processing generally.
Subsystem 28 may include both an I/O processing unit (IOP) and a local RAM memory 31, and main subsy~tem Z9 similarly may include a central processing unit (CPU) 32 and main RAM memory 33. Subsystems 28 and 29 are linked by a system bus 34, capable of connection to other subsystems.
Subsystem 29 and the IDLC 20 are linked by a an IOP
subsy~tem bus 35, capable of connecting with plural IDLC
tevices.
As indicated later in this description, the IDLC
contains an autonomous logical element for Direct Memory Access (DMAC) which in the illustrated configuration ,.

.
. , ~

BC9-90-001 23 2 0 3r~9 provides access to RAM 31 in a direct access mode. As noted further, some system applications will not require a separate I/O subsystem, and in such configurations the functions of IOP system 28 and host system 29 would in essence be combined into a single system entity appearing at the interface to bus 35. In that situation, the DMA control element of the IDLC would operate to control access to main memory 33.
In operation, at system start-up CPU 32 initiates ; subsystem 28, controller 21 and Ll circuits 22; the latter through control path 26. The Ll circuits scan line 24 for a repetitive frame pattern and, upon detecting such, establishes internal clocking synchronism to bit, byte, channel and frame time division slots on line 24, both inbound and outbound.
J Operating in a differently structured time division frame at the BTDM, circuits 22 pass signals received from inbound channel time slots to IDLC 20 for further handling.
The IDLC extracts and evaluates destination address information (ignoring signals whose destination is other than that of the local node), strips protocol and link specific information such as frame delimiters from channel and frame slots as appropriate (channels containing voice signals will be in "clear" form without delimiters), check~
parity and passes the remaining information to system 23 for further processing. Control data messages in the incoming stream may call for a response, and in such instances, information for the appropriate response is prepared in system 23 and passed to the IDLC. The IDLC adds source and de8tination addre89e9, frame delimiting 8ignals and parity 8ignals and passes the information along to circuits 22 for tran8mittal to line 24. Via series of such bid~rected messages, duplex connections are established between the local node and remote nodes, in the time channels on line 24, and signals representing data and/or digitizet audio information (e.g. voice) are exchanged over such connections.
It 8hould be noted that within the IDLC processing relative to data transfers at IF 27 is essentially synchrGnous (although slightly phase displaced relative) to the timing of channel slots on llne 24, whereas processing 203~911 relative to transfers of signals over bus 35 is essentially asynchronous in relation to channel timing on line 24.

4. ARCHITECTURE OF IDLC DEVICE

Figure 3, a block diagram of the logical organization of sub~ect IDLC device, illustrates positioning of the device between IOP bus 35 and IF 27 previously discussed, and division of the device circuitry into synchronous and asynchronous sections, 50 and 51 respectively. This sectioning is of particular interest presently. Also shown are principal logical partitions in each section, each partition understood to contain one or more autonomous elements to be shown and described later. Section 50 operates in synchronism with appearances of channel times slots at IF 27 to perform operations relative to re~pective communication channels. Operations in section 51 relative to any channel are performed in asynchronous relation to respective time slot appearances at IF 27. RAM (random access memory) units 52 and 53 are accessible to partitions in both sections, whereas RAM unit 54 is accessible only to partitions in the asynchronous section. The synchronous section contains logical partitions 60-64, and the asynchronous section contains partitions 65-67.
All of the partitions and RAM units may be contained within a single LSI chip envelope as previously noted, but for certain applications discussed later it may be desired to provide TS RAM unit 53 in a separate module located close to the IDLC chip on a common card or board. The RAM units have predetermined access characteristics, capacities, address allocations and functional usages described later.
Partitions 60, 62, 65 and 66 form a pipelined logical processing chain relative to communication data received from IF 27 ("receive" data) in time division channels, said chain 8panning sectlon8 50 and 51. Partitions 61, 62, 65 and 66 form a similar pipelined chain relative to data being transmitted in channels at IF 27 ("transmit data").
Partition 64 forms a logical chain for collecting statu8 information throughout the IDLC and Ll circuits (device status, Ll status, channel status, etc.), and cooperates :, with partition 67 to present such information to the ; IOP/host system via interruption of the latter.
Partition 67 serves as a "slave" of the host system to provide the latter with bidirectional access to IDLC
memories 52-54, whereby the host system may access said memories for loading information to control operations of the IDLC and for retrieving status information collected by partition 64. A feature of this arrangement is that the separate path through partition 67 reduces the possible extent of interference between operations conducted via that path and in-line communication processes conducted via partitions 65 and 66.
Autonomous elements in each partition comprise registers and special purpose discrete logic circuits (as distinct from Program Logic Arrays, microprocessors, etc.), most of which are implemented presently as finite state machines. The term "autonomous" as used here is intended to denote a degree of functional autonomy between elements in each of the pipelined processing chains mentioned above (for receive data, transmit data and status data) such that performance of a function by any element in a chain, relative to any network channel, is not critically time dependent on respective slot durations at IF 27 and less time dependent on activities of any other element in the same chain than it would otherwise be if implemented without such autonomy.
Resource manager element 63 (abbreviated RSM) operates in response to signal~ received from the Ll circuits at IF
27 indicating channel time slot transitions operates to direct status swapping operations between TSR 53 and other partitions in synchronous section 50; including partitions 60-62 and 64. These transfers are bidirected, so that j relative to a channel whose slot is ending partition states are saved (for continuation of respective channel processes ; in respective elements when the same channel slot reappears ; at 27), and relative to an active channel whose slot is beginnlng partition states are set to provide continued process service relative to that channel. As so initiated, each partition'8 finite state machine(s) sequence for the duration of the new slot to perform the L2 processes ;

:
. .

~C9-90-001 26 203~91~

assigned to the respective partition relative to the current state of that channel.
Receive partition 60 is responsible for reception of data (and/or voice) signals from IF 27 in whatever protocol is currently active on each network data channel (SDLC, HDLC, LAP-B, LAP-D, etc.). Voice channels are "clear" (no protocol specific delimiters, etc.). Relative to each data channel, partition 60 is responsible for stripping protocol-specific information (e.g. destuffing HDLC stuffed bits), recognizing addresses, detecting protocol-specific control functions (e.g. abort/idle indications in HDLC, frame boundary indications, etc.), and forming interrupt status indications for receive events (e.g. CRC error, FIFO
buffer and IOP buffer overflow conditions, frame endings, etc.).
Transmit partition 61 handles bit serial transfer of data and control bits to IF 27, in whatever protocol is currently active on each channel (SDLC, LAP-B, LAP-D, etc.;
voice i8 sent in the clear). It also generates protocol-specific information to be sent with the data (e.g.
HDLC stuffing bits, abort/idle indications in HDLC, frame delimiters, etc.), and forms interrupt status indications for transmit events (e.g. FIFO buffer underruns, end of control block chain for transmission, etc.).
FIFO management partition 62 interfaces between FIFO
RAM 52 (later abbreviated as FIFOR) and the receive and transmit partitions to transfer receive and transmit data between per channel queues in the RAM and these partitions on a FIFO (first in first out) basis, and to manage the 'utilization of such queues. Partition 62 monitors the state of occupancy of each channel queue in RAM 52, and ~upplies ,request8 to DMA (Direct Memory Acces9) partition 65 in the iasynchronous section which evoke actions through master I/O
(MIO) partition 66 causing data to be transferred between re8pective queues and host sy8tem memories via bus 35. The reque8t8 from partition 62 to partition 65 are actually latched by a 8eparate DMA Request Queue (DMARQ) partition not 8hown in Fig. 3, and handled by the latter on an asynchronous ba8i8.
,Thus, receive data queues are emptied on a FIFO basi8 ibefore they overflow as a result of activity at IF 27, and ~C9-90-001 27 2034911 transmit data queues are replenished with new data before they underflow relative to IF 27.
Interrupt (INT) partition 64, having circuit portions operating in both synchronous section 50 and asynchronous section 51, operates to: receives signals indicating reportable hardware and channel process events and conditions from all other IDLC elements and the Ll circuits;
pass associated flagging requests to slave I/O (SIO) partition 67; and collect status information relative to such events and conditions for asynchronous retrieval by the IOP/Host system. Such events and conditions include hardware errors, channel errors, channel processing events (frame boundary transitions, end of transmission, etc.). Relative to such requests, partition 67 engages in interrupt communication with the host system via bus 35 for transferring the related status information.
As previously indicated, each autonomous element (and/or sub-element) in each partition includes logic which is generally implemented as one or more "finite state machines". These sequence through successions of states for performing respectively assigned functions relative to each active network channel. As any channel on the network link is configured for operation under a selected voice or data communication protocol, a set of state variable parameters i9 inserted into TSR 53 from host interface 35 (via SIO
partition 67) to set up initial states for the autonomous elements in partitions 60-64 relative to that configuration.
During subsequent appearances of the respective channel time 81Ot at IF 27, state swaps between RAM 53 and autonomous elements in partitions 60-64 cause said elements to operate intermittently to perform assigned logical processes relative to communication data received and sent ln that slot.

5. OPERATIONS - GENERAL
'' ,Referring to Figures 3 and 4, at power-up signals !presented at host interface 35 force the IDLC and Ll circuits to reset modes. In this mode, logical elements in all IDLC partitions are cleared of non-relevant status and set to idle states. Then Ll and IDLC circuits are ~C9-90-001 28 203491 initialized, again by host signals presented at interface 35. Such information includes critical initial parameters for channel processing, information for controlling activation of channels and information for controlling basic operations of DMA partition 65. The initializing information for the Ll circuits is transferred via line 69 to not-shown registers in the Ll section. Initializing information for asynchronous section 51 of the IDLC is passed via bus 35, MI0 66 and DMA partition 65 to RAM's 52 and 54. Initializing information for synchronous section 50 is passed to RAM 53 via bus 35 and SI0 67.
After initialization, the IDLC is set to an active mode 7 and processing begins for activating network channel functions. Channels are activated individually. In addition to loading of initial critical parameters for each channel during IDLC initialization, before a channel can be activated control parameters must be entered into RAM's 52-54 and certain registers discussed later for conditioning all processing partitions to perform functions required for the re8pective channel types. Upon activation, signals indicating appearances of the respective channel time slot are sent to the IDLC from Ll via BTDM IF 27, and processing relative to the channel begins. During such processing full duplex links are established in the network channels, between the local node and remote nodes, information is transferred over such links, and status information relative to 8uch channels is collected in RAM 53 and made available to the host system via SI0 67.
Referring to Figure 4, state swapping processes conducted by RSM, relative to communication channels as80ciated with time slots at the BTDM interface (in thi8 figure, consecutive slots N and N~l), involve transfers of four types of variables; transmit-specific, receive-specific, interrupt-specific and global. State swaps (saving of element processing states relative to a channel as~ociated with a time slot now enting, and reloading of previously saved states relative to a channel whose time slot is now beginning) are conducted only relative to active channels. Global variables are common to transmit, receive and interrupt processing. A small portion of one global variable, indicating the channel type, is prefetched ~C9-90-001 29 2~13~31~

relative to both active and inactive channels in order to distinguish such.
Transmit-specific variables are transferred relative to elements in transmit pipeline partitions 61 and 62. Receive-specific variables are transferred relative to elements in receive pipeline partitions 60 and 62 (as will be seen later, partition 62 comprises separate sub-partitions 62R
and 62T for respectively conducting receive and transmit processing operations). Interrupt-specific variables are transferred relative to INT partition 64. Global variables are transferred relative to resource manager (RSM) partition 63.
Global variables, defining channel-specific configuration and protocol associations, are transferred relative to configuration registers CCR (Configuration Control Register) and HPCR in RSM 63 in synchronism with channel processing (see intermediate and detailed descriptions of RSM which follow). While registered in RSM, these variables are effectively shared by all partitions.
- Other transient variables relating to handling of Jf interruption event status are held in registers CEISR
(Channel Events Interrupt Status Register) in INT, EOPISR
(End Of Process Interrupt Status Register) in INT, IHEISR
(IDLC Hardware Error Interrupt Event Status Register) in INT, and VHR (Vector Holding Register) in SIO. Contents of CEISR and EOPISR are swapped relative to TSR in synchronism with channel time slot appearances. The contents of IHEISR
and VHR are held static until retrieved by the IOP.
Other global variables defining HyperChannel a~ociations are held in register HCR (HyperChannel Configuration Register) in SIO on a static basis (not synchronously saved and reloaded; see later description of HyperChannels). Other variables defining device configuration parameters not specific to any channel are held static in regi8ter ICR (IDLC Configuration Regi8ter) in SIO.
Transfer8 of receive, transmit and interrupt variable8 are true saving and reloading "9waps", but the transfers of channel-~pecific global variables relative to registers CCR
and HPCR in RSM 63 are one way only (although these variables may differ from channel to channel, they do not ~C9~90-001 30 203~9~
change as a function of IDLC processing relative to any channel and therefore need not be saved as channel slots conclude).
The state swap actions (S) are staggered in phase within each time slot period; global and interrupt first, transmit-specific next and receive-specific last. While the global variables are loading, the partitions in both pipelines are halted (H). It is understood of course that these actions are omitted during time slots associated with inactive channels.
As a new channel time slot N~l begins (BOS/N~l), RSM
9ignals the synchronous partitions in the transmit pipeline to prepare for transmit-specific swapping. If channels N and N+l are both active, elements in the transmit pipeline whose state machines are in stable states from which they can resume on the next appearance of channel N time slot immediately ~ignal "DONE" conditions to RSM and have their transmit process states swapped relative to respective state storage areas in TS RAM (if N is inactive no state information will be transferred to TS RAM, and if N~l is inactive no state information will be loaded from TS RAM).
The ~tate information saved relative to channel N (assuming it is active) is sufficient to enable respective elements to resume processing for that channel without 1099 of continuity when the respective time slot recurs. Similar actions occur at the phase of receive-specific swapping.
Elements not in stable states, when processing relative to an active channel N, and signalled by RSM to prepare for state swapping, sequence to their next stable states before a~serting DONE 9tatus and undergoing state swap9. As will be ~hown later, the staggering of the 9wapping actions relative to transmit and receive processe9, and the subdivi9ion of same into directional specific and global stages, coordinated with 8pecific present phasing of signal tran~fers to and from IF 27, provide highly efficient usage of RAM 53 and the transmit and receive partitions (without which larger RAM and more circuitry in the pipeline partitions would be needed).

6. _ _DLC ORGANIZATION - INTERMEDIATE

~cg- go-ool 31 203~91~

This section and following subsections provide intermediate level descriptions of the IDLC logical organization and operations, with particular reference to Figure 5.

6.1 ABBREVIATIONS

This section provides an alphabetically ordered listing of abbreviations (Abbr.) of element and register names used in Figure 5, with explanations of functions performed by each named item. Items marked with asterisk (*) are common to all channels.

CCR CHANNEL CONFIGURATION REGISTER/channelized (replicated for each channel), this is used to select the channel protocol (SDLC, LapB, LapD, clear/voice, other) and indicate the channel type (inactive, B/D, HO number 1-5, Hl, Hll, H12, etc.) ', CEISR Channelized Error Interrupt Status Register/stores channel error status information for transfer to host DMAC DMA control element/cooperates with MIO to transfer data between FIFOR and host bus 35;
includes registers for storing data in transit ' between MIO and FIFOR

DMAR DMA RAM/stores per-channel control information for DMAC

DMARQ DMA Request Queue/receives and queues requests for per channel data transfer action from RFM and TFM

EOPISR End Of Process Interrupt Status Register/buffers end of process status information for transfer to SIO

FIFOR FIFO RAM/stores per-channel data in transit between FIFO managers (transmit and receive) and DMAC

~C9-90-001 32 2034911 HCR Hyperchannel Configuration Register/defines ~ hyperchannel configurations - HPCR Protocol Configuration Register/together with part of CCR customizes channels for HDLC type protocols ., .
. I_RQ Interrupt Request/path for Ll interrupt requests *

ICR IDLC Configuration Register/common register for placing chip elements in various modes: normal operation, reset, forced error normal, forced error reset, and quiet IHEISR IDLC Hardware Error Interrupt Register/buffers error status relative to IDLC hardware error conditions affecting all channels Ll Level l/refers to level 1 circuits 22 (see Fig. 2) MIO Master I-O/IDLC element interfacing between host IOP bus and IDLC DMAC element .~ , MUX Multiplexor/circuits linking IOP bus to MIO and SIO
~, RDCRl-4 Receive DMA Configuration Registers (four in DMAC
. and two in RFM, with per channel backups in FIFOR
~' and DMAR) define channel configuration setups of DMAC and RFM for DMA transfers of received data;
parenthetic indications "(R)" and "(U)" in Fig. 5 respectively characterize registers used in read . only and read/write (updatable) modes RFM Receive FIFO Manager/IDLC element for managing transfers of receive data between RVl and FIFO
RAM, and initiating action by DMAC, relative to data ~tored in FIFO RAM, via requests placed in DMARQ

~ ~C9-90-001 33 Z0349~

RFM_TSl,2 Receive FIFO Manager Time Swap Words 1 and 2/registers in RFM holding state information which must be saved on time swap RLl Receive Layer l/IDLC element for transferring receive data between BTDM interface 27 (see Fig.
2) and RV

RLl_TSl,2 Receive Layer 1 Time Swap Words/registers in RLl holding state information which must be saved on time swap RSM Resource Manager/IDLC partition controlling time swapping between TSR and receive, transmit and interrupt partitions ", RV Receive Validation/IDLC element performing layer 2 processing of receive data including stripping of protocol specific information, address examination, error checking, etc.
;~
.~. RV_TSl Receive Validation Time Swap Word/RV state information to save on time swap TDCR Transmit DMA Configuration Register/four registers ~ per channel in DMAC and two per channel in TFM
:- which define configuration setup of DMAC and TFM
relative to DMA fetching of transmit data in respective channels; parenthetic indications "(R)"
and "(U)" in Fig. 5 respectively characterize registers used in read only and read/write ,. (updatable) modes TFM Transmit FIFO Manager/IDLC element for managing transfers of transmit data between FIFOR and TVl, and initiating DMAC action to repleni~h transmit queue in FIFOR, via requests placed in DMARQ

TFM_TSl,2 Transmit FIFO Manager Time Swap Words 1 and 2/TFM
state information which must be saved on time swap BC9-90-001 34 203491~.

TLl Transmit Layer l/IDLC element for transferring transmit data between TV and BTDM interface 27 TLl_TSl,2 Transmit Layer 1 Time Swap Words/TLl state information which must be saved on time swap TSR Time Swap RAM/RA~I external but locally accessible to the IDLC (see RAM 53, Fig. 3) TV Transmit Validation/IDLC element performing layer - 2 logical processing of transmit data, including insertion of protocol specific information, error check references, etc. in data channels .
, TV_TSl Transmit Validation Time Swap Word/TV state information to save on time swap , .
VHR Vector Holding Register/common register for chip and channel interrupt status vectors 6.2 TRANSMIT/RECEIVE DATA PATHS

Wherever possible in Fig. 5, numbers of partitions shown previously in Fig. 3 are retained, and elements in those partitions are identified by like numbers with one or more letters (e.g. 61L).
Fig. 5 illustrates ma~or information processing paths in and through the IDLC. These consist of paths for handling transmit data (data received from the host at IF 35 and transmitted in channel time slots at IF 27 after intermediate processing in IDLC) and receive data (data received at IF 27 and proce8sed within the IDLC for transfer to host interface 35), paths for transferring initializing and control information from the host system to the IDLC
RAM'8, paths for collection of information reportable to the ho8t via interruption (data indicating events and conditions and status data specific to same), paths for conducting state swaps (between IDLC elements and TSR 53), and host acce~s paths to IDLC RAM's (through which stored information, for instance channel event status, is BC9-90-001 35 203~91~

accessible to the host system for monitoring). This section discusses the transmit and receive data paths.

6.2.1 TRANSMIT DATA PATH

Data to be transmitted in channel time slots at IF 27 ("transmit data") enters the IDLC via bus 35, MUX circuits 80, and MIO partition 66. MUX 80 serves as a switch for routing signals over bus 35 between host system memory and MIO 66 and between host system processing entities and SIO
67. The source data for transmit data is retrieved from host memory by a DMA (direct memory access) process controlled by DMAC element 65C in response to DCB (Data Control Block) command vectors prepared in DMAR by the host system.
A feature of the present invention is that in response to chaining indications in ~uch DCB's the DMAC acts to retrieve additional DCB's from IOP/host memory; thereby reducing IOP/host processing activities in respect to such additional DCB's. This allows the sub~ect device to retrieve both additional DCB's and the transmit data associated with those DCB' 8 from scattered areas in IOP/host memory. Other benefits and advantages will be explained below.
After passing through MIO, transmit source data is buffered in DMAC, and deposited in per channel queue spaces in FIFOR 52. The process for fetching such data from host memory is invoked relative to individual channels in response to requests transferred from Transmit FIFO Manager (TFM) element 62T to DMA Request Queue (DMARQ) element 65Q
as TFM acts to empty respective channel queues in FIFOR.
TFM removes transmit data from the per channel queue 8pace8 in FIFOR, on a first in fir8t out basis, and passe8 it to Transmit Validation (TV) element 61T which performs certain validation level processes on the data. Data resulting from processing in 61T is passed to element 61L
(TLl) which perform8 level 1 proces8ing and transfers resulting data bit serially to IF 27 in response to specific requests pre8ented at IF 27 by the Ll circuits (Z2, Fig. 3).
The processing in TV 61V for data channels includes insertion of protocol-specific framing information. This, together with the above-mentioned DCB chaining feature in DMAC, permits the IDLC to transfer large blocks of data from ~C9-90-001 36 Zo3~9~1 scattered spaces in host memory, and introduce diversely formed and spaced protocol framing information into such data in accordance with individual channel configurations.
As a result, extensive processing responsibility is offloaded from the IOP and host systems.
Note in reference to above-mentioned elements 61V, 61L, 62T, 65C and 65Q, that respective partitions shown at 61, 62 and 65 in Fig. 3 each contain plural elements, and in certain instances are sub-partitioned. Transmit partition 61 contains elements 61T and 61L performing different processing functions on transmit data. FIFO partition 62 is actually sub-partitioned into transmit FIFO and receive FIFO
partitions, 62T (TFM) and 62R (RFM) respectively, for separately managing FIFO queueing of transmit data and receive data. DMA partition 65 contains functionally autonomous elements 65C (DMAC), for overall DMA control, and 65Q (DMAQ) for receiving per channel requests from partitions 62T and 62R and queueing such requests relative to DMAC.
;~ In respect to transmit data, requests transferred by TFM to 65Q, and presented by the latter to 65C, indicate depletion of respective channel data queues. In response to ~uch request9, and asynchronous to appearances of respective channel time slots at IF 27, elements 65C and MIO operate to gain access to IOP memory via bus 35 (or host system memory depending on what i8 connected to bus 35) and retrieve therefrom transmit data which is transferred to respective channel queues in FIFOR.
These operations of DMAC are controlled via registers TDCR 1-4 in DMAC, the latter loaded from per channel TDCR
1-2 spaces in FIFOR 52 and per channel TDCR 3-4 spaces in DMAR 54. During DMAC action relative to any channel~
registers TDCRl, TDCR3 and TDCR4 are loaded with respective channel control information needed to acces9 external memory, retrieve transmit data (in sets of up to 4 bytes), and po~ition such bytes in FIFOR. Register TDCR2 is a 4 byte buffer in which transmit data is held en route to FIFOR.
Registers TDCRl, TDCR3 and TDCR4 are loaded when a not-shown "transmit DMA state machine" in DMAC (to be shown and described later) is initialized relative to any channel queue requiring service.

~C9-90-001 37 ~03491~

The processes for transferring transmit data, from IOP/host memory to FIFOR, are carried out in asynchronous relation to appearances in time of respective channel time slots at (BTDM) interface (IF) 27. However, the handling of transmit data by elements which 62T, 61V and 61L is carried out synchronous with said slot appearances, and states of those elements relative to transmit processes in active channels are cyclically swapped in synchronism with respective slot appearances. As noted previously, the state swaps are between those elements and TSR 53 under direction of RSM 63.
Element 61V processes transmit data in accordance with channel requirements and passes it to element 61L for eventual serialization and transfer to interface 27.
Although transfers of transmit data at 27 are bit serial, as much as a full byte of data may be transferred during any channel time slot. Each bit transfer is effected by a request-acknowledge handshake between level 1 circuits and TLl, and all transfers are carried out during a small window of time within the slot for purposes explained later. During that window, in the time slot of any active channel, the Ll circuits send a variable number of requests for bit transfers, from 1 to 8, and TLl responds by presenting transmit data bits with acknowledging signals.
Relative to active data channels, second layer (validation level) processing by 61V includes insertion of protocol specific framing information, and insertion of address and check reference information (e.g. CRC check bits). As noted previously, digitized voice signals are transferred in the clear; not requiring explicit destination addresses inasmuch as their destinations are fixed when re9pective channel links are established).
Data passing through elements 61V and 61L is handled in parallel and simultaneously, in a pipelined manner, albeit in synchronism with appearances of respective channel time slots at interface 27. Note, in regard to pipelining, that although states of elements 61V and 61L relative to any channel are swapped in synchronism with transition~ of respective channel time slots at IF 27, transmit data i9 passed to IF 27 bit serially and only in response to per bit requests presented by the Ll circuits 22 (Fig. 2) to element ~C9-90-001 38 203491~
6lL (within elements 6lL and 61V transmit data is handled in bit parallel sets). Thus, it will be understood that the processing required in these elements to transfer a byte or other unit of data to IF 27 may span one or repetitions of respective channel time slots at 27, but due in part to the pipelining just mentioned (and in part to the queued handling in asynchronous section 51) such data is presented in "assembly line" fashion at IF 27 at a rate ordinarily commensurate with the rated signal speed in the channel.

6.2.2 RECEIVE DATA PATH

Receive data is received bit serially from IF 27 at element 60L (RLl), deserialized into bytes with some additional processing in that element (including processing to distinguish destination addresses and discard data not intended for the local node), and handed over to validation level element 60V (RV) for "second level" processing. That processing includes stripping protocol-specific framing information from data received in data channels, CRC
checking of such data, and transfer of resulting receive data to RFM (Receive FIFO Management) element 62R for loading into receive data queue spaces in FIFOR 52 allocated to respective channels. States of fullness of receive data queues in RAM 52 are monitored by element 62R, and when action is needed requests are presented to DMARQ 65Q causing DMAC 65C to operate to forward queued received data from FIFOR to per channel "circular buffers" in host IOP memory on a first in first out basis.
In IDLC section 50, states of elements 60L, 60V and 62R
are "swapped" relative to network channels in synchronism with appearance9 of re9pective channel time slots at IF 27, and processing of receive data relative to any channel is conducted in synchronism with appearances of respective time ~lots. The state ~wapping proce9se5, between respective elements and TSR 53 are directed by resource managing element (RSM) 63. In I~LC section 51 all operations relative to receive data are conducted in asynchronous relation to appearances of respective channel time slots.
As in the tran~mit path, the receive element shown at 60 in Fig. 3 actually comprises autonomous sub-elements 60L

~C9-90-001 39 Z03491~

and 60V which respectively provide first and second layer handling of data received at IF 27. As in transmission, states of these elements are swapped in synchronism with appearances of channel time slots at IF 27, and therefore processing of data in any channel by these elements invariably occurs in synchronism with appearances of respective time slots (although processing required for transferral of a byte of receive data through any of these elements may span several frames of time slot repetitions, the per-channel buffering allotted to each channel, in each element and in TSR 53, permits pipelined processing of such data to be conducted in a manner such that the ultimate rate of transfer of such data through these elements is commensurate with the rate of transmission across IF 27, whereby under normal circumstances overruns will not occur).
Element 60L (RLl) conducts first layer processing operations on receive data (deserialization, removal of HDLC
opening and closing flags, etc.), and element 60RV (RV) conducts second layer (validation) processing on datà
forwarded to it from 60L (addres~ recognition, stripping of protocol specific information, CRC checking, etc.). As data becomes available for forwarding from element 60RV, requests presented by that element cause RFM 62R to transfer such data to respective channel queues in FIFOR 52. ~8 any such channel queue reaches a predetermined state of fullness (which is well before it can overflow), RFM 62R requests action by DMAC 65C, via DMARQ 65Q, which result eventually in action taken by DMAC to empty the respective queue (in first in first out order).
;

6.3 INTERRUPT PATHS

-Interrupt managing element (INT) 64 is responsible for collection and locallzed storage of status information !(hardware 8tatus in IDLC and Ll circuits, and channel proce8s ~tatu8) required to be reported to the ho8t 8ystem.
Slave I/O (SIO) element 67 interfaces to the host system via bus 35, for providing interrupt request indications to the ho5t when status information is available locally, and also for providing direct access paths 89 from the host system to RAM's 52-54, and registers in both INT and SIO, by means of ~C9-90-001 40 203~911 which the host can directly access locally stored status information.
Paths 89 are bidirected so that the host system can also directly program operations of the IDLC, by setting initial element state and control information into RAM's 52-54, (see discussion of paths 89 under Host Control Paths below). INT 64 has connections to all other IDLC elements, for receiv ng event flagging signals and associated event status information through path 90 marked "all", and similar paths 91 to Ll circuits 22. Chip select line 92, extending from SIO 67 to Ll circuits 22, prepare~ the Ll circuits for transfer of their status information. Line 69 previously discussed is used to pass initializing information directly from host interface 35 to circuits 22.
Registers ICR, HCR and VHR in SIO 67, and register IHEISR in INT 64 (see definitions above), are common to the entire IDLC chip/device. Outputs of ICR and HCR can be broadcast through element 64 and path 90 throughout the IDLC
to establish operating conditions; ICR to establish idle operating mode throughout the chip, and HCR for establishing hyperchannel operating configurations (see cross referenced co-pending application pertaining to Hyperchannels). VHR
holds an interrupt vector, associated with reportage of chip and channel status, collected throughout IDLC via path 64, 90. Register IHEISR in INT 64 serves as a focal point for collection of hardware error information; throughout the IDLC via path 90 and from Ll circuits via path 91.
The other two registers in INT 64, CEISR and EOPISR, are common to all channels but are essentially "channelized" (replicated for each channel on the network).
Within the space allotted to each channel in TSR 53 there are "images" of these registers. During the time slot synchronous state swapping process previously discussed, RSM
63 loads register CEISR in INT (with CEISR image information fetched from TSR) 80 that its contents correspond synchronously with those of the channel whose time 810t is currently appearing at IF 27. Register EOPISR in INT i8 a focal point for collection of end of process channel status information and if its contents are altered during a time slot period the information is transferred by RSM into one of 16 EOPISR buffers in the TSR space allotted to the ~C9-90-001 41 2 0 3i~9 respective channel. The buffer selected is one designated by pointer information in register CEISR during the time slot.
See also discussions of Time Swap Paths and TSR below. The contents of the 16 EOPISR buffers associated with any channel form a 16 deep status queue relative to the respective channel.
Register CEISR provides a focal point for transfer of per channel error interrupt status information to the host, and register EOPISR forms a focal point for presentation of end of process status information per channel to the host.
Such status information is distinct from and is needed to supplement the more general information passed through VHR.
End of process status information per channel includes end of frame status information per channel which may recur at the rate of time slot frames (hence the need for a 16 deep queue for this type of information).
The logical configuration of INT 64 permits it to determine relative time urgency of pending interrupt contitions/events and to order presentation of associated interrupt requests and status information in accordance with such determination, so that bus 35 and the host system are not pre-emptively used for unimportant event communications.

6.4 STATUS SWAP PATHS

RSM 63 directs time slot synchronous state swapping activities between TSR 53 and the elements which process transmit and receive data, as well as between TSR 53 and status registers in both RSM and INT. Certain of the status register transfers are unidirectional relative to TSR
(read-only or write only) as follows. Registers CCR and HPCR
in RSM hold information which does not change during processing relative to individual channels (backing information in TSR is loaded from the IOP/host system when the channels are configured and does not change thereafter until the channel is reconfigured); hence, respective transfers from TSR are read-only. Transfers from register EOPISR in INT to TSR are write only. This register holds status information representing events occurring during channel processing, and its contents are placed into one of 16 backing buffer locations in TSR allotted to the ~C9-90-001 42 Z03491~

respective channel in accordance with pointer information in regi~ter CEISR. The handling of the pointers and the status information in the backing locations, and the nature of the information fields stored in ~OPISR, are such that loading of that register from TSR is never required.
J' Relative to all of the receive and transmit elements (60L, 60V, 62R, 62T. 61V, 61L) within the synchronous section, the state swapping transfers are bidirectional. The state of each element relative to the channel whose time slot is ending is saved in a pre-allocated space in TSR, and -~ the state of the same element relative to the channel whose time slot is beginning is initiated from previously saved information in a pre-allocated space in TSR (see Fig. 6).
RSM receives advance indications of frame and channel time slot transitions, from IF 27 via line 94, enabling it to prepare for the state swapping activities with timing , tolerance that allows for elements whose states are to be swapped to sequence to stable states assuring unambiguous continuity of processing in the next appearance of the currently ending time slot. Referring to Fig. 4, the preparation consists of prefetching (P) CCR bits defining the next channel type.
Thereafter, state variables associated with transmission processing in previous and next channels are swapped, followed by loading of global variables co~non to transmit and receive processing in the next channel (into registers CCR and HPCR in RSM), followed by swapping of receive state variables associated with previous and next channels. The loading of the global variables in effect reloads the channel type field loaded during prefetching;
but since this field does not change during internal IDLC
i' processing the reloading does not change it. The state 9wapping exchange9 relative to tran9mit and receive element9 are conducted through paths indicated at 95-97.
Relative to INT, collection of channel statu9 information occurs only during respective channel time - slots. The status information is buffered in registers CEISR
and EOPISR and 9aved in TSR during the state swapping pha9e of INT. Interrupt indications are transferred to SIO and presented by the latter at bus interface 35. Later, and asynchronous to channel time 910t9, saved information i9 . .
' .

~C9-90-001 43 203491 ; collected by the IOP/host system through direct access to TSR via SIO and path 89.

6.5 HOST PROGRAM CONTROL INTERFACE

Paths 89 from SIO to INT and RAM's 52-54 are bidirectional. In the direction from IDLC to interface 35, these paths allow the IOP/host system to collect status information from TSR and registers in SIO and INT
(specifically, register VHR in SIO and register IHEISR in INT). In the opposite direction (called the host control interface), these paths allow the IOP/host system to set initial state and control information into RAM's 52-54 and into registers within the IDLC logical elements.
Thus, for instance, the host/IOP complex can insert state information into TSR for establishing initial operating states in elements within the synchronous part of the IDLC relative to selected channels. Advantage of having this separate path is that it does not interfere with the normal communication paths at the MIO interface, and it allows for each channel to be activated and deactivated independently o all other channels. Also, the host/IOP can act through this same path to set individual element register8 for configuring or controlling IDLC operations; in certain instances, dynamically and with minimal interference to communication processes. It can, for instance, modify registers ICR and HCR in SIO for configuring IDLC to certain operating modes (e.g. reset), and it can modify registers such as HPCR in RSM for dynamically informing elements such as INT of actions taken relative to certain interrupt status queue~ in TSR (see description of interrupt handling operatlon8 ln 8ectlon 6.6 and detailed descriptions of RSM
and INT).
; In re8pect to the above-mentioned use of the path 89 for loading element 8tate information into TSR, relative to ~elected channel8, refer to Figure 6. Note that TSR 53 contains a block of spaces dedicated to each channel, and within the block allocated to each channel there are a number of word 8paces reserved for "time 9wap" words "ABC--_TSON"; where ABC represents synchronous processing elements (e.g. RV, TV, etc.), TS represents "time swap word"
:' . .

~C9-90-001 44 203491~
and N is O or 1. Note further that each channel block contains spaces reserved for control information (CCR, HPCR) for customizing the configuration and communication protocol in the respective channel) and status information (CEISR, EOPISR) for indicating events reportable to the host/IOP
system through interrupts.
Referring to Figs. 7 and 8, using path 89 to access FIFOR 52 and DMAR 54, the IOP/host can initialize DMA
control parameters, TDCR and RDCR, which determine the handling of IDLC originated DMA data transfers across interface 35. Included in these parameters are control words which can be used to define data block lengths and byte sequencing (TDCRl and RDCRl), and control words (TDCR3 and TDCR4, RDCR3 and RDCR4) which can be used to define operations of the DMAC partition relative to individual channels.
TDCR3 holds address information defining the space in IOP/host memory from and to which transmit data is to be transferred. TDCR4 holds a DCB command array defining the transmit operation (with potential via chaining indicators to extend operations to additional DCB' 9 accessible via IDLC
DMAC action). RDCR3 and RDCR4 hold address parameters defining boundaries of a circular buffer space in IOP/host memory to which received data is to be transferred.

6.6 OPERATIONS - INTERMEDIATE

In an ISDN Primary Rate environment, the IDLC supports 32 channels with a maximum data rate in each channel of 64,000 bits per second (64 kbps) full duplex, or an aggregate rate in each of 128 kbps. This rate is sufficient to accommodate full duplex transmi9sion of either data or digitized voice in any channel, and for hiBher data rates channels may be variably grouped into hyper-channels.
On power-on reset, the IOPthost system sets all regi~ters in the IDLC and Ll circuits, and all locations in RAM's 52-54 to initial value9, and then enables the IDLC by writing to the ICR (IDLC Configuration Register) register in SIO (~ee discu~8ion of that register below). All of these actions are taken across bus 35, and through SIO. The re8isters in each of the IDLC logical partitions are ' ., '" ' ' .

accessible through not-shown extensions of paths 89. SIO
decodes addresses of individual RAM units and partition registers and passes suitable request signals to the units and partitions. The partitions and RAM units arbitrate these requests along with requests from other partitions, and when ready assert acknowledgement to SIO whereupon the relevant information transfers (from IOP to RAM unit address locations or individual partition registers) are completed.
Then the IOP initializes the Ll logic via path 69 and performs operations through that path to verify that the Ll circuits can successfully transfer data across the network.
At this point, RSM is receiving signals indicating channel time slot transitions from Ll circuits, via BTDM IF
27 and connection 94, and directing state swapping transfers between the other elements in the IDLC synchronous section and TSR. Also, the other elements have been activated and are ready to process data.
After this has been done, individual channels in the IDLC can be activated by writing appropriate values to associated registers (from IOP via SIO). After activation of any channel the IOP enables data transfer in the Ll circuits, causing those circuits to request transmission of data to the channel from the IDLC and forward received data to the IDLC. All data transfers are across the BTDM IF 27 in the respective channel's time slot, and all processing of received and transmitted data in the IDLC synchronous section is conducted only during the respective time slot.
Data transmission is accomplished by retrieval of data from IOP memory, via DMAC operations defined by DCB's stored in the associated channel space in DMAR, transfer of such data to respective channel spaces in FIFOR, further transfer of the data by TPM to TV, and proces8ing of the data in TV
and TLl to produce required formats. The data is handled in byte units by TFM, TV and TLl and pas8ed blt serially across IF 27 in respon8e to individual bit transfer request~ posted by Ll circuits. Up to a byte (8 bits) of data may be transferred during one channel time slot. At the IOP
interface 35, transmit data is transferred in 4-byte unit8, and in FIFOR each channel has a buffer storage space for holding 4 bytes.
, BC9-90-001 46 Z0349~1 Data reception is accomplished by reverse processing of data in RLl and RV, transfer of resulting data to RFM and via the latter to respective channel receive spaces in FIFOR, and forwarding of the data from FIFOR to circular buffer spaces in IOP memory through operation of DMAC in response to control information preset into DMAR. At IF 27 the data is received bit serially, in response to individual requests presented by Ll circuits during the channel time slot. Up to a byte of data may be transferred during a time slot. In RLl, RV and RFM, the data is handled in byte units.
FIFOR holds up to 4 bytes of receive data per channel. At IOP interface 35 , receive data is transferred in 4-byte units.
Relative to transmit data in e.g. HDLC format, TV
generates CRC's for outgoing frames and passes the data to TLl. TLl generates opening and closing flags for each frame, inserts stuffing bits in data as required to sustain transparency (of data in relation to control characters) and passes the data with CRC and flags to IF 27 bit serially.
Relative to receive data in e.g. HDLC format, RLl searches for opening and closing frame flags and discards them, detects stuffed bits in data and discards same, performs octet alignment checking on remaining data, and forwards same to RV. RV performs address recognition and CRC checking functions before forwarding the tata to TFM.
All transfers between DMAC and bus 35 are through MIO.
MIO services transfer requests from DMAC by arbitrating for the bus and sequencing buR control, address and data signals to perform the transfer.
Interrupt requests relative to critical channel proces8 conditions are presented to INT from RSM, RFM, TFM and TLl.
RSM reports TS RAM parity errors to INT. RFM and TFM are focal points for reporting channelized hardware errors (bus errors, FIFO parity errors, etc.) to INT relative to events in respective partitions and in the DMAC partition. RFM also acts as a focal point for interrupt requesting relative to RLl and RV, and TFM acts similarly rèlative to TV. Thus, requests from RFM cover all "reportable" channel process conditions encountered within the receive pipeline (DMAC, RFM, RV, RLl), and requests from TFM and TLl cover all such , .

~C9-90-001 47 ~03~91~

conditions encountered in the transmit pipeline (DMAC, TFM, TV, TLl).
In response to such requests, INT acts during one or more time slots of the respective channel to assemble CEIS
(Channelized Error Interrupt Status) and EOPIS (End Of Proce~s interrupt status) words. The CEIS words describe channel error conditions, while the EOPIS words describe channel communication frame transition events. The CEIS
words also contain addressing information for locating EOPIS
words .
These words are written from INT to TSR by operation of the state swapping mechanism in RSM. In TSR, these status words are saved in spaces dedicated to respective channels;
each EOPIS word being saved in 1 of 16 spaces allotted as a queue to EOPIS parameters. The particular space in the EOPIS
queue to be written at each access is defined by pointer information furnished to RSM by INT. The queue is used in a "circular" manner; the pointer advancing in unit increments to a last space and from that space "wrapping around" to a first space. The pointer information is also stored by INT
in the CEIS status word which is written via RSM to TSR, and i8 thereby available to the IOP for monitoring. The CEIS
word also contains information defining the number of outstanding words in the queue, which is updated by INT as new entries are written to the queue.
Relative to each such status word written to TSR, INT
assembles a vector identifying the associated channel, and sends it along with a request to SIO. SIO stores the vector in register VHR, activates an interrupt signal on bus 35, and, when IOP acknowledges, places the vector on the bus.
Later, IOP decodes the vector, determines which channel is involved, and acts through SIO to retrieve the associated CEIS word. Examining this word, IOP determines if there are outstanding entries in the EOPIS queue. If there are, when IOP i8 ready to deal with those parameters, it acts through SIO to retrieve one or more of the queue entries; providing address information to SIO derived from the pointer information in the previously retrieved CEIS and modifying the CEIS information in TSR to reflect the number of entries remainin8 outstanding in the respective EOPIS queue.

sC9-90-001 48 20349 At such times, the I~P acts further through SIO and program control path 89 to acces~ the HPCR regi~ter in RSM
and alter information in the latter to indicate that the contents of the associated channel's EOPIS queue have changed, and to indicate further the number of outstanding queue entries removed. INT uses this HPCR information to determine if the queue is not empty; i.e. if it needs to generate another interrupt relative to the queue.
As INT writes EOPIS words into each channel queue, and updates the associated CEIS word to indicate the number of entries currently outstanding, if the number reaches 16 INT
will sets a bit in the 16th entry to indicate a full queue condition. When IOP retrieves that entry it notes the toggled full bit as an indication that some subsequent entries may have been written over; i.e. as an indication that its information relative to communication framing event~ in the respective channel may be incomplete.
The IOP can disable a channel by first halting data tran~fer on that channel in the Ll logic, and then disabling the channel in the IDLC by setting channel type bits in the respective channel control register (CCR) to a value indicating an inactive channel. The IOP can disable the IDLC
entirely by setting a mode field in the ICR register to a predetermined value (for further information refer to the detailed description of the SIO element hereafter).
With certain exceptions noted here, information transfers between the IDLC and its external interfaces, and between elements within the IDLC, are conducted by exchanges of request and acknowledgement signal~. Exceptions with respect to data transmission and reception are at the BTDM
interface and at the interface between RLl and RV.
At the BTDM interface TLl must present a bit of tran~mit data within a predetermined time after appearance of a request from Ll circuits for bit transfer, and RLl must accept a receive bit within a predetermined time after Ll indicates that it is ~ending same. If data byte buffers in TLl (there are 2) are both empty when a request for bit tran~fer appears at 27, an underrun indication is given to TV whlch then presents an interrupt indication to INT.
Similarly, if the (single) data byte buffer in RLl i8 full when tran9fer of a receive bit i9 indicated at 27, RLl ~C9 - 90- 001 49 20349~

asserts an overrun indication which is passed to INT via RV
and RFM. INT then collects and stores the related status information and generates a related interrupt request to IOP
via SIO.
At the interface between RLl and RV similar synchronous transfer restrictions apply; namely, that RV must accept a byte of receive data presented by RLl within a predetermined time after RLl indicates that it is presenting that byte.
The time can vary depending upon the current slot phase at the BTDM interface. In general, the time is the lesser of the earliest time at which another bit could be received at the BTDM interface or the time at which RV status would be saved (see discussion of "DONE" indications in description of RSM hereafter).
All other IDLC transfers are full handshake request-acknowledge. TFM moves transmit channel data from a respective 4-byte buffer in FIFOR to TV one byte at a time.
Each transfer is initiated by a request from TV and completed with an acknowledgement from TFM. As soon as the last of 4 bytes is transferred from the FIFOR buffer, in an operation which is not concluded by that transfer, TFM posts a request for additional data to DMARQ. On an asynchronous basis, requests in DMARQ are serviced by DMAC which interacts with MIO to arbitrate for bus 3S, directly access IOP memory and transfer 4 bytes of additional tran~mit source data to FIFOR. Depending on the size of bus 35, the 4 byte transfer may be accomplished in one or more stages, but to DMAC the transfer appears a~ a single operation. As it completes its processing of each transmit data byte, TV
asserts a transfer request to TLl and the latter when ready accepts the byte and asserts an acknowledgement.
Similarly, in receive data handling, RV requests transfer action from RFM as it completes processing of a received byte, and RFM when ready accepts the byte and asserts acknowledgement. The byte is stored in FIFOR within a 4-byte receive data storage space allotted to the respective channel, and when that space fills with the last of 4 bytes RFM posts a request to DMARQ. Asynchronously, DMAC 8ervices that request and moves 4 byte from FIFOR to a directly acce9sed designated circular buffer space in IOP, after intermediate arbitration for bus 35 by MIO.

20;~49~
~C9-90-001 50 Note that the IDLC design can be varied to accommodate a variety of different bus interfaces 35, by merely changing designs of MIO and SIO, and without changing any of the other partitions or significantly altering the aggregate circuit count of the device.
..

7. TIME-SWAP RAM (TSR) AND RESOURCE MANAGER (RSM) Time-Swap RAM TSR contains blocks of spaces allocated to individual processing elements in the synchronous section of the IDLC responsible for reception of data from the BTDM
interface (RLl, RV, and RFM) and transmission of data to the BTDM (TFM, TV and TLl). Each block contains spaces dedicated to time division multiplex (TDM) processing time channels serviced by the IDLC synchronous processing elements, which correspond to network communication channels sampled in associated time slot positions on the BTDM and interfaced to by the Ll circuits.
Each channel space indicates the communication status of the respective network channel/slot and relative to active channels contains a "time swap" status word and interruption status information relative to those channels.
The tilne swap status defines the processing state of the associated IDLC element relative to the respective channel after the last appearance of the associated time slot at the BTDM interface. The interruption status information defines events occurring in respective channels and is stored in TSR
for eventual transfer to the IOP/host complex.
The interruption status information is gathered and stored under the direction of the interrupt processing element (INT). The TSR 8pace allotted for such information is sufficient to permit queueing up of statu~ for each channel relative to plural events occurring at different times, whereby the retrieval action by the IOP/host complex may be efficiently conducted relative to plural events. The INT element is responsible for managing these queues.
Processing channels which are active and currently enabled for communication are serviced by the IDLC
processing elements in synchronism with appearances of respective time slots at the BTDM interface. At the end of each slot associated with an active channel, the respective ::

~C9-90-001 51 Z03491~

processing elements cooperate with Resource Manager RSM to save their latest processing status in the TSR space associated with that channel and the respective element, and at the beginning of a time slot associated with the next active channel the elements cooperate with RSM to reload status saved relative to that next channel during its last service/slot appearance.
During each active channel processing slot, and on signal from RSM, the IDLC processing elements cooperatively perform processing and buffering operations relative to data being received and transmitted through the elements in the associated channel. The data is handled bit serially at the BTDM interface (plural bits may be transferred during any slot), and in bit parallel, byte serially between processing elements.
The elements directly interfacing to the BTDM (TLl, RLl) perform serializing and deserializing functions on the data, and in addition the elements at various stages of handling perform processing functions relative to data carried in framed formats (e.g. relative to channels configured for HDLC protocol communications). These functions presently include insertion and deletion of delimiting flags and fill patterns relative to formatted channels, insertion and deletion of ~tuffing bits into data in protocol channels (for sustaining transparency relative to control characters), address recognition in reception for selectively restricting processing to data appropriately addressed relative to the local node of the IDLC/IOP, insertion and checking of CRC (cyclic redundancy check) information, etc.
TSR i8 also accessible to the IOP, via the Slave I/O
element SIO, for programmable entry by the IOP of initializing information relative to the elements and channels, and for retrieval of interrupt status information relative to the channels.

7.1 TSR ORGANIZATION

Fig. 9 illustrates the physical and logical organization of TSR, and Fig. 6 illustrates how space in TSR

~9-90-001 52 203~91 is apportioned to communication channels and how the space of each channel is used.
Referring to Fig. 9, TSR comprises a 2048 x 36 static RAM 101 (see disc~ssion below of Fig. 6 regarding space allotted to individual channel parameters and reserve application). If tolerance of RAM faults is significant, two 2048 x 36 RAM's should be provided and one or the other used depending upon which is totally free of error. Minimally, TSR requires 1024 x 36 capacity if less reserve space is acceptable.
The access controls include logic 102, multiplexor circuit 103 and register 104. Addressing of storage spaces within the RAM is controlled by address multiplexor circuit 105 and address register 106. Data is input to TSR through data multiplexor circuit 107 and buffer register 108, and output from TSR through buffer register 109. Outputs of register 109 are applied to inputs of RSM and SIO along with acknowledging signals (TSR_RSM_ACK or TSR_SIO_ACK) designating one of the partitions as selected.
It will be noted that inputs to circuits 102, 103, 105 and 107, as well as outputs from circuit 102, appear in a notation "A_B_C"; where A and B are abbreviated partition names and C denotes a function. In this notation, which will be used extensively throughout following descriptions of all partitions, the partition designated first represents the source of a respective signal and the partition designated second represents the destination of that signal within the illustrated circuitry. In some instances the destination partition is omitted but understood to be at least that of the illustrated partition.
Thus, in Fig. 9, "RSM_ADDRESS" is understood as representing "RSM_TSR_ADDRESS", and as denoting a set of address signals from RSM transferrable via multiplexor 105 to register 106. Similarly, all inputs in Fig. 9 having RSM
a9 indicated 90urce are understood as directed exclusively to TSR. TSR inputs from SIO are an exception to the above rule, since SIO has access to all of the RAM partitions TSR, FIFOR and DMAR. In respect to SIO inputs in this figure, destinations of all address, data and parity functions are all RAM partitions in the IDLC. The function selecting TSR
as exclusive destination is the active one of "SIO_TSR_RD"

:, ~C9-90-001 53 203~91~

or "SIO_TSR_WR" (the only signals from SIO shown with explicit destination).
Multiplexor circuits 103, 105 and 107 select between respective inputs presented by RSM and SIO. Multiplexor 105 selects between address inputs presented by these partitions, multiplexor 107 selects between data inputs presented by these partitions, and multiplexor 103 selects between parity inputs presented by these partitions.
Selected input data is written along with corresponding input parity into the address position of TSR designated by the corresponding addre~s input. Input data is presented in 32 bit parallel sets of "actual data" accompanied by 4 bit parallel sets of input parity associated with individual 8 bit byte subsets of the actual data. It follows that outputs to buffer 109 consist of 4 output data bytes with respective 4 parity bits.
Control logic 102 is a finite state machine circuit having control inputs as shown, acknowledging outputs to RSM
and SIO as shown, and RAM controlling output 102A for controlling enablement of access to the RAM and the direction of acce~s (read or write). Read and write accesses are also referred to below as fetch and store operations respectively. The state machine circuits have the following possible states and operate according to the following state sequencing rules.
1. Reset state - assumed only when "SIO_RESET" is active; next state (when "SIO_RESET" goes inactive) is state 0.
2. State O (RSM Ownership State) - provides the following actions. If "RSM_LOCK_UP" is active, "TSR_RSM_ACK" is asserted to pre-emptively select RSM
inputs over SIO inputs. The latter function is ; under5tood as requiring enablement of RSM input selection at multiplexors 103, 105, 107 and at not-shown selector circuit8 within logic 102 for "RSM_RD_WR" and RSM_REQ (the former being in one state or another depending on whether the operation is a read or a write, and the latter being asserted for either a read or a write). If the last acce8s was a read and RSM
is requesting a write then a chip select function in i ~C9-90-001 54 Z~91~

controls 102A, relative to RAM 101 is held off (see state 3 explanation below). This extra cycle is needed to allow adequate time for turn around of off-chip drivers. If the current access is a read, set internal LAST_ACCESS_READ latch 102L;
otherwise reset it.
This last action is needed to keep track of the type of access previously performed (see discussion of state 3 below).
If RSM_LOCK_UP is inactive, examine the SIO request. If SIO_TSR_WR is active, transfer the SIO data and parity to RAM 101 (at the address designated by SIO_ADDRESS), and reset latch 102L. If SIO_TSR_RD is active assert all control signals but hold off accessing RAM 101 (see explanation of state 1 below).
Advance to state 0, 1 or 3 according to the following.
Next state is state O if RSM_LOCK_UP is active and other conditions for advancing to state 3 are absent, or if no requests are pending. Next state is 1 if the ; only request pending is an SIO read (SIO_TSR_RD active and RSM_LOCK_UP ls inactive). Next state is 3 if RSM_LOCK_UP and LAST_ACCESS_READ are active, and RSM_RD_WR i8 indicating a write request.
3. State 1 (SIO Read Ownership) - If SIO_TSR_RD is active, enable read access to location designated by SIO_ADDRESS. Next state unconditionally is state 2.
4. State 2 (SIO Acknowledgement) - Assert TSR_SIO_ACK, relative to SIO request. TSR_DATA is valid if and only if SIO_TSR_RD was active. Next state is unconditionally state 0.
5. State 3 (RSM Police State) - this state guards against back-to-back read and write accesses by RSM
with insufficient intervening time to permit RAM inputs and outputs to stabilize. This state is entered when RSM attempts a write access while LAST_ACCESS_READ is active (~ee state O above). If the second requested operation is a write, it may be performed without delay in this state. Next state is O. Output of RAM 101 on read accesses, TSR_DATA, is presented to RSM and SIO
along with an acknowledgement selecting one of the partitions. When RSM accesses TSR it asserts .

~SC9-90-001 55 203~911 RSM_LOCK_UP, preemptively blocking SIO access. If RSM
is attempting a read access, it automatically enables reception of TSR_DATA at the corresponding RSM input, and otherwise ignores that input. If SIO and RSM are simultaneously attempting read access, SIO will ignore its TSR data input because TSR_SIO_ACK will be inactive. Next state is state 0.

7.2 TSR SP~CE ALLOTMENTS

Referring to Fig. 6, in the primary rate ISDN
environment, the 2048 36-bit wide "word" spaces in TSR
(recall previous discussion of preferred TSR size as 2048 x 36) are apportioned equally to 32 channels, so that each channel i9 allotted 64 word spaces. Each such space is usable for storing four 8-bit data bytes together with four related parity bits. The specific word space allocations for channel O are illustrated as representative of those for all channels. Address boundaries are illustrated in hexadecimal notation; those for channel spaces appearing at the left, and those for word spaces within representative channel O
appearing at the right.
Each channel space includes 27 word spaces for specific word parameters and 37 reserved spaces (available for expansion and applicational variations). The specific word parameters for each channel include: 2 words defining general channel configurations and specific HDLC protocol configurations (CCR, HPCR), 3 words for saving transmit element states on time-swaps (TX_TSl), 5 words for saving receive element states on time-swaps (3 RX_TSl, 2 RX_TS2), and 17 channel status words (CEISR and EOPISROl - EOPISR16).
Specific bits and functions of each of these words will be dlscussed later (configuration words CCR and HPCR in the description of the RSM element, time swap words in the de~criptions of individual transmit and receive elements, and status words in descriptions of INT and SIO elements.

7.3 RSM

The Resource Manager partition (RSM) manages the time swapping of receive/transmit processing element states relative to dedicated locations in TSR, as well as the bidirectional transfer of information required for management of channel interruption status processing between INT and TSR. RSM also serves as a logical focal point for detecting and logging hardware errors conditions relative to all parts of the IDLC chip and the Ll circuits.
RSM monitors the BTDM interface for "beginning of slot"
(BOS) indications, signifying ending of one time slot at the interface and beginning of another, and prepares for requisite time swap activities relative to the IDLC transmit elements (TV, TLl), receive elements (RLl, RV), FIFO queue management elements (RFM, TFM) and INT. RSM also customizes the status saving and reloading functions so that they are not performed relative to inactive channels; although RSM
performs a preloading operation for retrieving a portion of the CCR (Channel Configuration Register) word associated with each channel (active or inactive) in order to determine if the respective channel is active.
A reason for not saving element status relative to inactive channels (ignoring the useless aspect of such actions) is that since Host/IOP/SIO have independent write access to respective channel state storage areas in TSR, any saving activity by RSM might potentially overwrite state information ~ust newly written by IOP/SIO with incorrect state information. A reason for not loading element ~tatu~
relative to inactive channels (again ignoring the useless aspect of such) i9 that state information passing between TSR and the elements is parity checked in RSM; thus, the loading process relative to inactive channel~ containing state information of indefinite form could give rise to unnecessary parity error indications/interruptions.
A~ part of its preparation for state saving, while processing is concluding relative to an active channel, RSM
verifies that processing relative to that channel in each synchronous processing element ha8 reached a stable concluding 8tate suitable for saving.
Synchronous proce8sing elements sub~ect to state 8wapping (RLl, RV, RFM, TLl, TV, TFM, and INT) continuously present state signals to RSM while processing relative to any active channel. Such state signals are writable by RSM
to TSR for saving, but RSM does not perform such transfers ~C9-90-001 57 Z03~91 until a predetermined phase of the processing/slot cycle at which under normal circumstances the states saved will represent valid data.
During processing relative to active channels, the synchronous elements receive early "end of slot" indications (EOS) from RSM, and state machines in these elements then have a predetermined but short amount of time to attain stable state from which processing can be unambiguously resumed when the respective channel slot reappears. This time is different for each element. During normal operation, these elements if not instantly in stable states when EOS is manifested will reach such states within the required time, and once in such state, they will assert respective DONE
indications to RSM.
At the end of the predetermined times just mentioned, RSM writes (saves) respective element states to TSR, but also checks for respective DONE indications. If any DONE
indication has not been returned when due, RSM generates a logic timeout indication internally, which is detected by INT as a hardware error condition requiring associated status recording and interrupt action relative to SIO/IOP.
RSM also monitors signal transfer activity on the BTDM
interface to ensure that it is properly phased relative to state swap activities in IDLC If RSM detects transfer action while status is being loaded or saved, it generates a timing error indication, RSM_LlL2_ERROR, to INT and continues processing.
The possibility of data corruption denoted by this indication is eventually reported to the IOP/Host, and action if required is taken by the latter system to ad~ust Ll circuit operations to maintain a more suitable level of synchroni8m (see di8cussion of BTDM Interface hereafter, and note therein the definition of the time window during which "burst" data tran8fer8 between Ll and IDLC are permitted).
In respect to loading of synchronous element states from TSR, for preparing these elements for processing relative to an appearing or reappearing active channel slot, RSM synchronizes the start of processing relative to that channel by presenting "START" signals to the elements at appropriate instants of time after EOS. These start signals are not presented until elements which exchange data have all been loaded with status.
In the exemplary primary rate ISDN environment, slot times have minimum durations of 3.8 microseconds and the IDLC runs on a 20 MHz clock relative to which the minimum slot time is measured by 76 clock cycles. In RSM, assignment of times to its various functions is determined by subtracting overhead time (time needed for all TSR stores and fetches) from minimum slot time, and distributing the remaining clock cycles evenly among all other time swapped functions. Since overhead time is affected by TSR
availability, SI0/host accesses to TSR (for interrupt status retrieval and/or channel state initialization) may reduce the time allowed for other functions during any time slot.
The tracking of overhead time is accomplished using cycle counter 121 as described below.
Referring to Fig. 10, RSM comprises: configuration registers 115 and 116, multiplexor circuits 117 and 118, parity generation circuit 119, parity check circuit 120, cycle counter 121, slot generation circuitry 122 and state machine 123. State machine 123, described below, contains address generation logic for determining addressing of TSR
channel spaces and for supporting addressing of such relative to dynamicall~ varied hyperchannel mappings.
Registers 115 and 116 are 32 bit wide registers serving as buffers for configuration defining words. Register 115, the configuration control register (CCR), receives configuration control words defining individual channel configurations during processing time slots assigned on a time division ba8is to respective channels. Regi8ter 116, the H~LC protocol configuration register (HPCR), receives control words defining protocol configurations during process time slots assigned to channels in which protocol formatted communication8 are being conducted.
Configuration word8 transferrable to these regi8ter~
are stored or storable in TSR (see Fig. 6), in spaces allocated to individual channels, and specific bit field allocations within each wort are illustrated in Figs. 11 (for CCR) and 12 (for HPCR). Outputs of registers 115 and 116 extend in 32 ,bit parallel cable banks (shown as single lines) to associated inputs of multiplexor 117 and all other ~cg - go - oo 1 5 9 20~91 autonomous elements in the IDLC synchronous section. With reference to Figs. 10 - 12, bit fields within these registers have the following definitions and usages.

CCR (1 per channel):
RES (reserved) - 13 bits (10 at the left and 3 at the right) - reserved for expansion or future applications.
Channel T~pe (CT) - 3 bits - distinguish channel type as one of: B/D (up to 64 kbps, Layer 1 dependent), H0 number 1, 2, 3, 4 or 5, Hll, or H12.
Protocol Code (PC) - 4 bits - having 16 definable values of which 12 are reserved and 4 designate individual ones of the following protocols: SDLC, LapB, LapD, Clear (no protocol; e.g. for Voice channels).
Transmit DMA Enable (TDE) - 1 bit - enables or disables transmit DMA control operations by DMAC. Bit should be set to enabling state only after TDCRl - TDCR4 have been properly initialized (see description of DMAC
partition below).
Receive DMA Enable (RDE) - 1 bit - enables or disables receive DMA operations (transfer of receive data from FIFOR to IOP/Host memory). Should be set to enabling contition only after RDCRl - RDCR4 have been properly initialized (see description of DMAC below).
Receiver Enable (RE) - 1 bit - enables or disables processing of received data according to de3ignated protocol. Relative to data channels (e.g.
SDLC/LapB/LapD), detection of flags, aborts, idles, bit de-stuffing, bit to byte assembly, byte queueing in FIFOR, deqtination address recognition, CRC checking, and word (4 byte) at a time transfer to IOP storage.
Relative to clear channels, bit serial to byte assembly, byte storage in FIFOR, and transfer to IOP
memory a word (4 bytes) at a time. Processing of data is unter assumption that most significant bit arrives first.
_ort Request (AR) - 2 bits - evoking one of following actions: abort only on (receive) data overrun condition, send abort data pattern (seven l's followed by predetermined pattern), send idle pattern (15 . .
', . , ', ~C9-90-001 60 203491~

consecutive l's), send inverted idle pattern (15 consecutive 0's). Field valid only when Protocol code is that for SDLC, LapB or LapD. When AR designates any of the last 3 actions, TDE bit must be set to 0 (disabled) and TE bit must be set to 1 (enabled).
Abort InterruPt Mask (AIM) - 1 bit - relative to aborts occurring between frames, either causes interrupt to be generated or no action, depending on bit value.
Inter-Chain Fill Select (ICS) - 1 bit - affects DMAC
operations during transmit DCB chaining. Depending on bit value, causes DMAC to insert either a series of 'fill' flags ('01111110') between chained data or an 'idle pattern' ('111...111 t; at least 15 l's) between closing flags and the beginning of the new chained data. Bit function valid only when PC set to value for SDLC, LapB or LapD.
Inter-Frame Fill Select (IFS) - 1 bit - selects fill pattern to be inserted between data protocol frames as either fill flags or idle pattern following closing flags (see ICS definition).
Address Reco~nition OPtion (ARO) - 2 bits - causes selective forwarding of received data frames depending on option field value. Options include: disabled (all frames forwarded), forward 1 (forward only broadcast frames and frames having single byte destination address), forward 2 (forward only broadca~t frames and 1, frames having 2 byte specific destination address), forward 3 (forward only frames having broadcast addresses for SDLC and LapD (since no broadcast address exists for LapB and clear channels, all frames in 9uch channels are forwarded)). Option values are valid only when PC value is that for SDLC, LapB or LapD.
Recognized broadcast addresses are: first byte after opening flag i8 'FF' Hex (for SDLC), second byte after opening flag is 'FF' Hex (for LapD), none (for LapB) ,Tran8mit Enable (TE) - 1 bit - enables or disables transmit da~a transfer out of FIPOR. When disabled, no flags, aborts, idles or CRC check symbols are transmitted at BTDM IF. When enabled, data and framing symbols are transmitted at BTDM IF upon request from layer 1 hardware.

203~91~
~C9-90-001 61 Invert Data Stream (IDS) - 1 bit - when this bit i9 active, data is sent and received at BTDM interface in inverted form (otherwise in true form). Enabled state of this bit intended to support 64kbps restricted operation. Both ICS and IFS should be in disabled conditions when this bit is enabled to avoid transmission of more than 7 consecutive O's on link.

HPCR (1 per channel):
To~le - 1 bit - used to indicate that SWRC value is valid. IOP toggles the value of this bit each time it updates the SWRC field in association with retrieval of interrupt ~tatus from TSR. Bit is valid only when QM
bit in ICR (see description of SIO below) is enabling.
Status Words Read Count (SWRC) - 5 bits - used by IOP
to indicate to INT partition the number of status words read from the associated channel's 16 word EOPISR queue in TSR after an interrupt. INT uses this count to determine if it needs to generate another interrupt relative to the current contents of the queue. Field valid only when QM bit in ICR is enabling.
Link Station Address (LSA) - 16 bits - used to program the specific address to be recognized when ARO field in CCR has a value calling for 1 or 2 byte address recognition. For 1 byte recognition, upper 8 bits in this fleld should be set to the station address value and lower 8 bits to O. For 2 byte recognition, entire field is programmed to station address value. Field valid only when PC parameter in CCR i8 desi~nating SDLC, LapB or LapD protocol. When receiving LapD, command/re8ponse bit (next to least 9ignificant bit in first byte of frame) is masked automatically by receive partition elements, and frame is forwarded only if remaining seven bits in same byte (in 1 byte recognition mode) or those bits plus bits in next byte (for 2 byte recognition mode) match the LSA value, or if a broadcast pattern i9 detected.

In addition to its inputs from register~ 115 and 116, multiplexor 117 has ten other banks of 32-bit wide parallel inputs, or a total of 12 input banks. Multiplexor 117 is ~C9-90-001 62 203491~

operated by state logic 123 to selectively connect one input bank at a time to its output 125, in accordance with not-shown selection control inputs from logic 123. The other 10 input banks serve to transfer time swap words to be saved (written to TSR); 3 from transmit processing elements (TLl, TV, TFM), 5 from receive elements (1 from RLl, and 2 each from RV and RFM), and 2 from INT (CEISR and INT_EOP).
Multiplexor output 125 connects to RSM_DATA input of TSR, parity generator 119 and SIO. Output of parity generator 119 connects to RSM_PARITY inputs of TSR and SIO.
If RSM has asserted write selection inputs to TSR
(RSM_TSR_RD_WR and RSM_LOCK_UP active while RSM_TSR_REQ is inactive), the aggregate 36-bit wide expression formed by RSM_DATA and RSM_PARITY is written into a TSR location designated by an associated RSM_ADDRESS output of logic 123.
Thus, during any time slot, logic 123 can repeatedly operate multiplexor 117 ant access controls of TSR to sequentially store some or all of the parameters which can be input to the multiplexor, and thereby perform the various status 8aving operations associated with element state swapping.
It should be noted that RSM itself does not undergo state swapping relative to TSR but only fetches CCR and HPCR
in a read-only context as it prepares for successive channel slots. Values stored in the associated registers are not rewritten to TSR since they do not change over the course of any time slot. However, such values are at certain times of interest to the IOP/Host complex and are therefore made accessible to SIO via multiplexor 117 and bus 125.
Multiplexor 118 receives TSR_DATA outputs, resulting from RSM read accesses to TSR, and selectively connects them to its time 9wap state loading bus (RSM_TS_BUS) 126 which connects to inputs of all time swapped elements. Specific elements to receive individual outputs are designated by RSM_XXX_LOAD outputs of logic 123 (where XXX represents the destination element abbreviations). Thus, state words read out of TSR can be distributed to respective elements Inputs from TSR to multiplexor 118 are also applied to parity check circuits 120 to be checked by the latter. If parity error is detected, circuits lZO activate one of two error indicating outputs (TSR_PARITY_ODD or TSR_PARITY_EVEN) as a function of the odd/even value of the number assigned ~C9-90-001 63 Z03~911 to the channel relative to which the error has been detected; that value being derived via circuits 122 and 123.
These parity error indications are sent to the INT partition for invoking error interrupt action, and since activities of INT span consecutive slots in relation to activities of the receive and transmit elements, the odd/even distinction allowed by the two outputs is needed to enable INT to a~sociate the error with the correct channel.
Multiplexor 118 also receives inputs from SIO_DATA
output of SIO for distributing those outputs to the time swapped elements. This function is provided only for diagnostic usage since the normal source for state loading is TSR. In association with activation of SIO_DATA, SIO
provides state controlling inputs SIO_RESET to logic 123 for conditioning RSM to appropriate initial states, and inputs SIO_RSM_RD, SIO_ADDRESS and SIO_RSM_WR, for directing distribution of SIO_DATA to time swapped elements via RSM
multiplexor 118. In response to the latter RD and t7R inputs, RSM decodes the address and asserts the appropriate control inputs to multiplexor 117 and the destination element (RSM_XXX_LOAD to the latter). This is only permitted when RSM is not performing real time channel status swapping between TSR and the elements.
Cycle counter 121 is used to determine the current state in each slot. It divides the available slot time (minimum 3.8 microseconds) into intervals of post processing for previous slot, variable TSR access times, preprocessing for next slot and data transfer times. A policing mechanism in the state machine portion of logic 123 ensures that data transfers occur only when respective partitions are prepared. Counter 121 is reset upon reception of an Ll_LSOF
(last slot of frame) or Ll_BOS (beginning of slot) indication from the BTDM interface; the latter indicating the approaching end of the current slot and the beginning of the next one. To allow for accommodating a range of different time slot durations (in other application environments of the IDLC), counter 121 is prevented from overflowing within that range.
Slot generation logic 122, comprising 2 registers and a six bit counter, determines associations between time slots appearing at the l~TDM interface and IDLC processing ~C9-90-001 64 203~9~1 channels. Due to variable hyperchannel mapping in the IDLC, individual time slots at the BTDM interface may not map identically to individual channels (i. e. for some channels the slot mapping may be many-to-one). Logic 122 receives the Ll_LSOF and Ll_BOS indications from the BTDM interface along with mapping control inputs from state logic 123 and provides outputs to logic 123 indicating the current channel/slot associations. Incrementing of the counter in logic 122 and associated hyperchannel mappings are determined by address generation functions within logic 123 conditioned at least in part on the CT (channel type) field in CCR 115.
Slot generator 122 also presents 3 indications to the DMARQ partition; including a 5-bit time slot indicator, RSM_TSI, a 5-bit HO indication, RSM_DMARQHO, and a l-bit Hl indication, RSM_DMAR QHl. The TSI indication identifies the BTDM time slot associated with the channel currently being proce~sed in the synchronous section. The HO and Hl indications, derived from logic 123 via connections of the latter to the output of the channel type field CT in CCR 115 (Fig. 11), are used to identify HO type and Hl type HyperChannel associations of current slots (refer to CCR
field descriptions above and to descriptions of DMARQ and HyperChannel which follow).

7.3.1 RSM ADDRESS LOGIC AND STATE MACHINE

State machine logic 123 sequences through the following states with associated output effects as described. Relative to TSR fetch operations, it ~hould be noted that fetched data is acce~sible 2 state cycles after the state initiating the respective fetch.

State 30 (Initial State):
Wait for 910t transition intication from BTDM IF
(Ll_BOS or Ll_LSOF), and determine if internal mode value (value defining the current operating mode of RSM) should be updated. Mote value is only sampled and updated when next slot count is zero, so that RSM does not sequence out of reset mode (~et by SIO/Host) in the middle of an ISDN frame. In this ~tate cycle counter 203491~
~C9-90-001 65 121 is reset and SIO access to RSM registers and TSR is allowed. After Ll indication, the next state transition is a function of the current mode. If in "reset" mode, no transition i9 made. If in "diagnostic" mode, next state is state 2. If in "normal" mode (neither reset nor diagnostic mode), next state is state 0.
State O (Read CCR):
Access controls to TSR are activated to fetch the CCR
for the channel associated with the next time slot.
This is actually a pre-fetch in which only a small part of the CCR is actually latched and used by RSM;
specifically, the 3 bit channel type field CT. This information is used only for enabling the logic to determine if the next channel is active. As noted earlier, in this and other fetch operations the fetched information is not available at RSM until 2 state or internal clock cycles after the fetch is initiated. In this and other RSM accesses to TSR, RSM_LOCK_VP is asserted to pre-empt access to TSR. RSM effectively has total control of its interface to TSR once TSR_ACK is returned, and RSM can perform any requisite access operations without SIO interference. In this and other fetch accesses to TSR, RSM_TSR_RD_WR and RSM_REQ are asserted, the latter distinguishing the operation as a fetch/read. This state is held until TSR_ACK is active, and at that time the next state, state 23, is entered.
State 23 (Read CCR Wait State):
This is a wait state for a single read of TSR, during which the CCR for the next channel to be served is read from TSR to the TSR_DATA bus (note again the presently allowed delay of 2 state cycles from fetch start to avallability of fetched data). Next state is state 31.
tate 31 (Load Pre-CCR ReRister) The CT field of the CCR word appearing at TSR_DATA is latched into an internal "Pre-CCR" register in the state machine logic. As with all data fetches from TSR, parity is checked by parity check circuits 120. Parity error outputs of the latter are input to INT partition, and distinguished as having occurred during either an odd or even numbered slot time (TSR_PARITY_ERROR_ODD or TSR_PARITY_ERROR_EVENT). Since activities of INT span ~C9-90-001 66 203~-9~

portions of consecutive slots relative to associated activities of other partitions, this distinction i9 needed to enable INT to associate the error with the correct channel/slot. Next state is state 25.
State 25 (HyPerChannel Mappin~ State):
The pre-CCR latches are examined, and RSM conditions itself for addressing TSR in accordance with the channel type (CT) bits in pre-CCR. For instance, some channels are processed in single BTDM time slots (ordinary B and D type channels and voice channels) while others (HyperChannels) span plural time slots.
Thus, the pre-CCR examination permits RSM to determine which channel address block in TSR it currently must access. This will be understood further from the discussion of the HCR register in the description of SIO below. Furthermore, the enabling bits in pre-CCR
distinguish channels as either active or inactive, and relative to inactive channels operations for saving and loading state parameters are suppressed, thereby allowing for TSR to be accessed for other purposes (e.g. for SIO data transfers to or from IOP/Host complex). In this state, the logic waits for 29 internal clock cycles to have elapsed since reception of Ll_BOS or Ll_LSOF, based on information furnished by cycle counter 121, and then enters next state, state 2.
State 2 (Store TFM TSOl State):
If the previous channel (the channel associated with the slot effective prior to BTDM indication) is active, controls for write access to TSR are activated (RSM_LOCK_UP and RSM_TSR_RD_WR) and first state word of TFM is presented for saving relative to the channel address space in TSR associated with the previous channel. In respect to this and other "time swapped"
element state words, reference should be made to descriptions below of re9pective elements for details of fields within each word and usages of each relative to respective elements and INT. The state logic waits for appearance of acknowledgement from TSR
(TSR_RSM_ACK), and checks that DONE signals from TFM, TV and TLl have all been asserted by that time. If they have not, error indicator RSM_LOGIC_TM is asserted . .
' ' . ~
: . . ..

~C9-90-001 67 203~91 relative to INT. The storing of element state words is accomplished dynamically at different phases of the current BTDM IF slot, provided that slot is associated with an active channel, and the respective TDE bit in the associated CCR is enabling. With respect to saving of the TFM state word additional conditions are that no end of DCB chain condition or FIFO parity error in TFM
has been encountered. Next state is state 4.
State 4 (Store TV_TS01 State):
In this and following states calling for write access to TSR RSM_LOCK_UP is held asserted, fully pre-empting TSR (for RSM, to the exclusion of SIO). If the previous channel is active, and associated CCR bit TE is enabling, the fir~t state variable of transmit element TV is saved. The CCR bits TE and TDE are provided j specifically for allowing SIO, acting under IOP
direction, to be able to update values in respective TSR locations without exposure to having RSM overwrite the updated values with out of date state information from the transmit and receive elements. Next state is state 6.
State 6 (Store TLl_.TSOl~:
The third transmit variable, TLl_TSOl, i9 stored provided TE bit in associated CCR is enabling. Next state is state 7.
State 7 (Fetch TSR_TLl TSOl):
If the next channel is active, RSM_LOCK_UP and RSM_REQ
are asserted, with appropriate addressing of TSR, and the process for fetching the first state variable for TLl relative to that channel (TLl_TS01) is initiated relative to TSR. Due to the pre8ently allowed 2 cycle latency in TSR reads, the fetchlng process is initiated in this 9tate, but the respective data will not be valid on TSR_DATA bus until two states after this ~tate. Next 9tate is state 5.
State 5 (Fetch TSR_TV_TS01) ; This starts the fetching process relative to TSR for the state variable of TV associated with the next channel, provided the next channel is active. Next state is state 3.
State 3 (Fetch TFM_TS.01 Load TSR_ TLl TS01):

.: ~

~Cg-90-001 68 2 03~ 9 If next channel is active, this starts fetching of the first state variable for TFM relative to that channel, while asserting the load signals relative to TLl for loading the state variable fetched 2 state cycles earlier. The data being loaded appears on bus 1~6, and parity checking of that data is performed by RSM logic 120. On parity error, appropriate indication is presented to INT as previously explained. Next state is state 9.
State 9 (Fetch HPCR. Load TV) Fetch HDLC protocol configuration term for next channel to HPCR register, and load TV with state variable fetched in state 5 (assert RSM_TV_LOAD). Parity of TV_TSOl is checked and receive side DONE signals (RFM, RV, RLl) are verified. Note that INT is started earlier and allowed to run longer than transmit or receive elements in each slot, in order to ensure that all exception conditions generated are synchronously logged by INT. Next state is state 1.
State 1 (Fetch CCR, Load TFM) CCR is re-read (see state 0), for two reasons. First, to handle any required HyperChannel remapping, and second to fetch the bits not available in the pre-CCR
register (a~ noted above, earlier pre-CCR fetching involves retrieval and use of only the channel type field, so for efficiency the internal latching facilities constituting the pre-CCR register is tailored to the type field and not the full CCR
expression). In respect to HyperChannel remapping, HyperChannels span plural BTDM time slots, and the CCR8 associated with 9uch channels may not be the one8 prefetched at the time of the first slot. If the previous channel is active, ~ignal RSM_TFM_LOAD for loading TFM (with previou81y accessed TFM_TSOl) is as8erted and parity of the variable being loaded is checked. Next state i~ state 28.
State 78_~Wait State / Load HPCR) This is a wait state to allow for any off-chip drivers to be turned around. Signal for loading general variable HPCR into RSM register 116 is asserted, and i ~C9-90-001 69 203~91~

parity of that parameter is checked. Next state is state 22.
State 22 (Store EOPISR / Load CCR) By this state, INT should have asserted its DONE signal (INT_DONE) and should be presenting new EOPIS status (End Of Process Interrupt Status), if it has such, for storage in the associated channel's 16 deep queue (see Fig. 6), where it becomes available for IOP access via SIO. If DONE has not been asserted, then a logic time out error is posted and processing continues. EOPIS is posted if the previous channel (the channel now concluding) was active, and the associated EOP valid bit has been set (see description of INT below~. Note that in any of the previous states where parity is checked, occurrence of parity error is signalled to INT
when the error is detected; a time which may either ; precede or coincide with the processing interval for the associated channel in the respective destination element, and this time relationship is indicated to INT
by assertion of a respective PARITY_ERROR_ODD or PARITY_ERROR_EVEN indication. Posting of EOPISR in this manner is needed to ensure that any interrupt status vector CEISR (channelized error interrupt status vector) associated with hardware error is posted once and only once relative to any channel (to avoid redundant error reportage to the host system). Signal for loading CCR to register 115 in RSM is asserted and parity of the CCR variable i8 checked. Next state i9 state 12.
State 12 (Store INT_TSOl) The 8tate variable for INT is stored if the previou9 (concluding) channel was active or if a parity error has been generated relative to that channel. This is needet to ensure that interrupts associated with hardware failures within an element, but indicated repeatedly by parity errors, will be generated once and only once relative to the host system (see state 22).
Next state is 8tate 13.
,~ State 13 (Fetch TSR_INT_TSOl) The as90ciated 9tate variable for INT is fetched if the new channel is active or if a parity error occurred ~C9-90-001 70 203~911 earlier in the pre-CCR fetching sequence for that channel. Again, this ensures that INT will register only a single interrupt for errors which might repeat during the slot sequence. Next state is state 29.
State 29 (Wait State) A wait state to turn off-chip drivers around. Next state is state 14.
State 14 (Store RV_TSOl / Load TSR_INT_TS01) This is the first state for saving receive element ; status relative to the previous channel. If that channel was active and reception was enabled in its CCR
(RE bit ON), respective status of RV is sent to TSR
with appropriate address and selection functions. That status (see description of RV below) includes bits indicating states of CCR bits RE and RDE saved by RV
relative to the previous channel (needed because CCR of next channel has been loaded). Load signal for INT
status word is asserted and parity of that word is checked. Next state is state 16.
State 16 (Store RLl_TS01) In this state, the START pulse for the INT partition is asserted if the next channel is active or parity error has occurred in any previous state of the present state sequence. The status word for RLl relative to the last channel is stored in TSR if the channel was active and had an enabling reception bit RE in its CCW. Next state is state 18.
State 18 (Store RFM_TS01) Store RFM status relative to the previous channel if that channel was active and had its CCR RDE bit enabling. Next state is state 20.
Stat~ 0 (Store RFM_TS02) Store ~econd status word for RFM if previous channel active and RDE enabling. Next state is state 10.
State 10 (~t~re V T~
Store second status word for RV if previous channel active and RE bit enabling. START pulse to transmit elements (RSM_XMIT_START) is asserted if next channel is active and no parity errors have occurred. Next state is state 11.
State ll~_(Fetch TSR_RV_TS02) ~C9-90-001 71 203~9~1 Next state for RV is fetched if next channel is active.
Next state is state 21.
State 21 (Fetch TSR_RFM_TSOl) Fetch first state word for RFM if next channel active.
Next state is state 19.
State 19 (Fetch TSR_RFM_TS02 / Load TSOl in RV) Second state word fetched for RFM if next channel active, and second state word loaded to RV and parity checked if channel active. Next state is state 17.
State 17 (Fetch RLl state / Load RFM) If next channel active, state word for RLl is fetched and first state word for RFM is loaded to RSM and parity checked. Next state is state 15.
State 15 (Fetch 1st RV state / Load 2nd RFM state) If next channel active, fetch first state word for RV
(TSR_RV_TSOl), load second state word to RFM and check its parity. Next state is state 26.
State 26 (Load RLl) If next channel active, first state word for RLl is loaded and parity checked. Next state is state 27.
State 27 (Load RVl) If channel active, load first state word (TSR_RV_TSOl) to RV and check parity of that word. Next state is state 24.
State 24 (Start Receive) This i~ the last state of the sequence. Since next slot becomes previous slot upon reception of Ll_LSOF or Ll_BOS, slot generation logic is conditioned to update its registers when one of these appears. Receive start (RSM_RCV_START) is asserted if current channel is active and no parity errors have occurred on fetches.
Ne~t state i~ initial state 30.
State ELSE (Error State) Thi~ i9 a forbidden state which can only be entered through occurrence of hardware error in the state logic. If this state is reached, hardware error indication RSM_ERROR_STATE is asserted relative to INT
and an attempt at recovery i~ made by sequencing next to state 30.
..

8. BTDM INTERFACE

,. :: `' ' ' .:

~C9-90-001 72 203~9~

Lines, signal exchanges, and methodology of operation at the Burst Time Division Multiplex (BTDM) Interface (IF) are described next with respect to timing diagrams in Figs.
13-15. Details of specific Ll circuits which may be relevant to this interface, but are not considered relevant to presently claimed subject matter, are contained in the previously cited co-pending cross-referenced application entitled "Burst Time Division Multiplex Interface For Integrated Data Link Controller". Said applica~ion and its relevant disclosure details are incorporated herein by the present reference thereto. Hereafter, for simplicity, the BTDM interface will be referred to simply as the "BTDM" or "interface".
The BTDM provides an exact functional and logical break between Layer 1 and Layer 2 processes as defined by Open Systems Interconnect (OSI) specifications of the International Standards Organization (ISO). The layer 2 processes are performable in whole or part within the present IDLC device (in the presently described embodiment for the ISDN primary rate environment many but not all layer 2 functions are performed in the IDLC, but other layer 2 functional responsibilities must be assumed in the IOP
and/or host systems).
The BTDM itself is neither defined nor contemplated by OSI. Rather, it represents what is considered presently to constitute a unique approach to organizing the timing of transfer functions between Layer 1 and Layer 2 hardware such that the presently desired throughput of the IDLC is attainable in and beyond the representative primary rate ISDN environment.
The BTDM use8 a rather small number of lines (6) to transfer data at high speeds (up to 2.048 Megabits per second full duplex) between the IDLC and Ll circu~t~. It provides the flexlbility needed for sustaining such transfers in the exemplary ISDN primary rate environment;
e.g. for 32 full duplex B type channels, with data transfer rates in each channel of up to 64 kbps in each direction.
One understands, of course, that depending upon specific networks and media to which the Ll circuits couple such circuits may assume a variety of forms. Of relevance presently is the general composition of those circuits as ~C9-90-001 73 203~91~

needed to sustain the specific signals, signal timings, and signal phasings characteristic of the BTDM. That general composition is fully described in the above-mentioned co-pending patent application, and is not relevant to any presently claimed matter. Hence, only the associated circuit functions will be discussed herein.
The interface allows the Ll hardware to control the data rate in any slot from 0 to 64 kbps per channel full duplex, and thereby to support voice/clear channels, B type channels, and lower speed D type channels (16 kbps per channel full duplex), M type channels and S type channels;
as well as HyperChannels formed by aggregating time slot capacities of plural B type channels (see later description of HyperChannels). Furthermore, the transfer timing flexibility of the interface allows for varying slot and frame durations on a dynamic basis to support varying communication traffic needs.
Although implemented to be suitable for supporting both ISDN primary rate and ISDN basic rate as Ll protocols, and HDLC as principal L2 protocol, the BTDM is not restricted to the8e protocols. It can be used therefore to support any other Ll, L2 protocols defined by OSI or IBM (e.g. Async or Bisync), and has the speed and characteristics suitable for accommodating transfer of encoded voice in any channel.
Interface data transfer signalling is performed in sharply time-compressed bursts occupying a short duration window of time within each channel time slot. Transmit and receive transfers are conducted simultaneously. The "dead time" between bursts, also called setup time, is designed to optlmize the efficiency of channel processing and state 8wapping functions performed in the IDLC, and is believed to inherently minimize the LSI circuit cell count required for multi-channel communication service, as well as to minimize the buffer storage capacity needed per channel in the IDLC.
The interface 8upport8 a high degree of flexibility in the methods which can be employed to transfer data, under layered protocols (OSI, SNA), between local and remote chip modules, and facilitates transfer of time division multiplexed (TDM) channelized data in HDLC format between Layer 2 device8 such as the IDLC and a variety of Ll circuits.

~C9-90-001 74 203~91~

The interface supports 'X' TDM data channels, each capable of transferring 'Y' bits of full duplex data in per channel TDM time slots of duration 'Z', where: 'X' can range from 1 to 32, '~' can range from O to 8, and 'Z' is a minimum of 3.8 microseconds, and 'X' times 'Z' is less than or equal to 125 microseconds. Note that foregoing figures are tailored to ISDN European requirements, and in implementations tailored specifically to ISDN North American requirements 'X' should range from 1 to 25, 'Y' should range from O to 8 for B and D type channels, and 'Z' should be the same minimum of 3.8 microseconds.
In respect to the above parameters, note that they are tailored to the presently contemplated ISDN environments. In other environments, it is believed that the range of Y (bits transferrable per slot window) for the indicated limits of X
and Z could be increased to 16 without difficulty. It also 8hould be noted that although the present BTDM
implementation is designed specifically for coupling a single Ll circuit unit with a single IDLC type device it is contemplated that a similar interface design could be used to couple plural Ll circuit modules with a single IDLC
device or even plural IDLC devices.
A feature of the interface, described in more detail in the related patent application, is what is termed "positive slip" operation in all channels. Interface timing presently is paced by specific elements in the Ll circuits in such fashion that under normal operating conditions possibilities of overrun and underrun (overrun in reference to transfers of receive data rom Ll to IDLC and underrun in reference to transfer of transmit data from IDLC to Ll), due to clock drift between internal Ll clocking and clocks at remote network nodes, are effectively eliminated or at least minimized. In other time-dependent interface8, it is con8idered normal for clock drift to cause intermittent 81ipping effects such that occasional overrun and underrun are expected and dealt with by posted error indications and host-initiated frame retransmission8. Such error postings and retransmissions, which obviously are wasteful of host system processing time and also tend to consume or restrict interface bandwidth usage, are effectively eliminated or minimized by positive slip operation.

~C9-90-001 75 2 ~3i~9 The BTDM contains data and control lines having relative signal timings illustrated in Figs. 13 and 14.
Single lines, RDATA and TDATA, respectively carry received and transmitted data (received data from Ll to IDLC, transmitted data from IDLC to Ll ) . Control lines LSOF and BOS transfer reference timing pulses, from Ll to IDLC, respectively indicating "last slot of frame" and "beginning of slot" points of time relative to TDM time frames and time slots. LSOF is both the beginning of slot indication for the last frame slot and an advanced end of frame indication.
Durations of pulses on LSOF and BOS are 50 nanoseconds or one (IDLC, Ll) machine clock cycle. Each frame slot is allocatable to a communication channel, and each communication channel may be dynamically allocated one or more slots per frame. Active B, D, and clear/voice channels, are each allotted one slot per frame, and several slots (not necessarily contiguous in time) may be allotted collectively to a single HyperChannel (see description below of HyperChannels).
During each slot, transfers of receive and transmit data occur bit serially within an 800 nanosecond "window".
The window for receive data starts 800 nanoseconds before the BOS pulse indicating the beginning of the next slot, and ends 50 nanoseconds before that pulse. The window for transmit data starts at the same time as the receive window but, due to the phasing of transmit requests and corresponding transmit bit transfers, ends almost coincident with the next BOS indication.
Each bit is transferred in a 100 nanosecond interval defined by a respective pulse from the Ll side (RDATA_VALID
pulse accompanying each receive bit sent by Ll, and TDATA_REQ pul8e asserted for each tran8mit bit to be sent by IDLC element TLl). During any slot, the number of bits transferred in each direction (i.e. the number of 'RDATA_VALID' and TDATA_REQ pulses presented by Ll circuits) is variable (from 0 to 8 in present ISDN environments), and this variability allows Ll to regulate the fullness of its transmit and receive buffers 80 as to achieve the above-mentioned positive slip action.
The rest of the slot interval, at least 2.95 microseconds in duration, is "setup time", allowing the IDLC

:
,, , ~C9-90-001 76 203~911 to complete all minimally required handling of data received in the previous slot (the slot prior to BOS pulse following receive transfer), perform channel state swapping relative to the next slot (the one started with the next BOS after transfer window) and complete all minimally required handling of transmit data relative to the channel and transfer window associated with the next slot.
The theoretical (nominal) slot duration for the European ISDN rate (2.04~ megabits per sec.) is 3.91 microseconds, but the duration at the present interface is held to a slightly shorter duration (minimally 3.8 microsec.); i.e. the slot rate at the BTDM is slightly higher than the nominal slot rate expected at the network interface taking into account "worst case drift" between local Ll clocks and remote clocks. Maintenance of this "advanced slot rate", and regulation at Ll level of the number of bit~ transferred per slot, effectuates positive slip action; i.e. ensures that receive and transmit buffers on the Ll side (with minimal capacity in each of 2 bytes per channel) can not respectively overflow and underflow due to clock drift between internal Ll and network side clocks. On the IDLC side5 the rate of processing within the transmit and receive pipelines, and anticipated worst case rate of DMAC access to IOP memory, are designed to ensure more than adequate ability to meet any pace set by Ll for positive ~lip control.
Fig. 15 illustrates timing of internal Ll clock~, Cl_CLOCK and B2_CLOCK, associated with generation of BTDM
data bit clocking functions TDATA_REQ and RDATA_VALID. Cl is a master clock and B2 is a slave clock (derived from Cl).
Each internal clock pulse has 20 nanosecond (ns) duration.
Con8ecutive Cl and B2 pulses are non-overlapping, and the start of B2 follows the end of the immediately preceding Cl by a 'guard' space of about 5 ns. Each machine cycle in Ll (50 ns) starts with the rise of a B2 pulse, and consists of 4 clock phases; one associated with the duration of the B2 pulse, another with the interval from the end of that B2 to the rise of the following Cl, a third associated with the duration of that Cl pul9e, and a fourth associated with the guard space from the end of that Cl to the rise of the next B2.

~C9-90-001 77 203~91~

Transfers of receive and transmit bits are unacknowledged. IDLC is required to latch receive data bits at predetermined phase of RDATA_VALID indicated by '****', and to latch Ll requests for bit transfer at predetermined phase of TDATA_REQ indicated by 1****1. Ll must latch transmit data bits presented by IDLC at predetermined phase of TDATA indicated by ' '.
In addition to the above data and control lines, a number of lines are shown as associated with the BTDM, but are actually lines coupling the Ll circuits to the IOP/host system, some connecting directly to the IOP bus and others coupling thereto indirectly through the SIO element of IDLC.
These lines allow the IOP to directly control initiation of the Ll circuits and retrieve interrupt status information directly from those circuits. Names and functions of these lines are indicated below.

_ameFunction CHIP_SELECT Input to Ll from SIO, indicating detection of a valid IOP originated address (and IOP originated data, if the operation required by the IOP is a write) which is in the Ll address space. This signal is also an indication that valid conditions pertain to lines: READ/WRITE, ADDRESS, ADDRESS_PARITY, and for write operations:
DATA and DATA_PARITY. This line remains active until the address i9 removed.
READ/WRITE Input to Ll from SIO designating data transfer operation to be performed relative to the designated address. Binary 1 and O levels on this , line respectively designate Read and Write j functions. The line signal state is valid when CHIP_SELECT is active.
ADDRESSA 12 bit input to Ll from SIO
designating address (A12 - AO; A12 most significant bit) within Ll to or from which data is to be transferred when CHIP_SELECT is active.
3 ADDRESS is valid whenever CHIP_SELECT i8 active.
SIO actually receives a 24 bit address from IOP
(A23 - AO), and decodes the high order bits (A23 to Al2) to generate CHIP_SELECT and transfer the , BC9-90-001 78 203~91~

low order bits to Ll (for further decoding by latter as needed).
DATA A TTL Tristate bidirectional 16-bit (2 byte) bus between IOP bu~ and Ll. During read operations, Ll side is required to disable its data drivers within 20 nanoseconds after deassertion of CHIP_SELECT.
DATA_PARITY Ll parity input from IOP during write operations, consisting of high (H) and low (L) parity bits associated respectively with high and low bytes on DATA. If Ll detects parity error it does not assert -DTACK, and sets a status bit associating the error with data. That bit can be read by IOP/SIO to determine the cause of the associated DTACK timeout. -ADDRESS_PARITY Ll input from SIO (2 bits~ indicating parity of associated (full and half) bytes on ADDRESS. If Ll detects address parity error it inhibits assertion of -DTACK as for data parity error and sets status bit associating error with address. IOP/SIO can read that bit to determine cause of associated DTACK timeout.
-DTACK Tristate output from Ll used to acknowledge data transfer. Asserted only after valid data has settled on DATA during read operation, or after data has been latched on a write operation, and only if associated data and address parity are correct. Signal should be removed no later than 20 ns after deassertion of CHIP_SELECT.
-CHIP_INTERRUPT Ll output to INT element of IDLC, used to reque8t generatlon by latter of Ll hardware ~ fault manual interrupt vector. INT/SIO will j generate associated interrupt at the IOP bus interface at level prespecified by IOP. This line 8hould be held active by Ll until IOP re8ponds to the IDLC interrupt request by requesting a statu8 read operation from an internal status regi~ter in ¦ Ll. The line should thereafter be held deactivated j for at lea8t 100 ns to complete the 8equence.
~ Since INT does not queue up Ll manual interrupt .. . .
:" '' ' '~

requests, the Ll circuits are responsible for collection of status relative to plural Ll events in local status registers of those circuits.
Furthermore, since manual vector generation by INT
may be delayed relative to other interrupt status exchange activities, allowance for such delay must be made in the Ll process.
-CHANNEL_INTERRUPT Ll output used to request generation by INT of Ll Channel Interrupt Manual Vector. This interrupt is treated the same as the chip interrupt above. The only difference is at the IDLC where it is given a lower priority than the chip interrupt. Also, it causes a unique vector to be generated which is different from the chip interrupt vector.
-RESET Input to Ll from SIO causing a master ; reset of all Ll circuits to a reset state. It can be activated at any time and is not gated by CHIP_SELECT. It remains active for a minimum of 100 milliseconds.

9. RECEIVE REGISTERS AND RECEIVE LOGICAL ELEMENTS

This section describes elements RLl and RV, and includes descriptions of registers and state machine logic in each element.

9.1 RLl FUNCTIONS

This sub-section describes functions and logical ,. organization of RLl.
RLl functions are:
1) Receive data de~erialization. RLl receives data bit serially, at the BTDM, in bursts of O to 8 ~, blts per channel time slot, deserializes the data into I 8 bit bytes and passes the latter to RV for further bit ¦ parallel byte processing.
I 2) Detection and deletion of protocol specific characters ~nd control signal patterns from data passed to RV; e.g. HDLC flag characters (OllllllO), idle patterns (15 or more consecutive l's), and abort ' '' .~. 7~

BC9-90-001 80 203~91~

patterns (7 to 14 consecutive l's). As such characters and patterns are detected they are discarded (not passed to RV).
3) Removal of bits inserted at transmitting nodes for transparency; e.g. removal of stuffed O bits from HDLC data, which have been inserted to prevent simulation of flag characters or special patterns (idle or abort) in the "message data".
4) Setting of indicators for alerting INT element to frame reception status, and to reception of protocol specific patterns such as HDLC abort and idle patterns. Relative to received HDLC data, RLl sets indicators upon detection of flag characters, idle patterns and abort patterns. Upon detecting a flag character, pattern detection logic in RLl acts to distinguish if that character represents the beginning or end of a frame. If it represents the beginning of a frame, RLl sets an internal frame state indication to denote that. If it represents the end of a frame, RLl sets the internal frame state indication to denote : that and presents an end of frame indication, eof_ind, to RV which the latter processes and forwards to INT.
If a non-flag byte is detected following setting of internal beginning of frame status, internal frame i status is set to denote the middle of a frame. If an ; idle pattern is detected, RLl presents an idle indicator, idle_ind, to RV which the latter forwards to INT. If an abort pattern is detected RLl presents an abort indication, abort_ind to RV which the latter ~ forwards to INT.
5) Abort masking. RLl can be dynamically conditioned (by Host/IOP via SIO, RSM and TSR) to selectively mask out detection of abort patterns j outside of a frame, thereby providing host programs with flexibility to eliminate undesired interrupts related to such detection.
6) Octet alignment checking. Upon detecting a frame closing flag, RLl performs an octet alignment check to verify that the number of bits received during the frame, le8s the number de~tuffed, represents a multiple of 8.

~C9-90-001 81 203491 7) Detection/deletion of shared symbols in protocol specific patterns. Relative to HDLC sources which use a shared O between consecutive flags (011111101111110) to reduce the overall number of bits transmitted, RLl is responsible for detecting and deleting such flags. Also, relative to HDLC sources which use a single shared flag between frames (to represent the end of one frame and the beginning of another), RLl is also responsible for distinguishing such flags and setting the appropriate internal frame status and external end of frame indication.
8) Data inversion. RLl supports reception of inverted data protocols (e.g. inverted HDLC) and is responsible for detection, deletion and indication of flag characters, idle patterns and abort patterns received in inverted form.

g.2 RLl LOGIC

Referring to Fig9. 16-18, RLl comprises state machine logic 150 which controls all RLl operations and in addition performs certain pattern detection functions relative to received data. RLl also contains an 8-bit check register 152, an 8-bit data register 153, and a 6-bit service register 154. Outputs of logic 150 and register 154 form the RLl status word, RLl_TSOl, which is presented to RSM for status swap saving.
Referring to Fig. 18, time swap status word RLl_TSOl comprises: two 8-bit fields termed RLCR and RLDR, a 4-bit field named RLTC, a 3-bit field named RLDC, a 2-bit field named RLFS, and a 7-bit field named RLSTAT. Meanings of respective field names and Informatlon presented ln each fleld are lndlcated next.

RLCR- Represents the RLl Check Register state. It continually reflects the contents of check shift reglster 152.
RLDR - Represents the RLl Data Reglster state. It contlnually reflects the content of data reglster 153.

~C9-90-001 82 2034911 RLTC - Represents the RLl Transparency Count state.
` It corresponds continually to the state of the transparency count; a count of consecutively received 1 bits which is used for detection of flag characters, idle ~: patterns and abort patterns, as well as for recognition of need for destuffing action in accordance with HDLC rules (see state machine discussion below).
RLDC - Represents the RLl Data Count; a count of the number of valid data bits received (modulo 8). It is used after detection of a valid frame closing flag for determining octet alignment. This count is reset when an abort, idle or flag is detected.
RLFS - Represents the RLl Frame State count (refer to description of frame states 0, 1, 2 and 3 in the state machine discussion below). Its value distingui~hes phases of HDLC frame reception, and is used for determining when received data represents message data to be passed to RV.
RLSTAT- Represents the state of the RLl status register 154 as shown in Fig. 17. Its bits, ~`, designated bits 0-6. indicate the most recent status of reception in the re~pective channel as follows.
; Bit 0 - idle pattern received ~ Bit 1 - end of frame pattern received ,~, Bit 2 - abort pattern detected Bit 3 - reserved Bit 4 - octet alignment error detected 4, Bit 5 - reserved Bit 6 - reserved Data bits presented by BTDM (BTDM_DATA with BTDM DATA_VALID) are shifted into check register 152 within a clock cycle (50 ns) of their presentation. Depending upon the channel protocol, such data i9 selectively shifted into data regl~ter 153 and different actions follow.
Relative to clear channels, bits are shifted into register 153 without specific pattern checks, and as the 8th BC9-90-001 83 ~03~9~

bit of a sequence is received (as determined by state machine 151), the parallel output of data register 153, RLl_RV_DATA, is presented to RV with a ready indication, RL_RV_DATA_RDY. Whenever such indication is given, RV is required to latch the 8 bits within a clock cycle of their presentation (i.e. the transfer is synchronous and not acknowledged).
Relative to data channels configured for HDLC, or other specially framed transmission protocols requiring selective detection of predetermined bit patterns, selective deletion of such patterns, and transfer of indications associated with detection of such patterns, RLl performs the following operations.
Bits are shifted serially into both check register 152 and data register 153, and as each bit arrives logic 150 acts to determine if it and the previous 7 received bits represent a flag (01111110). If those bits represent a flag, data register 153 is cleared without any transfer to RV, further determination is made of frame opening or closing 8tatus and indication to RV is set in register 154 if appropriate.
As each bit is received logic 150 also acts to determine if that bit and its 6 predecessors form part of an idle or abort pattern (a pattern containing more than six con~ecutive l's). If this is detected, the data register is cleared without transfer to RV, and an indication of idle or abort status is set relative to RV. After detecting an abort or idle pattern (which in effect invalidates any subsequent data until a new opening flag arrives), logic 150 continues to examine arriving bits looking for a flag, and continues to discard received groups of 8 bits, by clearing the data register without tran8fer to RV, until a flag is detected.
After detecting an opening flag, logic 150 continues to check for flag8, idle and abort pattern8 as above, but also check8 each received bit along with its 6 predecessors to determine if that bit is a "stuffed" bit (a 0 bit following 5 con8ecutive l's preceded by a 0). Each stuffed bit is discarded (by preventing 8hifting of the data register and of that bit into the data register), and each group of 8 bits remaining after such discarding is transferred to RV in a synchronous transfer (see discussion of clear data above).

~C9-90-001 8~

As it detects opening and closing flags, idle patterns and abort patterns, logic 150 sets associated indications in service register 154, and as any new indication is set into register lS4 logic 150 directs presentation of the register contents to RV. The bit layout of register 154 is shown in Fig. 17 and explained below.
Referring to Fig. 17, register 154 contains seven bits, including five 1 bit fields named: IDLE, EOF, ABORT, RES, and OCTET, and one 2-bit field named RES. The 3 RES bits are reserved, and the other bits when active provide indication functions associated with respective names; i.e. IDLE and ABORT respectively indicate detection of idle and abort patterns, EOF indicates detection of a closing (end of frame) flag, and OCTET indicates detection of octet misalignment.
When operating relative to HDLC transmitted in inverted form, a not-shown inverter gate disposed at the input to registers 152 and 153 is actuated to invert all received bits. Thus, operations of logic 150 relative to such signals are in effect identical to operations relative to uninverted HDLC signals.

9.3 RLl STATE MACHINE STATES

The state machine logic 150 has states designated reset state and states 0 to 3 as follows.

Reset State Entered when SIO_RESET is active. All internal status registers are reset and output control and status indications are deasserted. Next state is state O (upon deactivation of SIO_RESET).
State9 0 and 1 Wait for RDATA_VALID indication from BTDM. Upon receiving 9uch take one of the following actions.
- In clear channel mote, simply shift the bit on the RDATA line into the data register.
- In bit-oriented protocol mode, shift the RDATA bit into the check register and examine the (internal) transparency count for determining if the received bit is a stuffed 0. If it is not, shift the bit ~C9-90-001 85 203~911 into the data register and increment the reception bit count. If destuffing is required, inhibit shifting of the data register (and therefore of the just received bit into that register) and do not increment the bit count.
Next state is state 2.
State 2 In clear channel mode, check internal count of bits shifted into data register. If ~ame indicates register is full, assert data ready signal (RLl_RV_DATA_RDY) to RV (as noted above, this is a synchronous transfer, and RV must accept the data within a 50 ns clock cycle or post an error indication). In bit oriented protocol mode, examine the check register to determine if a flag (01111110) has been received. If a flag is detected, clear the data register (effectively dropping the flag from the ~ignal stream passed to RV), and update frame 'i variable a~ needed according to the following.
'. - Frame state O denotes reception outsite a valid protocol frame ("looking for opening flag").
- Frame state 1, indicating possible start of a frame, is set when flag is detected while frame state i8 0 or 1 (consecutive flags are transmittable). Upon detecting a flag, data register i8 cleared and bit count i9 reget.
- Frame state 2, indicating an open frame, is set if a non-flag byte is detected while frame state is 1. In this frame state, the bit count i9 examined and if it indicates the data register is full the ready indication is set relative to RV and the iA byte is transferred from the data register to RV
as in clear channel mode operations.
- Frame state 3, indicating the end of a frame, is set if a flag is detected while frame state is 2.
f Data register is cleared and end of frame indicator i9 asserted relative to INT. In this frame state, the bit count is examined for octet alignment and if not a multiple of 8 the octet alignment error indicator is set relative to INT.
If a flag is not detected examine check register for idle or abort pattern (7 or more consecutive BC9-90-001 86 ~03~9~

l's). If such is detected, set appropriate idle or abort indicator relative to INT, clear data register and reset bit count. If RDATA_VALID is inactive, next state is state l; else, next state is state 3.
State 3 Wait for RDATA_VALID to go inactive. Next state is ctate 1.

9.4 RV FUNCTIONS

RV receives data and status indications from RLl, performs CRC (Cyclic Redundancy Check) calculations, checks for overflow condition, and passes the data with additional status indications to RFM. When end of frame indication is received from RLl, RV passes the CRC check result to RFM
along with status of both RLl and RV. RV also performs address recognition on received data frames, based on the address recognition option bits ARO in the CCR (refer to RSM
description above), and may selectively discard frames based on such recognition. Options allowable are: receive all frames, recognize/transfer only frames with a predetermined destination address byte or predetermined broadcast address, recognize only frames with a predetermined 2-byte destination address or broadcast address, and recognize only frames with a broadcast address.

9.5 RV LOGIC

Referring to Fig. 19, the ma~or circuit elements in RV
are registers 170 and 171, CRC calculator circuit 172 and state machlne logic 173.
Registers 170 and 171 form a 2-deep queue for pipelined 8torage of communication data and status received from RLl.
Each register provides storage for a byte of data and associatet 8tatus indications. Each byte of data presented by RLl, RLl_RV_DATA, is latched into register 170 (DATA_STATUS_A) along with related frame status, RLl_R~_STATUS, from RLl indication register 154 (indicating end of frame, abort, idle and octet alignment status), and ~C9-90-001 87 subsequently shifted in parallel into register 171 ( DATA_STATU S_B ) .
Thus, RV supports the apparent burst speed sustainable at the BTDM. Since RLl can receive up to a byte of data in one channel time slot, it is possible for RLl to receive 2 bytes of data relative to one channel in consecutive appearances of the respective time slot, and therefore the 2 byte queueing capacity in RV is needed.
CRC calculator 172 cumulatively calculates the CRC
check function relative to data requiring such, and passes the result to RFM upon receiving a valid end of frame f lag detection indication.
RV operates on a synchronous time multiplexed basis;
its status relative to each active channel being saved to TSR via RSM as the respective channel slot concludes, and reloaded via RSM when that slot reappears. Processing relative to each channel begins when a start indication, RSM_RCV_START is activated by RSM, and ends when an end of slot indication, RSM_RCV_EOS is given by RSM. While its 7 status is being saved relative to one active channel and being reloaded relative to another active channel, RV (logic - 173) is placed in a halted state.
Upon receiving the start indication, RV processing re~umes at the state held when proces~ing relative to the same channel slot last concluded. Upon receiving the end of slot indication from RSM, RV state logic 173, if not in a stable concluding state will sequence to such before halting (e.g. if in a state where data must be received from RLl, the data will be latched in register 170 before the halt state is assumed). Upon reaching such state, logic 173 asserts the partition's done indication, RV_DONE, to RSM.
- Data and status indications are presented by RLl along wlth re9pective ready indication8, RLl_RV_DATA_RDY and RLl_RV_STATUS_RDY; the latter conditioning logic 173 to control latching of the re8pective data and 8tatu8. A8 noted before, tran8fers from RLl to RV are synchronous, and require RV to latch the data and status within a 50 ns machine cycle period of their presentation. Transfers from RV to RFM are asynchronous request-acknowledge operations;
RV 8tate logic 173 presenting RV_RFM_REQ and RFM returning RFM_RV_ACK.

BC9-90-001 88 203491~

RV swap status consists of two time swap status words, RV_TSOl and RV_TS02, shown respectively in Figs. 20 and 21.
RV_TSOl represents the combined contents of registers 170 and 171, and RV_TS02 represents the status of check circuit 172. On reloading, corresponding swap status information is fetched from TSR by RSM and presented via RSM_DATA to registers to all major circuit units in RV.
Referring to Fig. 20, the fields of RV_TSOl have the following names and functional significance.
RVDO - RV data register O (8 bits). Corresponds to data byte portion of register 170 (Data A), and represents the most recently received data byte. While in this register data undergoes CRC
calculation processing.
RVDOP - RV Data O Parity (1 bit). Odd parity for the byte in RVDO.
RVDl - RV data register 1 (8 bits). Corresponds to data byte portion of register 171 (Data B); and represents the data to be prncessed further if needed (e.g. for address recognition) and transferred to RFM. When ready, data is moved from RVDO
to this register.
RVDlP - Odd parity (1 bit) for data in RV data register 1 RVARS - RV address recognition state (2 bits) relative to data frames sub~ect to address recognition option. Indicates 1 of 4 states: 1. waiting for data on which to perform address recognition; 2.
address has been recognized or recognition is disabled (all data in frame will be forwarded to RFM and an interrupt will be generated upon receipt of an end of frame indication); 3 or 4.
no adtress recognized, this frame will be ignored.
RVDF - RV data registers full (2 bits).
Indicate 1 of 4 states: 1. RVDO and RVDl both empty; 2. only RVDl contains valid BC9-90-001 89 ~03~911 data; 3. only RVDO contains valid data;
4. both RVD0 and RVDl contain valid data.
RVLBF - Last byte of frame indication (2 bits).
Indicate one of: 1. Neither RVDO nor RVDl contains the last byte of current frame; 2. RVDl contains the la~t byte of current frame; 3. RVD0 contains the last byte of current frame; 4. Both RVD0 and RVDl contain the last byte of current frame (i.e. registers 170 and 171 both contain end of frame indications).
RVI - RV Initialized indication (1 bit). Set by IOP/SIO to indicate initialization of state swap variables for RV relative to the current channel slot, and reset by RV to acknowledge that it has ~ensed this and moved to a normal processing state relative to the channel.
RVLAR - RV Last Address Recognition Option (2 bits). Last value in the ARO filed of the CCR associated with this channel. At each RSM start, RV logic compares this field to current ARO to determine if ARO
value has been changed (by IOP/SIO). If change i9 detected, new value of ARO is moved into this field. Upon detecting a next start of frame RV will begin address recognition processing according to new ARO value in this field.
, Referring to Fig. 21, fields in RV_TS02 have the following names and functional significance.
RVCRC - RV CRC remainder (16 bits). When end of frame indication is received from RLl this field i~ checked to verify correct receptlon of the frame, and then reset to all l's.
RVS0 - RV Status Register 0 (7 bits). Status most recently received from RLl; 3 bits unused, others indicate frame state ~C9-90-001 90 20349~

(EOF, idle detected, abort detected, octet alignment status).
RVSl - RV Status Register 1 (8 bits). Next status to be passed to RFM. When ready, status is shifted from RVS0 to this register; 4 bits in this regi~ter indicating frame state, another bit i indicating CRC check status, another bit indicating buffer overflow status in the RLl RV pipeline, 2 bits are unused.
RVIO - RV Internal Overflow indication (1 bit).
Indicates internal overflow condition if the registers within RV. When this bit } is set no data is forwarded to RFM.

9.6 RV STATE MACHINE
. --Logic 173 consists of 2 state machines, and additional combinational loglc circuitry for interfacing to RLl and gating RLl data and status into register 170 under the synchronous clocking constraints described previously. The combinational logic simply receives data and status from RLl, along with respective ready indications (RLl_DATA_RDY
and RLl_STATUS_RDY), checks to see if the register is full or empty, and completes the transfer if the register is not indicated as full. If the transfer is completed a latch is ~et to indicate that (that latch being reset by operation of ; MOVE state machine when contents of register 170 are moved to register 171. If register 170 is full when data or status ready indication is received, the data or status is di8carded and a bit in register 170 is set to indicate overflow status.
The 2 state machines, named MOVE and PROCESS, control all other RV functions. MOVE controls transfers of data and statu~ from "A" register 170 (DATA_STATUS_A) to "B" register 171 (DATA_STATUS_B), and PROCESS controls processing of the data (CRC checking, address recognition, etc.) and interfacing to RFM. These 8tate machines are described next.

MOVE State Machine State 0 (Idle State) ~C9-90-001 91 Z03~91 In this state, RSM can safely swap state status and state data, provided the RV_DONE
indicator is active. After new state status and data have been loaded relative to any active channel, RSM asserts RSM_RCV_START, and MOVE advances to state l.
L State 1 (Processing State) Data and status are moved conditionally from register A to register B, and data is moved conditionally from register A to CRC
calculator 172. If end of slot indication from RSM is received (RSM_RCV_EOS), MOVE
returns to state O after handling of any concurrent RLl data or status ready functions has been completed relative to register A.
If not halted, and data/status are available in register A, next action depends on status of register B and CRC calculation.
If register B contains only ent of frame status, MOVE loops until register B is emptied by PROCESS state machine.
If register B contains both end of frame status and the last data byte of a frame, MOVE checks the CRC remainder for validity (must be 'lDOF'X hex). If the remainder is invalid, MOVE sets the CRC invalid bit in register B (see state 2), and loops in this state until register B is emptied by PROCESS.
I register B contains only valid data and register A contains only end of frame statu~, the frame status is moved from register A to register B, the data in register B is indicated as the last byte of a frame, and regi~ter A i~ made available for receipt of data and statu~ from RLl If reglster B has neither valid data nor end of frame status, and register A has both, both are moved from register A to B. In that event, the data i~ simultaneously entered into the CRC calculator, register A is made available for receipt of more data and BC9-90-001 92 203~91 status, register B is marked as holding the last byte of a frame, and MOVE advances to state 2.
- If register B has neither data nor end of frame status and register A has only end of frame status, the status is moved to register B. The CRC remainder (note states 2 and 3 below) is checked for validity . If the CRC
remainder comparison fails, the CRC invalid bit in register B is set. If register A has only valid data, the data is passed to register B and CRC calculator simultaneously and MOVE advances to state 3.
State 2 (Wait For CRC Calculation On Last Byte Of Frame) - CRC calculation takes 1 machine cycle to calculate one bit, and since the data movement is 8 bits at a time the full calculation takes 8 machine cycles. MOVE
decrements an internal count from 8 to O in successive machine cycles and then returns to state 1 where it checks the CRC remainder for validity as the final CRC remainder of the frame (note how this state is entered above).
State 3 (Wait For CRC Calculation On Other Than Last Byte) - Machine cycles are counted down from 8 to O
as above, and MOVE returns to state 1.

PROCESS State Machine State O (Idle State) - Simllar to state O in MOVE (wait for RSM_RCV_START). On receiving start indication, PROCESS advances to state 3.
State 1 (Address Recognition Processing) - If halted by RSM_RCV_EOS, returns to state O.
If not halted and ARO indicates all frames receivable and recognition status (RVARS
field in RV_TSOl) indicates invalid address has been recognized, data in register B
(register 171) is discarded until frame end ~ ~C9-90-001 93 20~4911 indication has passed through register B).
Note that the scenario for this situation (all frames receivable and invalid address recognized) is that the ARO has changed since the current frame started, rendering the current frame invalid.
If register B has either data or ending frame status, and recognition status indicates that a valid address has been recognized, PROCESS
goes to state 2 (to pass data or ending frame status to RFM).
If ARO indicates addresses are recognizable and recognition status indicates invalid address has been recognized, data in register B is discarded until the start of a new frame. If register B contains either data or frame end status and valid address has been recognized~ PROCESS goes to state 2 (to forward the data or frame end status to RFM).
If frame. state such that addresses need to be recognized presently, data in registers A and B are compared with the address pattern held in the LSA portion of the HDLC register in RSM. If the pattern matches, recognition status is get to indicate valid address has been recognized, address recognition concludes for this frame, and PROCESS goes to state 2 to forward data. If compared addresses do not match, status is set to indicate invalid address recognized and PROCESS stays in state 1 to cause all following data to be discarded.
State 2 (Transfer Data/Status to RFM) RV_RFM_REQ is asserted to RFM. ~pon receiving acknowledgement, RFM_RV_ACK, indication is set that register B is available for data or status transfer (depending on which part of B
was full), and PROCESS returns to state 1.
Note that if end of frame status is transferred, on return to state 1 PROCESS
will merely be waiting for end of slot .~ .
,~
.
''' . , .. : ~

Z03~9~1 :
indication from RSM and then return to state O. If data only is transferred, on return to state 1 PROCESS will be waiting for additional data to forward and then return to this state, etc.
State 3 (Process Dynamic Change In ARO) - If status loaded by RSM indicates a newly initialized channel (RVI bit in RV_TS~l set), PROCESS resets the newly initialized indication and compares the latest address recognition option (ARO) bits (in RSM_CCR) with the previous ARO state (RVLAR field in RV_TSOl) to determine if the ARO state has changed. If it has, the latest option is copied into the status positions of the RVLAR
field of the next saved RV_TS01. Next state is state 1.
- If loaded status does not indicate newly initialized channel, the last ARO and present ARO are still compared, and if they don't match the present ARO is written into the last ARO field position. Next state i9 state 1.
- If the ARO has changed from recognizing addresses to receiving all frames, and recognition status presently does not indicate recognition of invalid address recognition status i9 set to indicate valid address recognized, so that rest of frame will be received as normal. Next state is state 1.

10. TRANSMIT REGISTERS AND TRANSMIT LOGICAL ELEMENTS

10.1 TRANSMIT LAYER 1 (TLl) FUNCTIONS

TLl interfaces between the Transmit Validate element TV
and the BTDM for transferring transmit data from TV to the network. Recall that TV receives transmit data from FIFOR
(FIFO RAM), via Transmit FIFO Manager element TFM, and such data is loaded into FIFOR via asynchronous action of DMAC in ; . .

BC9-90-001 95 203~91~

response to requests asserted by TFM to DMARQ (DMA Request Element).
TLl performs functions which are the reverse of those performed in RLl, including:
- Data byte serialization - Flag, abort and idle generation - Transparency - zero bit stuffing - Underrun detection - Flag sharing - Data inver~ion - Alternate register usage for output data TLl receives data bytes from TV, and transfers data bit serially to the BTDM in response to bit requests TDATA_REQ
presented at BTDM by the Ll circuits. In TLl, data is funneled through a pair of byte registers, TLDl and TLD2 (discussed below in the description of TLl Logic), so that during any slot time TLl may be storing up to 2 bytes of data relative to the channel then being served, and thereby be prepared to deal with any rate of Ll requests within the rate limits of the ~TDM; which allows up to 8 requests to be burst within a slot, and thereby contemplates that during a slot bits of 2 consecutive bytes may have to be sent (since transmission generally will not be octet aligned).
If underrun occurs in spite of this, TLl will generate an appropriate underrun indication for interrupt processing, follow by transmitting an abort pattern, follow that by sending an idle fill pattern, and after the abort pattern has been sent generate appropriate indication of that event.
In addition, TLl i~ adapted to react quickly to any change made in the abort control bits (AR and AIM) in the CCR, and begin transmitting an abort pattern. Thus, TLl can be effectively cont~olled at any time, by the IOP/Host acting through SIO ant TSR, to abort a transmission, and thereby for in~tance reduce unnecessary u~e of network channels for continuing transmissions known to be in error.
Relative to channels communicating in HDLC protocols, TLl will be detecting tran~mission~ of 5 consecutive 1'~, representing non-delimiting data (not flag, not idle and not abort), and insert (stuff) a O bit to prevent receipt of ~uch data as delimiting. Furthermore, TLl will distinguish start and end of protocol me~sage frames and insert opening ~cg - go - oo 1 ~ 6 Z03~91 and closing flags at respective phases of transmission. If the protocol requires bit inversion, TLl will take care of that.
TLl operates in a time division multiplex synchronous manner, whereby its state relative to any active channel is loaded (from TSR via RSM) during the associated BTDM time slot appearance and saved (to TSR via RSM) as the slot ends.
Its time swap state consists of a single word, TLl_TSOl described below with reference to Fig. 24. TLl contains a 9-bit status indication register discussed below with reference to Fig. 23, whose contents are saved in time swapping as part of TLl_TSOl.

10.2 TLl STATUS INDICATIONS

TLl status indications, shown in Fig. 23, consist of 8 used indicator bits (bits O - 6 and 8) and 1 unused bit (bit 7).
The "servicing abort" bit (bit O) indicates an abort pattern is being transmitted (or an inverted abort pattern if inverted HDLC is in effect). This bit is set by the hardware and saved during status swapping to provide a mechanism whereby an abort pattern being transmitted can be remembered across BTDM frames.
The end of frame bit (bit 1) is set when a byte requested from TV i9 indicated by the latter to be the last data byte o a frame. When this bit is on, TLl will automatlcally send a closing flag after the last data byte, and TLl will reset this bit when that flag has been sent.
After a closlng flag has been sent, a fill pattern consi~t~ng of a series of flags or idles is transmitted a9 needed. A fill pattern is needed when TV sends a specific ending indication, TV_ENDFRAME or TV_ENDCHAIN. The form of the pattern is determined by a bit in the CCR; the IFS
(interframe fill select) bit if ENDFRAME is indicated or the ICS (interchain fill select) bit if ENDCHAIN is indicated.
The data reg order bit (bit 2), in con~unction with the states of the data regl and data reg2 empty indicator bits (bits 3 and 4) determines the order of data transfer relative to data registers TLDl and TLD2 mentioned above.
Data fetching action relative to TV is evoked when either ~C9-90-001 97 Z03~9~1 bit 3 or 4 is on, indicating that the respective register is empty. When these bits are both off, data is taken out of the registers for transfer to BTDM in the order indicated by the order bit. If both bits are on, the order bit determines the sequence of data loading into the registers.
The underrun indicator bit (bit 5) is used to remember that a data underrun has occurred. When this condition occurs, bit O (abort service) will also be set. When TV has no new frame data to send after the last byte of a frame and closing flag have been sent, the underrun indicator will be set requiring TLl to generate a Fill pattern. The on/off state of the inter-frame fill select bit (IFS in RSM_CCR) determines the form of the pattern; idles if on, flags if off.
The abort raised bit (bit 6) is used to indicate that an abort has been indicated relative to INT. This bit is reset when the a~sociated request in TFM has been acted upon and reset by INT.
The TFM reset bit (bit 8) is used to indicate that TFM
has been reset (deactivated, reinitialized and reactivated).
This bit is used to reset the abort condition.

10.3 TLl LOGIC

TLl logic is shown schematically in Fig. 22. Details are gi~en below. The logic includes state machine logic 176, consisting of 3 discrete state machine units 176A, 176B and 176C, data registers TLD 1 and 2, respectively indicated at 177 and 178, abort/idle/flag generator 179, mux circuit 180, status indicator register 181 (TLSI) for holding the status bit indications shown in Fig.23, a bit pointer register 182 also called TDBP (for Transmit Data Bit Pointer), a source selector register 183 also called TLDSS (for Transmit Layer 1 Data Source Selector), and a transparency counter 184 also called TLTC (for Transmit Layer 1 Transparency Counter).
State machine unit 176A (called TLl State Machine) controls receipt of transmit data bytes from TV and their loading into data registers 177 and 178 in accordance with the order and empty indications in status indicator register 181. As data is transferred to registers 177 and 178, unit 176A ad~usts the order and empty indications in register 181 ~C9-90-001 98 203491 - appropriately. Details of the states of this unit are given below in paragraph 10.3.1.
State machine unit 176B (called Reset State Machine~
monitors the state of Transmit FIFO manager TFM to ensure that data transmissions are properly coordinated with initialized states of TFM. By observing the TDE (Transmit Data Enable) bit in the input RSM_CCR from RSM, and the TLl_DONE output from unit 176A, unit 176B determines when TFM has been deactivated, reinitialized and reactivated through external actions of IOP via SIO. These external actions are required as each unit of data block transfer to the network is completed in order to coordinate operations relative to each succeeding block of data with chaining functions conducted by DMAC relative to its transfer commands (see description of DMAC below). Details of states of this state machine unit are given below in paragraph 10.3.2.
State machine unit 176C (also called Ll Transfer State Machine) supervises transfers of transmit data from registers 177 and 178 to the BTDM interface, and operations associated with such transfers; these operations including 8erialization, zero bit insertion, and special character insertion (flag, idle, abort, etc.). Details of states and operations of this unit are given below in paragraph 10.3.3.
In performing its functions, this unit uses and controls the mux 180 and auxiliary logic units indicated at 179, 180a, and 182-184. Mux 180 and logic units 179, 180a, and 182-184 are described in the description of this unit's states in paragraph 10.3.3.

10.3.1 TLl STATE MACHINE

- TLl STATE MACHINE 176A receive8 communication transmit data from TV, a byte at a time, and loads it alternately into regi8ter~ 181 and 182, depending on which is empty (if both are empty the one empty the longest is loaded). Empty states of these registers are determined from "reg order"
and "reg empty" indications (Fig. 23) in status indication re8i8ter 181, and such indications are modified as each regi8ter is loaded to indicate that the respective reBister is not empty and to point to the other register as the next BC9-90-001 99 203~911 load destination. The empty indicators are turned on by Ll Transfer State Machine unit 176C (to indicate empty status) as the last data bit in each data register is sent to the BTDM interface (see paragraph 10.3.3 below). If an external reset indication is received, SIO_RESET (not shown in this Figure), this state machine clears the status indication register and assumes its state O. States of this state machine are summarized next.
State O (Wait For Start) - Upon receipt of start si~nal from RSM, RSM_XMIT_START, this unit deasserts TLl_DONE and ~ transitions to state 1. Note that assertion of ; TLl_DONE requires coincident DONE assertions by this unit 176A and Ll Transfer unit 176C, inasmuch as TLl_DONE indicates to RSM that TLl as a whole is ready for state time swapping action.
Such coincident assertion is represented in the Figure at 176a by a dot representing a logical dot-AND connection).
State 1 (Wait For Data) - If servicing halt indication (RSM_XMIT_EOS), or abort indication (see state 5), unit transitions to state O.
- If servicing end of frame indication ! (TV_TLl_ENDFRAME) from TV, unit waits until flag ha~ been sent (by Ll transfer unit 176C, as indicated by clearing of end_of_frame indicator bit in regi8ter 181) and remain in state 1.
- IP neither of foregoing conditions pertains, and one or both data registers 177, 178 is empty and data is available to be loaded (TV_DATA_RDY being a8serted) unit transitions to state 2. In connection with this action, unit determines first if data from TV is accompanied by an end of frame indication, and if it is, unit sets end_of_frame indicator in register 181 accordingly before transferring to state Z.
- In any other circumstance, unit remains in state 1.
State 2 (Accept Byte From TV) BC9-90-001 100 203~9~

- Unit checks for abort_raised status indication in register 181. If no abort raised indication present, unit latches data into the appropriate empty data register 177 or 178, resets the empty indicator bitrelative to that register, asserts acknowledgement of data receipt to TV (by raising TLl_TV_DATA_ACK), and transitions to state 0. By checking for abort before performing the data transfer, the unit is prevented from accepting data presented by TV until the DMAC and TFM have been appropriately reinitialized.
Else (Hardware Error State) - This state is assumed only when catastrophic hardware error is detected. DONE is asserted and error state indication, TLl_INT_ERSTATE, is asserted to INT. The unit continually attempts to recover by sequencing from this state to state 0.

; 10.3.2 TFM RESET STATE MACHINE (176B) This unit monitors the TDE (Transmit DMA Enable) bit in RSM_CCR and the TLl DONE indication to determine when the transmit FIFO manager TFM has been deactivated, reinitialized and reactivated by external actions (SIO/IOP).
This mechanism is required for resuming operation after an abort has been generated due to underrun, parity error detection or specific external request. It ensures that new tata will not be sent out before the respective channel has been reinitialized.

Reset Mode - Upon activation of SIO_RESET (while this unit is in any of the numbered states below), unit sets TFM_RESET indicator bit in register 181, resets abort_raised and/or servicing_abort indicator bits in register 181 and transitions to state 0. This indicates that TFM status has been appropriately reinitialized by external action after a prior abort.
- State 0 (Wait For TFM Deactivation) BC9-90-001 101 203~911 - If TLl_DONE is not asserted and TDE bit in CCR is not active (indicating that TFM is disabled), transfer to state 1.
State 1 (Wait For TFM Reactivation) - If TLl_DONE not asserted and TDE is active (indicating that TFM has been reactivated), unit resets TFM_ RESET bit in status indicator register (Fig. 23), as well as any active abort indicators (abort_raised and/or servicing_abort) and returns : to state 0.

; 10.3.3 Ll TRANSFER STATE MACHINE (180C) This unit is responsible for interfacing bit serially to the BTDM bus, and for performing associated functions (serialization, zero bit insertion, flag generation). When an external reset (SIO_RESET) is detected, this unit resets - the relevant part~ of the status indication register and assumes state 0.
This unit performs its operations by using and controlling mux 180, and auxiliary logic 179, 180a, and 182-184. Mux 180 performs the data serialization function relative to data registers 177 and 178 as required for transferring contents of those registers bit serially to the network via the BTDM interface. In controlling mux 180 relative to these registers, unit 176C uses pointer indications provided in counter-registers 182-184 to determine byte sources of input to mux 180, and selection of particular bits from the selected source. Unit 176c ad~usts these pointer indications as they are used.
: Register 183 (Transmit Layer 1 Data Source Selector regi8ter) indicates the source of the next byte to be transferred (register 177, register 178 or special character ' generator 179), and register 182 (Tran8mit Data Bit Pointer register) indicates the next bit to be tran8ferred from the ; selected byte source. As bits are transferred from a source register, the bit pointer is incremented to point to the next bit in that source, and as the bit pointer reaches a J value corresponding to the position of the last bit, the transfer of that bit is accompanied by actions relative to indicator register 181 to set appropriate status indication BC9-90-001 102 203~91~

(e.g. indication of empty status relative to register 177 or 178).
Counter-register 184 (Transmit Layer 1 Transparency Counter) is used for determining zero bit insertion during transmission of data relative to channels operating under bit-oriented protocols. In such channels, transmit data must be prevented from appearing as special (flag, idle or abort) characters. For this purpose, it is necessary to prevent the appearance of more than 5 consecutive logical l signals in the transmit data stream. Counter 184 is used to count consecutive logical 1 data signal transfers relative to registers 177 and 178, and when the count value reaches 5, mux 180 is directed to insert a zero bit (using 0 generator 180a as its source) and the count value is reset to 0.
Circuits 179 generate abort, idle and flag characters, individual bits of which are selected by mux 180 for transfer to the network when needed to signal abort, idle or flag (frame end) conditions in the outgoing signal bit stream.
States of unit 176C are now summarized as follows.

If SIO_RESET is asserted while the unit is in any state, the unit clears the status indicators in register 181 and transitions to state 0.
State 0 (Wait For Start) - Upon detecting RSM_XMIT_START, unit advances to state 1. Else unit remains in state 0. No 9ignal~ are asserted and no status indications are modified in this state. In this state, TLl time swap status, TLl_TS01, is valid for time swap storage by RSM, and for next channel loading from RSM.
State 1 (Determine Current Status) - protocol code in RSM_CCR is evaluated to determine if current channel is "clear" (no protocol) or - operating on a bit oriented protocol (HDLC/LAPB/LAPD).
- if bit oriented, unit checks abort request option (AR field in RSM_CCR) to determine if abort should be forced. Abort is also forced if data parity error indication, TV_PARITYE, is received. If abort pattern needs to be sent, the bit pointer field TLDBP in TLl_TS01 is reset to 7 (8 if running inverted HDLC), and a sta$us indicator bit is set to indicate abort being serviced. Also, the source selection indicator TLDSS (shown as residing in register 183 in TLl but in practice residing in a register in TV and presented as an input to TLl) is set by TLl to indicate to mux circuit 180 that abort generation logic (part of special character generation logic 179) is to be selected as the current byte source of signals to be sent to BTDM. When the TDBP value sequences to 0 (indicating that the re~uired pattern has been sent completely), TLDSS and TDBP are updated to point to a source of inter-frame fill patterns (another part of logic 179) designated by RSM_CCR as the next data source (this will only occur at the beginning of channel initialization). Next state is state 4.
- if clear channel, next state is state 2.
State 2 (Clear Channel Waiting For Ll to Take Data) - if transmit data request, BTDM_TDATA_REQ, i~
active present data bit desi8nated by bit and register pointers, decrement bit pointer (TLDBP) and check for underrun error. If underrun indicator is set clear internal indications and determine register source of last byte sent (via source pointer TLDSS), and set up source pointer to continually send out the same byte (as a fill pattern to prevent illegal octets from being ~' transmitted). Next state is state 3.
~ State 3 (Clear Channel, After Ll Has Taken Data) J - If transmit data request is inactive, check data pointer TDBP and indicators to determine if underrun error has occurred (both data register8 empty and TLDBP value i~ 0). If underrun, reset pointer TLDBP, retain source register indication, and assert interrupt indication to INT. If not ;

BC9-90-001 104 2 03~ 9 underrun, but TLDBP value 0, set TLDSS to point to other data register as source and set TLDBP value to 8. Next state is state 2 unless the transmit data request has not gone inactive (in that case remain in state 3 and wait for it to go inactive).
State 4 (Bit Protocol, Waiting For Ll To Take Data) - If tran3mit data request is active, present bit designated by bit and register pointers and decrement bit pointer. Check transparency counter (TLTC in TLl_TSOl), and present stuff bit if needed ~count is 5 and TLDSS is pointing to one of the data registers). Increment TLTC if 1 data bit is being sent, and reset TLTC if O data bit is being sent. Next state is state 5, unless end of slot indication is being asserted by RSM
(in latter case, next state is state 0). If the transmit data request is inactive and an unserviced abort request or parity error is outstanding, next state is state 5, else remain in state 4.
State 5 (Bit Protocol, After Ll Has Taken Data) - If transmit data request inactive, check abort and parity error indicators and data pointer. If indicators require abort or parity error action, reset TLDBP to 7 (8 if inverted HDLC) and set TLDSS to select abort pattern as source. If no abort is needed, TLDBP is 0 and data i9 still being sent (no end of frame indication) determine which register needs to be sent next and set TLDSS
to indicate that. If no data is available select closing flag or fill pattern (TV_TLl_ENDCHAIN
overrides any end of frame indication in determining the fill pattern to be sent). Underrun occurs if both data registers are empty and there is no end of frame indication from TV. Upon detecting underrun, appropriate indicator bit is set and TLDSS is set to point to the abort pattern generator as next source. Next state is state 4.

10.4 TLl TIME-SWAPPED WORD TLl TSOl The TLl time swapped word TLl_TS01, shown in Fig. 24 and described below, comprises two 8-bit fields TLDl and TLD2, a 4-bit field TLDBP, a 3-bit section TLTC, and a 9-bit field TLSI. The sources of these fields in Fig. 22 are:
registers 177 and 178 for TLDl and TLD2, register 182 for TLDBP, counter-register 184 for TLTC, and register 181 for TLSI. These fields have the following usages in TLl.

TLDl and TLD2 (TLl Data Registerl and TLl Data Register 2) - These ref1ect the contents of data registers 1 and 2 shown at 177 and 178 in Fig. 22.
These registers receive data from TV in alternating ("ping-pong") fashion.
TLDBP (TLl Data Bit Pointer) - Points to the next bit to be sent from the current data source to the BTDM. The current source is indicated by TLDSS (Fig. 26 and register 183 in Fig. 22), and can be data register 1, data register 2, or the abort/idle/flag generator 179 (Fig. 22).
TLTC (TLl TRANSPARENCY COUNT) - counts consecutive 1 data bits sent out in bit protocol channels, and stuff bit i~
inserted when count value becomes 5; value is incremented when 1 data bit is sent and reset when either stuff bit or 0 data bit is 3 sent.
TLSI (TLl STATUS INDICATORS) - reflects the latest state of the status indicators (Fig. 23).

10.5 TRANSMIT VALIDATE (TV) FUNCTIONS

The tran8mit valitate element (TV) interfaces between the transmit FIFO manager (TFM) ant TLl for transferring transmit data. TV operates in time division multiplex, in ~ynchronism with BTDM time slots defined by RSM, and undergoes 8tate swapping via RSM and TSI relative to active ; channel slots. Ma~or functions of TV are:
DATA TRANSFER

. .

~ BC9-90-001 106 203~91 Transmit data bytes are fetched from TFM to an internal data register, one at a time, processed as described below, and transferred to TLl. Fetch requests are issued to TFM when the internal register is empty.
CRC GENERATION -In protocol oriented channels, each fetched byte of transmit data is applied bit-serially to calculation logic which performs both CRC remainder calculation and parity checking. After the last data byte of a protocol frame has been passed to TLl, the 2-byte CRC remainder is inverted and transferred to TLl, high order byte first.
CRC BYPASS
Relative to data in clear channels (e.g. digitized voice), CRC generation and parity checking are bypassed; i.e. the application of these functions is selected as a function of the channel type field CT in the CCR.
.
10.6 TV LOGIC

Referring to Fig. 25, TV comprises data register 190, state machine 191, CRC calculation logic 192, and multiplexor 193. Register 190 receives transmit data from TFM, via TFM_TV_DATA shown at 194, and its output is applied to CRC calculator 192 and multiplexor 193. The output of calculator 192 is applied to a second input of multiplexor 193. Multiplexor 193 is controlled by state logic 191 to select its input from data register 190 while data is being handled. In protocol oriented channels, at frame end, multiplexor 193 is controlled to select its input rom calculator 192.
Calculator 192 performs CRC residue generation and parity checking. If a parity error occurs, circuit 192 conditions state logic 191 via not shown connection to produce output indication of such, TV_PARITYE.
State machine 191 has an input connected to SIO_RESET
line and is reset when SIO activates that line. ~nit 191 receives controlling inputs from RSM defining end of slot and start of slot processing points in time (RSM_XMIT_EOS
and RSM_XMIT_START, respectively). Prior to the start of . .

~C9-90-001 107 Z03491~

processing relative to an active slot, state information is transferred by RSM from TSR to TV (via RSM_TS_~US
accompanied by RSM_TV_LOAD), and channel configuration information is presented via RSM_CCR.
State logic 191 distinguishes empty status of register 190, and at such times presents data requests to TFM, via TV_TFM_REQ. When ready, TFM presents a data byte at TFM_TV_DATA accompanied by acknowledge signal at TFM_TV_ACK.
;When register 190 contains data, unit 191 presents a data ready indication to TLl, via TV_TLl_DATA_RDY, and actuates multiplexor 193 to present the data at TV_TLl_DATA. When the data is accepted, TLl returns acknowledgement at TLl_ACK.
Relative to protocol oriented channels, TFM presents indications to TV of end of frame conditions, TFM_TV_EOF, and end of chain conditions, TFM_TV_EOC. TV uses these indications to insert CRC bytes and prepare for terminating its operations.
At end of slot, indicated by RSM_XMIT_EOS, TV prepares for having its time swap state saved. This status is continually presented at TV_TSOl, but TV must present its done indication to RSM, TV_DONE, before the saving function is executed.

10.7 TV STATE MACHINE

State machine 191 has the following repertoire of : states.
RESET STATE
-- This is the state assumed when SIO_RESET is -activated. The CRC calculator is cleared and the state machine is forced to its idle state (state O)--STATE 0 (IDLE STATE) -- Wait for RSM_XMIT_START, assert TV_DONE and go to state 1.
STATE 1 (STATUS DETERMINE STATE) - Determine status of the current channel by examining channel type and protocol defining codes in RSM_CCR.
- In clear channel, check is made to ensure TV
i8 not attempting to send CCR remainder BC9-90-001 108 Z03491~

(valid only for protocol mode). If TV data register is full a~sert TV_DATA_RDY. If TV
data register is not full, assert TV_TFM_REQ
request to TFM for more data. Next state is state 2.
- In ~IT PROTOCOL channel, examine abort indications from TLl. If an abort condition exists, next state is state 8. If data register has valid data, assert TV_DATA_RDY
to TLl and next state is state 2. If data register is not valid send CRC bytes to TLl or assert TV_TFM_REQ to TFM as needed. If more data is requested, next state is state 3. If first CRC byte is being sent, next state i8 state 5. If second CRC byte is being sent next state is state 6.
STATE 2 (WAIT FOR TLl_ACK) - If TLl_ACK is active lower TV_DATA_ RDY and reset valid data bit relative to data register. If a bit protocol channel is being served, next state is state 7 for CRC calculation. In this situation, set CRC load control signal to indicate start of calculation. Otherwise, next state i~ state 1 to request more data from TFM. If RSM_XMIT_EOS is active before TLl acknowledges data transfer, lower TV_DATA_RDY and go to idle state 0 to prepare for swap (this is one example of the "adaptive" facility discussed earlier which allow9 such autonomous elements to alter their states before swapping when end of slot indication from RSM coincides with an unanswered request for data transfer relative to another element). In any circumstance other than foregoing, the next state is state 2.
STATE 3 (WAIT FOR TPM_ACK) - If TFM_ACK and TFM_TV_DATA are active (notice that TFM_TV_DATA is further qualified by TPM_TV_NDI to be actlve) load data register and set valid data status relative to data register. If TFM_TV_DATA
and TFM_TV_EOF are active this indicates last byte ; of frame is being transferred from TFM, therefore ~' ~C9-90-001 109 203~91~

set associated control indication to remember to send out CRC bytes next after TLl has acknowledged receipt of last byte indicated by TFM and proceed to state 6. Otherwise go to state 2.
STATE 5 (SEND FIRST CRC BYTE) - If TLl_DATA_ACK is active lower TV_DATA_RDY to prepare for second CRC byte transfer and go to state 6. If RSM_XMIT_EOS is active before TLl acknowledges byte transfer, lower TV_DATA_RDY and go to idle state 0. If TLl_DATA_ACK remains inactive, next state is state 5.
STATE 6 (SEND SECOND CRC BYTE) - If TLl_DATA_ACK is active, lower TV_DATA_RDY, prepare for data byte transfer and go to state 1.
Also preset CRC counter for next frame. If RSM_XMIT_EOS is active before TLl acknowledges byte transfer, lower TV_DATA_RDY and go to state 0, else next state is state 5.
STATE 7 (CALCULATE CRC) - Wait until CRC count is 0, then next state is state 1 to reque~t more data, else next state is ~, state 7 STATE 8 (ABORT STATE) j- If RSM_XMIT_EOS is active next state is state 0, 'else next state is 1. Preset CRC count for next frame).

10.8 TV STATE SWAP WORD TV_TS_01 The state swap word for TV, TV_TS01, is shown in Fig.
26. It contains an 8-bit field TVDR, a 16-bit field TVCR, a 1 bit field TVDV, a 2 bit field TVDS, a 1 bit field TVOE, a 1 bit field TVEC, a 1 bit field TVDP and a 2 bit field TLDSS. The usaRe and significance of each of these is discussed below.
.
TVDR (Transmit Validation Data Register) - Content of data register 190 TVCR (Transmit Validation CRC Register) - State of the cumulative CRC remainder calculation for the current frame. When end of frame is encountered this field is appended to the outgoing data passing to TLl.
TVDV (Transmit Validation Data Valid) - State of this bit indicates if data register has valid data (on indicates valid data to be forwarded, off indicates data register is empty) TVDS (Transmit Validation Data Select) - Pointer to source of next byte to be sent to TLl (source is one of: TV data register, TV CRC
register upper 8 bits or TV CRC register lower 8 bits) TVOE (Transmit Validation Operational Error) - When active this bit indicates that an operational error has been detected (e.g. invalid state), and causes all TV processing operations to be halted.
TVEC (Transmit Validation End Of Chain) - An end of chain indication received from TFM.
Requires the last byte of CRC transfer to TLl to be accompanied Sy an end of chain indication preparing the latter for fill pattern transmittal.
TVDP (Transmit Validation Data Parity) - Odd parity for contents of TVDR
TLDSS (Transmit Layer 1 Source Select) - In order to minimize the number of time swapped words required relative to TSl, these bits are saved through TV and used by TLl at start of channel processing. These 2 bits act as a pointer to one of four sources of next data byte to send out in TLl: data registers 1 and 2 in TLl, source of flag signal in TLl or source of idle/abort pattern in TLl.

11 FIFO RAM_(FIFORl AND FIFO MANAGER PARTITIONS

FIFO RAM (FIFOR) and the FIFO managers (RFM and TFM) cooperate to queue communication data in transit between the DMA Controller (DMAC) and the synchronous transmit and receive elements (RLl, RV, TLl, TV). Llke time swap RAM
(TSR), FIFOR include~ logic for directing its data flow relative to other partitions.

BC9-90-001 111 203491~

11.1 FIFOR STRUCTURE

Referring to Fig. 27, FIFOR partition comprises a 128 x 36 static RAM array 200 receiving inputs through bus selector circuits 201 (from SIO, RSM, RFM, TFM, and DMAC) and providing outputs at 202 to a data bus (FIFOR_DATA) indicated at 203. Bus 203 extends to SIO, RFM, TFM and DMAC.
State machine logic 204 operating in association with request latches 205 controls the operations of selector 201 and array 200.
Array 200 contains 128 data word storage spaces, each word space consisting of 36 bit storage spaces (32 data bit spaces and 4 parity bit spaces in each word space).
Referring to Fig. 7, in the exemplary primary rate ISDN
application half of the space allotted to each channel is reserved for transmit DMA configuration register words TDCRl, TDCR2 and the other half is reserved for receive DMA
configuration register words RDCRl, RDCR2. The RDCRl,2 and TDCRl,2 spaces of each active channel store status and communication data information relative to respective channels. Bit usage in each word space is discussed below in reference to Figs. 33-36.
Data inputs to array 200 from SIO, RFM, TFM and DMA
control (DMAC) partitions are provided through selector circuits 201. Data outputs are directed to those partitions via bus 203, with specific destinations designated by acknowledge outputs from state logic 204 at 206. Addressing of the array is direct in certain instances and indirect in others. In each instance, the accessing partition provides an indication to request latches 205 of the read or write direction of the desired access (e.g. SIO_FIFOR_RD or SIO_FIFOR_WR). In re9pect to such read/write request9, TFM
and DMAC have separate inputs for requesting reading or writing of either 1 word or 2 consecutive words (RFM and SIO
alway9 is9ue 1 word read/write reque9t5).
When SIO i9 acce99ing the array, it provides an explicit address input, via SIO_ADDRESS_~US, which selector 201 transfers to address input of array 200. If data is being written, a data word supplied at SIO_DATA is transferred by selector 201 to the data input of the array.
Data being fetched to SIO (or the other partitions) appears oC9-90-001 112 Z03~91 at bus 203. FIFOR_SIO_ACK at 206 designates SIO as destination.
When data is being written to the array from TFM or RFM, or fetched from the array to those partitions, address input to selector 201 is provided indirectly as a combination of the time slot indication from RSM, RSM_TSI, and select functions appearing at output 207 of state logic 204. RSM_TSI effectively addresses the block of (4 word) positions assigned to the respective channel, and select functions at 207 provide addressing offset to a particular word location in the block. In respect to receive data tran~fers from RFM, which are one byte at a time, RFM
provides additional address input RFM_FIFOR_BPP (BPP
represents "byte position pointer") resolving the address selection to a byte position within a selected word space.
When RFM is writing to the array, it presents a byte of receive data at RFM_FIFOR_DATA along with byte position pointer RFM_FIFOR_BPP; the latter designating a specific byte location within the block addressed by RSM_TSI and word 8elected at 207. When TFM i9 writing to the array, it writes only status word information, presenting the latter at TFM_TDFSW_DATA. When data is being fetched to either RFM or TFM, a full wort is output at bus 203 along with an associated acknowledge at 206, FIFOR_RFM_ACK or FIFOR_TFM_ACK serving to designate the destination partition.
When DMAC is accessing the array, addressing inputs are developed as combinations of channel number inputs from DMAC, DMAC_CHN_NBR, and select output~ at 207. Data is presented for writing at DMAC_FIFOR_DATA, and fetched data is transferred to DMAC via bus 203 along with FIFOR_DMAC_ACK
at 206.
Output~ from array 200 to bus 203 are pa~sed in parallel to parity check circuit 202a which performs a parity check operation on the data. If parity error is detected, that circuit furnisheg an error indication, FIFOR_P~RITY_ERROR, at 202b. Such error indication i~
pre~ented to the requesting partition, and u~ed by the latter to provide error interrupt indication to INT
partition (for logging of related statu~ in CEISR/TSR, and ~C9-90-001 113 203491 reportage to IOP as a channelized error condition; see later description of INT).
Read/write and cloc~ing functions of the array are controlled via outputs of logic 204 at 20~ (derived from inputs to request latches 205). Single read or write requests take 3 machine clock/state cycles (3 x ~0 ns) to complete. One cycle sets up the request selection functions, and activates the read/write and not-shown clock enabling inputs of the array. A next cycle latches the clock enablement and selection functions to provide glitch free clocking to the array. A next third cycle activates the acknowledge outputs and deactivates clocking and selection signals. Successive (double word) accesses are completed in cycles, by overlapping the first cycle of the second access with the last cycle of the first access.

11.2 FIFO RAM STATUS AND DATA

In FIFOR, each communication channel slot is allotted 4 word spaces (Fig. 7). Two of these spaces (RDCRl, TDCRl) hold DMA control information relative to the respective channel, and the other two (RDCR2, TDCR2) serve as buffers in which data being received and transmitted is queued.
Details of bit usage in the DMA configuration register word spaces RDCRl,2 and TDCRl,2 of array 200 are indicated in Figs. 33-37. RDCRl and TDCRl are used to hold certain ~tatus and control parameters relative to respective (active) channels, and RDCR2 and TDCR2 spaces are used as 4-byte queues relative to receive and transmit communication data passing through respective (active) channels.
In each active channel having a receive path, receive data is transferred one byte at a time from RV via RFM into (specifically addressed) byte po~itions in the respective RDCR2 space in array 200. Relative to each actively transmitting channel, tran~mit data is transferred one byte at a time from TDCR2/FIFOR to TFM, and from the latter to TV. In the transfer to TFM, the full word TDCR2 is fetched, and byte selection is performed by TFM. Transfers from RFM
to array 200 and from the array to TFM are conducted during respective synchronous (time-swapped) operations of RFM and TFM de9cribed below.

~C9-90-001 114 When an RDCR2 space becomes filled with 4 bytes, RFM
posts a request to the DMARQ (DMA Request Queue) which causes the DMAC partition operating (asynchronously) in association with MIO partition to transfer the 4 bytes to a space in external (lOP/host) memory de~ignated by address information in the re~pective RDCRl field named RDCA
(Receive DMA Current Address; 22 bits). The external memory is addressed as a circular buffer (refer to DMAC detailed description which follows). The remaining 10 bit spaces in RDCRl consist of 8 reserved bit spaces (RES), a l-bit space RPE (Receive Parity Error) for indicating parity error detected at the FIFOR output to DMAC, and a l-bit space RBC
(Receive Boundary Check) for indicating boundary check conditions encountered during the transfer (refer to DMAC
description).
Similarly, when a TDCR2 active channel word space in FIFOR becomes empty, TFM posts a request to DMARQ causing DMAC (asynchronously) to fetch data from external (IOP/host) memory using control information provided in part in the a~sociated TDCRl space (refer to DMAC description for full discussion of the TDCRl fields). Briefly, the fields in each TDCRl word consist of: 7 reserved bits (RES), a 16-bit TDBC
(Transmit DMA Byte Count) field defining the byte length of the current external data buffer space, three 2-bit fields and three l-bit fields. The 2-bit field~ are: TBC (Transmit Buffer Count) pointing to the next byte in TDCR2 to be transferred to TV, TOPQ (Top of Queue) pointing to the first valid byte location in TCR2 (and is particularly needed when less than 4 bytes have been loaded into TCR2), and PE
(Transmit DMA Parity Error) indicating if parity error occurred in the DMAC transfer relative to either or both external memory and FIFOR. The l-bit fields, which represent external access condition indications settable by DMAC
(refer to DMAC description for specifics), are: ECD (End of ` Chain Detected), EFD (End Of Frame Detected), and NDI (No Data Indicator).

11.3 FIFO RAM STATE MACHINE STATES

To simplify the following description, the l-bit and 2-bit status functions of TDCRl relevant to FIFOR are ':

:. . . ~
.

2034bll ~C9-90-001 115 referred to collectively as the transmit DMA FIFO status word (TDFSW), the DMAC channel number addressing input to FIFOR is termed the DMAC address, and the time slot addressing indication from RSM to FIFOR is called the RFM
address or TFM address according to which partition is actually accessing FIFOR.
STATE O (ARBITRATION STATE):
- All requests for accessing FIFOR are constantly latched (at request latches 205). This state prioritizes the requests in accordance with predetermined arbitration rules and loads data as~ociated with the prevailing request into FBS
. (FIFOR Bus Selector) 201.
~ - Priorities in descending order are: TDFSW updates ; from TFM, DMAC 2-word read requests, DMAC one-word write requests, DMAC one-word read request, DMAC
2-word write request, DMAC write parity error, RFM
read request, RFM write reqùest, TFM one-word read request, TFM 2-word read request, SIO read request, and SIO write request.
- When the selected request is for writing a TDFSW
update for TFM (TFM_FIFOR_WRl), the address and the updated TDFS~ data (TFM~TDFSW_DATA) are selected by FBS (FIFO Bus Selector) 201. The first byte select, write and clock enable control inputs are activated. In this circumstance the next state ; is state 11.
- When the request is for reading two words from FIFOR to DMAC (DMAC_FIFOR_RD2), DMAC is assumed to be requesting both the current external address, stored in the RDCA field of the RDCRl word space addre8sed by the DMAC address, and the receive data 8tored in the as80ciated RDCR2 space (both ~paces desi8nated in part by DMAC_CH_NBR). The associated word space~ are 8equentially adtressed, and the read controls are activated. Next state is state 1.
- When the request is for writing one word to FIFOR
froln DMAC (DMAC_FIFOR_WRl), it is assumed DMAC is updating the word containing the associated channel's RDCA, and the associated FIFOR addre8s ~C9-90-001 116 is selected by FBS. The array control signals are activated for write. Next state is state 18.
When the request is reading one word to DMAC
(DMAC_FIFOR_RDl), DMAC i~ assumed to be requesting the TDBC in the associated channel's TDCRl space.
The re~pective address is selected by FBS, and the array signals are activated for write. Next state is state Z.
When the request is for a 2-word write from DMAC
~DMAC_FIFOR WR2), DMAC is storing both the TDBC
and transmit data. FBS selects the appropriate word addresses sequentially, the array controls are activated for successive writes, and next state i~ state 12.
When the request is for writing a parity error indication from DMAC to FIFOR (DMAC_FIFOR_PE_WR
request latched), a parity error has been detected by the DMAC as the results of either DMAC requests one or two-word reads from FIFOR. The respective TDCRl or RDCRl is selected through the combination of DMAC_CHN_NBR, DMAC_RCV_REQ, and FBS selects.
Next state is state 14.
When the request is an RFM read (RFM_FIFOR_RD
active), RFM is requesting status information from the associated RDCRl. Address selection is made accordingly (as a function of RSM_TSI and word position selection outputs from the state machine), and controls are activated for a read.
Next state is state 4.
When the request is a one byte write from RFM
(RFM_FIFOR_WRl active), for transferring a byte of receive data, byte address is selected by FBS in response to RFM_FIFOR_BPP and controls activated for write. Next state is state 15.
When the request is a transmit data read to TFM
(TFM_FIFOR_RDl active), the required TDCR2 address is selected by FBS (as a function of RSM_TSI and internally generated word position indications) and the controls are activated for a read. Next state is state 5.

~C9-90-001 117 zo349~

- When the request is a 2-word read for TFM
(TFM_FIFOR_RD2), TFM is seeking access to both the TDCRl and TDCR2 spaces of the respective channel.
These spaces are addressed sequentially (as a function of RSM_TSI and internally generated word position selection signals) and the controls are -~ activated for reads. Next state is state 6.
- When the request is a one word read for SIO
(SIO_FIFOR_RD active), the address furnished by SIO (SIO_ADDRESS) is selected, array controls are activated for read, and next state is state 7.
- When the request is a word write to FIFOR from SIO
(SIO_FIFOR_WR active), SIO address is selected, controls are activated for write and next state is state 17.
STATE 1 (READ RDCA TO DMAC):
i~ - Array controls activated to access the array for reading RDCRl location of DMAC address (DMAC_CH_NBR). Next state is state 8.
STATE 2 (READ TDBC TO DMAC):
~:~ - Array controls activated to access array for reading TDCRl location of DMAC address. Next state is state 20.
STATE 3 (WRITE TRANSMIT DATA AND START WRITE FOR UPDATED
TDBC):
- Assert FIFOR_DMAC_ACK to inform DMAC transmit data has been written and updated TDBC and TDFSW must be presented to be written next. Array enable is deactivated after this, but select and write acces~ controls held active. Next state is state 13.
STATE 4 (READ ~OUNDARY CHECK AND PE STATUS TO RFM):
- Array controls activated for read relative to associated channel's RDCRl, then deactivated. Next state is state 21.
STATE 5 (READ TRANSMIT DATA TO TFM):
- Array controls activated to read associated channel' B TDCR2, then deactivated. Next state is state 23.
STATE 6 (READ TDFSW TO TFM):

BC9-90-001 118 zo349~

- Array controls activated to read associated channel's TDCRl, then deactivated. Next state is state 10.
STATE 7 (READ WORD TO SIO):
- Array controls activated to read word at SIO_ADDRESS, then deactivated. Next state is state 22.
STATE 8 (FIRST ACK TO DMAC ON 2 WORD RECEIVE SIDE READ):
- FIFOR_DMAC_ACK asserted to DMAC. DMAC address jad~usted to second word (RDCR2) location of same channel. Clock enable activated for second read access. Next state is state 9.
STATE 9 (READ RECEIVE DATA AFTER DMAC):
- Array controls activated for second read then deactivated. Next state is state 20.
STATE 10 (FIRST ACK TO TFM; 2 WORD READ, TDESW & TRANSMIT
DATA):
, - FIFOR_TFM_RD_ACK asserted to have TFM accept TDFSW
info on bus 203, and prepare to accept transmit data next. Clock enable activated for next read and TFM address ad~usted for next word (TDCR2) ~, location. Next state is state 16.
STATE 11 (UPDATE TDFSW FOR TFM):
'- Array clock activated for writing to appropriate .jTDFSW/TDCRl space. Clock enable deactivated. Next state is state 19.
STATE 12 (WRITE TRANSMIT DATA FOLLOWED BY TDBC):
, - Array clock activated for writing transmit data from DMAC to TDCR21 space of associated channel.
Addres~ ad~usted to next word space (that of associated TDCRl). Clock deactivated. Next state i i8 8tate 3.
STATE 13 (WRITE TDFSW AND TDBC AFTER TRANSMIT DATA):
- - Clock activated to acce~s array for writing to TDCRl space, then deactivate. Next state 20.
STATE 14 (WRITE DMAC PARITY ERROR):
- Clock activated to acce~s array to write to TDCRl PE space. Clock deactivated. Next state 20.
STATE 15 (WRITE RECEIVE DATA BYTE FOR RFM):

, . , :................................... , , . , : ,, ~o349~

- Array accessed to write data byte from RFM to RDCR2 space of associated channel/slot. Clock deactivated. Next state 21.
STATE 16 (READ TRANSMIT DATA TO TFM AFTER HAVING READ
TDFSW):
- Array accessed to read transmit data from associated channel's TDCR2 space to TFM (TFM
selects appropriate byte). Clock deactivated. Next state 23.
STATE 17 (WRITE DATA WORD FOR SIO) - If a fla~ is not detected examine check register for idle or abort pattern (7 or more consecutive l's). If such is detected, set appropriate idle or abort indicator relative to INT, clear data register and reset bit count. If RDATA_VALID is inactive, next state is state l; else, next state is state 3.
- Array accessed and SIO_DATA word written to location of SIO_ADDRESS. Clock disabled. Next state 22.
STATE 18 (WRITE RDCA FOR DMAC):
- Array accessed to write to RDCRl space of channel number indicated by DMAC. Clock enable deactivated. Next state 20.
STATE 19 (ACKNOWLEDGE TDFSW WRITE OF TFM):
- FIFOR_TFM_ACK assert~d. Array controls deactivated. Next state 0.
STATE 20 (ACKNOWLEDGE TO DMAC):
- FIFOR_DMAC_ACK asserted. Array controls deactivated. Next state 0 STATE 21 (ACKNOWLEDGE TO RFM):
- FIFOR_ACK_RFM asserted. Array controls deactivated. Next state 0.
STATE 22 (ACKNOWLEDGE TO SIO):
- FIFOR_SIO_ACK asserted. Array controls deactivated. Next state 0.
STATE 23 (ACKNOWLEDGE TO TFM OF TRANSMIT DATA READ):
- FIFOR_TFM_RD_ACK asserted. Array controls deactivated. Ne~t state 0.

_1.4 RFM FUNCTIONS

BC9-90-001 120 zo349~

RFM (Receive FIFO Manager) transfers receive data bytes between RV and specifically addressed byte locations in RDCR2 word spaces of FIFOR, and by requests to DMARQ
initiates transfers of receive data to host IOP memory from FIFOR (under the direction of DMAC). RFM also can access status information in RDCRl spaces of FIFOR (e.g. for ascertaining if parity error occurred during related DMAC
transfers from FIFOR to host IOP memory).
RFM operates synchronously with RV and RLl, as a time division multiplexed engine, to service active channels in synchronism with appearances of respective channel time - slots at BTDM. As is the case for the other synchronous elements, RFM is started and halted by RSM at regular time intervals related to said slot appearances. When signalled to halt (RSM_RCV_EOS), RSM transfers to an idle state and asserts RFM_DONE as indication to RSM that it is in a stable state suitable for time swap exchange of status words (RFM_TS01 and RFM_TSO2) associated with ending and beginning channel slots. The new status words are loaded in response to load control signals from RSM (RSM_RFM_LOADl and RSM_RFM_LOAD2). After loading of new channel status RFM is signalled to start by RSM_RCV_START.
-. In operation relative to any active channel, RFM
s accepts receive data bytes presented by RV, and stores them j ~n specific byte locations of associated channel word spaces : RDCR2 in FIFOR. As each such space becomes filled, RFM posts a request in DMARQ to cause DMAC to transfer the contents of that space (asynchronously) to external IOP memory. RFM also processes status information received from RV, keeps track of the number of bytes received in each frame, and indicates end of frame status to the INT partition. It also processes status conditions posted by DMAC in the RDCRl spaces of FIFOR and reports po8ted boundary check and parity error condition8 to the INT partition.

11.5 RFM TI~E SWAPPED WORDS 1 AND 2 The time swapped words transferred between RFM and TSR
(RFM_TS01 and RFM_TS_02) under control of RSM are indicated in Figs. 29 and 30.

, ,................. . . . . . .

Z0349~

RFM_TSOl comprises: an 8-bit field RFMD containing any data received from RV and not yet transferred to FIFOR; a l-bit field RFMDP indicating the parity of data stored in RFMD; a 2-bit field RFMBP holding a byte pointer to the next byte position in FIFOR/RDCR2 into which receive data for the current channel is to be transferred; a 3-bit field RFMS
indicating the current state of RFM relative to the respective channel as one of: idle (no valid data received), active (valid data received for placement in FIFOR), or "between frames" (an idle, abort or end of frame indication has been received from R~, requiring associated status po~ting by RFM to INT once the associated FIFOR contents have been DMA'd to IOP); an 8-bit field RFMIS indicating interrupt status of RFM as one of: idle pattern received, end of frame detected, abort pattern detected, octet alignment error detected, CRC error detected, buffer overflow condition detected relative to FIFOR/RDCR2; and 8 reserved bit positions (unused presently but available for other indications).
RFM_TS02 comprises a 16-bit field RFMFBC, indicating the number of bytes received by RFM relative to the respective channel during the current frame, and 16 reserved/unused bits. Upon detection of end of frame, idle or abort condition, RFM ad~usts the value in RFMFBC (to ensure that CRC bytes are not included in the count), and the ad~usted value together with the value of RFMIS in RFM_TS01 are passed to (picked up by) INT during the latter's interrupt request handling process.

11.6 RFM LOGIC

The logical organization of RFM is indicated in Fig.
28. RFM compri8es 8tate machine logic 220, bus selector 221 for tran8ferring receive data ant status information pre8ented by RV (in re8ponse to 8elect functions provided by 8tate logic 220), data regi8ters 222 for receiving the information selectet by selector 221 (in response to control 9ignals provided by ~tate logic 2Z0), and time 8wap ~tatu8 register9 223 for holding the currently effective time 9wap 8tatus word8 of RFM (this partition has two such words and two registers 223 for holding them).

:, ".

BC9-90-001 122 ~

In normal operations of RFM, state logic 220 would make the following transitions: start in idle state (state 0), transfer to state 4 upon reception of RSM_RCV_START to wait/check for indication that the FIFOR buffer is not full (if buffer is full wait in state 4 until it is not full before proceeding), transfer to state 10 to check for FIFOR
parity error and also to check for boundary check condition by reading RDCRl status posted by DMAC. In the absence of parity error or boundary check conditions, transfer to state 1, to wait for data transfer request from RV, then to state 5 to store data in FIFOR, and return to idle state O upon receipt of end of slot indication RSM_RCV_EOS. Details of state logic 220 follow.
State O (Idle State) - This is the state in which RFM can safely swap its time swap status words. In this state, the RFM_DONE indication can be asserted (following receipt of RSM_RCV_EOS), allowing RSM to operate TSR to store the current status of RFM presented from regi9ters 223 to outputs RFM_TSOl and - RFM_TS02. Also, in this state new status can be loaded into registers 223 from RFM_TS_BUS in response to load control signals from RSM
(RSM_RFM_LOADl, RSM_RFM_LOAD2). After loading status RSM starts RFM processing by assertion of RSM_RCV_START.
: - In this state, RFM waits for RSM_RCV_START. When this signal is active, the state of the receive DMA enable bit (RDE) in RSM_CCR is checked. If that bit is off (current channel not enabled for reception) next state is state 8. If that bit is on, and RFM state status (RFMS and RFMIS fields in RFM_TSOl) indicate previous error in this channel, go to state 8. else, go to state 4.
State 1 (Examine newly loaded status in RFM_TSOl, 02) - State status is checked to initiate the ta9k9 required relative to the current state. If halted by RSM while in this state, go to state 0. If 9tatus indicates previou9 detection of idle pattern, go to state 2. If status indicates data wa9 received previously but has not yet been . ~

. , , , . . . ~ , . .. : .:: ,., 20349~

written to FIFOR, raise write request to FIFOR, RFM_FIFOR_WR_REQ, and go to state is state 5. If status indicates previous receipt of end of frame indication from RV, go to state 9 to report same to INT. If status indicates previous detection of parity error or boundary check condition, go to state 8. If status indicates severe logic error encountered, return to state O.
State 2 (Process Data And Frame Status Received From RV) In this state, data and status (end of frame, abort or idle) presented by RV are processed.
RV_RFM_REQ active indicates data is valid at RV_RFM_DATA input to selector 221.
RV_RFM_RE Q STATUS active indicates status is valid at RV_RFM_STATUS input of selector 221. Depending upon which input is active, data or status, respective acknowledgement, RFM_RV_D_ACK or RFM_RV_S_ACK is activated.
If end of frame status and data are received from RV simultaneously, state status is set to indicate end of frame reception, and data receipt acknowledgement is given to RV by RFM_RV_D_ACK.
Status of FIFOR data buffers in RDCR2 is checked to determine if they hold 2 or more bytes of valid data. If they do, RFM_DMAR QSET is activated to request DMAC service and next state is state 11.
If number of bytes held in FIFOR at this time is less than 2, RFM_DMAR QSET is not activated and next state is state 6.
If only data is received from RV, state status is 8et to indicate receipt of a data byte, acknowledgement to RV is given via RFM_RV_ACK, the receive data byte count (RFMBC in RFM_TS02) is increased by 1, and next state is state 5.
If only end of frame status is received, state status i8 modified to indicate that, the frame byte count is decreased by one if it is greater than O (to adJust for transfer of CRC), acknowledgement is returned to RV via RFM_RV_S_ACK, and the number of valid bytes :.
'~ .
. . , ~

BC9-90-001 124 zo349~

contained in the FIFOR data buffer is checked. If there are at least 3 valid bytes in the buffer, the request bit to DMARQ (RFM_DMARQSET) is activated and next state is state 11. If there are less than 3 bytes in the buffer next state is state 6 without activation of request to DMARQ.
The number of valid bytes in FIFOR at end of frame reception is important because this condition occurs only in channels operating under HDLC
protocols, in which the last 2 bytes transferred from RV are CRC remainder bytes that are not part of the frame data count; hence, the count must be ad~usted on the fly to reflect the true received data count.
- If an abort or idle frame status is received from RV, the number of valid data bytes in FIFOR is checked. If there are no valid data bytes in FIFOR, next state is state 9. If there is one byte, next state is state 6. If there are two bytes, frame byte count is decreased by one and next state is state 6. If there 3 bytes, frame byte count is decreased by one and next state is state 3.
State 3 (Decrease Frame Byte Count By One) - Frame byte count is decreased by one and next state is state 6.
State 4 (Wait For DMAC to empty FIFOR data buffer) - If halted by RSM while in this state transfer to state 0. In this state the request signal from DMARQ (DMAR QRFM_REQ), which when active indicates that DMAC service ha~ been reque~ted relative to the FIFOR data buffer (when such service is completed DMAC turns this signal off), is checked repeatedly for indication of completion of DMAC
service relative to the FIFOR data buffer. Upon receipt of such indication, transition to state 1~ .
State 5 (Write Received Data To FIFOR Data ~uffer) - In this state, a8sert write request to FIFOR, RFM_FIFOR_WR_REQ. When FIFOR acknowledges (with FIFOR_RFM_ACK), apply byte position pointer , -: ' , .. : ~

BC9-90-001 125 z03*9~

RFM_FIFOR_BPP to address a byte location in the FIFOR data buffer to which the received data byte is written. Update pointer, to point to next position, and state status to indicate data has been written to FIFOR. Check status of the FIFOR
. data buffer. If full~ activate RFM_DMAR QSET to request DMAC service and go to state 4. If the buffer is not full, go to state 2 without action relative to DMARQ. If halted by RSM before completing the foregoing actions, return to state 0.
State 6 (Decrease Frame Byte Count By One) - Frame byte count value is decreased by one and next state is state 9.
State 7 (Clean Up State) - Clear frame byte count, set state status to indicate beginning of a new frame, and transition to state 4.
State 8 (Pass Frame Status From RV to INT) - This state is entered as a result of the RDE
(receive DMA enable) bit in RSM_CCR being off. In this state all frame status received from RV is passed to INT by activation of RFM_INT_REQ and processing by INT of RFM status presented at RFM_TS01,02. All received data is di~carded.
Return to state 0 when RSM_RCV_EOS is activated.
It is the responsibility of the host/IOP complex to ensure that the RDE bit in a channel's CCR is set active if data is to be received with normal DMA action in that channel.
State 9 (Report Error Or Frame Status To INT) - An interrupt request to INT, RFM_INT_REQ, is raised to report error or frame status. Possible interrupts are: FIFOR parity error (see state 10), boundary check condition encountered, or end of frame indication received. Go to state 8 if parity - error or boundary check condition is presented, or ~ to state 7 if normal frame ending status is ;; reported.
State 10 (Read Boundary Check Bit From FIFOR) ,:.

:, BC9-90-001 126 z0349~

- Assert RFM_FIFOR_RD_REQ relative to current channel's RDCRl space. When FIFOR acknowledges this request, check for FIFOR parity error (FIFOR_PARITY_ERROR active). If such error is indicated, go to state 9 and set status indicator denoting this occurrence. If RDCRl indicates that a boundary check occurred during the associated DMAC transfer, set state status to indicate this condition and go to state 9. If neither FIFOR
parity error nor boundary check condition has occurred, go to state 1. If halted by RSM, go to state 0.
State 11 (Decrease Frame Byte Count) - Decrease frame byte count by one and go to state 4.

11.7 TFM FUNCTIONS

The transmit FIFO manager TFM is a time division multiplexed synchronous element. It is started and stopped by RSM in synchronism with appearances of channel time slots at the BTDM. TFM manages transfers of communication transmit data (relative to active channels) from FIFOR to TV. Such data i8 queued (in sets of 4 or less bytes) in TDCR
(transmit DMA configuration register) spaces in FIFOR, in particular in TDCR2 spaces (Figs. 7, 36~. The data is transferred from external IOP memory to FIFOR by DMAC (in sets of 4 or less bytes), and extracted from FIFOR by TFM
one byte at a time. Control information relative to each channel queue is stored in the associated TDCRl space in FIFOR.
The form and content of the information stored in the TDCRl and TDCR2 spaces in FIFOR is indicated in Figs. 35 and 36, and described briefly both here and in the description of DMAC below.
TDCRl (Fig. 35) contains: three l-bit indications, three 2-bit indicatlons, one 16-bit indication and 7 reserved/unused bit spaces. The l-bit indications are: ECD
(end of chain detected), EFD (for end of frame detected), and NDI (no data indication, meaning that a DMAC service has encountered an end of buffer condition leaving no further '' .

, BC9-90-001 127 ~03~

data to be transmitted). The 2-bit indications are: TBC
(transmit buffer count, pointing to the next byte in FIFOR/TDCR2 to be transferred to TV), TOPQ (top of queue; in any instance of queue service, DMAC may transfer 4 or less data bytes and this indicator points to the location of the first "valid" byte), and PE (indicating one of the following 4 DMA parity error conditions: no error, FIFOR parity error, DMAC control RAM parity error, parity errors encountered both in FIFOR and DMAC control RAM). The 16-bit indication, TDBC (transmit DMA byte count), represents the byte length of the current external data buffer from which DMAC is retrieving data and indirectly indicates command chaining points for the DMAC (see DMAC description below for more details).
TDCR2 (Fig. 36) comprises a queue of four transmit data byte spaces, TD~l - TDB4, into which transmit data retrieved by DMAC is placed. As noted above, in any instance of DMAC
service 4 or less bytes are retrieved and placed in the i queue, and the location of the first valid byte so placed is defined by the TOPQ indicator in TDCRl.
TFM is also responsible for initiating timely replenishment of transmit data queues in FIFOR, in coordination with real-time requirements of channel communication processes. TFM monitors the status of the transmit data queue in FIFOR for each active channel, and as the queue becomes empty TFM asserts a reque~t to DMARQ to initiate (asynchronous) replenishment action by DMAC
relative to external IOP memory.
Control information indicating the status of DMAC
~ervice relative to each active channel is stored in that ; channel's TDCRl word space in FIFOR (Fig. 7), and TFM
monltors control information TDFSW (transmit data FIFO
status word) in the first byte of TDCRl for detecting end of frame points in the transmit data ~tream and for passing related ~ignals via TV to TFl enabling the latter to carry out CRC and flag insertion functions relative to channels configured for bit oriented protocols (e.g. HDLC). At such times, TFM increments a frame count in its time swap word by one, ant presents an interrupt request to INT for passing the frame transition information along to the host system ..

BC9-90-001 128 20349~

(see description of INT below for details of how the information is actually passed).
The DMAC process for retrieving transmit data allows for chaining of retrieval commands relative to (e.g.
scattered) data blocks in IOP memory (see DMAC description below for details) with a certain degree of autonomy relative to the IOP/host systems. TFM also monitors the TDCRl/TDFSW information for end of chain detected (ECD) indications. ~pon detecting such, TFM relays related indications to TLl via TV, for enabling TLl to insert fill patterns if required until DMAC service relative to the chained block is effective. The chain transition condition is also reported to INT (see description of INT below). At such times, TFM becomes inactive relative to the associated channel and explicit action by SIO/IOP is required (see description of SIO below) to reinitalize the channel and reactivate TFM; ensuring that any required coordination, between IOP/host systems and DMAC, for effectuating chaining, i9 carried out before resumption of channel communications.
When TFM i8 halted by an end of slot indication from RSM, RSM_XMIT_EOS, while performing operations relative to an active channel, a time swapped word TFM_TSOl, defining TFM's state relative to that channel, is saved by RSM in TSR. If the next appearing channel is active, another word TFM_TSOl, defining TFM's status relative to that channel, is loaded into TFM (from TSR by RSM), and TFM is restarted, by signal RSM_XMIT_START from RSM, to resume processing relative to the new channel.
The TFM statu8 word saved by RSM during swapping does not include the ~ransmit data byte, if any, which may have been fetched by TFM from FIFOR and not yet transferred to TV
when RSM halts the current channel slot operation. This i8 becau8e each tran8mit data fetch by TFM ls initiated by a request from TV and conclute8 normally (no intervening halt) with a byte transfer to TV together with a TFM
acknowledgement. The logic of TV is arranged so that if it ha8 an outstanding (unacknowledged) data fetch request to TFM when halted it will withdraw that request and save status requiring it to present the same request to TFM when next restarted relative to the same channel. The logic of ., . .

~C9-90-001 129 Z03491~

TFM is arranged, when halted before completing a transmit data fetch from FIFOR, to withdraw the request so that on the next service of the same channel TV will reissue its request to TFM. Since the pointer TBC, which defines the next byte position for TFM to fetch data from the FIFOR
transmit buffer queue is not changed by TFM until the fetched byte has been passed to TV, if TFM is halted during an incomplete fetch no special action is required to ensure that the correct byte will be fetched by TFM from FIFOR when TV repeats its request.

11.8 TFM TIME SWAPPED WORD

The form and content of TFM's time swapped word TFM_TSOl is shown in Fig. 32. The word consists of 6 actually used bits and 26 reserved/unused bits. For reasons explained above, and rediscussed in the states 0 and 6 de~criptions below, this word does not include any transmit data associated with an incomplete fetch (a fetch not completed when TFM is halted by RSM). The 6 used bits include a 4-bit field TFMFC (TFM Frame Count), indicating the number of frames of transmit data which have been transmitted relative to the associated channel, and a 2-bit field TFMS (TFM State) defining the state of TFM relative to the associated channel as one of: initialized (by external action of SIO/IOP; see de~cription of SIO below), normal processing, halted due to parity or logic error, or halted due to end of chain condition.

11.9 TFM LOGIC

The logical organization of TFM i9 shown in Fig. 31.
TFM comprises ~tate machine logic 240, register 241 for storing TDFSW information fetched from FIFOR/TDCRl, register 242 for storing the TFM time swapped wort TFM_TSOl a850ciated with the channel currently being proces~ed in TFM, and multiplexor/~elector circuit 243 for selecting data byte portions of transmit data words appearing at 245 and transferring the selected bytes to output 246.
Register 241 receives TDCRl status information from FIFOR, via FIFOR_DATA bus 245, and presents output status ;

BC9-90-001 130 Z03~91~

- data at its output, TFM_TDFSW_DATA; e.g. for write transfer back to FIFOR when control output TFM_FIFOR_WRl is given by logic 240. Time swap word register 242 is loaded from RSM_TS_BUS, during time swap action by RSM, and presents its current contents at TFM_TSOl output, to be saved to TSR by RSM when TFM is halted and logic 240 is presenting TFM_DONE
(indicating that it is in stable state O appropriate for time swap word saving).
. Multiplexor/selector 243 is operated by logic 240 to perform transmit data byte selection relative to its input - 245 from FIFOR. In response to fetch requests TV_TFM_REQ
from TV, transmit data is read from FIFOR to selector input 245 in word parallel form. Logic 240, using the buffer count s pointer information TBC in TDFSW regi~ter 241, selects the appropriate byte to be presented to TV at output 246, TFM_TV_DATA. When the data at output 246 is valid for transfer to TV, logic 240 asserts TFM_TV_ACK to TV and the data is accepted instantly (within 50 nanoseconds) by TV.
LoKic 240 asserts TFM_TV_EOC when passing the ECD (end of chain detected) indicator portion of TDFSW from register 241 to TV, and TFM_TV_EOF when passing the EFD (end of frame detected) indicator portion of TDFSW to TV. The logic asserts TFM_EOP_STATUS in association with TFM_INT_REQ when passing end of process status to INT (see description of INT
below for details of end of process interrupt status ~ handling). Other outputs and input8 of the logic are f3 explainet below in the description of its states.
j States of state logic 240 are:
f ; State O (Idle State) The state in which it is "safe" for RSM to conduct time swapping of TFM_TSOl information (without possibilit~ of 1089 or ambiguity due to transient interaction between TFM and either TV or FIFOR or DMARQ). In thi8 8tate TFM can assert its Done indication to RSM (TFM_DONE), indicating that TFM
is in a stable state suitable for safe execution by RSM of state time 9wapping. When this state is entered after end of slot/halt indication from RSM
(RSM_XMIT_EOS), RSM stores the contents of register 242 in the associated channel space of ,., .
: , , TSR. If the next channel slot is associated with an active channel, RSM presents an associated previously saved status word at RSM_TS_BUS and asserts RSM_TFM_LOAD to cause logic 240 to load that word into register 242. Upon activation of RSM_TFM_LOAD logic 240 also resets an internal status bit (not shown) NEW_TDFSW which when set indicates that the state of TDFSW/TDCRl has changed and may require specific action by TFM to update the associated information in FIFOR (see discussions of state 2 and 6 below~.
After completing the state time swap, RSM restarts TFM by asserting RSM_XMIT_START. At that time, the state logic transitions to state 1 if the transmit DMA enable bit (TDE) in RSM_CCR is on, and otherwise tran~itions to state 9.

State 1 (Examine Newly Loaded Status) In this state, status newly loaded into register 242 during 8tate 0 operation (TFM_TSOl for channel currently being served) is examined. If the status indicates need for DMAC action to fill the transmit data queue in FIFOR (field TFMS
indicating newly initialized status), a request to DMARQ, TFM_DMAR Q SET, is asserted and the logic transitions to state 2. The request to DMARQ
instantly (within 50 nanoseconds) causes setting of a request latch in DMAQR (see description of that element below) and return of acknowledging indication DMAR QTFM_REQ to logic 240. The request to DMARQ causes asynchronous action by DMAC to fetch transmit data from external IOP memory to FIFOR, ant the signal DMAR QTFM_REQ i9 not turnet off until DMAC completes its action (which could involve more than one cycle of TPM service relative to the associated channel). However, the DMARQ operates in synchronism wlth TFM relative to it8 DMAR QTFM_REQ signalling functions 80 that the signal will remain on each time the associated channel is 8erviced by TFM unless and until it is turned off by action of DMAC.
,.
"~.

.. .. .. .....

BC9-90-001 132 zo349~

If state status in register 242 indicates normal processing status, logic 240 transitions to state 2 or 3 depending re~pectively upon whether DMAR QTFM_REQ is active or inactive. As noted above, although DMAC operates asynchronously in servicing a TFM request for FIFOR refilling, DMARQ
operates in synchronism with RSM and TFM with respect to this DMAR QTFM_REQ acknowledgement signalling function (also see DMARQ description below), and the function is deactivated relative to any channel only when DMAC complete~ the required action. Therefore active state of this signal is invariably associated with the channel currently being serviced by TFM, and indicates that the requested DMAC function (filling of FIFOR
queue) i~ incomplete.
If state status indicates detection of error or end of chain condition from the previous proce~ing interval of the same channel, the logic transitions to state 9.

State 2 (Wait For Data Buffer In FIFOR To Be Filled) In this ~tate (entered from state 1 or 6), the ~tate logic waits for the tran~mit data buffer in FIFOR to be filled via DMAC action requested by earlier as~ertion of TFM_DMAR QSET relative to the channel currently being served.
Indication that thi~ action is completed i9 given when DMAR QTFM_REQ i9 turned off relative to the channel currently being serviced (see state discus~ion above). If the action is completed during She current 910t, the logic transitions to state 3.
If end of slot is received before completion (RSM_XMIT_EOS), logic transitions to state lZ or state 0 depending respectively on whether or not internal latch, NEW_TDFSW, has been set indicating that TDFSW has been changed. If the latch has been set the logic asserts TFM_FIFOR_WRl before transferring to state 12 (to initiate writing of the altered TDFSW, from output TFM_TDFSW_DATA to : 2034911 ' FIFOR/TDCRl). As noted earlier this latch is set only when TDFSW has been changed due to completion of a requested action, and the latch is invariably reset at the beginning of each new slot; therefor its appearance in set condition during any slot invariably denotes completion of a requested action relative to the channel currently being serviced, and need for storage of associated new TDFSW information in FIFOR.

State 3 (Wait For Data Request From TV) If TV_TFM_REQ is active (TV requesting data to be fetched), the logic asserts TFM_FIFOR_RD2, to initiate back-to-back fetching of status (TDCRl) and transmit data (TDCR2) words from FIFOR, and transitions to state 4. The data fetch will yield all 4 bytes of the TDCR2 queue but the logic operates multiplexor/selector 243 to select only a single byte to appear at TFM_TV_DATA using the buffer count pointer TBC in the fetched TDFSW.
Upon arrival, the status word is placed in register 241, and the selected byte of data is passed immediately to TV via selector 243 and TFM_TV_DATA. If these action~ are completed, the value of TBC is ad~usted to point to the next data byte to be fetched, and NEW_TDFSW latch is set.
I end of slot (halt) indication RSM_XMIT_EOS is received during thi8 state, the logic transitions either to state 12 or state O depending on the state of NEW_TDFSW. If that latch is set, the logic as8erts TFM_FIFOR_WRl (to write the new TDFSW information back to FIFOR) and transitions to 8tate 12. If the latch is not set the logic transition8 to 8tate 0.

j State 4 (Receive TDFSW And Transmit Data From FIFOR) If FIFOR acknowledges the first read request (8tate 3) by activating FIFOR_TFM_RD_ACK, the TDFSW information is latched into register 241 and FIFOR parlty indication (FIFOR_PARITY_ERROR) is checked. If parity error is indicated, set status ~C9-90-001 134 2~3~91~

to indicate parity error and go to state 11.
Otherwise go to state 13 to prepare for arrival of the transmit data from the second read request (issued in state 3).
If halted by RSM_XMIT_EOS, logic asserts TFM_FIFOR_WRl and transitions to state 12 if NEW_TDFSW latch is set. If latch is not set it goes to state 0.

State 5 (Select Byte Of Transmit Data Sent From FIFOR) In this state the data part of the dual read request issued in state 3 arrives at FIFOR_DATA
and is received without explicit acknowledgement from FIFOR. The data received is a full word (TDCR2) and selection of a byte of that word is made by the logic as a function of the TDFSW
buffer count value (TBC) stored in register 241 during state 4. The selected byte is presented at TFM_TV_DATA and when valid at that position TFM_TV_ACK is asserted, and the NDI bit in TDFSW
is also passed to TV as TFM_TV_NDI. If the TBC
indicates that the byte being selected is the last byte in the TDCR2 queue, the end of chain (ECD) and end of frame (EFD) indicators in TDFSW (at the output of register 241) are also presented to TV
via TFM_TV_EOC and TFM_TV_EOF respectively. If these actions are completed the logic transitions to state 10.
If halted by RSM and NEW_TDFSW is set, the logic asserts TFM_FIFOR_WRl and transitions to state 12.
If halted and the latch is not set logic goes to state 0.
,~
State 6 (Check Status Of ECD and EFD Indicators In TDFSW) - Thi8 9tate entered from 8tate 5 via state 10.
~, - If both end of chain and end of frame are indicated in the TDFSW currently held in register 241, the transmitted frame count (TFMFC in TFM_TSOl register 242) is incremented by one, state status (TFMS in register 241) is ad~usted to ~C9-90-001 135 z0349~

indicate end of chain condition reached, and logic transitions to state 11. If only end of chain is indicated, only ~tate status TFMS is changed to indicate end of chain condition reached and logic goes to state 11. If only end of frame is indicated the frame count is incremented by one, TFM_DMARQ SET is asserted, and the logic goes to state 2. If neither end of chain nor end of frame is indicated, TFM_DMAR QSET is asserted, and the logic transitions to state 2.

State 7 (Wait For Additional Data Request From TV) This state differs from state 3 in that the TDFSW
is currently available in register 241;
accordingly, if TV is requesting data during this state, the logic asserts only a single read, TFM_FIFOR_RDl, relative to FIFOR/TDCR2 and transitions to state 8.
If halted by RSM and NEW_TDFSW is ~et, the logic asserts TFM_FIFOR_WRl (to write changed TDFSW in FIFOR) and goes to state 12. If halted and TDFSW
is unchanged, it goes to state O.
., State 8 (Walt For Data To Arrive From FIFOR) - When data arrives from FIFOR, the TBC bits in TDFSW are used to select the appropriate byte and - the TBC value is also checked to see if the byte :~ being selected is in the last queue position (i.e.
. if the queue is emptied by transfer of this byte).
,. If the byte selected is the last, ECD and EFD
indicator8 in TDFSW are passed to TV with the selected data byte, and the logic tran~itions to state 6. If the selected data byte is not the last " one in the queue, the TBC value is updated to - point to the next byte in the queue, NEW_TDFSW is set, and the logic goes to state 7.
- If halted by RSM ant NEW_TDFSW is set, logic asserts TFM_FIFOR_WRl (to write the changed TDFSW
to FIFOR) and goes to state 12. If halted and TDFSW is unchanged, logic goes to state O.

BC9-9~-001 136 z0349~

State 9 (Check Need To Update TDFSW) - In this state (reached from state l or ll), the logic checks to determine if TDFSW needs to be updated. If it does the logic transitions to state 12. If it does not the logic goes to state O.

State lO (Checking Validity Of TDFSW Received From FIFOR) - The TDFSW received from FIFOR during state 4 is checked for validity by evaluation of its top of queue (TOPQ) and buffer count (TBC) pointers.
- If TOPQ points to the first byte location in the TDCR2 queue, and TBC points to the last byte position in the queue, logic goes to state 6. If TOPQ points to first position and TBC to other than the last position logic goes to state 7.
- If TOPQ points to second byte position and TBC points to first byte position, TDFSW is invalid. In this circumstance, state status TFMS is set to indicate error and logic goes ~ to state 11. If TOPQ points to second byte -~ position and TBC point~ to last position, logic goes to state 6. If TOPQ points to ~l second po~ition and TBC to other than first ' or last position, logic goes to state 7.
- If TOPQ points to third byte position and TBC
to either the first or second position, TDFSW
is in~alid. State status ig set to indicate ,A error and logic goes to state 11. If TOPQ
points to third position and TBC to last position logic goes to state 6. If TOPQ and -; TBC both point to thlrd position logic goes to state 7.
s - If TOPQ points to last byte position and TBC
to the same position, logic goes to state 6.
If TOPQ points to last position and TBC to any other position, error state ~tatus is set and logic goes to state 11.
- Before exiting thi8 state, the TBC tran~mlt data byte pointer is ad~usted to point to the next byte ~C9-90-001 137 Z03491~

to be fetched from FIFOR when the next request from TV is received (if not pointing to the lact byte position). Note that this state is entered from state 5 provided that the transmit data fetching action of the latter state is completed relative to TV. Note also that if the pointer TBC
is pointing to the last position at this time, a request for DMAC action will have been posted resulting in activation of DMAR QTFM_REQ
(indicating to TFM that the queue is being ~erviced), and upon deactivation of that signal (by DMAC after completing the service) TFM state logic is required to fetch the new TDFSW
information supplied by DMAC which will include new TBC and TOPQ values.

State 11 (Generate Interrupt Request To INT) - As~ert interrupt request to INT, via - TFM_PARITY_ERROR if state ~tatus indicates parity error or via TFM_INT_REQ otherwise, and go to ~tate 9. Assertion of latter request indicates to INT that TFM_EOP_STATUS currently asserted by the logic i~ valid (see description of INT below for details of how this information is processed).

State 12 (Write Updated TDFSW to FIFOR) - Wait for FIFOR to acknowledge write request, TFM_FIFOR_WRl, issued in any other state (for updating TDFSW). When FIFOR_TFM_WR_ACK goes active, deassert write request and go to state O.

State 13 (Align For Second Read of RD2 Operation) - This state is used to align with the timing of FIFOR relative to the second read of a pair of consecutive read requests initiated by TFM_FIFOR_RD2. Next state is state 5.

12 INTERRUPT HANDLING ELEMENTS - INT. SIO

i .- . : - . .

Interruption reporting relative to the IOP/Host is handled by Interrupt Handler (I~T) and Slave I/O (SIO) partitions. INT monitors requests throughou~ the IDLC and from the Ll circuits, those related to communication channel events as well as those related to hardware failures, posts related interrupt requests to SIO along with associated vector information pointing to the interruption source and manages the storage of related status information in TSR and one of the INT common registers discussed below (IHEISR).
SIO passes the interrupt requests and vectors to the IOP/Host System, and provides access paths from IOP to TSR
and registers in both the IDLC and Ll circuits for enabling IOP to asynchronously retrieve stored status associated with interrupt requests (see e.g. path 89, Fig. 5; also description of SIO below). Although SIO is involved in processes other than interrupt handling (initialization/
reset functions, dynamic programming of time swap status, etc.) it is described in this section because of its ma~or involvement in the transfer of interruption requests and 9tatus information.

12.2 INT FUNCTIONS

INT monitors requests relating to reportable events, throughout the IDLC and from the Ll circuits, assembles a vector (1 byte) identifying the source of the associated condition or event, oversees storage of status information related to the event/condition and passes the vector along with a request to SIO. SIO presents corresponding requests to the IOP via SIO_INT (Fig. 43), a line continuously monitored by the IOP. When that line ls active, and the IOP
is available for dealing with it, the IOP acknowledges the reque9t and retrieve9 the associated vector from SIO. When ready to perform the required interrupt handling process, the IOP uses the vector to perform a table lookup operation establishing the IDLC or Ll interrupt source, and acts through SIO to retrieve the associated status information.
Event8 reportable to INT from the IDLC fall into three ma~or categorie9: End Of Proce89 (EOP) Channel Interrupt9, Channelized Error Interrupts and Hardware Error Interrupts.
EOP and channelized error interrupts each have 32 Z03~9~

sub-categories corresponding to individual source channels.
EOP interrupts indicate expected events in individual channels (e.g. frame end d~tection). Channelized Error interrupts indicate hardware error conditions affecting particular channels (e.g. parity errors in retrieval of a particular channel's data or state information from one of the IDLC R~M's). Hardware Error Interrupts indicate catastrophic hardware error conditions potentially affecting all channels.
Two vector categories are allotted for requests made by the Ll circuits. These distinguish Ll requests as relating to hardware error events and channel condition/error events.
Ll requests/vectors are prioritized to be attended to before channelized IDLC requests, but not before IDLC
non-channelized hardware errors. Relative to each category of interrupts a corresponding vector is formed by INT and passet to SIO/IOP with an associated request. Status information related to requests originating from Ll and the IDLC is stored respectively in the Ll circuits and the IDLC, and retrieved by asynchronous action of IOP/SIO. Status information relative to IDLC hardware errors is stored in an INT register (IHEISR) and status related to IDLC channelized events and error conditions i9 stored in TSR (refer to discussion of EOPISR queues and CEISR register spaces below).
The vector generated by INT and passed to SIO/IOP
indicates the interruption category/source. ~ector formation and usage is described below in section 12.2.6. Formats and functional handling of IDLC status parameters is described next.
J
~ 2. ~ END OF PROCESS (EOP) CHANNEL INTERRUPTS
' The8e indicate particular expected event~ in communication channels (e.g. detection of receive frame end and transmit chain end events, relative to receive and transmit processes, etc.). Related End Of Process Interrupt Status (EOPIS) words (32-bits each) are latched by individual receive and transmit elements, and stored by RSM
under direction of INT in End Of Process Interrupt Channel Register (EOPISR) spaces in TSR (Fig. 6).

Each channel is allocated a queue of 16 such spaces in TSR (EOPISROl - EOPISR16, Figs. 6, 41), which is managed by INT and IOP as a circular buffer. Each channel also has a single register space (CEISR) in TSR for storage of a Channelized Error Interrupt Status (CEIS) word described below. Information stored in each channel's CEISR indicates the status of that channel's EOPISR queue, and includes a Next Status Location (NSL) pointer indicating the next queue location available for storing new EOPIS information (see paragraph 12.2.2 below). The NSL pointer is modified by INT
as an entry is written to the queue position designated by the current value of the pointer.
For each IDLC vector indicating an EOP condition, the IOP is required to read a single EOPIS word from the queue (via SIO). An indication (NOV) of the number of vectors currently pending on each channel's queue is stored in the respective CEISR/TSR space. This indication is incremented by INT in association with the writing of status entries into the queue, and decremented by INT when it receives indication that one or more status words have been removed from the queue by IOP (see discussion of single-status and multi-status modes below). Therefore it indicates the "fullness" of the queue. INT detects imminent overflow of a queue when a certain number of vector9 are pending on that queue (the number is different for single and multi-status operating modes described below).
There is no explicit indication of when a word has been removed from the queue, nor is there a requirement for ortering such removal in alignment with the order of entry into the queue. Furthermore, relative to queue entries made in multi-status mode, as discussed below, the IOP is not required to read such entries while in the interrupt handling routine by which it processes associated vectors (allowing for simplification of such routines); nor is it required to acknowledge its processing of such entries in line with its status retrieval processing, although it gives lndication of its handling via updates of HPCR toggle and SWRC parameters as discus~ed below. This eases real time constraints which otherwise would be imposed on the IOP
status retrieval process.

~cg- go-ool 141 2034911 The HPCR toggle and SWRC (Status Word Read Co~nt) functions mentioned above are monitored by INT to determine when to update the CEISR functions NOV and NSL, the latter determining when and where new EOPIS entries are made. The HPCR register in which the toggle and SWRC are stored is located in RSM (see description of RSM above).
There is also no restriction as to the number of queue entries which can be retrieved by the IOP at one time (in 7'multi-status" mode). Thus, if a queue contains 10 EOPIS
words at a given time it is possible for IOP/SIO to retrieve all lO (or fewer) in one execution of its retrieva~ process.
Since IOP updating of toggle and SWRC parameters in the HPCR
need not be tightly tied to its queue retrieval processing, it is possible for more entries to be placed on a queue by INT/RSM after the IOP has accessed earlier entries, and for such later entries to be retrieved before HPCR parameters are updated. Thus, it is permissible for the IOP in its updating of the HPCR to account for entries retrieved in separately performed queue accessing processes.
It should be understood by those skilled in the art that remotely originated transmissions provide indications of the numbers of frames received at remote nodes. Thus, the IOP has the ability to compare the number of frames actually transmitted by the IDLC with the number of such frames upposedly received at remote nodes. Since the IOP also knows at any instant of time how many transmit frames have been made available to the IDLC/DMAC for chained handling, the IOP can if desired regulate the number of frames made available, relative to its handling of receive frame end lnterrupt status retrieval (EOPISR queue entries), so as to ensure that barrin8 abnormal operation of the IDLC queue over10w can not occur.
The point to note here is that balancing of tran8mission load~ and interrupt ~tatus retrieval activities, to avoid inefficient channel link usage in the network while averting overloading of the IOP, is a function of the IDLC design. But it also 8hould be clear that this balancing is Pacilitated presently, since retrieval processing by the IOP of IDLC EOPISR multi-status mode queue entries (representing receive frame end events) can be handled separate from the processing of associated interrupt BC9-90-001 142 203~9~

vectors and also separate from the updating of toggle and SWRC parameters (i.e. that these functions can be handled efficiently within the IOP on a multitask basis). It also should be clear that in the IDLC vector presentation, status queueing and queue management are separately manageable on an efficient multi-task basis.
Another point to note is that EOPIS entries are made only relative to channels configured for protocol communications (e.g. HDLC) as distinct from clear channels carrying e.g. voice telephone signals (the latter handle data in continuous streams without special frame delimiting flags, etc., and associated links are established via exchanges of control signals carried in separate channels).
The form of the EOPIS word is shown in Fig. 40. The number of bits in each field is indicated in parenthesis below the field mnemonic. The "A" below field IQO (Interrupt Status Overflow Indicator) indicates that this parameter is considered always valid, and therefore should be checked by the IOP routine whenever the associated entry is removed from the queue. When IQO is set to indicate that the queue has overflowed, no further entries to the queue are allowed until the respective channel's CEISR parameter has been reinitialized (by IOP/SIO).
Fields labelled T and R are respectively associated with transmission and reception process conditions. The T
fields consist of the three l-bit indications: XMIT EOC
(transmit end of chain reached or not reached), XMIT ABT/IDL
(transmit abort/idle sent or not sent; sent as consequence of underrun detection in the channel), XMIT UNDR (transmit underrun encountered or not encountered).
The R field5 include four l-bit "source" indications and six statu9 indications; of the latter four are l-bit parameters, one is a 4-bit parameter, and the remaining one is a 16-bit term. The 80urce indications include: SRC EOF
(~ource is or is not an end of frame encountered), SRC ABC
(~ource is or is not address boundary check encountered), SRC ABT (source is or is not abort indication received), and SRC IDL (source i~ or is not idle indication received). The status indications include: RDD (receive DMA Disabled, indicating if DMA reception in respective channel's CCR is disabled or enabled), TX CNT (count of the number of frames BC9-90-001 143 Z03491~

transmitted in the current chain up to the time at which the respective interrupt request was posted), RCV OAS (receive octet alignment status effective when request posted), RCV
CRC (CRC e~ror detected or not detected at the time of posting), RCV OVF (the receive side of FIFOR did or did not overflow), and RCV DBC (receive DMA byte count, indicating the number of data bytes DMA'd to IOP memory during the currently received frame; this indication relative to HDLC
protocols includes the total of data and CRC bytes, and is valid only when RCV OVF is not indicating overflow and one of the source indicators SRC ABT, SRC IDL or SRC EOF is active). The following should be noted relative to the foregoing R fields.
When EOF is active, the tran~mit count TX CNT is valid and IOP should check the status parameters to determine the length of the data DMA'd into its memory (RCV DBC) and to see if OAS, CRC or OVF error conditions were encountered during reception of the frame.
When SRC ABC is active, RCV DBC status is valid.
Transmit interrupts will continue to be processed, but receive interrupts will be suppressed. IOP recovers from thi~ condition by disabling reception in the respective channel, programming a new boundary address and re-enabling reception.
When SRC ABT is active, the channel wa9 impliedly receiving a frame when the remotely originated abort signal was detected. When thi9 occurs, only RCV DBC statug is valid in the 8tatu9 field9. The RCV CRC ~tatus indication will be set active and should be ignoret.
If SRC IDL i~ active and the respective channel is being operated in half-duplex mode, the IOP is effectively lnformed that the channel llne should be turned around to permlt tran8misslon ln that channel. In this circumstance, only RCV DBC status 18 valld. RCV CRC will be set active by the IDLC but 8hould be lgnored.
If RDD indicates receive DMA ls dlsabled, and SRC ABC
19 inactlve, RCV DBC ~hould be ignored (this circumstance lmplle9 the DMAC was previously disabled, and therefore no valid data could have been DMA'd to IOP memory).
TX CNT is a cumulative count of the number of frames transmitted by the IDLC. It is inserted by the IDLC relative " ZO:~491~

to each EOPIS word associated with reception of a frame (i.e. into R fields) for several reasons. Due to the transmit DMA chaining capability of the IDLC (see DMAC
description below), it was decided to conserve IOP bus bandwidth and processing time by eliminating IDLC interrupts of the IOP to report transmittals of individual frames.
Nevertheless, in order to provides integrity on the receive side of each full duplex channel link, it is necessary to furnish this transmitted frame count information to the IOP
on a timely basis, inasmuch as received frames include a receive count sent by re~pective sources of such frame~
which represent the number of frames received by the source.
Thus, the count of transmitted frames is needed by the IOP
to distinguish erroneous receive count indications and maintain transmission integrity (e.g. by retransmitting frames not actually received).
Another advantage or potential application for providing timely indications of transmitted frame counts to the IOP, relative to a device such as the IDLC having tran8mit DMA chaining capability, is that it enables the IOP
to free up buffer space on a timely basis for dynamically sustaining chained transmittal activities. Using TX CNT to verify that at least certain frames have been transmitted by the IDLC and remotely received, the IOP can insert new transmission data into at least those portions of its buffer memory space which contain the already transmitted data of those certain frames. Thus, the amount of IOP buffer space required or sustaining chained IDLC transmittal can be reduced relative to what would be required if the IOP had to wait for an end of (transmittal) chain indication from the IDLC before freeing up buffer space.
When RCV OAS indicates octet misalignment, or RCV CRC
inticates CRC error, the respective frame apparently contains error and should be discarded by IOP.
When RCV OVF indicates FIFOR overflow, the value of RCV
DBC if other than O indirectly indicates the location of the last byte which was DMA'd into IOP memory, and may be useful to determine the location in IOP memory at which DMA
transfer of the next receive frame should begin. If the DBC
value is O no further calculation is required to determine that next location.

~C9-90-001 145 ~0349~

12.2.2 CHANNELIZED ERROR INTERRUPTS

These interrupts are ass~ciated with hardware errors affecting a particular channel and not other channels;
either FIFOR parity error or TSR parity error relative to a channel space. As noted above, the status associated with these interrupts includes parameters for managing the EOPIS
queue of the associated channel. A unique vector is generatable for each channel's channelized error interrupts.
After this type of interrupt, the channel must be disabled and re-enabled before re-use.
The form of the CEISR information is shown in Fig. 39.
There are 15 reserved/presently unused spaces and 17 actively used fields. The latter include four single-bit indications WVA, PTV, IQO and SWA, two 2-bit indications PE
and IM, one 4-bit parameter NSL and one S-bit parameter NOV.
The active fields are individually described in section 12.2.9 below.

12.2.3 HARDWARE ERROR INTERRUPTS

These concern catastrophic hardware related errors which can affect all channels. Associated status consists of an IDLC Hardware Interrupt Status (IHEIS) word which is held in a dedicated register in INT (the IHEISR register). The word consists of 14 actively used l-bit parameters having mnemonic labels and form indicated in Fig. 38. The remaining 18 spaces in the IHEISR register are unused/reserved. The 14 actively used indicators consist of 10 "status" indicators and 4 "source" indicators.
Statu~ indicator8 are set active by the IOP without a formal interruption from the IDLC. The related status conditions occur when the IDLC detects error while attempting communication with the IOP; either as a result of IOP/SIO direct acce9s or DMAC operation. When ~uch errors are detected, the IDLC withholds acknowledgements to the IOP
which cau~e a tlmeout lapse/error to be generated in the IOP
~leating to the setting of the IHEISR status indicators without formal interruption processing).
Source indicators are set active as a result of a catastrophic error condition occurrence. Such error conditions typically are not recoverable and usually indicate that the IDLC i~ not operational. The source bits are useful for diagnostic fault isolation purposes.
The individual status and source indicators and their usage are described in section 12.2.9.2 below.

12.2.4 TRANSMIT INTERRUPT PROCESSING

The IDLC can generate three distinct interrupts during transmit processing in any channel (refer to discussion above of EOPISR "T" bit indications): end of chain detected, data underrun detected and abort/idle sent. As noted earlier, interrupts are not generated for completion of individual protocol frame transmissions, since information needed by the IOP relative to such events is furnished indirectly with receive frame end interrupts status (via the TX CNT inserted in the latter).

12.2.4.1 END OF CHAIN

The process culminating with generation of the end of chain detected interrupt begins with DMAC fetching of a chained DCB command having its ECI (end of chain indication) bit set active (see description of DMAC below for additional information). Usually in this circumstance the DCB will also have its EFI (end of frame indication) bit set active. This condition indicates that the last byte of transmit data in the IOP buffer pointed to by the DCB represents both the end of a frame and the end of a chain (the last data to be transferred).
Upon fetching the last data byte of the chain from the IOP buffer, the DMAC 8tores it in FIFOR and sets the ECD and EFD bits actlve in the channel's TDCRl status word in FIFOR.
DMAC continue8 to monitor the DMARQ for service requests relative to the same channel even though the end of chain has been detected, 8ince all further action relative to thi8 condition must be evoked by TFM.
When TFM fetches the last data byte of the chain from FIFOR and passes it to TV, it also checks the TDCRl ECD and EFD indicators. When the latter are set they are passed to TV (8eparately or along with the last data byte if that byte ., hasn't already been passed). Also, after it has updated the transmit frame counter, TFM sets an end of chain indicator that goes to INT. This causes INT to latch up the frame count in preparation for its inclusion in an associated EOPIS word to be entered on the EOPISR queue. TFM then transfers to an end of chain state relative to the respective channel, and remains in that state until the IOP
reinitializes the TFM_TSOl status word (in association with reinitialization of the channel). In the end of chain state, TFM will not respond to any data requests from TV relative to the respective channel, and it will not present transmit DMA requests to DMARQ relative to that channel.
Having received thç end of chain indication and latched the frame count, and while operating in channel slot ~ynchronism, INT sets its status available indicator and checks to ensure that a valid next status word location is available in the respective EOPISR queue. When RSM swaps out the INT related status variables at the end of the respective channel slot, it ~tores the contents of the INT
CEISR regi9ter in the respective channel's CEISR space in TSR, and checks the status word available indicator. Finding it set active, RSM stores the EOPIS (presented at the INT_EOP output of INT; see discussion below of INT logic) in the respective channel's EOPISR queue, at the location pointed to by the next location latches in the CEISR
register in INT (see discussion of INT logic below).
If the channel currently being served has no interrupts outstanding, or the chip is operating in a single vector mode, INT constructs a l-byte vector identifying the source of the interrupt (channel and condition) and passes it along with a reque8t to SIO. When available, SIO ~atches the vector and as80ciated request and drive an interrupt line active on the IOP bus (see SIO description below). Later, IOP acknowledge8 the interrupt line active condition, at which time SIO places the vector on the lower byte section of the IOP data bus. Still later, IOP branches to its interruption handling program routine, and acts via SIO to retrieve EOPIS statu8 from the respective channel'8 queue.

12.2.4.2 DATA UNDERRUN

Z0349~
During transmit processing in any channel, a data underrun occurs if: TLl is in "middle of frame" state (has sent the opening flag of a frame and at least one bit of valid data), has both data registers empty (see description of TLl above), and has received a BTDM request for transmit data to be sent.
When this occurs, TLl sets an internal status bit indicating underrun error and begins transmitting an abort pattern. After sending the abort, TLl sends the fill pattern specified by the IFS field in the associated CCR. TLl also monitors the TDE bit in the associated CCR to determine when the respective channel has been reinitialized by the IOP.
Upon sensing that the TDE bit has been disabled and reactivated, TLl clears the internal underrun error indicator and monitors the data ready indicator from TV.
When that signal goes active, data from TV is accepted and normal transmit processing resumes.
TV monitors the TLl underrun status indicator and will clear its data register, re-initialize and wait for the indicator to clear before resuming normal processing. While in this abort state, TV will not activate the data request signal to TFM or the data ready indicator to TLl (TV_TLl_DATA_RDY).
When TLl sets its underrun error indicator, it also pulses a related indication to INT. In response, INT latches the current transmit frame count from TFM, activates the status available indicator to RSM and provides the offset address from its internal CEISR register to RSM for locating the next valid entry space in the EOPISR queue. It also constructs a vector (see vector discussion below) and passes it along with a request to SIO for presentation to IOP. RSM
store8 the updated CEISR in TSR (in the space determined by concatenating the offset address to the base address of the queue).

12.2.4.3 AbORT/IDLE SENT

TLl tran8mit8 an abort pattern when an underrun i8 detected or the IOP sets the abort request option in the CCR
to a value designating such action. TLl transmits a fill pattern of selected form between frames or DMA chains BC9-90-001 149 203491~

depending on values in the ICS or IFS fields in the CCR. It also sends a fill pattern when IOP sets the abort request CCR option to a particular value.
Upon completing transmission of the abort pattern, TLl pulses the abort/idle sent indicator to INT, causing the latter to latch the transmit frame count value and construct an EOPIS status word and vector as described previously. If the CCR abort request option specified idle pattern transmission, the abort/idle indicator will be pulsed after both the abort and idle have been sent.
12.2.5 RECEIVE INTERRUPT PROCESSING

12.2.5.1 RECEIVE PROCESSING

During synchronous receive processing (in RLl, RV, and RFM), RLl responds to receive data ready indicators from the BTDM to shift receive data bits into RLl's checking register. Relative to each bit in a protocol channel, RLl determines whether the bit is part of a control sequence (flag, abort, idle) and selectively shifts the bit into its receive data register in accordance with a transparency determination (if the bit is the first O bit after five consecutive l's it i8 deleted, and otherwise it is retainet by shifting it into the data register). If the bit i9 retained, a data count is incremented.
This proces~ing of bits continues until the data count reaches 8. If that occurs and a control sequence is not detected, a byte i8 forwarded from the data register to RV
(RLl pulsing a data ready indicator and RV acknowledging), and latched in RV's data register O.
If RLl determines that a control sequence has been received, it purge8 lts data regi8ter and resets its data count (control 8equence8 are not forwarded to RV although indications of their reception are). It then activates indications leading to interrupt activity as outlined below.
If a received control sequence is determined to be the first flag of a frame, RLl ad~usts its frame state indicator to indicate be8inning of frame. If the sequence is determined to be a closing flag, the frame state indicator is ad~usted to indicate frame end status and a corresponding ..

indication of frame end status is passed to RV. Thereafter, RLl clears its status and begins processing for the next frame.
If an abort or idle sequence is received, RLl resets its status indicator to initial state, clears its data register and data count, forwards an associated abort or idle received indication to RV along with associated status, and clears its status to begin new frame processing as with end of frame detection.
In each frame slot, RV ignores all inputs from RLl until it receives a start indication from RSM. Upon receiving the start indication, RV checks its data register 1 to determine if it holds valid data to be forwarded to FIFOR. If there is valid data, RV generates odd parity for it, asserts a data ready indication to RFM, and upon receiving acknowledgement sets an indication that data register 1 is empty. If data register O is occupied at this time, its contents are immediately shifted into data register 1 and data register O is marked empty.
In parallel with transfer actions to RFM, RV monitors its data ready indicator from RLl and when the latter is active a data byte is latched into data register O (provided that register O is then empty). If data latched into data regi~ter O is indicated to be the first byte of a frame, it (and possibly the next byte) is (are) examined for address recognition if that function is enabled. If the address does not match those allowed for in the comparison, an internal indicator is set that causes all data in that frame to be discarded. If the address matches, all data in the frame i9 shifted through the CRC calculation logic in parallel with its movement to data regi8ter 1.
When frame end i9 recognized, and all frame data has been pa~8ed to RFM, RV verifies the CRC remainder and reports CRC status along with RLl status and end of frame received condition to RFM. Note that when RV receives the frame end indication from RLl it immediately shifts the CRC
byte~ through the CRC generator and forwards them to RFM.
Therefore, when end of frame indication is received, RV
checks the CRC register to determine if it has the predetermined value associated with transfer of a valid frame sequence and correct CRC check bytes (hex lDOF). Thus, it is not nece~sary for RV to explicitly compare the CRC
check bytes to the final CRC remainder before forwarding them to RFM.
Upon receiving an abort or idle indication from RLl, RV
reports the condition to RFM and reinitializes. Upon being started in any slot by RSM, RFM checks its internal status to determine if it had previously posted a request to DMARQ.
If so, it ignores all data requests from RV until it senses the request bit in DMARQ has been reset by DMAC action. Then it examines transfer status by reading the FIFOR status word (TDCRl) and, if appropriate, marks the FIFOR buffer (TDCR2) as empty.
When the FIFOR buffer is empty (or only partially full) RFM responds to an active data ready indicator from RV by writing the respective data into the appropriate FIFOR/TDCR2 byte location and updates its byte location pointer. If the last byte written fills the buffer, a request to DMARQ is set and the buffer is eventually emptied by DMAC action.
Upon writing data to the FIFOR buffer RFM asserts acknowledgement to RV and waits for the RV data ready indication to be de-asserted and re-asserted. Upon writing to the buffer, RFM also updates a receive byte count.
When end of frame indication is received from RV, RFM
examines the buffer 8tatus to determine the number of bytes left in the buffer. If two or less bytes are left, RFM
assumes they are part of the CRC field (which does not have to be transferred to IOP memory) and resets the byte count.
If three or more bytes are left in the buffer, RFM sets a request to DMARQ and waits for the appropriate response indicating DMAC action. Upon tetermining that all data for the frame ~ust ending has been sent to IOP memory, RFM
ad~u~ts the receive DMA byte count to ensure that the CRC
bytes are not included, and then pa8ses the count to INT
along wlth an associated interrupt indication and other pertinent ~tatus. RFM then re8ets the byte count and status and begins proce~sing for the next frame.
DMAC processes receive requests in a manner similar to its handling of transmit requests (but in opposite direction). For each transfer of receive data from FIFOR, DMAC cooperates with MIO to arbitrate for access to the IOP
bus, and upon gaining access transfers the appropriate address parameters and control indications to write the data into IOP memory. The receive process presently does not allow for DMA command and/or block chaining, but the buffer space in IOP memory is managed by IOP and accessed by DMAC
as a circular buffer. Thus, by proper IOP management and IOP/SIO/IDLC coordination, arbitrary length blocks of receive data larger then the IOP buffer capacity can be moved through the buffer from FIFOR.
The various interrupt processes carried out between the receive partitions and INT are discussed next.

12.2.5.2 FRAME END RECEIVE INTERRUPT PROCESSING

As noted earlier, when RLl detects end of frame it sends a corresponding indicator and status to RV, which in turn passes an indicator and composite status (of RV and RLl) to RPM, after first ad~usting for CRC checking.
After adjusting to exclude CRC bytes from the data sent from FIFOR to IOP (via DMAC) and to exclude such bytes from the final data byte count, RFM presents an end of frame indication to INT causing the latter to latch RLl/RV/RFM
status from RFM its EOPIS register. INT then constructs an associated vector and passes it along with a request to IOP
via SIO. INT also acts to write the status into the EOPISR
queue in TSR via RSM. The actions by INT are conditioned on the queue not being in overflow condition (in the overflow circumstance its actions relative to IOP are varied to indicate the overflow condition).

12.2.5.3 ABORT/IDLE RECEIVE INTERRUPT PROCESSING

Upon detecting receipt of an abort or idle 8equence, RLl 8end8 a corre8ponding indication and status to RV which pas~e8 a corre8ponding indication with composite statu8 (RLl, RV) to RFM. As in the end of frame situation, RFM
passes corresponding indication and status to INT. INT forms a corresponding vector and passes that along with a request to IOP via SIO, and also stores corresponding statu~ in the EOPISR queue in TSR if space is available. Queue overflow is handled the same in this circumstance as in the frame end situation.

20349~1.
12.2.S.4 DMA BOUNDARY CHECK RECEIVE INTERRUPT PROCESSING

When DMAC finishes servicing an RFM reque~t (relayed via DMARQ), it updates the current receive DMA address and compares it to a programmed boundary address value (set by IOP/SIO at IDLC initialization). If the compared addresses are equal, DMAC updates DMAR status (RDCR3, RDCR4), sets a boundary check bit in RDCRl in FIFOR and clears the request set bit in DMARQ (to effectively acknowledge/indicate completion of service to RFM).
Upon detecting DMAC completion, RFM examines RDCRl status. If it finds a boundary check indication, RFM report~
statu~ to INT along with a corresponding indication. As before, INT builds a vector and status word, and sends the former to IOP (via SIO) with a request and the latter to the EOPISR queue in TSR via RSM. After indicating status to INT, RFM goe8 into a disabled ~tate until IOP reinitializes it~
time swappet word (RSM_TSOl) for the respective channel. In this state RFM will acknowledge data requests from RV but not transfer data from RV to FIFOR nor increment the receive DMA byte count nor forward data transfer requests to DMARQ.
It will however forward present interrupt indications to INT
relative to any received indications of reception of end of frame, abort or idle patterns.
., ~ 12.Z.5.5 PROCESSING OF HARDWARE ERRORS DURING RECEPTION

' .
Channelized hardware errors detected during reception processing (parity errors in readout from TSR, FIFO or DMAR, logic timeout8 generated by RSM while waiting for DONE
indications from receive partitions, forbidden state condition~ detected in receive partition state machines, interface timing errors (BTDM data ready and RLl not ready), errors associated with SIO attempts to access addresse~ not allocated to the IDLC, and errors detected during MIO
communications on the IOP bus) are in essence handled the same as corresponding errors detected during transmit processing. Relative to each such error an indication is passed to INT from the receive partition detecting the error and INT takes action to generate a corresponding interrupt vector.

~C9-90-~01 154 20349~1.

When parity error is detected during receive processing, the partition detecting the error pulses an error indication to INT, INT enters an error state, posts an error vector to SIO/IOP and suspends processing pending an IOP/SIO in~oked restart. Since the RAM's are channelized, such errors are usually channelized. Consequently, the suspension is limited to the channel being serviced when the error occurred.
On detection of logic timeout error RSM posts an interrupt indication to INT. The latter latches the LTO
(Logic Time Out) bit in its IHEISR (IDLC Hardware Error Interrupt Status Register) register (see paragraph 12.2.8 below), generates an error vector, passes the latter to SIO/IOP along with a request and retains associated status in its IHEISR register for retrieval by IOP/SIO. Processing continues until IOP disables the IDLC.
On detection of hardware state error, the partition affected post~ error indication to INT. INT latches the ESD
(Error State Detected) bit in its IHEISR regi~ter and proceeds as in the logic timeout ~ituation.
On detection of interface timing (receive) error, RLl pulses an indication to INT, INT sets the ITE (interface timing error) bit in its IHEISR register and proceeds as in the previous two situations.
On detection of SIO addressing error, SIO withholds acknowledgement of the designated tran~fer from IOP (causing IOP to detect an acknowledgement timeout error), and pulses an indicator to INT. INT sets appropriate status bits in its IHEISR register, but does not generate an interrupt (since IOP will detect the error via its timeout).
On detection of MIO error, error indications are pre~ented to both DMAC and INT. INT sets the DTO (DMA
Time-Out) bit in its IHEISR register as a status indication.
DMAC ~ets an error indicator in FIFOR/RDCRl for the channel who8e request wa8 being serviced at the time of error occurrence and resets the request bit in DMARQ. Upon recognizing the DMARQ acknowledgement/reset and examining FIFOR 8tatus RFM detects the error condition and posts a channelized error indicator to INT. INT thereupon constructs a vector and channelized 8tatus for reportage to IOP which IOP may use with the hardware error status to ascertain the source of the bus failure. In most cases, processing for the affected channel will be suspended until an IOP invoked restart occurs.

12.2.6 INTERRUPT VECTOR FORM, GENERATION AND IOP VSAGE

Interrupt vectors generated by INT are each ~ingle byte encoded numerical values corresponding to the source of the interrupt. The source is one of: IDLC chip level hardware error, Ll chip level hardware error, Ll channelized event or error, IDLC channelized error or IDLC channel proces~ event.
Relative to IDLC channelized error and process events the source i~ further resolved to indicate the specific one of 32 channels which was being serviced when the respective (parity) error or process event was detected. Thus, the vector number in effect ranges over 67 values (2 associated with IDLC and Ll chip level hardware errors, 1 with Ll channelized event~ or errors, 32 with IDLC channelized errors and 32 with IDLC channel process events).
IOP uses the vector to access a respective one of 67 entries in a lookup table in IOP memory. The table entries specifically indicate respective interrupt source identities, as noted above, together with any additional information required by IOP to conduct its interrupt handling process. Due to the manner by which the vector i~
constructed by INT, the table and portions thereof are relocatable by IOP within different portion~ of 256 word segment of its memory; i.e. the range addressable by 8 bit~
and (the INT vector) and a base value fixed by IOP.
When the interrupt ~ource is other than IDLC
channelized event or error (i.e. IDLC hardware error related, Ll hardware error related, or Ll channel event related), INT forms the vector using the 6-bit IIVO (IDLC
Interrupt Vector Offset) number in the ICR (IDLC
Configuration) regi8ter which is located in SIO (Fig~. 5 and 43) and a 2-bit value associated with the source. The 2 bit value is generated by the INT_CHP state machine component of INT (~ee paragraph 12.2.7 below) and concatenated in that state machine to the IIVO offset value transferred from SIO/ICR to form the full vector (INT_CHP_VECTOR). The offset value, which i8 programmably selected by IOP and set into :.................................... ... .

BC9-90-001 156 203491~

ICR by IOP/SIO when the IDLC is initialized, is used by IOP
to select one of 64 offset positions (relative to a base location fixed by IOP). Each offset position represents a boundary of a 4-word group of positions. The 2 bit value concatenated by the INT state machine is used by IOP to select 1 of 4 locations within the group of positions designated by the offset value.
When the interrupt source is IDLC channelized, the vector is formed using a 2-bit offset value taken from the CIVO (Channel Interrupt Vector Offset) field in the ICR
regi~ter and a 6-bit value internally determined by the INT_ CHN state machine in INT. The offset and internally determined values are concatenated in the state machine to form the full vector (INT_CHN_ VECTOR) which is presented to SIO/IOP. The offset value is programmably determined by IOP
; and set into ICR during IDLC initialization. IOP uses the 2 bit offset to locate one of 4 offset positions, at boundaries of 4 separate respective 64-word groups of locations in IO~ memory, relative to a base position/value fixed by IOP. IOP uses the 6-bit value to address one of 64 locations within the space designated by the offset value.
The addressed location contains the information needed by IOP to interpret the vector and link to the required interrupt handling process.

12.2.7 INT PARTITION LOGIC

Fig. 37 shows ma~or logical components (state machines, etc.) of the Interrupt (INT) partition along with ~ its regi~ters,external interfaces and control signals. The 1 partition includes state machines 260 (INT_CHN) and 261 (INT_CHP), CEIS register 262 EOPIS latches 263 and IHEISR
register 264.
State machines 260 and 261 operate as discretely separate logical units; unit 260 operating in channelized mode relative to process events and channelized parity error occurrences, and unit 261 operating asynchronously relative to hardware error events in both IDLC and the Ll circuits as ~ well as channel events occurring in the Ll circuits.
i Reglster 262 is used to latch CEIS information relative to the channel currently being served. latches 263 are used . , BC9-90-001 157 20~4911.

to latch EOPIS information relative to that channel.
Register 264 is used to hold status information relative to hardware errors.
The main functions of INT partition are to respond to interrupt indications, including internal IDLC requests and external requests from the Ll circuits, to collect and store interrupt status relative to such indications, to manage the (channelized) EOPISR queues (in TSR), to construct vectors relative to indications from the other partitions and to present such vectors along with associated interrupt requests to the SIO partition for transfer to the IOP. IOP
uses the vectors in table lookup operations to locate information identifying respective interrupt sources (Ll channel, Ll chip hardware, IDLC chip hardware, process event in a specific 1 of 32 IDLC channels, or parity error occurrence in a specific 1 of 32 IDLC channels) 9 uses the table information to link to an appropriate interrupt handling routine, and uses that routine to retrieve the associated interrupt status from the IDLC via SIO.
INT_CHN state machine 260 operates relative to channelized IDLC process events, while INT_CHP state machine 261 operates relative to IDLC hardware related error conditions and Ll conditions (chip level errors and/or channelized events).
INT_CHN operates in the time swapped environment. In time slots associated with active channels, RSM loads channelized time swap status from TSR into register 262, via RSM_TSR_BUS, and starts operation of INT_CHN state machine with RSM_INT_START pulse. Bit assignments in CEISR are shown in Fig. 39, and discussed below in paragraph 12.2.8. During its operation, INT_CHN receives channel event inputs from TLl, TFM and RFM in EOPISR status latches 263, in response to respective request indications (TLl_INT_REQ, TFM_INT_REQ, RFM_INT_REQ). These latches are cleared before any of the recelve or tran~mit processes start. Their values during INT
operation are not specifically interpreted by INT_CHN.
INT_CHN uses a 2 bit internal register to hold a temporary EOP WAIT STATE LATCH value, which is not saved acros~ time slots, for determining action to be taken by INT_CHN in its state 7 as one of: store EOPISR status, ignore EOPISR status, or clear EOPISR status. If EOPIS or ,'.

CEIS status is to be stored, INT_CHN asserts INT_EOP to RSM
at end of slot, and transfers the contents of CEISR register 262 to RSM. RSM examines the SWA (status word available) bit in the transferred CEIS information to determine if EOPIS
status was latched (at TLl, TFM or RFM) during the slot.
If status was latched, it is RSM's responsibility to store the status from the respective latching partition into the EOPISR queue in TSR, using the Next Status Location (NSL) bits in the transferred CEIS information to locate the queue space to be written. RSM generates the actual TSR
address location to which the EOPISR is written by concatenating the NSL to a base address (in TSR) which is a predetermined function of the channel number.
Although RSM performs the EOPISR transfers into and out of TSR, management of the EOPISR queue is the responsibility of the INT_CHN state machine. INT_CHN state machine is also responsible for 'shutting down' EOPISR status queue when the queue is about to overflow beyond 16 events deep, or a parity error has been detected relative to TSR, FIFOR or DMAR. Parity errors relative to TSR and DMAR are respectively indicated via TSR_PARIT~_ERROR and DMAR_PARITY_ERROR. Parity errors relative to FIFOR are respectively indicated via RFM PARITY_ERROR and TFM_PARITY_ERROR.
In respect to each parity error, a unique hardware error interrupt is generated for the channel in which the error occurred. In respect to imminent queue overflow error, the IQO bit i9 set in the final (last entered) EOPISR status word in the queue.
INT_CHN state machine receives inputs from 2 register~, the ICR (IDLC Configuration Register) in SIO, and the HPCR
(HDLC Protocol Configuration Register) in RSM. ICR contents are programmed by IOP at IDLC initialization and are not channelized (apply unchanged to all channel processes). HPCR
i8 channelized (different for each channel) and is loaded from each channel'~ TSR space (see Fig. 7) during time swapping. Contents of each channel's HPCR word are programmably set by IOP/SIO. Presently relevant field~ in these registers are specifically described below.

203~911 INT_CHN state machine manages the EOPISR queue in one of two programmable modes based on the QM bit setting in the ICR register; single status mode or multi-status mode. The ICR/QM bit value is programmed by IOP at IDLC
initialization. INT receives that bit at ICR_QM (Fig. 37), and supports Single Status Word or Multiple Status Word formation based on the QM bit value. In single status mode, a single interrupt vector is generated and passed to the IOP
for each event entry on the EOPISR queue. In multi-status mode a single vector can be generated for multiple status event entries on the EOPISR queue.
There are performance advantages to multi-status mode in terms of reduced interrupt path length in the IOP
interrupt handling routines, but a disadvantage of added routine complexity in respect to management of IOP access to the queue. When using multi-status mode, IOP acknowledges the number of status words it has removed from the queue, by writing a related value in the (channelized) HPCR register and flipping the polarity of a toggle bit in that register;
refer to descriptions below of SWRC (status word read count) and TOGGLE fields in HPCR. These fields are input to INT at HPCR_EOP_TOGGLE and HPCR_MIC_ACK (Fig. 37).
The Previous Toggle bit Value (PTV) in CEISR register 262 is compared against HPCR_EOP_TOGGLE for a mismatch indicating that IOP has accessed the respective channel's queue and removed one or more entries therefrom. This mechanism is used by INT to protect against overwriting unremoved/pending queue entries. The Number of Outstanding Vectors (NOV) really means the number of status words on the EOPISR queue when INT is in multi-status mode. NOV will be decremented by INT with the value in HPCR_MIC_ACK after IOP
acknowledge9 the number of status words removed from the queue. This frees associated locations in TSR to be used again, thus maintaining circularity of the queue.
EOPISR queue acces8 by the IOP involves the following sequence of operations: (1) read CEISR (from TSR via SIO) to get pending status word count NOV (number of outstanding vectors) and queue offset address NSL (next status location) for beginning of pending entries; (2) read EOPISR status word or word9 from the queue (one word in single status mode, one or more words, up to 16, in multi-statuY mode);

, . ~

(3) read HPCR (from TSR); and (4) write updated (inverted) toggle polarity, SWRC and LSA (link station address) values if necessary to HPCR/TSR (as noted previously, INT monitors the HPCR toggle and SWRC functions and updates associated CEISR parameters PTV and NOV when appropriate.
Reading of queue entries in single status mode does not require explicit IOP acknowledgement (since each vector pertains to one and only one status word) and the TOGGLE and SWRC bits are not used/changed in this mode. Disadvantages of Single Status mode are indicated below relative to the number of status words which can be stored in the EOPISR
queue (14) and the additional path length of the IOP
interrupt handling rou$ine. In this mode, an interrupt request and vector are passed to IOP for each queue entry, and INT tetects queue overflow (cau~ing setting of IQO bit in last queue entry) when the number of pending entries in the queue/vectors reaches 14 (although the queue capacity is 16, this precaution is needed because of vector queueing in SIO, and absence of specific IOP acknowledgement of queue entry removals). Although the IOP does not specifically acknowledge queue entry removals in this mode, it is required to perform the entry removal while in the interrupt handling routine (i.e. it can not interrupt the routine and return to its task level until this is done, if overwriting of status on the queue i9 to be avoided).
In multi-status mode, IOP must explicitly acknowledge the number of status words which it has read relative to each vector by writing a corresponding value in the SWRC
field of HPCR. INT detects Interrupt Queue Overflow (IQO) when 16 vectors are pending on the queue (and sets the IQO
bit in the last entry to 1). In this mode, IOP execution of queue access can be delayed by returns to task level since multiple entries can be removet in one series of TSR
accesses.
When a vector associated with an IDLC channel condition is ready for presentation to SIO, INT_CHN state machine interfaces to the SIO partition via the SIO_CHN_BSY, INT_CHN_VECTOR ant INT_CHN_REQ signals. INT_CHN monitors SIO_CHN_BSY signal to tetermine if SIO's channel vector latch is busy or available. If available the vector (INT_CHN_VECTOR) is latched into the SIO partition where SIO
manages presentation of vectors on the IOP processor bus.
The 8 bit vector value generated by INT_CHN to SIO, relative to IDLC channel conditions (process end events and parity errors), uses the 2 bit Channel Interrupt Yector Offset (CIVO) in the ICR register to indicate the offset in IOP memory of a space containing the associated table entries for all channels, the S bit channel time slot indicator from RSM_TSI to further distinguish locations of entries associated with the source IDLC channel, and a single bit generated by INT_CHN to distinguish the location of the particular entry associated with the interrupt (that bit being one value if the associated interrupt relates to an ent process event and an opposite value if the associated interrupt relates to a channelized parity error.
If SIO_CHN_BSY is active when INT has a vector to transfer, INT_CHN examines the same indication during subsequent time slots in which the respective channel is served. Thus, INT_CHN competes on a channelized basis in its service of all IDLC channels for access to SIO and it~
single channel vector latch. Access to SIO's channel vector latch follows no algorithm ant is random, based upon many variable8 (e.g. IOP interrupt routine path lengths, IDLC
channel frame sizes, etc.). The EOPISR queue depth of 16 entries per channel offers a very low probability of queue overflow on any channel.
INT_CHN indicates completion of execution by setting the INT_DONE signal, which indicates to RSM that the CEISR
is stable and available for swapping. This should occur prior to the end of time slot indication (RSM_INT_EOS) from RSM. If INT_DONE is not active at this time, RSM detsrmines that a logic/hardware error ha8 occurred and set8 the LTO
(logic time-out) bit in IHEISR (8ee description of IHEISR
bit8 below). INT_CHP state machine monitors IHEISR and generates the associated interrupt request/vector.
INT_CHP state machine operates continuously across time slot8, ant mana~e8 chip level interrupt vectors relative to any of three possible sources: Ll hardware, Ll channel, IDLC
hardware. Ll hardware errors and channel conditions are respectively indicated to INT_CHP by Ll_CHP_VRQ and Ll_CHN_VRQ (Fig. 37). The ~ource relative to IDLC hardware errors is indicated by settings of bits in the source field section of the IHEISE register (Fig. 38~; bit ITE (Interface Timing Error) denoting a failure of synchronization between IDLC and Ll circuits, bit LTO (Logic Timeout) denoting a failure of IDLC logic to complete an operation within a critical time period (e.g. activation of INT_DONE prior to RSM_EOS as discussed above), bit ESD (error state detected) denoting that a state machine in an IDLC partition has transitioned to an unused/forbidden state, and bit DTO (DMA
Timeout) denoting failure of bus access between DMA and the IOP bus. If any of these bits are set the signal line IDLC_CHP_VRQ, from IHEISR register to INT_CHP, is active (i.e. IDLC_CHP_VRQ represents the logical OR of IHEISR bits ITE, LTO, ESD and DTO).
INT_CHP interfaces to SIO via SIO_CHP_BSY, INT CHP_VECTOR, and INT_CHP_REQ signals as shown in Fig. 37.
SIO_CHP_BSY is fed back to INT from a chip vector latch in SIO which is settable by INT_CHP_REQ, which is presented from INT to SIO in association with INT_CHP_VECTOR. The latter vector output is latched in SIO when SIO_CHP_BSY is inactive, and distinguishes the interrupt source as one of the above-mentioned three. SIO_CHP_BSY when active indicates that a vector/request has been received from INT but not yet tran~ferred from SIO to IOP.
The INT_CHP_VECTOR value contains the 6 bit IDLC
Interrupt Vector Offset value (IIVO) and a 2-bit value generated by INT_CHP, The offset value is extracted by INT
from the ICR register in SIO and represents an offset, relative to a base location in the IOP memory space, of a group of table lookup entries a~sociated with hardware related interrupt conditions reportable by INT. The INT
generated 2 bit value repre9ents the location within the group of a particular entry associated with the particular condition being reported. Together the 8 bits are used by IOP to acce~9 the particular table entry and link via the latter to an IOP interrupt handling routine appropriate for retrieving the related 9tatus information from either IHEISR
re8i8ter in INT or from registers in the Ll circuits.

12.2.8 _INT STATE MACHINES

BC9-90-001 163 203491~

12.2.8.1 INT_CHN STATE MACHINE

If SIO_RESET, then state = 0 State O (WAIT FOR RSM START PULSE) - If RSM start pulse ~RSM_INT START) is inactive, remain in state 0.
- If RSM start pulse is active and Interrupt Mode (IM in CEISR) is 'OO' (indicating INT is being activated for the first time on this channel), reset FIFOR parity error indication (PE in CEISR), reset status word available indication (SWA in CEISR), set IM to '11 - normal mode'; go to state 1.
- If RSM_INT_START is active and IM is '10 disabled' (indicating FIFOR parity error) or 'Ol-disabled' (indicating TSR parity error), then EOPISR queue for this channel has been 'shut down'; ~et EOP WAIT STATE LATCH to 'CLEAR EOPISR
STATUS'; go to state 7.
- if RSM_INT_START is active and IM is '11 - normal' then proceed with normal EOPISR queue processing :. state movements; If SWA/CEISR active (status available from previous slot process of this .j channel), increment the Next Status Word Location (NSL in CEISR), reset SWA and go to state 1.
State 1 (Check for Channelized TSR, RFM or TFM Parity Error; if none, check for IOP Acknowledgement Of EOPISR
Queue Status Readout; if none, check for EOPISR Queue Overflow Condition) - Check for channelized parity error. If PE bits in : CEISR indicate parity error (implying occurrence of not yet reported parity error relative to TSR
or FIFOR in prior service of this channel), or if TSR_PARITY_ERROR or RFM_PARITY_ERROR or TFM_PARITY_ERROR is current~y active, examine SIO_CHN_BSY to determine availability of channel vector latch in SIO to receive another channelized vector (reference SIO description below, and item 297 in Fig. 43).
.. , - If SIO_CHN_BSY i9 active then set EOP WAIT
STATE to 'CLEAR EOPISR STATUS'; go to state 7.
- If SIO_CHN_BSY not active, generate a Channe~ized Hardware Error Interrupt vector for this channel, latch it in SIO channel vector latch, and proceed with next action to identify cause of error.
If the cause was RFM_PARITY_ERROR or TFM_PARITY_ERROR, set IM mode to ~10 - disabled FIFO parity error'; go to state 2.
If the cause was TSR_PARITY_ERROR, set IM to 'disabled TSR parity error'; go to state 2.
If no parity errors are indicated and status is "waiting for vector acknowledgement" (WVA bit active in CEISR register 262), then compare Previous Toggle bit Value (PTV) in CEISR regi~ter with toggle bit in HPCR register settable by the IOP (HPCR_TOGGLE input).
If PTV and HPCR_TOGGLE bits are NOT the same then IOP has acknowledged retrieval of status from the EOPISR queue. The number of words read indication SWRC in HPCR (as indicated by HPCR_MIC_ACK input to this state machine) i8 valid. Go to state 4.
If PTV and HPCR_TOGGLE bits are the same then IOP
has not acknowledged EOPISR transfer for this channel and EOPISR is still pending on the queue relative to the last vector generated for the queue; no further vector9 are to be generated for this channel. Proceed with next operation to check for queue overflow.
If the EOPISR queue has overflowed for this channel (IQO set in CEISR), then set the EOP WAIT
STATE to 'CLEAR EOPISR STATUS'; go to state 7.
IP EOPISR queue is not about to overflow for this channel, set EOP WAIT STATE to 'STORE EOPISR
STATUS'; go to state 7.
If no TSR or FIFO parity errors and not waiting for IOP vector acknowledgement (WVA inactive), go to state 6.
State 2: (Wait for SIO_CHN_BSY) 20349~1 - If SIO_CHN_BSY is available, activate INT_CHN_REQ, and remain in same state - If SIO_CHN_BSY is busy and vector was for Channelized Hardware Error Interrupt, set EOP WAIT
STATE to 'CLEAR EOPISR STATUS'; go to state 7.
- If SIO_CHN_BSY is busy and vector was for EOPISR
status, check EOPIS queue overflow.
- If EOPISR queue has overflowed (IQO in CEISR
active), set EOP WAIT STATE to 'CLEAR EOPISR
: STATUS'; go to state 7.
- If EOPISR queue has NOT overflowed (IQO in CEISR Inactive) then set EOP WAIT STATE to 'STORE EOPISR STATUS '; go to state 7.
State 3 (Check EOPISR queue overflow condition) -: - Check EOPISR queue overflow on this channel, by comparing NOV to the maximum number of EOPISR
STATUS words based on the ICR_QM mode bit. If QM
bit is 1 (indicating multi-status mode) then maximum number of EOPISR STATUS words is 16. If QM
~' bit is O (indicating single_status mode) then the i maximum number of EOPISR STATUS words is 14.
- If QM bit i9 active and NOV count is 16 then set queue overflow bit (IQO in EOPISR) to indicate the queue has overflowed.
- If QM bit is inactive and NOV is 14 then set queue overflow bit (IQO in EOPISR) to indicate the queue has overflowed.
- Set EOP WAIT STATE to 'STORE EOPISR STATUS '; 8 to - state 7.
State 4 (Ad~ust vector count based on IOP
acknowledgement) - If the number of status words acknowledged HPCR_MIC_ACK by IOP is greater than the number of status word9 currently stored (NOV), assume that either an IOP programming error or an undetected TSR parity error has occurred. In either event generate a Channelized Hardware Error, set PE to parity error detected while reading TSR'; go to 9tate 1.
- If IOP acknowledges (HPCR_MIC_ACK) a number greater than zero, then decrement both the IOP
:' .. . .

BC9-90-001 166 203~911 acknowledge (HPCR_MIC_ACK) and vector count (NOV) values, remain in state 4. Note it takes one state transition for each decrement and compare.
If HPCR_MIC_ ACK equal zero then reset waiting for acknowledgement (WVA); go to state 7.
State 5 (Not used) State 6 (Generate EOPISR vector) If current vector count NOV is greater than zero then a vector needs to be generated for this channel.
If the SIO_CHN_BSY signal is busy (active) then skip vector generation during this time slot, try again next time slot, but continue with normal EOPISR status processing below.
If the EOPISR queue has overflowed (IQO set in CEISR) set the EOP WAIT STATE to 'CLEAR EOPISR
STATUS'. If the queue has not overflowed set the EOP WAIT STATE to 'STORE EOPISR STATUS'. Go to state 7.
If the SIO_CHN_BSY signal is available, generate an EOPISR vector for this channel. If queue mode (ICR_QM) is multi-status then capture current toggle bit (HPCR_TOGGLE) in HPCR register (for future comparison) and set wait for vector acknowledgement (WVA) active. If queue mode (ICR_QM) is single status decrement the vector count (NOV) register; go to state 2.
If current vector count NOV equals zero then no vector needs to be generated; go to state 7.
State 7 (Wait EOPISR status) Wait for status available indication from transmit or recelve element (SWA active) If end of slot indication received from RSM
(RSM_INT_EOS), go to state 0 If TSR_PARITY_ERROR active, set PE to '11 - parity error detected while reading TSR'. Set EOP WAIT
STATE to 'CLEAR EOPISR STATUS', remain in state 7.
If SWA bit is active (indicating either receiver or transmitter partition has latched status into EOPISR STATUS LATCH) and EOP WAIT STATE is 'STORE
EOPISR STATUS' then increment NOV, and set EOP

BC9-90-001 167 z0349~

WAIT STATE to 'IGNORE EOPISR STATUS'; go to state 3.
- If SWA is active and EOP WAIT STATE is 'IGNORE
EOPISR STATUS' then remain in state 7.
- If SW~ is active and EOP WAIT STATE is 'CLEAR
EOPISR STATUS' then reset the SWA bit, remain in state 7.
- If SWA is active and EOP WAIT STATE is set equal to the current EOP WAIT STATE, remain in state 7.

12.2.8.2 INT_CHP STATE MACHINE

If SIO_RESET then state = O
State 0: Wait Ll_CHP_VRQ, Ll_CHN_VRQ, or IDLC_CHP_VRQ
active - If Ll_CHP_VRQ active, give associated vector to SIO; go to state 4.
- If Ll_CHN_VRQ active, give vector to SIO and go to state 2.
- If IDLC_CHP_VRQ active, give vector to SIO and go to state 1.
State 1: Wait For Ll_CHP_VRQ or Ll_CHN_VRQ active, or IDLC_CHP_VRQ inactive . - If Ll_CHP_VRQ active give vector to SIO; go to state 5.
- If Ll_CHN_VRQ active give vector to SIO; go to state 3.
- If IDLC_CHP_VRQ inactive go to state 0.
State 2: Wait Ll_CHP_VRQ active, Ll_CHN_VRQ inactive, , or IDLC_CHP_VRQ active 3 - If Ll_CHP_VRQ active give vector to SIO; go to , 8tate 6.
: - If Ll_CHN_VRQ inactlve go to state 3.
- If IDLC_CHP_VRQ active give vector to SIO; go to ~, state 0.
. State 3: Wait Ll_CHP_VRQ active, Ll_CHN_VRQ inactive, or IDLC_CHP_VRQ inactive ; - If Ll_CHP_VRQ active give vector to SIO; go to state 7.
- If Ll_CHN_VRQ inactive go to state 1.
- If IDLC_CHPVRQ inactive go to state 2.

..

State 4: Wait Ll_CHP_VRQ inactive, Ll_CHN_VRQ active or IDLC_CHP_VRQ active - If Ll_CHP_VRQ inactive go to state 0.
- If Ll_CHN_VRQ actîve give vector to SIO; go to state 6.
- If IDLC_CHP_VRQ active give vector to SIO; go to state 5.
State 5: Wait Ll_CHP_VRQ inactive, Ll_ CHN_ VRQ active, or IDLC_ CHP_ VRQ inactive - If Ll_ CHP_ VRQ inactive go to state 1.
- If Ll_ CHN_ VRQ active give vector to SIO; go to ' state 7.
- If IDLC_CHP_VRQ inactive go to state 4.
State 6: Wait Ll_ CHP_ VRQ inactive, Ll_ CHN_ VRQ inactive, or IDLC_ CHP_ VRQ active - If Ll_CHP_VRQ inactive go to state 2.
- If Ll_CHN_VRQ inactive go to state 4.
- If IDLC_CHP_VRQ active give vector to SIO; go to s state 7.
State 7: Wait Ll_CHP_VRQ inactive, Ll_CHN_VRQ inactive, or IDLC_CHP_VRQ inactive - If Ll_CHP_VRQ inactive go to state 3.
- If Ll_CHN_VRQ inactive go to state 5.
- If IDLC_ CHP_ VRQ inactive go to state 6.

12.2.9 INT REGISTERS
"
Details of state parameters CEIS and EOPIS have been given above. Notes relating to CEISR usage, details of state function IHEISR and details of configuration designating functions ICR and HPCR are given next.
, . , : ~5~
., : Individual field titles and functions are generally indicated above. Specific function restriction~ and note~
;rrsl are given below.
WVA (Waiting For Vector Acknowledgement) - indicates pendency of vector acknowledgement from IOP.

BC9-90-001 169 203~911 - when acknowledgement is pending, INT is disabled from generating new interrupt vectors.
NOV (5 bits; Number Of Outstanding Vectors) - indicates number of valid outstanding vectors on the queue. When IOP acknowledges interrupt it can access this value to determine the number of valid EOPISR entries waiting to be read from the queue.
INT uses this value to determine when a queue overflow condition is occurring.
PTV (Previous Toggle Bit Value) - indicates previous value of the HPCR toggle bit;
by comparing this bit to the HPCR toggle bit, while operating in multi-status mode, INT
determines when IOP has accessed the EOPISR queue.
IQO (Interrupt Queue Overflow) - indicates if EPPISR queue has overflowed.
PE (Parity Error; 2 bits) - indicates one of the following states relative to IDLC RAM's: no parity error detected; parity error detected while reading TSR; parity error detected while reading FIFOR.
- this field should be read by IOP each time a channelized hardware error interrupt is generated by INT for a specific channel.
IM ( Interrupt Mode) - these bits indicate one of the following operating 3 modes of IDLC relative to the associated channel:
initialized (pending activation by RSM), disabled due to TSR parity error, disabled due to FIFOR
parity error, enabled (for normal operation).
SWA (Status Word Available) , - indicates when status is available for storage on the EOPISR queue (by RSM).
NSL (Next Status Word Location; 4 bits) - points to offset location within current channel's EOPISR queue segment in TSR at which next EOPIS status i8 to be stored; when status is available to be stored (SWA active), RSM uses this field as the lower 4 bits of the TSR address to access the queue (the other bits are tetermined by the channel number) NOTES

.
.. .

BC9-90-001 170 Z03~91~

- new CEIS values from INT are written by RSM to TSR
a maximum of 3.8 microseconds after an associated vector has been generated; thus any attempt to access CEISR/TSR prior to a 3.8 microsecond delay after vector generation may result in reading old CEIS information. Thus, access to this parameter by IOP/ISO should be delayed for at least 3.8 microseconds after IOP receipt of the vector (normally, the time required in IOP for leaving task mode and linking to the interrupt handling routine would exceed 3.8 microseconds, so no special delay action by IOP should be needed to meet this requirement).

12.2.9.2 IHEISR

Referring to Fig. 38, this register has 10 actively used "status indicating" bits (WPE, APE, LID, PWE, PIA, DPE, NDS, WSE, PPE, DBE) and 4 actively used "source" indicating bits (ITE, LTO, ESD, DTO) having the following uses:
WPE (Write Protect Error) - denotes attempt by IDLC to perform unauthorized write to a protected portion of its allotted address space (the writing action is inhibited) APE (Addres~ Parity Error) - IDLC/SIO has detected parity error in the address used during a programmed operation by IPO via SIO
(if the operation was a write it is suppressed) LID (Lost Interrupt Detected) - IDLC (SIO) has detected an interrupt acknowledge cycle (IACK) but has no pending vector to give to IOP
PWE (Programmed I/O Write Error) - indicate9 invalid attempt by IOP/SIO to perform back to back write operations relative to a 32 bit register location in the IDLC using non-sequential PIA (Programmed I/O Invalid Address) - indicates invalid attempt by IOP/SIO to access a reserved portion of the system address space allotted to the IDLC
DPE (Data Parity Error) BC9-90-001 171 20349~

- indicates detection of data parity error during programmed I/O write operation by IOP/SI~ to an IDLC RAM. Addressed location not updated when this error is detected.
NDS (No Data Strobes) - Neither of two data strobes expected during a read or write relative to an IDLC address (upper or lower strobe) was active during the operation.
- WSE (Write Data Strobe Error) , - Both upper and lower data strobes were inactive on a write sequence to internal IDLC register~
defined to be 32 bits wide.
s PPE (Programmed I/O Parity Error) - Data parity error detected during programmed read (by IOP/SIO) of IDLC address.
DBE (DMA Bus Error) ~ - BUS_ERROR active during a DMAC/MIO operation ; relative to IOP bus. IOP must read its status registers for more details, but this usually indicates either an address parity error or double bit ECC error detected (by IOP) during the operation.
ITE (Interface Timing Error) -~ - Indicates data transfer reque~t presented by Ll circuits when IDLC was not prepared to react (i.e.
a lack of synchronization between IDLC and Ll;
most likely due to a hardware failure).
LTO (Logic Time-Out) - Indicates failure of IDLC logic to complete required operation within a predetermined allotted time (usually indicates internal hardware failure).
ESD (Error State Detected) - Invalid 8tate detected in an IDLC partition state machine unit. Usually, due to hardware failure.
DTO (DMA Time-Out) - IOP did not respond to an IDLC DMA/MIO request within 50 microseconds. This time is normally ; sufficient for MIO to gain control of IOP bus, and failure to do 90 generally indlcates hardware error.

~C9-90-001 172 2034911.
12.2.9.3 ICR

The fields in this register are detailed in the SIO
description below (refer to section 12.3.2).

12.2.9.4 HPCR

Details of the fields contained in this register and their usage are given in the RSM description (refer to section 7.3) 12.3 SIO PARTITION

12.3.1 SIO OPERATIONS

SIO interfaces between INT and the IOP, for conveying interrupt requests and associated vectors to the IOP and for providing IOP access to individual register and RAM address space locations throughout the IDLC; both for supporting IOP
retrieval of interrupt status and/or diagnostic information and for enabling the IOP to programmably establish initial states of IDLC elements and channels. When communicating with the IOP bus, SIO i9 a "slave" of the IOP; i.e. all of it~ operations for transferring information over the IOP bus are dependent upon IOP initiative for execution. Also, its operations relative to the IOP and other IDLC elements are conducted in asynchronous time relation to processing operations in IDLC channel~.

12.3.2 SIO LOGICAL ORGANIZATIO~

Fig. 43 ~hows the logical organization and external interface8 of the SIO partition. This partition interfaces within the IDLC to the INT partition, to all IDLC RAM's and to ma~or registers in all other partitions. Externally, it interface~ to the IOP bus and Ll circuits.
Logical functions of the partition are performed primarily by two independently operating state machine units 280 (ICM or IOP Control Manager state machine) and 281 (PIO
or Program I/O Mapper state machine). As suggested by their names, the ICM state machine is responsible for interfacing ~C9-90-001 173 to the IOP bus 282, and the PIO state machine is responsible for the movement-of data over the programmable I/O interface 283-284 between SIO and the IDLC RAM's and other partitions.
The ICM state machine is solely responsible for interfacing to the INT partition with respect to transferral of interrupt requests and vectors from the latter to the IOP
bus, and also operates to control transfers of IDLC status information from latches 285 into which such data is written under control of PIO state machine.
The ICM state machine interfaces directly to the IOP
bus at 286-288, for exchanging control signals with the IOP
which control transfers of data between SIO and the IOP.
These control signals are designated in a notation "X_Y"
where X is the driving source and Y is the signal function.
A period (".") is placed either to the left or right of the signal name to associate that name with the line respectively to the left or right. For example, ".IOP_INTACK" associates with line 286 to its left (driven by the IOP) and represents the latter's acknowledgement of receipt of an interrupt reque~t/vector set; and "SIO_INT."
asqociates with line 288 to its right and represents an interrupt request indication driven by ICM/SIO.
Data outbound to the IOP is transferred from SIO bus triver circuits 289 to the IOP bus under enabling control of ICM state machine. Data inbound from the IOP bus is received at 290 along with IOP-driven address signals at 291. Inbound data and addresses are respectively checked by parity check circuits 292 and 293 having not-shown output connection to ICM for indicating errors to the latter.
Outbound data is presented to bus drivers 289 via ~elector circuits 294 and 295 both controlled by ICM state machine 280. Selector circuits 294 receive inputs from interrupt vector latch sources 296 and 297. Latches 296 receive hardware error vectors sent to it from INT under the control of INT_CHP state machine described above. Latches 297 receive channelized event/condition vectors under control of INT_CHN state machine described previously.
Selector circuits 295 receive data from read data latches 298. Latches 298 are loaded from outputs of selector circuits 300. Operations of circuits 300 and loading of latches 298 are controlled by PIO state machine 280.
,, .

,' .
.; , . . .... .. .. .

~C9-90-001 174 20349~

Circuits 300 selectively transfer data from RSM, TSR, FIFOR, DMAR, and several registers. The data path from RSM allows for transfer of the contents of the HPCR (HDLC Protocol Configuration Register) located in RSM. The other registers feeding selector 300 include the IHEISR register located in INT, and two SIO registers, ICR (IDLC Configuration Register) 301 and HCR (HyperChannel Configuration Register) 302. Details of ICR field assignments are given below, and details of the HCR fields are given in the HyperChannel description (section 15).
Referring to ICR Fig. 44, the fields are:
RES (Reserved 12 bits) MTO (Master Time Out, 4 bits) - programmable timer values which determine the length of time the IDLC will wait for a slave acknowledgement when performing a master operation SEM (Slave Error Mode) - The IDLC will not acknowledge a slave access which is in error if the SEM bit i9 inactive. It will acknowledge and assert a bus error indication in an erroneous slave access if the SEM bit is active RST (Reset) , - This bit provides the software a means to do a system reset via the SIO
QM (Queue Mode) - - This bit determines whether single or multiple status words are to be taken when a vector i9 j pre9ent (See INT logic element for detail) WP (Write Protect) - This bit is used to protect the contents of an Electrical Eraseable Read Only Storage (EEROS) element external to the IDLC
IIVO (IDLC Interrupt Vector Offset, 6 bits) - This field is used to generate the upper six bits of the eight bit manual vector for all IDLC chip level lnterrupts CIVO (Channel Interrupt Vector Offset, 2 bits) - Thi8 field is used to generate the upper two bit8 of the eight bit manual vector for all channel level interrupts TPS (TSR Page Select) , .

~C9-90-001 175 20349 - This bit is used to select either the upper or lower page of the TSR (Notice that a page in TSR
is lK x 36) MODE (3 bits) - This field places the IDLC to operate in various modes:
Normal operation, reset, forced error normal, forced error reset, and quiet. The various modes provide features for diagnostic purposes. When normal operation mode is set, the IDLC will start operating. When reset mode is set, the IDLC is in idle mode. When forced error normal mode is set, the IDLC operates in normal mode and forces parity error on all SIO write operations. When forced error reset mode is set, the IDLC operates in reset mode and forces error on all SIO write operations. When quiet mode is set, the IDLC
operates in normal operation mode but no interrupts will be asserted by the IDLC.

The IOP bus provides an 18-bit interface to SIO (16 data bits, 2 parity bits), and SIO interfaces to the 32-bit wide internal data busing of the IDLC. Inbound and outbound data is transferred over the IOP bus in 18-bit parallel units (two 8-bit bytes with two associated parity bits) accompanied by upper and lower data strobe functions (.IOP_UDS and .IOP_LDS) at 286 indicating which bytes are valid. Outbound data is loadable into latches 298 in 36-bit parallel units (4 bytes plus parity) and can be transferred o~er the IOP bus in a two-cycle transfer operation, in which 18-bit part8 of the data are multiplexed to the bus through ICM data selector 295.
Data inbound to SIO from the IOP bus is transferrable in 18 bit parallel data unit~ (two 8-bit bytes and associated parity bits), accnmpanied by 24 bit address units designating the ultimate destination within the IDLC. The IOP can direct data to 32 bit wide registers in the IDLC by sequentially transferring a pair of 18 bit inbound data units over the bu8 in a two-cycle transfer operation. The first 18 bit unit of such a pair is latched into data latches 304, allowing for parallel presentation of the pair , .

. ' .. : :- ~ .. . . .

~C9-90-001 176 2034911.

on 36-bit wide extension bus 305 (one 18 bit unit from latches 304 and the other directly from the IOP bus). Bus 305 (SIO_DATA_BUS) extends to the other IDLC partitions and RAM's.
Inbound address units are applied through ICM decoder 306 to ICM state machine 280, and through PIO decoder 307 to PIO state machine 281. Two bit latch 308 ("First Cycle Information" latch) is used by ICM to remember control parameters of the first cycle of a two-cycle back-to-back transfer operation; i.e. if the first cycle transfer is a read from the IOP or a write to the IOP, and if the least , significant addre~s bit of the first cycle is odd or even (the latter information is used to verify that the back to back transfers occurred on a word boundary).
; In inbound data transfers to other IDLC elements, the address decoded by ICM decoder 306 is applied to ICM state ~ machine and from the latter to ICM address latches 309 ; feeding into the PIO state machine. Using that information, PIO state machine determines when it should activate the output of its decoder 307 to provide the address SIO_ADDRESS_BUS which is distributed internally to other IDLC partitions and RAM's.
The data path to RSM (interface 283 and RSM_DATA at 284) allows the IOP to perform diagnostic read and write functions relative to the internal latches of RSM which are uset for time swapping.
- The ICM and PIO state machines intercommunicate through a request/acknowledge interface. ICM presents read and write requests (ICM_PIO_RD, ICM_PIO_WR) which PIO acknowledges (with PIO_RD_ACK, PIO_WR_ACK).
The ICM state machine has 32 possible states described below, by which it manages the asynchronous IOP bus protocol for slave transfers and the internal protocol for interfacing the 16 bit architecture of the bus to the 32 bit lnternal architecture of the IDLC. All control signals from the IOP (.IOP_RD/WR, .IOP_LDS, .IOP_UDS, .IOP_ADDR_STRB, .IOP_CHP_SEL, .IOP_RESET, and .IOP_INTACK) are latched prior to synchronous input to the ICM state machine whlch runs on a 50 ns clock. Parity checking on both the address and data buses of the IOP (IOP_ADDRESS, and IOP_DATA_BUS) is done on a byte basis.

U
! . . .

~C9-90-001 177 2 03 4 9 The start of an IOP bus cycle is indicated when both the chip select (.IOP_CHP_SEL) and address strobe (.IOP_ADDR_STRB) are active at the same time. The polarity of the .IOP_RD/WR signal indicates if the cycle is a write to the IDLC or a read to the IOP (logic 1 indicates read, logic O indicates write). The lower data strobe (IOP_LDS) and upper data strobe (IOP_UDS) indicate if the upper or lower 8 bits of the data bus (IOP_DATA_BUS) are valid on a write cycle or if either/both bytes are valid on a read cycle. Write cycles to 32 bit data registers in the IDLC
require two 16 bit IOP bus cycles to occur and the ICM
temporarily captures both data and parity in latches 304 on the first cycle. On the second cycle the ICM provides a full 36 bits (32 plus 4 bits parity) to the PIO State Machine.
Read cycles from 32 bit data registers also require two 3 16 bit IOP bus cycles, and the ICM selects the first 18 bits (16 data plus 2 bits parity) using selector 295 which multiplexes the 36 bits (32 data plus 4 parity bits) irom the PIO's READ DATA LATCH 298. The ICM ADDRESS LATCH 309 is used at the end of the first cycle to latch the current IOP
address for comparison on the second cycle to verify back to back addresses with only a change in address by comparing the second least significant bit Al in the addresses of the two cycles (IOP ADRESSES are numbered AO thru A24). ICM
First Cycle Information latch 308 remembers if the first cycle i9 a read or write, and the value of Al bit. This information i9 used on the second 16 bit cycle of a 32 bit read or write. After two successful back to cycles or an ICM
detectet error cycle the First Cycle Information is cleared to a 'no history' value. ICM does data parity checking on read cycles to further isolate internal data parity errors from IOP bu9 parity error9.
ICM indlcates completion of either a read or write cycle by drivlng its data acknowledge line (SIO_DTACK.) active. Any slave error detected during either a read or write bus cycle will cau9e the ICM to withhold activation of SIO_DTACR., and set the appropriate slave error status indication bit in the IHEISR register (refer to description of that regi9ter ln the previou~ INT description). IOP times out the SIO_DTACK acknowledge from ICM on all read and write ' .

.

~C9-90-001 178 Z0349~

operations, and takes appropriate diagnostic or other action when error is indicated.
The mechanism for ICM to indicate there is an interrupt vector available for the IOP processor, is to asynchronoucly drive the "SIO_INT." signal active. This eventually causes IOP execution of task programs to be suspended and generation of an interrupt acknowledge cycle on the IOP bus.
At this time the IOP drives ".IOP_INTACK" active causing either a chip vector (CHIP_VECTOR_LATCH) or channel vector (CHAN_VECTOR_LATCH) to be driven on the lower 8 bits of the IOP_DATA_~US by ICM.
Vector latches 296 and 297 are referred to as Vector Holding Registers (VHR) and can also be accessed by the IOP
in program I/O cycles (e.g. for diagnostic purposes).
ICM provides a layer of address decode (ICM ADDRESS
DECODE) which determines selection of Ll circuits, PIO
(other IDLC parts), or VHR on read and write data transfers (Note the VHR register are read only in normal SIO
operation). The Ll decode causes the Ll chip select (Ll_CHP_SEL) signal to become active and routes data between the IOP bus and the Ll circuits. The VHR decode allows read of the VHR registers. A decode into PIO space is defined to be an access to memory mapped I/O space in the IDLC which is distinct from addresses of the Ll circuits and VHR
registers. Such decodes cause ICM to request service from PIO, by activation of .ICM_PIO_RD or .ICM_PIO_WR, depending on the direction of the IOP bus cycle. The PIO State Machine acknowledges ICM requests using the PIO_ICM_ACK signal.
PIO provides a further layer of address decode 307 (PIO
ADDRESS DECODE) beyond that done in ICM. PIO manages multiplexing and latching of data between internal 36 bit IDLC busses (32 bit data, 4 bit odd parity, except DMAR
which has a 32 bit tata, 1 bit odd parity). PIO accesses TSR, FIFOR, and DMAR RAMs using request and acknowledge signals designating respective RAM's; e.g. SIO_TSR_RD (or WR) and TSR_SIO_ACK.
Via selector 300, PIO multiplexes 36 bit data buses from TSR, RSM, FIFO, DMACR, IHEISR register, ICR register, and HCR register to the READ DATA LATCH 298, during PIO read cycles. The RSM_DATA input to selector 300 is the read path to time 9wap registers in R5M for diagnostic purposes. The :
:
'.

.iC9 - 90 - 00 1 17 9 203491 IHEISR_DATA, ICR_DATA, and HCR_DATA inputs to the selector are read paths from the IHESIR register (in INT), the ICR
register, and HCR register respectively.
On write operations, PIO distributes 36 bit data via bus 283 (SIO_DATA_BUS) to the same IDLC elements. The ICR
and HCR registers are used within the IDLC to distribute configuration and hyperchannel information to RSM partition (refer to RSM description and HCR and ICR bit description~
previously given). SIO_IHEISR_SEL extends from PIO to INT
and is used for selection of IHEISR register on transfers of IHEISR data to the IOP.

12.3.3 STATE MACHINE STATES

12.3.3.1 ICM STATE MACHINE
, . .
If SIO_RESET, then state = O.
State O: Wait for IOP processor bus cycle start.
- If IOP chip select (IOP_CHP_SEL) and IOP address ~trobe (IOP_ADDR_STRB) on IOP bus are both active then wait 50 ns to allow address parity to become stable; go to state 31.
- If interrupt acknowledge (IOP_INTACK) and address strobe (IOP_ADDR_STRB) are active, then set VECTOR_SELECTOR path to transfer vector from CHIP_VECTOR_LATCH or CHAN_VECTOR_LATCH
(CHIP_VECTOR_LATCH has higher priority than CHAN_VECTOR LATCH). Note, even though the original cause for activating the IOP_INT signal, which causes the IOP to re~pond with IOP_INTACK, may have been the loading of CHN_VECTOR_LATCH with a ~ vector, the 9election of either channel or chip vector by ICM i8 done during the IOP_INTACK cycle.
- If no vectors are pending (ie. CHP_VECTOR_LATCH
and CHN_VECTOR_LATCH are empty), then set lo~t ,` interrupt bit (LID) in IHEISR; go to state 1.
; State 1: Vector Parity Generation Delay - Delay 1 clock cycle (50 n~) to allow valid parity : to be generated at the output of VECTOR_SELECTOR
- 294. Go to state 2.
State 2: Vector parity check ., . .

~cg - go - oo 1 180 - Check parity of VECTOR SELECTOR at 294a.
- If parity is good, as~ert data acknowledge (PIO_DTACK) on IOP bus; go to state 3.
- If parity is bad, withhold data acknowledge PIO_DTACK to cause DTACK time out condition in IOP. Set Program I/O read Parity Error bit (PPE) status indication in IHEISR; go to state 14.
State 3: Reset SIO_CHN BSY or SIO_CHP_BSY indication relative to INT (these signals are monitored by INT as indications of full or empty states of CHIP_VECTOR_LATCH and CHAN_VECTOR_LATCH.
- Reset either SIO_CHP_BSY or SIO_CHN_BSY based on current multiplexed position of VECTOR_SELECTOR
(ie. If CHIP_VECTOR_LATCH is selected reset ' SIO_CHP_BSY, and if CHAN_VECTOR_LATCH is selected - reset SIO_CHN_BSY).
- If IOP_INTACK is inactive go to state 15.
- If IOP_INTACK is active go to state 7.
' State 4: Wait for PIO read acknowledge (PIO_RD_ACK) active or address strobe (IOP_ADDR_STRB) inactive.
- If PIO acknowledges read (PIO_RD_ACK), save current IOP bus address bits in ICM address latch 309, and save First Cycle Information at 308 (to i allow fast access of data from latches 298 on next consecutive read cycle, as then there is no need to request data from PIO State Machine) ; go to state 5.
~ If IOP address strobe (IOP_ADDR_STRB) is inactive then clear First Cycle Information to 'no hi~tory', as current cycle is prematurely ending.
- If chip select (IOP_CHP_SEL) is active go to state 15.
- If chip select (IOP_CHP_SEL) is inactive go to state 0.
State 5: Read Data Parity Generation Delay State - Wait for read data parity to be generated on ICM DATA SELECTOR bus by waiting for 1 clock ~, cycle to elapse (ie. delay 50 ns); go to ' state 6.
State 6: Check PIO Read Data Parity ,.. .
, . , : .

~C9-90-001 181 203491~

- Check parity on upper or lower data bus based on processor bus control signals IOP_UDS and IOP_LDS.
- If parity is good then put out PIO~DTACK; go to state 14.
- If parity is bad clear First Cycle -~ Information to 'no history', set Program I/O
, read Parity Error (PPE) status indication in IHEISR register, DO NOT generate PIO_DTACK;
go to state 14.
State 7: Wait for Interrupt Acknowledge To Go Inactive - If interrupt acknowledge (IOP_INTACK) signal goes inactive, go to state O.
- If interrupt acknowledge (IOP_INTACK) remains active remain in state 7.
State 8: Not Used State 9: PIO Write, Wait for Data Strobes (IOP_UDS
~ and/or IOP_LDS) to go Active or Address Strobe - (IOP_ADDR_STRB) to go Inactive - If either latched data strobe (IOP_UDS or IOP_LDS) has gone active then use unlatched data strobe - signals to determine valid 16 bit bus cycles being , requested. Check data parity from IOP DATA BUS.
Verify valid back to back 16 bit cycles when First Cycle Information indicates previous cycle was a . . , write.
If data strobes (UDS,LDS) or address strobes IOP_ADDR_STRB are active remain in state 9.
If parity is good and first half of 32 bit cycle then latch data, save First Cycle Information ('write with Al = O'), latch address in ICM
ADDRESS LATCH and drive PIO_DTACK active to IOP;
go to state 14.
If parity i8 good and secont half of 32 bit cycle then issue write request to PIO (ICM_PIO_WR); go to state 10.
If parity is bad, set data parity error bit (DPE) in IHEISR, DO NOT generate PIO_DTACK; go to state 14.
If either unlatched IOP_~DS or IOP_LDS are inactive then IOP has failed to drive both data . . , . "
... .
., -: ,- , . .:
:................................ : : .. .. .

~C9-90-001 182 20~49~1 strobes active or programming restriction has been violated. In either case this is not a 16 bit cycle so set no data strobes (NDS) status indication in IHEISR, DO NOT generate PIO_DTACK;
go to state 14.
- If address strobe (IOP_ADDR_STRB) is inactive, assume IOP has had a PIO_DTACK time out and current cycle is prematurely ending; go to state O.
State 10: Wait for PIO Write Acknowledge or Address Strobe Inactive : - If PIO write acknowledge (PIO_WR_ACK) is inactive or addre~s strobe (IOP_ADDR_STRB) is active then remain in state 10.
- If PIO write acknowledge (PIO_WR_ACK) is active ~' then save First Cycle Information ('write with Al j - 1'), generate PIO_DTACK; go to state 14.
- If address strobe (IOP_ADDR_STRB) is inactive then assume PIO_DTACK time out, clear First Cycle Information to 'no history'; go to state O.
State 11: Not used State 12: Not used State 13: Layer 1 Write, Wait Data Strobes Active or Address Strobes Inactive - If data strobes (IOP_UDS or IOP_LDS) remain inactive or address strobe (IOP_ADDR_STRB) remains active, remain in state 13.
- If either latched data strobe (IOP_UDS or IOP_LDS) has gone active then put out Ll chip select ,~(Ll_CHP_SEL); go to state 14. Note that Ll chip itself is responsible for returning processor ,PIO_DTACK and not the IDLC although SIO partition must continue to monitor processor bus IOP_ADDR_STRB to determine when the current bus cycle ends (ie. when processor address strobe goe~
inactive).
- If address strobe (IOP_ADDR_STRB) goes inactive assume PIO_DTACK time out; go to state O.
:S~ate 14: Wait for Address Strobe (IOP_ADDR_STRB) Inactive ., , :, :,;
'' ' ''' ~ ~

~C9-90-001 183 20349~1 If address strobe (IOP_ADDR_STRB) is active, remain in state 14.
If address strobe (IOP_ADDR_STRB) is inactive and chip select (IOP_CHP_SEL) is inactive go to ~tate O.
If address strobe (IOP_ADDR_STRB) is inactive and chip select (IOP_CHP_SEL) is active go to state 15.
State 15: Wait for Chip Select to go Inactive If chip select (IOP_CHP_SEL) is active, remain in ~tate 15.
If chip select (IOP_CHP_SEL) is inactive go to state 0.
State 16: EEROS Read State O
Hold SIO_EEROS_CE and SIO_EEROS_OE active to meet EEROS read access time (EEROS i9 optional diagnostic read only memory not pertinent to present description); go to state 17.
State 17: EEROS Read State 1 Continue to Hold SIO_EEROS_CE and SIO_EEROS_OE
active to meet EEROS read access time; go to state 18.
State 18: EEROS Read State 2 Continue to Hold SIO_EEROS_CE and SIO_EEROS_OE
active to meet EEROS read access time; go to state 19.
State 19: EEROS Read State 3 Continue to Hold SIO_EEROS_CE and SIO_EEROS_OE
active to meet EEROS read access time; go to state 20.
-~ State 20: EEROS Read State 4 Continue to Hold SIO_EEROS_CE and SIO_EEROS_OE
active to meet EEROS read access time; go to state 21.
State 21: EEROS Read State 5 Continue to Hold SIO_EEROS_CE and SIO_EEROS_OE
acti.ve to meet EEROS read acces~ time. Data from EEROS should be valid on IOP DATA BUS, but allow another clock cycle for valid parity to be generated; go to state 22.
State 22: EEROS Read State 6 , . .

:.

~C9-90-001 184 20349~1.

- Continue to Hold SIO_EEROS_CE and SIO_EEROS_OE
active to allow EEROS read data to be gated onto IOP DATA BUS from EEROS, generate IOP_DTACK
signal; go to state 14.
State 23: Read Vector Holding Register (VHR) - Select either chip vector (CHIP_VECTOR_LATCH) or (CHAN_VECTOR_LATCH) channel vector based on active vector busy signals (SIO_CHP_BSY or SIO_CHN_BSY), : giving higher priority to chip level vector - generation.
- If no vectors are latched (ie. neither SIO_CHP_BSY
or SIO_CHN_BSY is active), present hard coded empty vector value on data bus. Reset selected vector busy indication; go to state 1.
State 24: EEROS Write State O
- If EEROS Write Protect bit (WP) in the ICR
register is not active, an EEROS write protect error i5 detected, set the WPE bit in the IHEISR, DO NOT generate PIO_DTACK; go to state 14.
- If EEROS Write Protect bit (WP) in the ICR
register is active, this is a valid EEROS write cycle, provide EEROS chip select (SIO_EEROS_CE) and EEROS write signal (SIO_EEROS_WE), generate PIO_DTACK; go to state 25.
State 25: EEROS Write State 1 ~: - Continue to hold SIO_EEROS_CE and SIO_EEROS_WE
active to meet EEROS write setup and hold times;
go to state 26.
~ State 26: EEROS Write State 2 .; - Continue to hold SIO_EEROS_CE and SIO_EEROS_WE
active to meet EEROS write setup and hold times;
go to state 27.
; State 27: EEROS Write State 3 . - Continue to hold SIO_EEROS_CE and SIO_EEROS_WE
: actiVe to meet EEROS write setup and hold times;
go to state 28.
.; State 28: EEROS Write State 4 - Continue to hold SIO_EEROS_CE and SIO_EEROS_WE
active to meet EEROS write setup and hold times;
go to state 29.
State 29: EEROS Write State 5 .

~C9-90-001 185 203~911 Deactivate SIO_EE~OS_CE and SIO_EEROS_WE signals to EEROS; go to state 30.
State 30: EEROS Write State 6 Generate IOP_DTACK signals to IOP; go to state 14.
State 31: Address Parity Check, Determine Slave Read or Write, Determine PIO memory mapped access, Ll memory mapped access, or Vector Holding Register (VHR) access.
If IOP address parity is bad, set address parity error (APE) bit in IHEISR, DO NOT generate PIO_DTACK; go to state 14.
If processor bus rd/wr signal (IOP_RD/WR) indicates read cycle and Vector Holding Register memory map is decoded, go to state 23.
If IOP_RD/WR signal indicates read cycle and PIO
memory map is decoded indicating an access to TSR, DMAR, or FIFOR, ICR register, IHEISR register, or HCR register then turn on data bus driver enable, select upper or lower PIO data bus multiplexer.
If the last read cycle access address in ICM
ADDRESS LATCH matches the current IOP address and Al = 1 then the data in PIO data latch is valid and can be directly gated on to IOP bus; go to state 5.
If current IOP address has Al = O then the PIO
partition must be accessed; output ICM_PIO_RD
signal to PIO state machine; go to state 4.
If Al = 1 and the last access was a write then this is a program I/O 32 bit write sequence error, set WSE status bit in IHEISR register, set First Cycle Information to 'no history', Do Not generate PIO_DTACK; go to state 14.
If IOP_RD/WR signal indicates read cycle and Ll addre~ses are decoded then set Ll_CHP_SEL select active; go to state 14.
If the IOP_RD/WR 8ignal indicates read cycle and EEROS memory map is decoded, go to state 16.
If IOP_RD/WR signal indicates write cycle and PIO
memory mapped addre8ses are decoded then access to TSR, DMAC, FIFO'8, ICR, IHEISR, or HCR i8 being attempted.
, .

BC9-90-001 186 Z034911.

- If Al = O and the last access was a PIO write with address bit 1 (Al) = 0 then current cycle is a program I/O write sequence error, set WSE bit in IHEISR, do not put out PIO_DTACK; go to state 14.
- If Al = O and last access was not a write cycle with Al = O then this is a valid PIO write cycle for first 16 bits; go to state 9.
- If Al = 1 and last access was a write with Al = O
and previous address and current address match then this is a valid PIO read cycle for second 16 bits; go to state 9.
- If Al = 1 but either the previous cycle was not a write with Al = O or the current and previous addresses do not match then this is a Program I/O
write error, set PWE bit in IHEISR, DO NOT
generate PIO_DTACK; go to state 14.
- If IOP_RD/WR indicates a write and the Ll chip addresses are decoded, activate Ll_CHP_SEL and go to state 13.
- If IOP_RD/WR indicates write cycle and EEROS
memory map is decoded go to state 24.
- If PIO, EEROS, Ll Chip, or VHR register address was not decoded then a Program I/O invalid address in IDLC memory map was accessed, set the PIA bit j in IHEISR register, DO NOT generate IOP_DTACK; go to state 14.

12.3.3.2 PIO State machine I If SIO_RESET, de-activate all selects, acknowledgmentst ant enable8; go to state 1.

~ State 1: Wait ICM_PIO_RD or ICM_PIO_WR
fi,~ - Wait for a read ICM_PIO_RD or write ICM_PIO_WR
request from the ICM.
- If no requests are active remain in state 1.
. - If either ICM_PIO_RD or ICM_PIO_WR becomes active, begin decoding IOP ADDRESS using PIO
! ADDRESS DECODE logic and move to state 2.
State 2: Select partition based on address 20349~1 If none o~ the partitions (TSR, DMACR, FIFO, or RSM) or none of the registers (IHEISR, ICR or HCR) addresses were decoded by PIO ADDRESS DECODER then an invalid address was decoded, go to state 5.
If a valid address for a partition was decoded, enable select line (SIO_DMACR_RD~ SIO_DMACR_WR, SIO_FIFO_RD, SIO_FIFO_WR, SIO_TSR_RD, SIO_TSR_WR, SIO_RSM_RD, or SIO_RSM_WR) to appropriate partition, based on the address decoded and the ~tate of IOP_RD/WR signal; go to state 3.
If a valid address for a register was decoded and the IOP_RD/WR signal indicates a write cycle, enable the select line to the appropriate register to strobe the data from the SIO_DATA_BUS into the register, generate PIO_WR_ACK ; go to state 4.
If a valid addres~ for a register was decoded and the IOP_RD/WR signal indicates a read cycle, enable the PIO SELECTOR and READ DATA LATCH to the appropriate register, generate PIO_RD_ACK; go to state 4.
j State 3: Wait Partition Acknowledgment for Read Wait for the appropriate partition acknowledgement (DMACR_SIO_ACK, FIFO_SIO_ACK, TSR_SIO_ACK or RSM_SIO_ACK), or the ICM_PIO_RD signal to become inactive.
If no acknowledgement or ICM_PIO_RD remains active then remain in state 3.
If ICM_PIO_RD signal becomes inactive this indicates the IOP bus cycle i9 pre-maturely ~-ending, set Program I/O read Parity Error bit (PPE) in IHEISR go to state 1.
If appropriate partition acknowledgement occurs, generate PIO_RD_ACK signal, go to state 4.
:~ State 4 : Wait ICM request de-assertion Wait ~or the ICM_PIO_RD or ICM_PIO_WR request to be d~-asserted.
If ICM_PIO_RD or ICM_PIO_WR are active remain in this state. If ICM_PIO_RD and ICM_PIO_WR are inactive go to state 1.
State 5 : Invalid Address State . .

BC9-90-001 188 Z03~9~1 - If an invalid address in PIO address space was decoded set Program I/O Invalid Address bit (PIA) in IHEISR register and do not respond to ICM
request. This will cause the IOP to eventually timeout the data acknowledge IOP_DTACK. Wait for either ICM_PIO_RD or ICM_PIO_WR to go inactive; go to state 1.

All remaining states are invalid/unused; if any of these are entered, assert Error State Detected bit (ESD) in IHEISR. Go to state 1.

13 DMARQ, DMA RAM AND DMAC ELEMENT

13.1 DMARQ

DMARQ (DMA Request Queue) is a set of "request"
registers and selection logic for conveying requests for action from the FIFO managers (RFM, TFM) to the DMAC (DMA
Control) partition, and for returning acknowledging (reset) indications from DMAC to the requesting partitions. DMARQ
provides an operational interface between synchronous processing elements of the IDLC (RFM, TFM) and asynchronous processing elements (DMAC). Requests from RFM and TFM are received in DMARQ register latches synchronously; i.e.
during respective time slots of pre~entation by RFM, TFM.
Logical organization of DMARQ is shown in Fig. 47. The request registers are organized into 3 distinct register queues indicated at 330, 331 and 332. Input selector circuit 333 routes request setting and resetting inputs to individual queues 330 - 332 and to selected bit positions within the queues. The 8etting inputs originate from TFM and RFM, and the resetting inputs from DMAC.
Output selector 334 presents indications of request bit 8tates in the queues to RFM and TFM in time multiplex; i.e.
in 8ynchronism with channel/slot processes. Indications to RFM, DMAR QRFM_REQ, when active in any time slot, indicate pentency of a request for DMA data transfer action relative to the receive 8ide of the channel as80ciated with that slot. Indications to TFM, DMAR QTFM_REQ, similarly indicate BC9-90-001 189 203~911 pendency of requests for data transfer relative to transmit sides of channels associated with respective slots.
Outputs of all positions in queues 330 - 332 are also presented in parallel to DMAC at outputs respectively designated 330a -332a. Positions having pending requests have active outputs and other positions have inactive outputs. Selection controller 335 directs the routing of request setting and resetting signals through input selector 333 (from the FIF0 managers and DMAC respectively), and the routing of indications of queued request status functions through multiplexing selector 335 to the time-slotted output~ at DMARQRFM_REQ and DMAR QTFM_REQ.
For reasons which will become apparent, as allowed mappings of BTDM slot time positions to HyperChannels and B
type channels is explained generally below, DMAC prioritizes its handling of requests at 330a-332a, according higher priority to Hl HyperChannel requests at 330a than H0 HyperChannel and B/D channel requests at 331a and 332a, and higher priority to H0 requests at 331a than to B/D requests at 332a. Between receive and transmit requests, priority is accorded (arbitrarily) to receive requests in each HyperChannel or channel over transmit requests in the same channel.
Each queue contains a number of request posting (bit) positions corresponding to the maximum number of respective channels associatable to the queue. Since only one Hl type HyperChannel is supportable in the 32 available slot times per BTDM time frame (see HyperChannel description in section 15, hereafter), the associated queue 330 contains 2 bit positions (one for receive data requests and the other for transmit data reque9ts). Since 5 H0 type HyperChannels are 8u8talnable (when no Hl HyperChannel is active), queue 331 contains 10 bit positions (5 for receive data requests from each of 5 H0 HyperChannels, H01 through H05, and 5 for transmit data reque9ts from the same HyperChannels).
Finally, since basic slot time positions at BTDM are assignable to intividual B/D type channels, queue 332 contains 64 bit positions (32 for receive data requests relative to such channels, and 32 for transmit data requests in the same channels).

BC9-90-001 190 2034911.

The parallel queue outputs at 330a, 331a and 332a have lines from each of the respective queue bit positions. Thus, 330a contains 2 lines (1 for receive, other for transmit), 331a contains lO lines (5 receive, 5 transmit) and 332a contains 64 lines (32 receive, 32 transmit). Each line when active indicates that a request is actively pending in the respective queue position.
Since HyperChannels receive IDLC service during plural time slots in each BTDM frame, while B type channels receive service only in a single slot per frame, it should be apparent that HyperChannel requests for DMA data transfer require faster DMAC service than B channel requests if the allotted bandwidth is to be used efficiently. Furthermore, since Hl HyperChannels have greater allotted bandwidth than H0 type HyperChannels, Hl requests must receive faster DMA
service than either H0 or B/D channel requests. Accordingly, the basis outlined above for according DMAC priority (to Hl reque8ts over H0 or B channel request9, and to H0 requests over B channel requests) should now be understoot.
Selection controller 335 receives request inputs from RPM and TFM to set requests for receive and tran8mit service in the DMARQ registers, RFM_DMAR QSET and TFM_DMAR QSET
respectively, and separate inputs from DMAC to reset such requests as they are serviced, DMAC_DMARQ RCV_RESET and DMAC_DMAR QXMIT_RESET respectively.
Relative to setting requests from RFM and TFM, - controller 335 receives additional selection steering inputs s from RSM. RSM_DMAR QHl or RSM_DMAR QH0 effectively designates one of the queues 330-332 (queue 330 if the Hl select is active, queue 331 if the H0 select is active, and queue 332 if nelther select source is active). The 5-bit ~ time slot indication pointer, RSM_TSI, effectively j deslgnates a pair of (receive and transmit) request po8itions in the selected queue. The request source, RFM_DMARQ SET or TFM_DMAR QSET, determines whether which position of the selected pair is actually set (the receive or transmlt position).
Relatlve to resettlng requests from DMAC, controller 335 receives coded input from DMAC, DMAC_H-B_SEL, designating selection of one of the queues 330-332, and a pointer lnput designating selection of a pair of register ., , 20349~

positions in that queue, DMAC_H_PTR or DMAC_B_PTR
respectively. The reset request source, DMAC_DMARQRCV_RESET
or DMAC_DMARQ XMIT_RESET, determines which member of the selected pair is reset (the receive or transmit member).
Relative to HyperChannels, each of which encompasses a plurality of BTDM slot positions (see description of HyperChannels below), the time slot indication RSM_TSI is translated by RSM from a value associated with the current time slot count to a value associated with the time position of a reference (first appearing) one of the time slots incorporated into that HyperChannel. Thus, all actions taken relative to the respective HyperChannel (in DMARQ, in time swapping relative to TSR, and in transfers relative to FIFOR) are directed to positions associated with respective reference time slots. The HyperChannel TSI translation by RSM is determined as a function of information placed into the HCR register by IOP/SIO when the HyperChannel mapping is established (see HyperChannel description below).
When ready to do so, DMAC services requests posted in queues 330 - 332, one at a time and in (descending) priority order: Hl receive, Hl transmit, HO receive, HO transmit, B/Normal Channel receive, B/Normal channel transmit. DMAC
state logic remembers the origin of each request selected to be serviced, and when ready to reset the request in DMARQ
that information is used to determine states of appropriate reset selection signals; selector DMAC_H-B_SEL, active one of the 2 pointers DMAC_H_PTR or DMAC_B_PTR, and active one x of 2 receive/transmit reset indicators DMAC_DMAR Q RCV/XMIT_ RESET. Thus, DMAC resets the respective request by activating inputs to ~election controller 335: (1) DMA~_H-B_SEL selecting one of the 3 queues 330-332; (2) one oP DMAC_B_PTR or DMAC_H_PTR, distinguishing a pair of i positions in the selected queue; and (3) one of : DMAC_DMAR QRCV_RESET or DMAC_DMAR QXMIT_RESET indicating which po9ition of the pair to reset.
During the processing interval of each slot assigned to - a HyperChannel, RSM translates time slot indication RSM_TSI
into a value associated with the respective HyperChannel and activates a respective one of RSM_DMAR QHl or RSM_DMAR QHO.
In time multiplex, and based on instantaneous values of RSM_TSI, RSM_DMAR QHl, and RSM_DMAR QHO, selection ~C9-90-001 192 ~0349~

controller 335 directs output selector 334 to place at its outputs 334R and 334T signals corresponding to states of associated bit positions in associated queues; such outputs corresponding to the status of receive DMA and transmit DMA
request handling in the channel currently being synchronously served (the one corresponding to TSI).
Outputs 334R and 334T are directed respectively to RFM
and TFM. Thus, when 334R indicates set status, while RFM has an associated request setting output, RFM will deactivate its output while maintaining internal status remembering that it has a request pending relative to the respective channel. When 334R indicates reset status, while the internal RFM indication is that of a pending request (thereby indicating to RFM that its request has been serviced by DMAC), RFM will reset its internal indication and resume processing of receive data relative to FIFOR.
Similar actions are taken by TFM relative to indications at 334T.
At system reset, all registers in queues 330 - 332 are reset. During subsequent receive data processing, as RFM
load8 a fourth byte of receive data into FIFOR, in the buffer space allotted to the channel currently being served (the RDCR2 space of that channel), RFM activates a request setting indication RFM_DMAR QSET to DMARQ. This causes DMARQ
to set a respective bit position in one of its queues, thereby presenting a set indication on a corresponding line at 330a, 331a or 332a, which signals pendency of a corresponding request to DMAC (for receive data transfer service). As DMAC completes its handling of the request (by completing the data transfer from the respective FIFOR
buffer to IOP memory), it provide9 inputs to DMARQ a8 described which 9erve to reset the associated queue posltion, effectively indicating to RFM during the associated time slot at 334R that the DMA transfer has been completed.
Similarly, as TFM empties a buffer space in FIFOR
allotted to the channel currently being served (the as80ciated TDCR2 space), it activates a setting request TFM_DMAR QSET causing a request to be transferred to DMAC
relative to that channel. And as the DMA service is completed, loading the respective FIFOR buffer with data ~C9-90-001 193 2034911 from IOP memory, indication of that event is given to TFM at 334T.
~' 13.2 DMA RAM AND ACCESS CONTROLS

The DMA RAM (DMAR) unit, with access controls, is shown in Fig. 48. It is used to store data presented by DMAC and SIO, and to fetch data to those partitions. Its channelized contents (per channel 3pace allocations) are shown generally in Fig. 8. As indicated in the latter figure, each channel i8 allocated 4 word spaces for storage of terms RDCR3, RDCR4, TDCR3, and TDCR4 (RDCR and TDCR respectively denoting Receive and Transmit DMA Configuration Registers), having forms shown in Figs. 50-53 discussed below.
Referring to Fig. 48, the unit comprises 128 x 33 RAM
array 350, receiving data and address inputs from selector circuits 351 and furnishing data outputs at 352 to bus 353.
Input selector 351 receives (addres~ and data) inputs from SIO ((SIO_ADDRESS_BUS and SIO_DATA_BUS) and DMAC
(DMAC_CHN_NBR, and DMAC_DMAR_BUS). Data outputs from the array (DMAR_DATA) are furnished to DMAC and SIO via bus 353 along with acknowledging outputs discu~sed below which effectively designate which partition is to receive the data.
Input DMAC_CHN_NBR to selector 351 represents a partial address of an associated channel space in array 350. It is ad~usted by the ~tate logic of DMAC to correspond either to the slot number of a B/D channel (equal to the value of DMAC_B_PTR) or to the reference slot number of a HyperChannel (the DMAC_H_PTR value), depending upon the type of DMAC reque8t currently being served (refer to description of request latches 355 below). Since each channel is allotted 4 word spaces in array 350 (those containing the associated RDCR3, RDCR4, TDCR3 ant TDCR4 parameters), the channel number function by itself i9 insufficient to address the individual word spaces.
Operations of array 350 are controlled by state machine logic 35~ in response to read and write request signals received in DMA request latche~ (DRL) 355. Inputs to latches 355 originate from SIO (SIO_DMAR_RD, SIO_DMAR_WR) and DMAC
(DMAC_DMAR_WRl, DMAC_DMAR_RD2 and DMAC_DMAR_WR2). The state ~C9-90-001 194 203491~

machine monitors the latched requests, resolves any contentions between co-existent requests to select one request at a time, and provides control signal outputs to array 350 at 356, acknowledging outputs to SIO at 357, and acknowledging outputs to DMAC at 358 and 359. The control signals at 356 include additional address bits required to complete the partial address designated by DMAC_CHN_NBR.
DMAC provides a qualifying input to latches 355, DMAC_RCV_REQ, for enabling state logic 354 to distinguish RD2 requests (DMAC_DMAR_RD2) associated with receive channel functions from WR2 requests (DMAC_DMAR_WR2) associated with transmit channel functions (the former requiring fetching of RDCR3, RDCR4, and the latter TDCR3, TDCR4). The qualifying input is used by the state logic to generate the appropriate partial address.
The state machine logic also provides acknowledgement and final completion indications to DMAC (DMAR_DMAC_ACKO, _ACKl, _DONE) at 360 for enabling the latter to determine when to begin the second of a pair of consecutive operations on a 2 word write (WR2) or read (RD2) rèlative to consecutive locations in the array (all DMAC reads are 2 word reads). The state machine also conducts an output parity check operation and provides indications of parity error (DMAR_PARITY_ERROR) to INT at output 361.
The state machine sequences through 3 states to perform each array access operation. A first state provides selection control signals at 362 to selector 351 directing the latter to select either DMAC or SIO address/data inputs (to simplify the discussion, the "channel number" input to selector 351 from DMAC, DMAC_CHN_NBR, is termed the latter's address input; although each such input requires an offset -- provided by selector 351 in response to specific selection inputs received at 362 -- to locate the specific 1 of 4 word spaces to be read or written relatlve to the channel de9ignated by that number).

_.2 1 (DMAR~ STATE MACHINE STATES

If reset, go to state 0.
STATE O (Arbitration State) ~C9-90-001 195 203~911.

This state prioritizes DMAC and SIO requests presented simultaneously to selector 351, giving priority to DMAC requests over SIO requests.
All read requests from DMAC are 2 word reads (DMAC_DMAR-RD2), as distinct from write requests which can be for either 1 or words. On such read requests, array control signals from the state machine to the array (at 35~) are activated; these designating array selection, read and clock enable functions. Selector 351 is operated -to pass the address (DMAC_CHN_NBR with offset) to be read to the array address lines. Go to state 6.
On a 1 word write from DMAC (DMAC_DMAR_WRl), array control signals are activated for array selection, write and clock enablement. The DMAC address and data are passed from selector 351 to the array. Go to state 7.
On a 2 word write from DMAC (DMAC_DMAR_WR2), array selection controls are activated, and DMAC address and data are input to the array, as for 1 word write. However, go next to state 8.
On read request from SIO (all are 1 word only), array controls activated for read and selector 351 i8 operated to pass SIO address (SIO_ADDRESS_BUS) to the array address input. Go to state 3.
On write request from SIO (all 1 word only), array controls activated for write selection and selector 351 i8 operated to pass SIO address and data inputs to respective array inputs. Go to state 9.
STATE 1 (First ACK to DMAC and Array Preparation For Second Read Access) On a DMAC read (all are 2 word only), this state is used to acknowledge the first part of the request and to prepare the array for the second word fetch. DMAR_DMAC_ACKO i8 asserted as the first acknowledgement (indicating that bus 353 contains valid data for DMAC), and parity of the output data is checked. If parity error i9 detected, the error indication to DMAC
(DMAR_PARITY_ERROR) is set. The address offset to dC9-90-001 1~6 2034911 be selected by selector 351 is adjusted to point to the next location to be read. The read and array select control inputs remain active from the previous state (state 6) and the array clock enable signal i9 re-activated. Go to state 5.
STATE 2 (First ACK of 2 Word DMAC Write) - DMAR_DMAC_ACKO is asserted to DMAC. DMAC address offset adjusted to point to next location to be written. Write select and array select functions remain active from previous state (state 8), and clock enable is re-activated. Go to state 10.
STATE 3 (Accessing Array For SIO Read) - Array controls activated for read (array clock is pulsed active and then deactivated). Go to state 13.
STATE 4 (Checking Parity On Second DMAC Read Access) - DMAR_DMAC_DONE and DMAR_DMAC_ACKl are asserted to DMAC. Array output data is parity checked. If there is parity error, the parity error indication to DMAC is activated. Array control signals are all deactivated. Go to state O.
STATE 5 (Reading Second Word of DMAC Read) - Array clock (re-activated in State 1) is de-activated. Go to state 4.
STATE 6 (Reading First Data Word On DMAC Read Request) - Array clock pulsed active then inactive. Go to state 1.
STATE 7 (Write Word For DMAC 1 Word Write Request) - Array clock pulsed active then inactive. Go to state 11.
STATE 8 (Write Fir8t Word Of 2 Word DMAC Write Request) - Array clock pul8ed active then inactive. Go to state 2.
STATE 9 (Accessing Array For SIO Write) - Array clock pulsed active then inactive. Go to state 13.
STATE 10 (Write Second Word On DMAC 2 Word Write) - Array clock pulset active then inactive. Go to state 12.
STATE 11 (Acknowledging DMAC 1 Word Write) ~C9-9~-001 197 203~9~

- DMAR_DMAC_ACK0 asserted, indicating that DMAC's data has been written into the array. Array control signals are deactivated. Go to state 0.
STATE 12 (Second ACK To DMAC On 2 Word Write) - DMAR_DMAC_ACKl asserted to DMAC. Array controls de-activated. Go to state 0.
STATE 13 (Acknowledging SIO Write) - DMAR_SIO_ACK is asserted. Array controls are deactivated. Go to state 0.

13.2.2 CONTROL WORDS STORED IN DMAR

Channelized control information used by the FIFO
manager and DMAC is stored in FIFOR in RDCRl and TDCRl (Receive and Transmit DMA Control Register) spaces allocated to each of the basic channels (see Fig. 7). Channelized control information used only by DMAC is stored in DMAR in RDCR3, RDCR4, TDCR3 and TDCR4 word spaces allocated to each basic channel (see Fig. 8). Information ~tored in the~e word spaces has the following specific form and usage.
RDCRl (see Fig. 33) consi~ts of 8 reserved/unused bits (RES), a receive boundary check (R~C) bit, a receive parity error (RPÉ) bit, and a 22-bit receive DMA current address (RDCA) field. The RBC bit is set active when the DMAC
encounters a boundary check condition (RDCA matches a preset boundary address RDBA in RDCR4 discussed below) while servicing an RFM request relative to a FIFOR receive data queue. RFM monitors the RBC bit, and when the latter is active passes an indication to INT which eventually results in IOP being informed of the check condition via interrupt.
RDCR3 (Fig. 50) comprises 2 reserved/unused bits, an 8-blt RDLAH (Recelve DMA Last Address High), and a 22-bit RDFA (Receive DMA First Address) field. The RDLAH field represents the upper 8 bits of a 20 bit address denoting the end of the re8pective channel's IOP receive buffer. Together with the RLAL field in RDCR4, the RDLAH field is used to determine the full end address of the respective channel's IOP receive buffer. RDFA represents the beginning address of the re9pective channel's IOP receive buffer (although IOP
memory addresses are 24 bits, the receive buffer, by convention, begins and ends on 4-byte boundaries; hence, the ~C9-90-001 198 20349~1 2 low order bits are always O and the 22 bits of this field fully determine the beginning address).
RDCR4 (Fig. 51) comprises a 12-bit RDLAL (Receive DMA
Last Address Low) field, and a 20-bit RDBA (Receive DMA
Bo~ndary Address) field. RDLAL represents the lower 12 bits of the address of the end of the respective channel's IOP
memory receive buffer. It is concatenated to the RDLAH field above to form a full end address representing the last valid address in the receive buffer. When DMAC reaches this address without encountering a boundary check, it begins tran~ferring data next at the beginning address RDFA. RDBA
represents the 20 high order bits of a boundary address (usually RDLA + 1) beyond the last address. As the receive buffer fills with data, the IOP can prevent overwriting of data at the beginning of the buffer by setting this address to a value associated with a protected portion of IOP
memory. If DMAC attempts to write to this address a boundary check condition is set and all further received data is ignored.
In practice, the buffer size is larger than a frame, and RDBA is set programmably (by IOP/SIO) at a value between RDFA and RDLA. Initially, the position designated by the RDBA is beyond the position which would be used to hold the last byte of a frame. Consequently, after DMAC finishes loading the first frame into the buffer, IOP receives frame end interruption, empties the buffer and moves the RDBA
pointer to another position pointing to a vacated space in the buffer.
Meanwhile, DMAC continues filling the buffer and when it arrives at the last address wraps to the first address and continues filling from there. In normal operation, the size of the buffer, the timing of action by IOP in response to the frame end interruption, and the location of the boundary address relative to the first valid buffer entry which has not been removed, should be adequate to ensure that valid receive data in the buffer is not overwritten.
However, if the current address used by DMAC matche8 the boundary address, the IOP is apparently not vacating the buffer at a suitable pace and valid data may be overwritten.
Accordingly, in that circumstance, receive processing is halted in the affected channel, and a boundary check 203491~
~C9-90-001 199 indication is passed to RFM via RDCRl causing an INT
interrupt to be generated notifying IOP of the abnormal condition.
TDCRl (Fig. 35) contains 7 reserved bits (RES), an ECD
(End Of Chain Detected) bit, an EFD (End Of Frame Detected) bit, a NDI (No Data Indicator) bit, a 2-bit TBC (Transmit Buffer Count) field, a 2-bit TOPQ (Top Of Queue), a 2-bit TPE (Transmit Parity Error) field, and a 16-bit TDBC
(Transmit DMA Byte Count). The 1 bit indicators are set by DMAC when respective end of chain, end of frame or no data indicated conditions are encountered (end of chain and end of frame are indicated by DCB bits, no data indicator is activated when DMAC encounters an end of buffer condition while servicing a request to fetch transmit data).
TDCR3 (Fig. 52) contains 8 reserved bits and a 24-bit TDBA (Transmit DMA Buffer Address) field. The TDBA field indicates the next source of transmit data (although 24 bits long, best practice would be to require the 2 low order bits to be zero and locate transmit data only on word (4/byte boundaries). The reason for this is that if data could be fetched at arbitrary byte boundaries, the result could be fetching of e.g. a single byte to FIFOR which in turn would pass through the IDLC transmit path (FIFOR, TFM, TV, TLl) much faster than 4 bytes and therefore increase the possibility of underrun.
Finally, TDCR4 (Fig. 53) comprises 10 reserved/unused bits, an ECI (End Of Chain Indicator) bit, an EFI (End Of Frame Indicator) bit, and a 20-bit DCBA (DCB Address, DCB is abbreviation for DMA Control Block) field. ECI and/or EFI
are respectively activated when DMAC encounters end of chain and/or end of frame indications in the current DCB. An active ECI indicates to DMAC that no further DCB's are to be fetched after the IOP transmit data buffer currently in u8e is exhausted. Active EFI means that after the current buffer is exhausted, the TFM must provide end of frame indication causing TLl to insert a frame end sequence after the last data byte is sent. The DCBA is the addre~s at which the next DCB of an unexhausted DCB chain is to be fetched.
13.3 DMAC

~C9-90-001 200 Z0349~1.

The DMA Controller DMAC interfaces to DMAR and FIFOR
for transferring receive data from FIFOR to the IOP and transmit data from the IOP to FIFOR under direction of control information stored in DMAR. Such transfers are initiated in response to requests posted to the DMARQ
partition by RFM and TFM, and latched in individual register positions of DMARQ as described earlier. DMAC interfaces to DMARQ for receiving latched requests, acting upon theln in a predetermined priority order, and clearing them (through resetting inputs to DMAR~ as described earlier).
Upon accepting a request from DMARQ, DMAC cooperates with MIO partition, DMAR and FIFOR to conduct a DMA data transfer between IOP memory and FIFOR. In this process, MIO
arbitrates for access to the IOP bus, and upon obtaining such conducts the data transfer between DMAC and IOP memory.
DMAC handles transfers relative to FIFOR and DMAR
separately. In its data transfer operations, MIO passes signals from DMAC to the IOP bus (read/write and address control signals and write data signals).
In the presently described embodiment, operations of DMAC relative to receive data differ from operations relative to transmit data in several respects. Receive data is processed relative to a single block of IOP memory with all operations of the DMAC tightly controlled by the IOP
through programmed loading of control information into DMAR
and FIFOR via SIO.
Transmit data i8 processed by the DMAC in response to data control block (DCB) command arrays stored in DMAR which are "chainable". The first DCB in a chain is loaded into DMAR by IOP (via SIO), but after the IDLC completes the data transmittal function defined by that DCB, and recognizes a chaining indication in the DCB, DMAC fetches another DCB
from IOP memory to DMAR and the process is repeated. Each DCB can point to a dlfferent block of IOP memory as the source of transmit tata (so that data in scattered blocks can be gathered by the DMAC through the actions of chained DCB's) and operations relative to chained DCB'~ can be carried out without interruption of the IOP (to indicate end of frame points in the tran~mittal proce~s).
Receive data is written from FIFOR (via DMAC and MIO) to a ~ingle block of IOP memory space managed by the IOP as ~C9-90-001 201 203~911.

a circular buffer. In normal circumstances, such data is loaded into successive buffer locations, from a highest address position to a lowest address, and then DMAC
automatically wraps/returns to the lowest position and repeats the progression. In such circumstances, IOP receives end of frame interruptions (from INT), and manages timely removal of data from the buffer, so as to permit repeated use of the buffer.
The buffer size is selected (by the IOP memory management software) to hold more than a frame of receive data relative to each active channel. After each frame end interruption, buffered data is removed (to another location in IOP or host memory) and the IOP reinitializes the associated channel and the control information in DMAR (via SIO). At each such reinitialization, IOP sets a new boundary address value in DMAR which imposes limits on DMAC access to IOP memory space. This boundary address is progressively moved to lie ahead of the space needed for entry of the next received frame.
In normal operation, the removal of data and repositioning of the boundary address by IOP will be conducted fast enough, relative to the data loading operations of DMAC/MIO, that the boundary address position 8hould not be overrun. An important function of the DMAC is to detect when its current IOP memory address for receive data coincides with the above boundary address, and to provide a boundary check indication at such times (for informing the IOP, via an associated interruption handled by INT and SIO, that valid data has been overwritten).
Transmit data is transferred from blocks of IOP memory designated by initial address functions in DCB's which are chalnable; i.e. they contain chaining indications (placed therein either initially when the DCB was loaded into IOP
memory, or through programmed operation via SIO while the DCB resides (whereby IOP can optionally extend the length of a DCB chain on a dynamic basis when its proce8sing capabilities permit such). Chained blocks of transmit data (i.e. blocks who8e lnitial locations are specified by chained DCB'8) may thereby be scattered, overlapping or coincide po8itionally in IOP memory depending upon processing capabilitie8 of the IOP.

~C9-90-001 202 2034911 An important function of the DMAC in respect to transmit data is to delimit frame boundaries in data being forwarded to link channels operating under framing protocols, and to indicate such to the IOP without corresponding INT interruptions. As explained earlier, this is done by including such delimiting information as part of the status associated with frame end receive data interrupts.

13.3.1 DMAC LOGICAL ORGANIZATION

The logical organization of the DMAC is shown in Fig.
49. It includes state machine logic indicated generally at 380, five registers shown at 381 - 385, a multiplexing circuit shown at 386 and a compare circuit shown at 387.
State logic 380 comprises two state machine units 380A
and 380 B respectively designated DMAC_A and DMAC_B state machines. Operations respectively controlled by these units, and specific state details, are discussed later.
Register 381, termed the RFA_NDA (receive first address and next DCB address) has different usage during DMAC
operations associated with transmit and receive data processing. When DMAC is processing/writing receive data to IOP memory, register 381 is used to latch and hold the RDFA
(receive data first address) word which is stored in the respective channel's RDCR3 location in DMAR.
When DMAC i8 processing/fetching transmit related DCB's, register 381 is used to hold a next DCB address fetched from either DMAR or IOP (DMAR via DMAR_DATA_BUS, IOP
via MIO_DATA_BUS). The next DCB address is taken from DMAR
when the DCBA field of TDCR4 is used, and from IOP directly when current transmit data runs out and a next DCB address is unavailable in TDCR 4 (e.g. when a DCB arrives pointing to an empty data buffer but containing a next chained DCB
address). When DMAC i8 ready to fetch a next DCB, the contents of register 381 are transferred to "current address register" 385 discussed below for use as the address to be placed on the IOP bus via DMAC_MIO_ADDR.
Register 382, termed the RBCA (Receive Boundary Check Address) register, is used to hold the RDBA function extracted from RDCR4 via DMAR_DATA bus 388. This function is ~C9-90-001 203 203~9~

compared, via compare circuit 387, with a current IOP
address held in register 385. I~ the comparands match, this indicates the receive buffer is full, and causes DMAC to terminate receive data processing in the respective channel and set boundary check indication to be forwarded to IOP by RFM via an INT interrupt.
Register 383, the RLA_T~C (Receive Last Address and Transmit Byte Count) register, has dual usage in receive and transmit processing. In receive processing, this register latches and holds the receive data last address components RDLAL and RDLAH, retrieved from RDCR3/4 spaces in DMAR via bus 388. During transmit data processing, register 383 holds transmit byte count information received either from FIFOR
(TDCRl), via FIFOR_DATA bus 389, or from IOP memory via MIO_DATA bus 390. The FIFOR data is used to get the current byte count and the IOP route is used to get a new byte count during fetching of a new DCB.
When the receive last address is latched in register 383, it is compared via comparator 387 with a current address in register 385. A match on such comparison indicates that the physical end of the receive buffer has been reached, and DMAC must replace the current address with the Receive First Address from RDFA/RDCR3 via bus 388. When the transmit byte count is held, it is decremented and passed through the "data hold" register 384 for return transfer to FIFOR.
The data hold register 384 also has multiple usage.
When transmit data i9 being fetched via bus 390, it is held temporarily in register 384 en route to FIFOR via multiplexor 386 output DMAC_FIFO_DATA. Handling of transmit byte count information in this register has been discussed above. When receive data is being processed, it is taken from FIFOR via bus 389 and held temporarily in register 384 en route to IOP memory via output path from that register to DMAC_MIO_DATA at 391.
Current atdress register 385 also has multiple usage.
At different phases of DMAC processing, it receives addresses for application to IOP memory (via DMAC MIO_ADDR), incremented transmit address values to be written back to DMAR via DMAC_DMAR_DATA, and incremented receive address values to be written back to FIFOR via DMAC_FIFOR_DATA

~C9-90-001 204 2 034 9~

output of multiplexor 386. The receive address and transmit address values are respectively input to the register from FIFOR (via bus 389) and DMAR (via bus 388). Input of next DCB addresses to this register has already been described.

13.3.2 DMAC STATE MACHINES

The state machine units DMAC_A and DMAC_B are logically tightly coupled. DMAC_A is mainly responsible for interfacing to MIO, DMAR, and DMARQ (including arbitrating requests for data transfer presented by DMARQ, and furnishing resetting control indications to DMARQ upon completion of service). DMA_B is mainly responsible for interfacing to FIFOR.
When requests accepted by DMAC_A from DMARQ require access to FIFOR, output DMAC_A_REQ from DMAC-A to DMAC_B is activated. In response, DMAC_B carries out the necessary task as designated by message codes asserted by DMAC_A at DMAC_A_MSG. The 2-bit message code designates one of the four ta8ks: (1) read transmit byte count from FIFOR; (2) write updated transmit byte count and data to FIFOR; (3) read current receive buffer address and data from FIFOR; (4) write updated current receive buffer address to FIFOR.
The following inputs and outputs are provided between state logic 380 and DMAR:

DMAR_DMAC_ACKO - Acknowledgement by DMAR of first transfer of a two word transfer DMAR-DMAC_ACKl - DMAR acknowledgement of second tran8fer DMAR_DMAC_DONE - DMAR indication of completion DMAC_DMAR_WRl - DMAC request for 1 word write DMAC_DMAR_WR2 - DMAC request for 2 word write DMAC_DMAR_RD2 - DMAC request for 2 word read DMAC_RCV_REQ Full designation DMAC_DMAR_RCV_RE~;
auxiliary addressing function to DMAR for distinguishing a DMAC_DMAR_RD2 request associated with a receive channel operation from a like reque8t associated with a transmit channel operation; the ~C9-90-001 205 Z0~4911.

first requiring location of RDCR3,4 parameters and the latter location of TDCR3,4.

Inputs and outputs between state logic 380 and MIO are:

MIO_DMAC_ACKO - MIO acknowledge of first word transfer between DMAC and IOP
MIO_DMAC_ACKl - MIO acknowledge of second word transfer MIO_DMAC_ACK2 - MIO acknowledge of third word transfer MIO_ DMAC_DONE - MIO completion indication MIO_ DMAC_PE - MIO indication of parity error at IOP interface DMAC_MIO_RDl - DMAC request for IOP mem 1 word read DMAC_MIO_RD3 - DMAC request for 3 word read (2 transmit data plus 1 DCB) DMAC_MIO_WRl - DMAC reque~t for 1 word write Inputs and outputs between logic 380 and FIFOR are:
FIFOR_DMAC_ACK - FIFOR acknowledge of transfer DMAC_FIFOR_RDl - DMAC request for 1 word read DMAC_FIFOR_RD2 - DMAC request for 2 word read DMAC_FIFOR_WRl - DMAC request for 1 word write DMAC_FIFOR_WR2 - DMAC request for 2 word write DMAC_FIFOR_PE_WR - DMAC indication of write parity error DMAC_CHN_NBR - DMAC channel slot indicator/address. Includes bit indication of receive or transmit and with respective rd or wr reque8t make8 up the complete adtre88 information needed by FIFOR
:., Input/outputs relative to DMARQ are:
H~R - input from HCR register in SIO
indicating active HyperChannel assignments and providing pointers relativ~ to respective ~C9-90-001 206 203491~

HyperChannels for use in addressing FIFOR and DMAR (see also description of DMARQ above, and later description of HyperChannels) RCV_RESET - (full designation DMAC_DMAR QRCV_RESET) signal to DMARQ to reset receive DMA request ~ust serviced.
XMIT_RESET - (full designation DMAC_DMAR QXMIT_RESET) signal to DMARQ to reset transmit DMA request just serviced.
DMAR QB_REQ'S - DMARQ request inputs to DMAC
associated with B channel requests DMAR QHO_REQ'S - DMARQ request inputs for HO
HyperChannels DMAR QHl_REQ'S - DMARQ request inputs for Hl HyperChannels DMAC_H_PTR - Output provided to DMARQ with DMAC_DMAR QRESET, when service to a HyperChannel has been completed, pointing to specific DMARq request bit position which is to be reset (resolves to specific HyperChannel and receive or transmit position of 9 ame).
DMAC_H-B_SEL - Output to DMARQ with DMAC_DMAR Q RESET distinguishing selection of HyperChannel request or B channel request for reset.
DMAC_B_PTR - Output to DMARQ when B channel is selected for reset, pointing to specific request position to be reset (resolves to specific channel number and receive or transmit position of same).
Other output:
DMAC_PARITY_ERROR - DMAC indication to INT of parity errors detected relative to FIFOR, DMAR or IOP memory via MIO

~C9-90-001 207 CONTROL SIGNALS- Outputs of state logic 380 to registers 381-385 TR~E/FALSE - Input from compare circuits 387 to state logic 380 Specific states of state machine units DMAC_A and DMAC_B are:

DMAC_A
In the following description, field parameter portions of RDCRl-4 and TDCRl-4 are designated by their respective abbreviated names (e.g. RDFA, RDLAH, etc.). Also, to simplify the description, the first byte of TDCRl containing 3 single bit and 2 two bit indications is referred to as TDFSW (transmit data FIFO status word).

STATE (FIRST LEVEL PRIORITIZATION OF DMARQ SERVICE
REQUESTS) - active service requests from DMARQ are prioritized, with Hl getting top priority, H0 next and B channel requests last - if an Hl request i8 active, assert DMAC_H-B_SEL to DMARQ (in effect designating selection of an H
request), activate DMAC_H_PTR to DMARQ with a code value corresponding to the Hl request position, and go to state 1.
- if an H0 request is active, and no Hl request, activate DMAC_H-B_SEL and DMAC_H_PTR (pointing to H0 request to be reset) and go to state 2.
- if a B request is active and no H requests, set DMAC_H-B_SEL to indicate B channel being serviced, raise DMAC_B_OTR with value designating specific B
channel request being serviced, and go to state 3.
STATE 1 (READ SELECTED HYPERCHANNEL'S STATUS AND
CONTROL INFORMATION) - 2 word read request (DMAC_DMAR_RD2) asserted to DMAR for fetching two words containing status and control information for the selected Hl HyperChannel. Depending on whether a receive or transmit process is being served, the requested information is in the RDCR3-4 or TDCR3-4 spaces in ~C9-90-001 208 2034911 DMAR allocated to the base channel slot representing the reference channel of the HyperChannel (see DMARQ description above and HyperChannel description below). Simultaneously, a DMAC_A_REQ and DMAC_A_MSG are presented to DMAC_B
state machine to request the needed FIFOR read accesses (1 word if a transmit is being processed, 2 words if a receive). Go to state 4.
STATE 2 (PRIORITIZATION OF HO REQUESTS) - Resolve contention, if any, among H0 requests in a predetermined selection order. The selected H0 channel is assigned last priority among HO
channels for next service in order to equalize the servicing over time of all H0 requests. Set internal H count to value of current H0 selection (giving that value lowest H0 priority for next H0 contention). Go to state 1.
STATE 3 (RESOLVING B CHANNEL CONTENTION) - Resolve contention, if any, among B channel requests in prearranged order. Selected channel then assigned last priority for next selection to equalize servicing over time of all B channel requests. Set internal B count to value of current selection. Go to state 1.
STATE 4 (WAIT FOR DMAR TO COMPLETE WORD FETCH REQUEST) - Wait for DONE indication (DMAR_DMAC_DONE) and go to state 5.
- In servicing receive process, first word from DMAR
(availability indicated by DMAR_DMAC_ACK0 active) includes the first address information RDFA and the RDLAH part of the last address. The RDFA is loaded into register 381 and the RDLAH into register 383. Second word (availability indicated by DMAR-DMAC_ACKl active) includes boundary address RDBA and low portion of last address RDLAL. RDBA is ~oaded into register 382 and RDLAL
into register 381 (replacing the already processed RDFA).
- In transmit proce89, first arriving word includes transmit data buffer address TDBA loaded into register 385. Second word includes chain end ~C9-90-001 209 203~91~.

indicator ECI, frame end indicator EFI and next DCB address (DCBA). All are loaded into register 383.
STATE 5 (WAIT FOR DMAC_B TO COMPLETE REQUEST SERVICE) - In this state the DMAC-A request bit set in state 1 is constantly checked. The bit is reset by DMA_B
when the latter finishes the requested read service relative to FIFOR. Go to state 6 if servicing receive, or to state 9 if servicing transmit.
STATE 6 (CHECK FOR PARITY ERROR OR BOUNDARY CHECK
CONDITION) - After all information has been fetched from DMAR
and FIFOR, check for associated indications of parity error (examine PE bit in RDCRl, which is set during state 3 of DMAC_B if parity error condition exists) and boundary check condition (active RBC bit in RDCRl) set during state 8. If parity error, all processing for this channel i8 suspended. Go to state 15 if error or boundary check condition found. If neither found, assert DMAC_MIO_WRl to write receive data (see state 5) in IOP memory receive buffer. Address for this write i9 derived from current address in register 385 and presented on DMAC_MIO_ADDR. Go to state 7.
STATE 7 (WAIT FOR MIO TO COMPLETE RECEIVE DATA WRITE) - Increment address in current address register when MIO acknowledges state 6 write request with MIO_DMAC_ACK0. Go to state 8.
STATE 8 (UPDATE CONTROL INFORMATION OF CHANNEL IN
SERVICE) - If current contents of address register match RDFA, transfer RDFA to address register. If address regi8ter matches RDBA function in register 382, a boundary check condition has occurred;
therefore an indicator bit RBC is set in and concatenated with the address in register 385 to be written back to FIFOR. If the current address is neither at the bottom of the receive buffer nor associated with a boundary check condition, DMAC_A_REQ and DMAC_A_MSG are activated to request DC9-90-001 210 203~91~

DMAC_B 1 word write service relative to respective receive channel space in FIFOR. Go to state 15.
STATE 9 (CHECK PARITY ERRORS AND DEPLETION OF CURRENT
BYTE COUNT RELATIVE TO TRANSMIT CHANNEL ) - After all words for transmit request (TDCRl,3,4) have been fetched (state 5) check for parity error indication (set in state 3 of DMAC_B if relative to FIFOR, and raised at DMAR_PARITY_ERROR if relative to DMAR). Go to state 15 if parity error found. If no errors, check if transmit byte count (fetched by DMAC_B to register 383) is 0. If it is, new DCB is needed. Raise 3 word read to MIO
(DMAC_MIO_RD3) and transfer DCBA (DCB address) from register 381 to address register 385 to prepare for its use by MIO, and go to state 11 to await new DCB. If transmit byte count is not depleted, transmit data word read from MIO at address located by DMAC_MIO_ADDR provided at output of register 383, and go to state 12.
~TATE 10 (CHECK FOR EMPTY NEW DCB) - Check new DCB received in state 11 for "empty"
condition (O valued transmit byte count). If empty, and neither ECI nor EFI in new DCB is set, another DCB is needed; so issue request for new DCB fetch and return to state 11. If empty, but either ECI or EFI is set, frame and/or chain has ended without more data to send; so update TDFSW
and concatenate it with transmit byte count, issue a8sociated 1 word write request to DMAC_B for returning the updated TDCRl word to FIFOR, and go to state 15. IF new DCB not empty, activate DMAC_MIO_RDl to request transmit data word read (using address loaded into register 385 during state 11) and go to state 12.
STATE 11 (WAIT FOR MIO TO COMPLETE NEW DCB FETCH) - Wait for new DCB words. First word from MIO is transmit data buffer address which is loaded into register 385 when MIO_DMAC_ACKO is active. Second word from MIO contains ECI, EFI bits and next DCB
address; loaded together into register 381 when MIO_DMAC_ACKl is active. Third word from MIO

203~9~1 ~C9-90-001 211 (available when MIO_DMAC_ACK2 active) is transmit byte count loaded into register 383. On activation of MIO_DMAC_DONE go to state 10.
STATE 12 (WAIT FOR MIO TO COMPLETE FETCH OF TRANSMIT
DATA WORD) - When transmit data word arrives (MIO_DMAC_ACKO
active), load it into register 384, increment transmit address, decrement transmit byte count, activate DMAC_B to update TDFSW/TDCRl status byte in FIFOR and go to state 13.
STATE 13 (CHECK FOR TRANSMIT BYTE COUNT STATUS) - Check updated transmit byte count for zero/empty status. If empty, the TDCRl/FIFOR ECI and EFI bits are updated to values of corresponding bits in TDCR3/DMAR. DMAC_A_REQ and appropriate me~sage DMAC_A_MSG are transferred to DMAC_B to update FIFOR with 1 or 2 word write (1 word if new DCB
empty, 2 words if not). Simultaneously, a 1 or 2 word write request is issued to DMAR (1 word if only updating transmit buffer address of old DCB;
2 words if updating both transmit buffer address and next DCB address). Go to state 14.
STATE 14 (WAIT FOR DMAR TO COMPLETE UPDATING DCB) - Upon arrival of acknowledgement from DMAR, transfer ECI, EFI and next DCB address from register 381 to register 385 for second word write to DMAR. Go to state 15.
STATE 15 (CLEAN UP REGISTERS AND RECYCLE) - Remain in this state until DMAC_A_REQ is reset by DMAC_B action, then reset all registers 381-385, then return to state O to start new cycle of operations.
DMAC_~
IF RESET, GO TO STATE O
STATE O (POLLING DMAC_A_REQ BIT) - In this state, the request bit from DMAC_A is continuously polled to see if service relative to FIFOR is needed. When the bit goes active, raise DMAC_FIFOR_REQ and decode the message on DMAC_A_MSG. Then output DMA_CHN_NBR to FIFOR for the latter's use as partial address. Depending on 203~9~1 ~C9-90-0~1 212 the message from DMAC_A, present FIFOR with one of DMAC_FIFOR_RDl or _RD2 or _WRl or WR2 to complete addressing information. Go to: state 1 if DMAC_A
message designates "read transmit byte count from FIFOR"; state 2 if message designates "write updated transmit byte count and data to FIFOR";
state 3 if the message is "read receive current buffer address and data from FIFOR"; or state 4 if the message is "write updated receive current buffer address to FIFOR.
STATE 1 (READ TRANSMIT BYTE COVNT FROM FIFOR) - Upon receipt of FIFOR acknowledgement (FIFOR_DMAC_ACK) transfer transmit byte count from FIFOR_DATA_BUS 389 to register 383. Check parity condition. If there is parity error, notify DMAC_A, set parity error status bit in PE field of TDCRl in FIFOR (to notify IOP via TFM and INT), and go to state 8. If no error, reset DMAC_A_REQ
bit and return to state 0.
STATE 2 (WRITE TRANSMIT BYTE COUNT AND DATA TO FIFOR) - On acknowledgement from FIFOR, transfer TDFSW and transmit byte count to register 384 to be written to FIFOR as the second word of the WR2 instruction given in state 0. The first word written is the transmit data which is in register 384 when the state 0 instruction to FIFOR is issued. Go to state 5.
STATE 3 (READ RECEIVE CURRENT DATA BUFFER ADDRESS AND
RECEIVE DATA FROM FIFOR) - On acknowledge from FIFOR, the receive current data buffer address is latched from FIFOR_DATA_BUS
to register 385, and its parity is checked. If in error, go to state 6 to write parity error indication into the PE bit in RDCRl/FIFOR
(eventually resulting in parity error condition recognition in RFM and notification of IOP via INT
interrupt). If no error, go to state 9 to receive second word from FIFOR.
STATE 4 (WRITE UPDATED RECEIVE CURRENT DATA BUFFER
ADDRESS TO FIFOR) BC9-90-001 213 Z03~91~.

- On acknowledge from FIFOR (acknowledging write operation relative to receive current data buffer address presented in state 0), reset DMAC_A_REQ
and return to state 0.
STATE 5 (ADJUST FOR 2 WORD WRITE) - This state serves to realign timing with the FIFOR
during a 2 word write (~ee state 2).
STATE 6 (WRITE PARITY ERROR INDICATOR FOR RECEIVE
CHANNEL) - When FIFOR has written RDCRl to revise the parity error indicator bit, activate DMAC_PARITY_ERROR
indication to INT (appears at DMAR_PARITY_ERROR
input of INT, Fig. 37). Reset DMAC_A_REQ bit and return to state 0.
STATE 7 (SECOND STATE OF 2 WORD READ) - On acknowledge from FIFOR, check for parity error in receive data word (second word read from FIFOR). If error occurred, go to state 6 to write parity error indicator into RDCRl/FIFOR. If no error, reset DMAC_A_REQ bit and return to state 0.
STATE 8 (WAIT FOR FIFOR TO FINISH WRITING STATUS WORD
CONTAINING ERROR INDICATOR IN TDCRl) - On acknowledge from FIFOR (of TDCRl write set up in state 1), reset DMAC_A_REQ bit and return to state 0.
STATE 9 (BUFFER STATE FOR 2 WORD READ) - This state used to allow for timing realignment during reading of second word in a 2 word read (see state 3).

The Master I/O ~MIO) partition arbitrates for control of the IOP bus in behalf of DMAC. Upon gaining control, MIO
performs a direct memory access transfer to or from IOP
memory using address and control parameters transferred by DMAC (also data, usually receive data, when the transfer is a write to IOP memory).
In a typlcal environment, the IOP processing engine could be a Motorola 68000 processor and the bus that of the 68000 allowing for external assumption of master control. In BC9-90-001 214 203491~

another typical environment, the IOP processor could be one of the family of International Business Machines Corporation processors using the Micro Channel bus architecture (Micro Channel is a trademark of the International Business Machines Corporation) which also allows for multiple bus mastership via arbitration. In such environments, the MIO
operates as a bus master upon gaining control of the bus (a 16-bit bus master in the 68000 environment; a 32-bit master in the Micro Channel bus environment).
Referring to Fig. 54, MIO comprises a state machine unit 400, a data register and parity check circuit 401 (accommoda~ing a number of bit~ corresponding to the parallel data capacity of the IOP bus), a multiplexor circuit 402 interfacing to the data output of DMAC
(DMAC_MIO_DATA), receiver and driver circuits, 403 and 404 respectively, interfacing to the data section IOP_DATA_BUS
of the IOP bus, driver circuits 405 coupled between the address input from DMAC (DMAC_MIO_ADDR) and the address section (IOP_ADDRESS) of the IOP bus, and timeout timer 406.
The IOP_DATA_BUS section presently accommodates bidirectional parallel transfer of 16 data bits and 2 parity bits. IOP_ADDRESS accommodates parallel transfer from MIO of 24 address bits and 3 parity bits.
Lines at the left side of the state machine unit 400 extend to control line elements of the IOP bus, and lines at the right side of unit 400 extend to DMAC. In the lines at the right side of the unit, there are three inputs from DMAC
to MIO designating different read and write control functions (DMAC_MIO_RDl, _RD3, _WRl), and four outputs from MIO to DMAC, 3 acknowledging respective operations des~gnated by the 3 DMAC inputs (MIO_DMAC_ACK0, _ACKl, _ACK2) and 1 providing a done indication (MIO_DMAC_DONE).
ACK0 acknowledges the first transfer of a 3 word read and/or the only word transfer of a 1 word read or write. ACKl and ACK2 re~pectively acknowledge the second and third word transfers of a 3 word read.
At the left side of unit 400, the condition of line IOP_RD/WR distinguishes between read requests (for transfer of data from the bus to MIO) and write requests (for transfer of data from MIO to the bus). IOP_BUS_REQ, when active, indicates to an external bus arbitrator circuit that MIO is seeking access to the bus. IOP_MIO_BUS_GR conveys a "grant" signal from the bus arbitrator to MIO indicating bus is available for use. IOP_BUS_GR_ACK is a signal from MIO to the bus arbitrator acknowledging the grant. IOP_ADDR_STRB is an address strobe signal from MIO defining the beginning of a bus cycle. IOP_LDS and IOP_UDS are lower data strobe and upper data strobe signals from MIO indicating respectively when the lower 8 bits and upper 8 bits on the data bus are valid. IOP_DTACK is an acknowledgement from the slave side of the bus (associated with IOP memory) indicating that the bu~ cycle is concluding.
Parity Error indications on the IOP side are provided via IOP_BUS_ERROR input to state unit 400, and parity error indication from unit 400 to DMAC is provided via MIO_DMAC_PE. Timer 406 times out expected responses to signals issued to the bu~ from unit 400 and conditions the unit to begin re-arbitrating for bus access when an expected response does not appear within a predefined time (see state machine state9 description below).
Upon receiving a request from DMAC, MIO asserts IOP_BUS_REQ. When the external arbitrator grants access with IOP_MIO_BUS_GR, MIO responds by asserting IOP_BUS_GR_ACK, and places the addre~ from DMAC on IOP_ADDRESS while activating IOP_ADDR_STRB. The polarity of IOP_RD/WR is set by MIO to determine the direction of transfer. On a write cycle, MIO drives data from DMAC onto the IOP bus. On a read cycle, receiver 403 tristates the bus to allow the IOP
memory controller to drive the bus and data is thereby received by MIO from the bus. MIO selectively asserts the upper and lower data strobe~ (IOP_UDS, _LDS) as needed to transfer the data, and then wait9 for IOP_DTACK indication that the data transfer portion of the cycle has completed.
MIO transfers data relative to DMAC 4 bytes at a time, and DCB fetche9 from IOP memory are 12 bytes (TDCRl, 3 and 4). Since IOP data bu8 is only 2 bytes wide, multiple bu9 cycles are needed for data and DCB transfers. Accordingly, when Rranted acce9s, MIO holds the bu9 for 2 bus cycles to transfer data and 6 bu9 cycles to transfer a DCB.
On the first cycle of a read transfer, data register 401 (16 bits wide) latches the data. On the second cycle of the same transfer, received data is directly gated to DMAC

~C9-90-001 216 2 03~ 9 along with the 16 bits held in register 401 over a 4 byte wide transfer path. In this manner, DMAC is presented with 32 bits of data at a time. Data register 401 includes a parity position which can be latched by unit 400 to generate a parity error indication.
Multiplexor 402 is used during write operations to gate 16 bits at a time from a 32-bit source register in DMAC to the IOP_DATA_BUS, via drivers 404, alternating between lower and upper 16 bit segments. Timer 406 is used by MIO to timeout a missing response from either the bus arbitrator or the IOP memory slave controls. When this occurs, MIO must release the bus and re-arbitrate for access.

14.1 MIO STATE MACHINE STATES

STATE 0 (IDLE STATE) - Reset all IOP bus control signals, and monitor DMAC_MIO_WRl, _RDl and _RD3 signal lines. If any of these lines is active, assert IOP_BUS_REQ, and start a 50 microsecond bus timeout in timer 406.
Go to state 1.
STATE 1 (WAIT TO CONTROL IOP BUS) - When IOP_BUS_GR is active, control of the bus is granted to MIO. Unit 400 makes sure that other bus masters are not "lingering" on the bus by checking for externally originated activity on IOP_ADDR_STRB, IOP_BUS_GR_ACK, and IOP_DTACK
(these lines are all bidirectional, tristated and driven by the master currently controlling the bus). Unit 400 waits for these lines to quiesce, and then asserts IOP_BUS_GR_ACK to respond to the received grant signal and hold off other bus masters. At the same time, the DMAC address is driven onto the address lines of the bus and if the operation relative to IOP memory is a write the DMAC data is driven onto the bus data lines.
Go to state 2 - If bus timeout expires before bus request is granted, a bus timeout error condition is detected. Unit 400 deasserts IOP_BUS_REQ (asserted ~C9-90~001 217 Z034911.

in state 0), and goe~ to state 14 for DMAC
notification.
STATE 2 (DEASSERT BUS REQUEST) - Deassert the bus request asserted in state 0, restart bus timeout timer and go to ~tate 3.
STATE 3 (START BUS DATA TRANSFER CYCLE) - A~sert IOP_ADDR_STRB to start the cycle, and wait for IOP_DTACK response from IOP memory controller.
If response received, and operation is a read from IOP memory, latch data on bus into data register 401 and go to state 4.
- If timer expires without response, relinquish bus by deasserting IOP_BUS_GR_ACK and go to state 14 for DMAC notification of bus error condition.
STATE 4 (TIMING DELAY STATE) - This ~tate used to prolong bus cycle after IOP_DTACK goes active (in state 3) in order to meet timing requirements of the (M68000) bus. Go to state 5.
STATE 5 (CHECKING BUS CYCLE EXCEPTIONS) - This state used to check for bus exceptions occurring during the transfer cycle (either IOP_BUS_ERROR or data parity error on read operation (indicated via not shown input from parity check circuit 407 between receiver~ 403 and MIO_DATA). If exception occurs, map the exception into data parity error, acknowledgement and completion indications to DMAC, by asserting MIO_DMAC_ACKO and MIO_DMAC_DONE with a data parity indication via MIO_DMAC_PE, and go to 8tate 0. If no exception occurs, go to state 6 regardless of which DMAC request is active.
STATE 6 (END FIRST BUS CYCLE) - Wait for IOP memory to deas5ert IOP_DTACK, 80 that second bus cycle can begin. Then wait for reassertion of IOP_DTACK and go to state 7. If timer expires before rea~sertion, go to state 14.
STATE 7 (START SECOND BUS CYCLE) - Drive the incremented DMAC addres~ (pointing to next 16 bit IOP memory location) onto the bus, with DMAC data if a write operation i~ requested, 203~91 ~C9-90-001 218 assert IOP_ADDR_STRB to start the second bus cycle, and wait for response from IOP memory controller. If response received go to state 8. If timer expires with no response, relinquish bus and go to state 14.
STATE 8 (ACK TO DMAC FOR ITS REQUEST) - Check type of request from DMAC. If it is a 1 word write, go to state 9. If it is a 1 word read, assert MIO_DMAC_ACK0 and go to state 13. If it is a 3 word (DCB) read, assert one of three acknowledgements as function of the 2 last address bits (all transfers start on a 4 byte boundary, so last 2 bits will change from 00 to 01 on second transfer, and from 01 to 11 on third transfer; so unit 400 will assert MIO_DMAC_ACKO if address bits are 00, MIO_DMAC_ACKl if bits are 01, and MIO_DMAC_ACK2 if bits are 11). On the second read, the data bits on the bus are concatenated with those in regi~ter 401 and DMAC is presented with 32 data bits at MIO_DATA. Go to qtate 10.
STATE 9 (END OF SECOND BUS WRITE CYCLE) - Check again for bus exception error via IOP_BUS_ERROR. If there is an error, set error indication (via MIO_DMAC_PE). Go to state 12.
STATE 10 (CHECKING BUS EXCEPTION FOR SECOND RE~D CYCLE) - Check for exception IOP_BUS_ERROR or data parity error indication (at 407). If any exceptions go to state 13 for notifying DMAC. If no exception, and the DMAC request is for a 1 word read, go to state 13. If DMAC request i9 a 3 word read, and last 2 addre8s bit~ are other than 11, go to state 11 for incrementing the DMAC address and reading more data. If last 2 addre~s bits are 11, go to state 13.
STATE 11 (READ DCB FOR DMAC) - If IOP_DTACK deasserted and reasserted go to state 3. If timer expires without deassertion and reassertion relinquish bus control and go to state 14.
STATE 12 (LAST STATE OF WRITE REQUEST) :

203~911 ~C9-90-001 219 - If IOP_DTACK is deasserted, assert MIO_DMAC_ACKO
to DMAC, reset timer, relinquish bus control and go to state 0. If timer expires before deassertion of IOP_DTACK, relinquish bus control and go to state 14.
STATE 13 (LAST STATE OF READ TRANSFER) - Assert MIO_DMAC_DONE to DMAC and go to state 0.
STATE 14 (EXCEPTION STATE) - Assert MIO_DMAC_DONE to DMAC, wait for DMAC to deassert its request and go to state 0.

15. HYPERCHANNELS

HyperChannels, also known as H-Channels, are aggregations formed by combining smaller channels to obtain increased bandwidths. CCITT recommendation~ for HyperChannels in ISDN environments contemplate HO type HyperChannels running at 384 Kbps, Hll HyperChannels running at 1.536 Mbps, and H12 HyperChannels running at 1.920 Mbps.
Sub~ect IDLC device, configured as described, supports 32 full duplex 'basic' channels ('B' or 'D' channels), each running at 64 Kbps. Each basic channel is assigned a corresponding one of 32 "basic" processing time slots relative to the BTDM. In this configuration, logic in RSM, DMARQ, DMAC and INT allows for formation and support of up to five HO HyperChannel~, by combining six basic channel slots per HyperChannel, or one Hll HyperChannel spanning 24 basic slots, or one H12 HyperChannel spanning 30 basic slots. When either an Hll or H12 HyperChannel is configured, HO HyperChannels can not be formed, although B/D channels may coexi8t in the 810t8 not u8ed by the HyperChannel (the 8 slot8 not used by Hll or the 2 slots not used by H12).
The IDLC goes beyond CCITT recommendations and allows any number of basic 810t8 to be assigned to larger channel8, for 8reate8t flexibility in bandwidth, a8 well a8 permitting a~signments of non-contiguous slots (allowing formation of HyperChannels even when a sufficient number of contiguous channels are unavailable due to current B/D channel usage).
The configuration of ba8ic time slots within any HyperChannel is programmable dynamically (by IOP) and logically transparent to processing elements of the IDLC.

203~gll.
~C9-90-001 220 15.1 HYPERCHANNEL FORMATION AND USAGE

In the IDLC, HyperChannel formation and usage is implemented via logic distributed in the SIO, RSM, DMARQ and DMAC partitions. Creation and operation of HyperChannels is logically transparent to all other partitions. HyperChannels are formed by collective assignments of inactive basic time slots, which presently are termed "constituent" slots.
A fundamental and unique idea behind the present technique of HyperChannel implementation is the assignment of an earliest appearing constituent slot in each HyperChannel as a so-called "reference" slot. All process status and configuration parameters of the entire HyperChannel are stored relative to that slot (in TSR, FIFOR, DMAR and certain registers discussed below).
Each constituent slot of a HyperChannel is logically a~sociated with the respective reference slot by virtue of logic in RSM and DMAC. During processing relative to a constituent slot other than the reference slot, associated addres~ing parameters (relative to TSR and FIFOR) are translated to those of the reference slot. Thus, relative to each constituent slot, configuration control and process state functions are time swapped relative to TSR locations assigned to the reference slot, and FIFO management control parameters are stored and retrieved relative to FIFOR
locations assigned to the reference slot.
This many-to-one remapping is defined by the CT
(Channel Type) field in the CCR register and contents of the HCR (HyperChannel Configuration Register). Recall that CCR's of basic channel~ are stored in TSR spaces assigned to re8pective channels, and fetched to a hardware CCR register in RSM during time slot service to the respective channel (refer to Figs. 5 and 10, and the earlier description of RSM). Recall also that HCR is a common register (one holding a fixed parameter not replicated across time slots) which is physically located in SIO (as a topological choice, but could as well be located in another partition) and has output8 coupled to other partitions (refer to Figs. 5 and 43, and to the description of HCR field assignments below).

~. ,,, - , . '. .:

203~911 dC9-90-001 221 When a HyperChannel is created, HCR register is programmably set by IOP to provide an associated pointer to a constituent reference slot, which appears earliest in the frame of slots at BTDM (that slot is also termed the FSC or first slot of the respective HyperChannel). Relative to each constituent slot of a HyperChannel, the CT (channel type) field in the associated CCR is set (by IOP/SIO) to indicate the respective channel type and number as one of: B/D, HOl, H02, H03, H04, H05, or Hl (either Hll or H12 depending on applicational environment).
The HCR contains five 6-bit fields which are associatable with up to five HyperChannels (see details below). Each such field contains an activity bit serving to indicate if the associated channel is active, and five bits constituting the FSC pointer to the associated reference slot. For economy and simplicity, all configuration and status parameters for a HyperChannel are stored relative to the reference slot, and the FSC pointer is used to address the reference slot during processing activities relative to associated constituent slots. Before the start of processing relative to each slot, RSM pre-fetches a CCR associated with that slot (see item "P" in Fig. 4), and use~ information therein to set up associated processing parameters for partitions acting relative to that slot. One such parameter is a time slot indicator, RSM_TSI, which relative to B/D
type channels corresponds to the physical time position of the respective slot.
The CT (channel type) field in the pre-fetched CCR
associated with each channel is a 3-bit code identifying the respective channel type as either ordinary B/D type or one of 6 HyperChannel types (Hl or one of 5 specifically numbered HO types; HOl - H05). RSM examines the CT field in each pre-fetched CCR to determine the channel association of the respective next processing slot. RSM maintains a slot count which relative to B/D channels is used as its external time slot indfcator RSM_TSI to the other partitions. Upon tetermining that a next slot is one assigned to a HyperChannel, RSM determines the activity state of the HyperChannel via the associated activity bit in HCR. If the HyperChannel i8 active, RSM replaces its present slot count with the value in the associated FSC field in HCR 90 that ~C9-90-001 22~ 203~91~

its external time slot indicator RSM_TSI assumes a value corresponding to the time position of the reference slot.
Thus, during loading of new state information relative to the next slot (into the synchronous processing partitions), the space in TSR associated with the reference slot is addressed, and during processing relative to that slot access to FIFOR is directed to the space associated with the reference slot. Furthermore, relative to data transfer processes in the asynchronous domain (DMAC), the status of requests pending in DMARQ is presented on a time multiplex synchronous basis to RFM and TFM. For this purpose, RSM furnishes DMARQ with its time slot indication RSM_TSI and, during time slots associated with HyperChannels, control indications of respective HyperChannel types (RSM_DMAR QHl or RSM_DMAR QHO
distinguishing re~pective HyperChannel types Hl, HOl, H02, . , H05). Accordingly, during time slots associated with HyperChannels, DMARQ uses the associated type indication from RSM to select associated request status for presentation to RFM/TFM, and during time slots associated with B/D channels DMARQ uses RSM_TSI to select associated request status for presentation. Refer to earlier description of DMARQ for additional details.
Requests queued by DMARQ are serviced by DMAC one at a time and in a predetermined priority sequence (see DMARQ
description). When a HyperChannel request is selected for service by DMAC, state logic in that partition associates the request positlon (in the DMARQ HO or Hl queue) to select the respective FSC function in HCR as associated address pointer DMAC_CHN_NBR relative to FIFOR and DMAR. DMAC state logic also develops an associated address pointer (DMAC_H_PTR) and reset operator function (DMAC_DMARQ RCV_RESET or DMAC_DMAR Q XMIT_RESET), which together polnt to the specific queue location of the selected request, and applies them to DMARQ for resetting that request (see DMARQ description).

15.2 HCR FIELD ASSIGNMENTS

HCR (Fig. 4S) contains a 2-bit field HCT (HyperChannel Type) and five 6-bit fields associatable with up to five HO

type HyperChannels HOn tn=1-5). Each 6-bit field includes an activity indicator bit HnA (n=1-5), and a 5-bit field used when the respective HyperChannel is active as a pointer FSCn (n=1-5) designating the time position of the reference slot (n=1-5).
The value stored in the HCT field (by IOP/SIO) indicate~ one of two restrictions on HyperChannel formation (although the 2 bits allow for 4 states only 2 of those are used presently) as follows: (1) Hl HyperChannel formation disabled (HO and B/D allowed), or (2) Hl HyperChannel in use (HO formation disallowed, but B/D still allowed).
The HnA bits when active indicate that an associated HyperChannel is active. H2A-H5A can only be active if HCT is in a state allowing for HO HyperChannel formation (Hl HyperChannel formation disabled). Active states of H2A-H5A
respectively indicate active states of correspondingly numbered HyperChannels H02-H05. Active state of HlA
indicates either an active Hl type HyperChannel or an active HOl type HyperChannel depending on the state of HCT (type Hl if HCT indicates Hl in uYe, type HOl otherwise).
Although information given by the HCT and HnA fields of HCR is seemingly redundant, it has a specific synchronizing purpose. In a general sense, the same information is available in CCR' 9 of associated slots, particularly in respective channel type fields CT and respective bits indicating enablement for communicative data transfers.
However, the HCR information is needed for synchronizing HyperChannel startup.
When a HyperChannel is formed, IOP programs control parameters for all constituent slots (in TSR, FIFOR ant DMAR), ~ets an appropriate reference slot pointer in HCR, and activates the associated HnA bit in HCR. This last action instantaneously establishes active status relative to all constituent slots. Were it not for this, it would be necessary to synchronize the loading of CCR information relative to all constituent slots so that the start of communication in any one constituent would not conflict with actions in another next appearing constituents slot which then might not yet be active. This would lead to error since such communication would of necessity require the full BC9-90-001 224 203~911 bandwidth of all constituent slots to avoid overrun or underrun.
Relative to active HyperChannel indications HnA, respective FSCn fields contain reference slot pointers used by RSM and DMAC. RSM uses such pointers relative to each constituent slot to translate an internal slot count, which effectively designates the physical time position of the respective slot, into an external logical time slot indication RSM_TSI designating the time position of the associated reference slot. The external indication is thus used for addressing locations in TSR and FIFOR assigned to the reference slot, whenever a constituent slot is serviced.
Relative to each active HyperChannel, RSM also develops control signals to DMARQ (RSM_DMAR QHl, RSM_DMAR QH0) for steering requests from RFM and TFM to particular queue positions in DMARQ (see earlier description of DMARQ).
DMAC uses the FSC pointers for determining its channel number (DMAC_CHN_NBR) and H pointer (DMAC_H_PTR) control functions relative to HyperChannel requests (see earlier descriptions of FIFOR, DMAR, DMARQ and DMAC). Recall that the channel number functions are used as (partial) addresses relative to FIFOR and DMAR, while the H pointer values are used as reset steering functions relative to DMARQ (in con~unction with either DMAC_DMARQ RCV_RESET or DMAC_DMAR QXMIT_RESET).

15.3 HYPE~ ANNEL LOGIC SCHEMATIC

Fig. 55 schematically illustrates the logic of the IDLC
applicable to HyperChannel formation and usage. Such logic i~ di8tributed as shown within the RSM, DMAC, and DMARQ
partitions. The distributed portions are described separately below. For logical clarity, Fig. 55 illustrates certain functions as performed by "discrete" logical elements (e.g. selector circuits, decoders, etc.), although in the present embodiment many of these functions are integrated within state logic of respective partitions.

15_3.1 R M PART OF HYPERCHANNEL LOGIC

RSM logic associated with HyperChannel usage includes selector circuitry 450. At the beginning of each constituent slot of a HyperChannel, circuitry 450 operates to transfer the information in one of the five numbered field groups in the HCR register (the groups HnA, FSCn; n=1-5) to its outputs. The selected activity indicating bit HnA is transferred to the activity indication output "Act. Ind.", and the associated reference ~lot pointer FSCn is transferred to the "Ref. Slot Ptr." output.
The HCR register is shown here and in Fig. 5 as residing in SIO, but it should be understood that this wa9 done for topological and signalling convenience (topological convenience in respect to distribution of circuit count in the partitions, and signalling convenience in respect to providing the shortest path from IOP to inputs of this register). This of course is not logically essential (i.e.
the register could be placed with possibly more logical consi8tency in RSM, or it could be placed with perhaps less overall convenience in any other partition).
The HCR group selection made by logic 450 is determined by the CT field of the pre-CCR applied at 451, the latter fetched by RSM from TSR early in each slot period, prior to the start of IDLC synchronous processing relative to the associated slot (see Fig. 4). The activity indication bit HnA in the selected field group is applied to AND gate 452, and the FSCn part of the selected group is applied to a further selector 453.
Selector 453 is responsive to the CT in the pre-fetched CCR to 8elect either a reference slot pointer FSCn supplied by ~elector 450 or a slot count presented by slot counter 454. Counter 454 counts slot transitions, modulo 32, defined by beginning of slot indications from BTDM. The FSCn function is selected if the CT in the pre-fetched CCR
de~ignates a HyperChannel type, and the value of slot count 454 is 8elected otherwi~e.
Input 455 of AND gate 452 is activated if the CT
function decoded by decoder 456 is designating a HyperChannel type. Input 457 of AND gate 452 is activated when RSM_ENABLE is pul8ed active by RSM at a transition pha8e as80ciated with the start of proce8s activity relative to the current slot; in general terms, at a point in the Z03491~

state swapping process such that the prior latched value of RSM_TSI is useful for addressing TSR spaces at which status of synchronous processing relative to the preceding slot is to be saved and the new latched value of the same parameter is useful to address TSR spaces from which status relative to the slot associated with the pre-fetched CCR is to be loaded.
Output 458 of selector 453 is latched in not-shown latches, and as intended to be indicated by dotted line connection 459 from the output of AND gate 452 to selector output 458, such latching is effected in time synchronism with the activation of the AND gate (in particular, when RSM_ENABLE rises). Thus, when the now current slot is one associated with an active HyperChannel, the value of RSM_TSI
latched at the output of selector 453 will be a reference slot pointer FSCn function chosen by selector 450, whereas if the now current slot is associated with an active B/D
type channel the latched value of RSM_TSI will be the current slot count.
The function latched at RSM_TSI is presented to other partitions (TSR, FIFOR, INT and DMARQ) as the now current time slot indication. Thus, addressing functions in these partitions are referred to the time position of a reference slot when the current slot is a constituent slot of a HyperChannel, and to the actual time position represented by the slot count otherwise. Note that as the RSM_TSI value is latched, the previous value is saved in a not-shown latch to preserve the address parameters needed to complete the saving of state information relative to the previous slot.
During the now current slot, the CCR is refetched (see RSM de~cription earlier) and its CT field i9 applied to decoter 460. When the applied CT designates an Hl HyperChannel type, a re~pective output 461 of decoder 460 is activated. When the applied CT de9ignates an HOn type HyperChannel (n=l to 5) a respective one of the 5 lines at decoder output 462 is activated. When the applied CT
designates B/D channel type not-shown other output of decoder 460 is activated. Decoder outputs 461 and 462 are supplied to DMARQ as respective HyperChannel type indications RSM_DMARQHl and RSM_DMAR QHOn, and used by the latter to steer input request setting signals (from RFM and ~C9-90-001 227 203~9~

TFM) and request resetting signals (from DMAC) to positions within DMARQ queues associated with type Hl and HO
HyperChannels (see description of DMARQ portion of HyperChannel logic below, and earlier description of DMARQ
partition, for additional details).

15.3.2 DMAC PART OF HYPERCHANNEL LOGIC

DMAC logic for HyperChannel use includes "cascaded"
selectors 470 and 471. In the earlier description of the DMAC partition, functions of these selectors are performed by the state logic of the partition, but for logical clarity these functions are shown here in association with discrete decoding entities.
Selector 470 receives as selectable inputs the FSC
fields of HCR, and is operated by DMAC_H_PTR when DMAC is servicing a HyperChannel request, to select the FSCn field specifically designated by the H pointer value. The H
pointer is generated by the DMAC_A state machine (see Fig.
49 and related earlier description of DMAC).
Selector 471 receives as selectable inputs the output of selector 470 and DMAC_B_PTR, the latter also generated by the DMAC_A state machine (Fig. 49), and selects one of those as a function of its control input DMAC_H-B_SEL (also generated by the state machine). The latter control input distinguishes which type of channel request is currently being serviced by DMAC, HyperChannel or B/D type channel.
DMAC select8 pending requests from DMARQ for DMA
transfer service (relative to IOP memory as described earlier), one at a time and in predetermined priority 8equence (refer to earlier descriptions of DMARQ and DMAC).
A8 a reque8t is selected for service, DMAC state logic remember~ it~ DMARQ output position, and use8 that to determine values of DMAC_H_PTR, DMAC_B_PTR and DMAC_H-B_SEL
to be generated when re8pective requests are to be re~et.
The state logic of DMAC also generate~ functions indicated at 472; DMAC_DMAR QRCV_RESET, DMAC_DMAR QXMIT_RESET and DMAC_RCV_REQ. The first two of these are supplied to DMARQ along with the above H and B
pointers for steering reset signals to queue positions respectively associated with receive and transmit operations ~C9-90-001 228 z0349~

(refer to DMARQ description) relative to the HyperChannel designated by the H pointer. DMAC_RCV_REQ is supplied to DMAR for conditioning the latter for addressing operations associated with receive requests (see earlier DMAR
description).

15.3.3 DMARQ PART OF HYPERCHANNEL LOGIC

This part of the HyperChannel logic includes portions of the selection controls and request queues associated with handling of HyperChannel requests for DMAC service.
Selection control 480 represents that part of the selector controls 335 shown in Fig. 47 which is relevant to handling of HyperChannel requests. Input selection control 481 represents that part of input selection controls 333 in Fig. 47 (the controls responsible for steering setting and resetting requests to appropriate positions in the DMARQ
request registration queues) which is relevant to handling of HyperChannel requests. Queues for Hl HyperChannel requests shown at 483 and 484 correspond respectively to queues 330 and 331 shown in Fig. 47.
Finally, output selection controls shown at 485 represent that part of output selection controls 334 in Fig.
47 which is relevant to presentation of HyperChannel request statu~ to RFM and TFM. Output controls 485 present request queue status in time multiplex in synchronism with the servicing of channel slots (in respect to HyperChannels, in synchronism with servicing of constituent slots). Status of requests for DMA receive data service are presented to RFM
at DMARQ RFM_REQ (corresponding to output port 334R in Fig.
47), and ~tatus of requests for DMA transmit data service are pre~ented to TFM at DMAR QTFM_REQ (corresponding to output 334T, Fig. 47).

15.4 EXAMPLE OF DYNAMIC HYPERCHANNEL FORMATION

An example of HyperChannel formation follows with the following scenario. Initial state: IDLC disabled for Hl type HyperChannel formation (i.e. HO allowed), and currently using BTDM slots 3-7, 12-~9 and 25-30 to su~tain active B

203491~

type channels and/or one or more (but less than 5) HO type HyperChannels.
The foregoing status and slot usage leaves 13 BTDM
slots available for other usage (slots 0-2, 8-11, 20-24 and 31). In general, groups of 6 basic slots can be used for HO
type HyperChannel formation. Thus, the available slots as above are candidates for potential assignment to either two HO HyperChannels (if 3 or less of such are currently active) and 1 B type channel, or to one HO HyperChannel and seven separate B type channels, or to thirteen separate B type channels. The following is a description of how 6 of the available slots could be assigned on a dynamic basis to a newly configured HO full duplex type HyperChannel (dynamic in the sense that processing in the currently active slots continues uninterrupted during formation of the new HO
HyperChannel).
To establish the HO HyperChannel, the local IOP/Host would have to first communicate with the remote IOP/Host to which it intends to link (presumably, through an existing active D channel signalling link between the local and remote systems. Such communication would request setting up an HO HyperChannel linkage. The response from the remote system would indicate its availability for such linkage (it would be available only if it were in a state permitting HO
formation and had six idle slots).
Assume that both local and remote nodes are configurable for HO formation and have capacity for such (and have so indicated in their communications). The next step would be for the local IOP/Host to instruct the remote node (via existing signalling link) to form an HO
HyperChannel. Upon acknowledgement of this communication, the local IOP/Host would begin forming the new HO
HyperChannel.
The fir8t 9tep in the formation would be for the local IOP/Ho8t to program the CCR's a8sociated with local slots 1, 2 and 8-ll with type field (CT) assignments designating each a8 a constituent 810t of a specifically numbered HO type HyperChannel; doing 90 by acces8ing the spaces in the local TSR assigned to those CCR's (via the local SIO) and loading appropriate information therein.

BC9-90-001 230 203~9~

Next, the local IOP/Host must load control parameters in TSR, FIFOR and DMAR, into spaces associated with the reference slot position, for sustaining the required HyperChannel operation in all involved partitions. These loading operations are conducted of cour3e via SIO, and include: (1) loading TSR with time-swap state parameters required for initiating synchronous transmit and receive processing in the designated HyperChannel; (2) loading FIFOR
with initial RDCRl and TDCRl control parameters required for FIFOR management in that HyperChannel; and (3) loading DMAR
with RDCR3,4 and TDCR3,4 control parameters required for controlling DMAC access to IOP memory and FIFOR for that HyperChannel.
Then the local IOP/Host would prepare spaces in its memory for sustaining the HO channel communications, and send a further communication to the remote IOP/Host (over the existing signalling link) indicating completion of its HO formation and readiness to activate the new HyperChannel.
When the remote IOP/Host acknowledges with same status, the local IOP/Host would set the FSCn and HnA field associated with the new HyperChannel's HO number (in the HCR register of the local IDLC); the FSC field being set to point to slot 1 as the reference slot for the respective HyperChannel, and the HA bit being set to its active state. Presumably, the remote system would be doing the same. This completes the process, and the new HyperChannel is now available for active data communication.

SUMMARY

It should be appreciated now that we have described a communications controller device formed by autonomous elements individually implemented by special purpose logic circuit8. Certain of the8e elements form a multiprocessing/multitasking pipeline in which communication data is operated upon in transit between external time division links and an external Host/IOP processing complex.
Multiple operations are performed on each byte of communication data in synchronism with appearances of respective time division slots in which such data is externally communicated.

BC9-90-001 231 203~9~

The processing pipeline contains extensive buffer queueing for sustaining high rates of communication data transfer through the device, and thereby between the external time division links and Host/IOP processing system.
To further facilitate speedy transfer, the device includes special DMARQ and DMAC partitions, interfacing between the synchronous pipeline and the external IOP system. The DMARQ
operates to translate synchronously generated requests for data transfer into asynchronously serviceable requests, and the DMAC partition acts on such requests asynchronously to perform data transfer operations between the device and memory associated with the IOP in a DMA (direct memory access) mode.
To further speed data transfer processes, the communication of information from the device to the IOP, relative to events ancillary to the movement of data, is carried out through a status communication path which is predominantly separate from the above-mentioned pipeline.
The device includes an interrupt handling partition which operates to prepare interrupt requests and interrupt request vectors on a synchronous basis relative to the processes in said pipeline. Such requests and vectors are presented on an asynchronous basis to the IOP over the status communication path.
The device also allows for synchronous storage of event status information associated with said requests in a memory shared for stot^ing control parameters governing the processing activities in said pipeline. The device also allows for queued maintenance of event status in said memory, relative to plural time spaced events occurring wlthin a communication channel in said shared memory, under the management direction of said interrupt handling partition. Flnally, the tevice ~ncludes a slave I/O
partition allowing the IOP to asynchronously access and retrieve said queued status with minimal lnterference to ongoing data communication processes.
Within it9 9ynchronou9 pipeline the device includes multiple autonomous transmit and receive processing elements operating in parallel to perform multiple different ta9ks on data being communicated; each element providing internal buffering of data supplementing the buffering provided by Z034gll, memories in the device. The elements operate synchronously under direction of a resource management element which control time swapping of state controlling parameters --including data being processed -- between the processing elements and a time swap memory within the device.
Accordingly, these and other aspects of the subject device are now defined by the following claims.

Claims (34)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A data link control (DLC) device for connection between a data communication network and a bus connecting to CPU
(central processing unit) and memory subsystems of a data processing system, said bus being subject to having multiple connections linking said data processing system to multiple devices, including said DLC device, data being transferred between said DLC device and multiple channels in said data communication network in cyclically recurrent time division time slots assigned to individual ones of said data communication network channels, data being transferred between said DLC device and said memory subsystem, via said bus, in asynchronous relation to associated data communication processes in said data communication network channels and respective said recurrent time slots, said DLC
device comprising:
memory means having storage spaces dedicated to said data communication network channels, the space dedicated to each of said channels including subspaces reserved for storing data being transferred between the respective channel of said data communication network and said DLC
device and subspaces reserved for storing control information defining data processing operations to be performed by said DLC device on said data that is being transferred;
plural autonomous special purpose logic circuit elements connected in tandem between said data communication network and said memory means to form at least one plural-stage data processing pipeline relative to said channels, each said pipeline conveying data between said data communication network and said memory means and performing plural processing operations to selectively modify said data as it is conveyed, logic circuit elements forming discrete processing stages in each said pipeline operating during each of said cyclically recurrent time slots dedicated to an active one of said channels to perform data processing tasks on data being conveyed relative to the respective channel through the respective pipeline stage, logic elements forming different stages in any one said pipeline performing different data processing tasks on data being conveyed through the respective channel; whereby each said pipeline serves as a multitasking data processing array relative to data undergoing transfer relative to each said active channel and as both a multiprocessing and multitasking array relative to data undergoing transfer relative to all active said channels; and means coupled to said memory means and said bus for transferring data relative to individual said channels, between storage spaces in said memory means assigned to channel configurations, and perform processing tasks on said data in accordance with respective formats and protocols;
whereby data can be entered into said data storage queues in a form common to all channels and exchanged in aid network time slots in diverse forms associated with respective channel configurations.

2. A DLC device in accordance with claim 1 wherein said data communication network channels include at least one channel which when active operates in a full duplex mode relative to a remote station connected to said data communication network in order to convey "receive" data originating at said remote station to said DLC device while concurrently transmitting "transmit" data from said DLC
device to said remote station, and wherein said DLC device pipelines comprise:
a multi-stage transmit pipeline, for conveying said transmit data from said memory means to said data communication network while processing said transmit data, and a multi-stage receive pipeline for conveying said receive data from said data communication network to said memory means while processing said receive data.

3. A DLC device in accordance with claim 2 wherein said network channels convey data simultaneously in different communication formats with different communication protocols and wherein:
said memory means contains storage spaces dedicated to each said channel for storing channel configuration register control information defining the type of communication function which the channel is currently performing, and wherein said DLC device includes:

a channel configuration register common to all channels for storing the channel configuration register control information of each channel while the DLC device is performing operations to advance movement of data through the respective channel;
supervisory autonomous logic elements coupled to said channel configuration register and individual stages in said transmit and receive pipelines, said supervisory autonomous elements operating in synchronism with said pipeline stages, and conditioning said stages to perform processing tasks on data in transmit through said stages, said operations defined in part by the contents of said configuration control register; whereby data can be transferred between said memory means and said memory subsystem in a format common to all channels and exchanged between said DLC device and said data communication network in diverse formats commensurate with respective channel configurations.

4. A DLC device in accordance with claim 3 wherein said channel configuration register control information is useful to configure a plurality of said channels for concurrently communicating digitized voice and data arranged in an HDLC
(high level data control) protocol between said data communication network and said memory subsystem, and wherein said autonomous elements constituting said pipeline stages perform the tasks required to accommodate said voice and HDLC data communications concurrently.

5. A DLC device in accordance with claim 4 wherein:
said autonomous logic elements constituting stages of said transmit pipeline process transmit data in transmit through said transmit pipeline, and contain logic effective relative to channels configured for transmitting data in said HDLC protocol for embedding HDLC frame delimiting symbols and Cyclic Redundancy Check (CRC) symbols into the transmit data of respective HDLC channels, on the fly, as said data is conveyed through said transmit pipeline from said device memory means to said data communication network;
and;
said logic elements constituting stages of said receive pipeline process receive data in transmit through said receive pipeline, and contain logic effective relative to channels configured for receiving data in accordance with HDLC protocols to perform processing tasks to strip HDLC
frame delimiting symbols from receive data arranged in said HDLC protocol and to perform CRC checks on said receive data, on the fly, as said receive data is conveyed through said transmit pipeline from said data communication network to said memory means.

6. A DLC device in accordance with claim 5 wherein said memory means and said autonomous logic elements constituting said transmit and receive pipelines operating at a rate sufficient to sustain concurrent service relative to at least 32 full duplex channels in said data communication network, with aggregate data rates in each channel of 128 kbps.

7. A DLC device in accordance with claim 5 wherein the entire DLC device is contained on a single LSI chip.

8. A DLC device in accordance with claim 5 wherein:
said data communication network contains one or more active channels operating in a full duplex mode;
said autonomous logic elements which constitute stages of said pipelines that interface directly to said data communication network interface to said full duplex channels on said data communication network in cyclically repetitive time slots dedicated to respective said full duplex channels, and operating during each such time slot to receive from 0 to n bits from the respective full duplex channel and to transmit from 0 to n bits to the respective full duplex channel, where n is greater than 2; and said autonomous logic elements constituting stages in said transmit and receive pipelines process data being conveyed respectively to and from each said full duplex channel in bit-parallel formats.

9. A DLC device in accordance with claim 8 wherein said data received and transmitted at said data communication network interface relative to each said full duplex channel, during a said time slot assigned to the respective channel, is transferred only in short duration bursts occupying a small portion of the respective time slot, whereby a major portion of each respective time slot is available for use by said DLC device for establishing various operating states associated with said data communication network channels in the autonomous elements constituting said pipelines.

10. A DLC device in accordance with claim 9 wherein said memory means contains storage spaces reserved to each channel for storing state control information for each said pipeline stage relative to the respective channel, said stage control information defining instantaneous task processing states of each said pipeline stage relative to the respective channel.

11. A DLC device in accordance with claim 10 comprising means coupled to said memory means and each element constituting a stage in said pipeline for controlling bidirectional transfers of state control information between said memory means and each said pipeline stage during each of said time slots; the state information transferred from the memory means to each pipeline stage during any time slot setting the respective stage into a task processing state corresponding to the state it was in at the end of the last previous recurrence of the same time slot, and the state information transferred from each pipeline stage to the memory means during each time slot representing the final task processing state of the respective stage in the respective slot; whereby said pipeline stages are conditioned during successive recurrences of a time slot assigned to a channel to continuously perform processing tasks relative to that channel.

12. A DLC device according to claim 11 wherein said DLC
device is contained on a single LSI semiconductor chip.

13. A DLC device in accordance with claim 1 wherein:
said memory means contains storage space reserved to each channel for storing event status information defining processing events occurring in the respective channel; and wherein said device comprises:
means operating in synchronism with at least one of said pipelines for collecting process event status information relative to channel process events occurring in said pipeline;
means for storing said collected event status information in said memory means spaces dedicated therefor;
and means for rendering said stored status information accessible to said CPU subsystem of said processing system, through a circuit path extending through said DLC device and said bus which presents minimal interference with transfers of communication data between said memory means and said memory subsystem of said data processing system.

14. A DLC device in accordance with claim 13 wherein said memory means spaces reserved to each channel for storing channel process event status information are configured to simultaneously store plural sets of information representing plural process events occurring in respective channels at different times, and said means for storing said collected process event status information stores channel process event status information representing plural channel process events occurring at different times in one channel in separate memory means storage spaces reserved to that one channel for that purpose.

15. A DLC device according to claim 14 including an autonomous interrupt management (INT) logic element interfacing to said pipeline stages of said DLC device and to said memory means of said DLC device, said INT logic element operating to collect said process event status information, to manage transfer of said process event status information to said DLC device memory means, and to instigate transfers of interrupt request signals from said DLC device to said CPU subsystem for prompting said CPU
subsystem to retrieve said stored process event status information from said DLC device memory means.

16. A DLC device according to claim 15 wherein all of said autonomous logic elements and said memory units of said DLC
device are contained on a single LSI semiconductor chip.

17. A DLC device in accordance with claim 1 comprising an autonomous DMA control (DMAC) logic element, interfacing to said memory subsystem via said bus, for directly controlling addressing of said memory subsystem, and for transferring communication data between said memory means of said DLC
device and said memory subsystem.

18. A DLC device according to claim 17 wherein said memory means includes storage spaces reserved to said DMAC element for storing control information defining operations to be conducted by said DMAC element relative to individual said channels; said control information including information defining addresses in said memory subsystem to and from which communication data is to be transferred relative to respective channels.

19. A DLC device according to claim 18 including a slave I/O (SIO) logic element, interfacing to said CPU subsystem of said data processing system via said bus, said SIO
element coupling said CPU subsystem with said DLC device memory means for enabling said CPU subsystem to transfer information to said memory means and retrieve information from said memory means with minimal interference to operations concurrently being directed by said DMAC element for transferring communication data relative to said memory subsystem.

20. A DLC device according to claim 19 wherein said information that can be transferred by said CPU subsystem to said DLC device memory means via said SIO element includes said control information for defining operations to be conducted by said DMAC element relative to individual said channels.

21. A DLC device according to claim 20 wherein said DLC
device is contained on a single LSI semiconductor chip.

22. A DLC device according to claim 19 wherein:
said DLC device memory means stores channel status information relative to process events occurring in individual said channels; and said information that can be retrieved from said DLC
device memory means by said CPU subsystem via said SIO
element includes said process event status information.

23. A DLC device according to claim 22 wherein said DLC
device is contained on a single LSI semiconductor chip.

24. A DLC device according to claim 18 wherein:
said control information stored in said DLC device memory means includes sets of device control block information stored relative to individual said channels, each control block set effectively defining a series of data transfer operations to be conducted by said DLC device for transferring a block of multiple bytes of data between said memory subsystem and said DLC device memory means relative to the respective channel, and wherein said stored control block sets contain one or more chaining indications; and said DMAC logic element is responsive to each said stored chaining indication, upon completing data transfer operations defined by the control block set containing the respective chaining indication, to retrieve another control block set from said memory subsystem which defines additional data transfer operations to extend the completed data transfer operations, whereby an operation in process relative to any channel is extended automatically by said DLC device without intervention of said CPU subsystem.

25. A DLC device according to claim 18 wherein:
said memory subsystem contains storage spaces configured by said CPU subsystem as circular buffers;
individual said circular buffer spaces being reserved by said CPU subsystem to individual said channels of said DLC
device for storage of data being transferred between said DLC device memory means and said memory subsystem relative to respective said channels; and said DMAC logic element of said DLC device is responsive to said control information stored in said DLC
device memory means for managing transfers of data from data storage spaces reserved to said channels in said DLC device memory means to said circular buffer spaces reserved to respective channels, and for managing containment of said data within predetermined boundaries of said circular buffer spaces.

26. A DLC device according to claim 1 wherein said DLC
device pipelines are adapted to perform discrete processing tasks relative to individual said channels during cyclically recurrent time division time slots reserved to respective said channels, and wherein said DLC device memory means comprises a plurality of discrete random access memory (RAM) storage units including:
a first RAM unit associated with said channels for storing data en route between said bus and said DLC device pipelines;
a second RAM unit for storing state control information relative to each of said channels defining task processing states of logic elements in said DLC device which constitute discrete stages in said DLC device pipelines relative to respective channels; and a third RAM unit for storing control information for controlling operations of said DLC device for transferring data between said first RAM unit and said memory subsystem of said data processing system.

27. A DLC device according to claim 26 wherein said DLC
device is contained on a single LSI semiconductor chip.

28. A data link control (DLC) device for connection between a data communication network and a bus connecting to CPU (central processing unit) and memory subsystems of a data processing system, said bus being subject to having multiple connections linking said data processing system to multiple devices, including said DLC device, data being transferred between said DLC device and multiple channels in said data communication network in cyclically recurrent time division time slots assigned to individual ones of said data communication network channels, data being transferred between said device and said memory subsystem, via said bus, in asynchronous time relation to associated data communication processes in said data communication network channels and respective said recurrent time slots, said DLC
device comprising:
memory means having storage spaces dedicated to said data communication network channels, the space dedicated to each said network channel including subspaces reserved for storing data being transferred between the respective network channel and said DLC device and subspaces reserved for storing control information defining data processing operations to be performed by said device on said data that is being transferred;
plural autonomous special purpose logic circuit elements connected in tandem between said data communication network and said memory means to form at least one plural-stage data processing pipeline relative to said network channels, each said pipeline conveying data between said data communication network and said memory means and performing plural data processing operations on said data to selectively modify said data as it is conveyed, logic circuit elements forming discrete processing stages in each said pipeline operating during each of said cyclically recurrent time slots dedicated to an active one of said channels to perform data processing tasks on data being conveyed relative to the respective channel through the respective pipeline stage, logic elements forming different stages in any one of said pipelines performing different data processing tasks on said data as it is passed through the respective pipeline; whereby each said pipeline serves as a multitasking data processing array relative to data undergoing transfer relative to each said active channel and as both a multiprocessing and multitasking array relative to data undergoing transfer relative to all active said network channels; and means coupled to said memory means and said bus for transferring data relative to individual said network channels between storage spaces in said memory means assigned to respective said network channels and storage spaces in said memory subsystem assigned to the same network channels;
wherein said network channels carry data simultaneously in plural different data communication formats, and includes at least one channel operating in a full duplex mode, relative to a remote station attached to said data communication network, to convey data from the remote station to said DLC device (receive data) while concurrently transmitting data supplied by said DLC device (transmit data) to said remote station, and said pipelines comprise:
a multi-stage transmit pipeline, for conveying transmit data from said memory means to said data communication network while processing said data, and a multi-stage receive pipeline for conveying receive data from said data communication network to said memory means;
wherein said memory means contains storage spaces dedicated to each channel for storing channel configuration register control information defining the data communication format of the respective channel, and said DLC device contains a channel configuration register common to all channels for storing the chanel, configuration register control information of each channel while the device is performing operations to advance movements of data through the respective channel;
wherein said device further comprises supervisory autonomous logic elements coupled to said channel configuration register and individual stages in said transmit and receive pipelines, said supervisory elements operating in synchronism with said pipeline stages, and conditioning said pipeline stages to perform processing tasks on data in transit through said stages, said operations defined in part by the contents of said configuration control register; whereby data can be transferred between said memory means and said memory subsystem in a formal common to all channels and exchanged between said device and said data communication network in diverse formats commensurate with respective channel configurations;
wherein said channel configuration register control information is useful to configure a plurality of said channels for concurrently communicating digitized voice and data arranged in HDLC (high level data link control) protocol between said data communication network and said memory subsystem, and wherein said autonomous elements constituting said pipeline stages perform the data processing tasks required to accommodate said voice and HDLC
data concurrently;
wherein autonomous logic elements constituting states of said transmit pipeline process transmit data in transit through said transmit pipeline, and operate relative to channels in said data communication network that are configured for transmitting data in HDLC protocol to embed HDLC frame delimiting symbols and Cyclic Redundancy Check (CRC) check symbols into the transmit data of respective HDLC channels, on the fly, as said data is conveyed through said transmit pipeline from said device memory means to said data communication network;
wherein autonomous logic elements constituting stages of said receive pipeline process receive data in transit through said receive pipeline and are effective relative to channels in said data communication network that are carrying receive data arranged in said HDLC protocol format to perform processing tasks to strip HDLC frame delimiting symbols from respective HDLC data and to perform CRC checks on said data, on the fly, as said respective data is conveyed through said pipeline from said data communication network to said memory means;
wherein said autonomous logic elements which constitute stages of said pipelines that interface directly to said data communication network interface to said full duplex channels on said data communication network in cyclically repetitive time slots dedicated to respective said full duplex channels, and operate during each such time slot to receive from 0 to n bits from the respective channel on the data communication network and to transmit from 0 to n bits to the respective channel on the data communication network, where n is greater than 2;
wherein said autonomous logic elements constituting stages in said transmit and receive pipelines are adapted to handle data being conveyed respectively to and from each said duplex channel in bit-parallel formats;
wherein said data received and transmitted at said data communication network interface, relative to each said full duplex channel is transferred only in short duration bursts occupying a small portion of the time slot allocated to the respective channel, whereby a major portion of each such allocated time slot is available to be used by said DLC
device for changing operating stages of said pipeline elements relative to different said channels;
wherein said memory means contains storage spaces reserved to each said channel for storing state control information for each said pipeline state relative to the respective channel; said state control information defining instantaneous tack processing states of each said pipeline state relative to the respective channel;
said DLC device further comprising supervisory means coupled to said memory means and said pipeline elements for controlling bidirectional transfer of said state control information between said memory means and each of said pipelines stages during each said time slot; the state control information transferred from said memory means to said pipeline stages at the beginning of each time slot serving to set respective stages to processing states they were in at the end of the last prior recurrence of the same time slot; the state control information transferred from said pipeline stages to said memory means at the end of each time slot representing final processing states of respective stages for the respective slot; said supervisory means comprising;
a special purpose resource managing (RSM) element for managing the cyclic saving and restoration of states between said elements in said pipeline sections and said memory means in synchronism with said time slots; said RSM element providing starting and ending indications to said pipeline elements for directing said pipeline elements to start and end processing tasks relative to a channel associated with a current slot;
said pipeline elements asserting DONE indications to said RSM element in response to said ending indications when the current slot is one assigned to an active channel; said pipeline elements further providing continuous output indications of their processing states during each slot;
said RSM element directing saving of said processing states of said pipeline elements to said memory means in response to said DONE indications from respective pipeline elements; and said DONE indications being delayable by said pipeline elements allow for said pipeline elements to reach stable processing states from which processing can be resumed without ambiguity.

29. A DLC device in accordance with claim 28 wherein said RSM element includes:
means coupled to the data communication network interface for receiving signals indicating beginnings of successive said time slots:
means responsive to said beginning of slot signals for providing successive ending and starting indications to said pipeline elements;

means interactive with said memory means prior to receipt of each beginning of slot signal for retrieving configuration control (CCR) information indicating if the currently occurring time slot is assigned to an active channel;
means interactive with said memory means upon receipt of the beginning of slot signal for retrieving configuration control (pre-CCR) information indicating if the slot then beginning is or is not assigned to an active channel;
means responsive to said DONE indications from said pipeline elements when said CCR information indicates that an active channel slot is ending for directing the saving of processing state indications relative to said slot from said pipeline elements to said memory means; and means responsive to said pre-CCR information indicating that the slot then beginning is assigned to an active channel for directing loading of state control information, relative to the respective channel, from said memory means to said pipeline elements.

30. A DLC device according to claim 29 wherein said DLC
device is contained on a single LSI semiconductor chip.

31. A data link control (DLC) device for connection between a bit-serial data communication network and a bit-parallel data transfer bus, said data communication network containing multiple bit-serial data communication channels, said bus connecting said DLC device with memory and and CPU
(central processing unit) subsystems of a data processing system, said bus being connectable to other devices besides said DLC device and being subject to contention between said DLC device and said other devices, said DLC device exchanging communication data bit-serially with individual channels of said data communication network, in cyclically recurrent time division slots assigned to respective channels, said DLC device comprising:
first and second RAM storage units, each having storage spaces reserved to individual ones of said data communication network channels;
said reserved storage spaces in said first RAM unit forming storage queues structured for storing plural bytes of receive data, plural bytes of transmit data, and plural bytes of control information, relative to each said channel, said receive data in each said queue comprising data received bit-serially from a respective channel in said data communication network during periods of recurrence of said time slots assigned to the respective channel, said transmit data in each queue comprising data which is to be transferred bit-serially to a respective channel in said communication network in periods of recurrence of said time slots assigned to the respective channel, and said control information in each queue defining positions of individual data byte storage spaces to which a next byte of receive data is to be transferred from a respective channel in said data communication network and from which a next byte of transmit data is to be transferred to the respective network channel;
said reserved spaces in said second RAM unit including spaces for holding control state information defining instantaneous processing states of said device relative to time slots assigned to respective said channels;
a first plurality of autonomous special purpose logic circuit elements connected in tandem between said network and said first RAM unit to form a plural-stage receive pipeline in which said receive data received from individual said channels is handled and processed by said DLC device during time slots assigned to the respective channels; said elements constituting said receive pipeline operating in synchronism with said assigned time slots for transporting said receive data of respective channels from said network to respective receive data storage queues in said first RAM
unit; elements constituting individual stages in said receive pipeline selectively performing various processing tasks on said receive data as it is transferred through respective said stages; including tasks for converting said receive data from serial to parallel form and tasks for selectively processing and removing protocol information contained in said receive data; whereby said receive pipeline operates as a multitasking processing array, relative to receive data handled during time slots assigned to a single network channel, and as both a multiprocessing and a multitasking array relative to receive data handled in time slots assigned to all channels;

a second plurality of autonomous special purpose logic circuit elements connected in tandem between said network and said first RAM unit to form a plural-stage transmit pipeline relative to transmit data being transferred from said first RAM unit to said data communication network channels during said time slots assigned to respective channels, said elements constituting said transmit pipeline operating in synchronism with said assigned time slots for transporting said transmit data from respective transmit data storage queues in said first RAM unit to said data communication network channels in said time slots assigned to respective channels, said elements constituting individual stages of of said transmit pipelines performing various processing tasks on said transmit data as it passes through respective stages., including tasks for converting said transmit data from parallel to serial formal and tasks for selectively inserting protocol delimiting characters into said data; whereby said transmit pipelines acts as a multitasking array relative to transmit data handled in time slots assigned to a single one of said channels, and as both a multiprocessing and a multitasking array relative to transmit data handled in the time slots assigned to all channels; and means coupled to said first and second RAM units and said bus for transferring said receive data and said transmit data relative to said channels between respective data storage queues in said first RAM unit and said memory subsystem.

32. A data link control (DLC) device for connection between a bit-serial data communication network and a bit-parallel data transfer bus, said network containing multiple bit-serial data communication channels, said bit-parallel data transfer bus connecting said DLC device with memory and CPU (central processing unit) subsystems of a data processing system, said bit-parallel data transfer bus being connectable to other devices besides said DLC device and being subject to contention between said DLC device and said other devices, said DLC device operating to exchange communication data bit-serially with individual channels of said network, in cyclically recurrent time slots assigned to respective channels, said DLC device comprising:

first and second RAM storage units, each having storage spaces reserved to individual ones of said network channels;
said reserved storage spaces in said first RAM unit forming storage queues structured for storing plural bytes of receive data, plural bytes of transmit data, and plural bytes of control information, relative to each said channel, said receive data in each queue comprising data received bit-serially from a respective network channel in periods of recurrence of said time slots assigned to the respective channel, said transmit data in each queue comprising data to be transferred bit-serially to a respective network channel in periods of recurrence of said time slots assigned to the respective channel, and said control information in each queue defining positions of individual data byte storage spaces to which a next byte of receive data is to be transferred from a respective network channel and from which a next byte of transmit data is to be transferred to the respective network channel;
said reserved spaces in said second RAM unit including spaces for holding control state information defining instantaneous processing states of said device relative to time slots assigned to respective channels;
a first plurality of autonomous special purpose logic circuit elements connected in tandem between said network and said first RAM unit to form a plural-stage receive pipeline in which said receive data of individual said channels is handled and processed by said DLC device during time slots assigned to the respective channels; said elements constituting said receive pipeline operating in synchronism with said assigned time slots for transporting said receive data of respective channels from said network to respective receive data storage queues in said first RAM
unit; elements constituting individual stages in said receive pipeline selectively performing various processing tasks on said receive data as it is transferred through respective stages; including tasks for converting said receive data from serial to parallel form and tasks for selectively processing and removing protocol information contained in said receive data; whereby said receive pipeline operates as a multitasking processing array, relative to receive data handled during time slots assigned to a single network channel, and as both a multiprocessing and a multitasking array relative to receive data handled in time slots assigned to all network channels;
a second plurality of autonomous special purpose logic circuit elements connected i n tandem between said network and said first RAM unit to form a plural-stage transmit pipeline relative to transmit data being transferred from said first RAM unit to said data communication network channels during said time slots assigned to respective channels, said elements constituting said transmit pipeline operating in synchronism with said assigned time slots for transporting said transmit data from respective transmit data storage queues in said first RAM unit to said network channels in said time slots assigned to respective channels, said elements constituting individual stages of said transmit pipelines performing various processing tasks on said transmit data as it passes through respective stages, including tasks for converting said transmit data from parallel to serial format and tasks for selectively inserting protocol delimiting characters into said transmit data; whereby said transmit pipeline stages act as a multitasking array relative to transmit data handled in time slots assigned to one of said channels, and as both a multiprocessing and a multitasking array relative to transmit data handled in the time slots assigned to all channels; and means coupled to said first and second RAM units and said bit-parallel data transfer bus for transferring said receive and transmit data relative to said channels between respective data storage queues in said first RAM unit and said memory subsystem; and wherein said network slots are assignable concurrently to multiple channels carrying voice and HDLC formatted data;
during any said slot n variable number of x data bits is transferable at said data communication network interface relative to a channel respectively assigned to said any slot; where x can range from 0 to n and n is at least 8;
said elements in said receive and transmit pipelines include layer 1 interfacing elements (RL1, TL1), which interface to said network during each slot for receiving and transferring data bit serially relative to a respective channel, validation elements (RV, TV) coupled to said layer 1 interfacing elements for exchanging data with said layer 1 interfacing elements in bit parallel byte sequential form relative to any channel, and memory management elements (RFM, TFM) for transferring data between said validation elements and said first RAM array relative to any channel in bit parallel byte sequential form;
said RL1 interfacing element in said receive pipeline operating on data bits received from said network relative to a channel configured for HDLC data communication to:
detect and remove bits inserted for transparency, collect bits to form bytes, remove bytes representing frame delimiting characters, and transfer remaining bytes sequentially to said RV element in the same pipeline; said RV element operating relative to remaining received bytes in said HDLC data to: perform CRC checking on said bytes and transfer said checked bytes to the RFM element in the same pipeline; said RFM element operating to transfer said bytes relative to said HDLC channel into byte spaces in the respective data storage queue in said first RAM;
said TFM element in said transmit pipeline operating relative to any channel configured for HDLC communication to fetch data bytes sequentially from byte spaces in the respective data storage queue in said first RAM and to transfer said bytes sequentially to said TV element in the same pipeline; said TV element operating relative to said HDLC channel for performing CRC checks thereon, transferring bytes sequentially to the TL1 element in the same pipeline, and generating and inserting reference CRC remainder characters into said transferred data; said TL1 element operating relative to said HDLC channel to: insert transparency bits, insert frame delimiting bytes, and transfer said data bit serially to said network in slots assigned to the respective channel; and said first RAM unit has a data queue space relative to each slot for storing at least 4 bytes of data relative to the transmit pipeline and at least 4 bytes of data relative to the receive pipeline.

33. A DLC device in accordance with claim 32 including:
means in each of said elements constituting said receive and transmit pipelines for continuously manifesting indications of respective instantaneous processing states, and means in each of said pipeline element for providing DONE indications during any slot when the respective elements are in stable processing states suitable for terminating processing relative to the channel assigned to that slot and for later resuming such processing relative to that channel;
a resource managing (RSM) element connected to said network, said first and second RAM arrays and said pipeline elements for directing the synchronous operations of said arrays and said pipeline elements relative to said network slots; said RSM element comprising:
means coupled to said data. communication network for receiving beginning of slot (EOS) signals indicating beginnings of slot periods at said network interface;
means responsive to said EOS signals for immediately retrieving configuration control (pre-CCR) information from said second RAM array indicating if the slot then beginning is assigned to an active channel, and subsequently retrieving additional configuration control (full CCR) information from said second array if the slot is assigned to an active channel;
means effective after receipt of said EOS signal for determining from previously retrieved full CCR information if the slot then ending is assigned to an active channel, and if it is sending end of slot (EOS) indications to each of said pipeline elements;
means responsive to DONE indications returned by said pipeline elements after said EOS indications for directing saving of respective pipeline element processing state indications in said second RAM array;
means responsive to said pre-CCR information indicating that the slot then beginning is assigned to an active channel for directing transfers of previously saved processing state information relative to that channel from said second RAM array to said pipeline elements; and means operative after transferals of said previously saved state information for providing start indications to said pipeline elements for initiating processing relative to the channel to which the slot then beginning is assigned.

34. A DLC device according to claim 33 wherein:
said bit transfers at said data communication network interface during any slot are conducted during a short duration time portion of the respective slot such that most of the slot time is available to said RSM element and said pipeline elements for preparing for and carrying out said state saving and loading operations.