CA2007554A1 - Code division multiplex system using selectable length spreading code sequence - Google Patents
Code division multiplex system using selectable length spreading code sequenceInfo
- Publication number
- CA2007554A1 CA2007554A1 CA002007554A CA2007554A CA2007554A1 CA 2007554 A1 CA2007554 A1 CA 2007554A1 CA 002007554 A CA002007554 A CA 002007554A CA 2007554 A CA2007554 A CA 2007554A CA 2007554 A1 CA2007554 A1 CA 2007554A1
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- CA
- Canada
- Prior art keywords
- spread spectrum
- spreading code
- code sequence
- spectrum spreading
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J13/00—Code division multiplex systems
- H04J13/16—Code allocation
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
ABSTRACT
A code division multiplex system for use in a spread spectrum communication system utilizes selectable length spread spectrum spreading code sequences. At the encoder, one of a plurality of a spread spectrum spreading code sequences having a given fixed length is selected for differential encoding in accordance with the input data to be transmitted. At the receiver correlator, a selectable length differential decoder is set to be responsive to a spread spectrum spreading code sequence having a length substantially equal to the length of the encoded spread spectrum spreading code sequence.
A code division multiplex system for use in a spread spectrum communication system utilizes selectable length spread spectrum spreading code sequences. At the encoder, one of a plurality of a spread spectrum spreading code sequences having a given fixed length is selected for differential encoding in accordance with the input data to be transmitted. At the receiver correlator, a selectable length differential decoder is set to be responsive to a spread spectrum spreading code sequence having a length substantially equal to the length of the encoded spread spectrum spreading code sequence.
Description
2no7s54 CODE DIVISION MULTIPLEX SYSTEM USING
SELECTABLE LENGTH SPREADING CODE SEQUENCES
F~L~ Of The Invention This invention relates to code d~vi~ion multiplex systems particularly for use in spread spectrum communication systems.
~ackcround Of the Invention Code div$~ion multiplexing in spread spectrum communication 8y8te~s is well known. In a spread spectrum communication sy~tem, a spreading code sequence i8 used to disperse the energy content of an original input data signal in the frequency spectrum. The individual bit~ of ~he spreading code sequence are called chips. In order to transmit each data bit in a spread spectru~ com~unication system, each individual data bit is first multiplied by the spreading codQ sequenco ln an exclusive OR gate. In a typical systemt for a data bit of zero, the spreading code sequence -~
itself i8 transmitted; while for a data bit of one, the inverse o~ the spreading code sequence is transmitted.
-1- DOC~ET NO. 1016 . ... . . ..
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:. ~ .. . .
, . .
.: .. .. ..
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Z')~75S4 At the receiver, the spreading code sequence is detected by correlating the received spread spectru~ signal with knowledge o the original spreading oode sequence which was used at the transmitter. one method and apparatus for encoding transmitted data and correlating received data in a spread spectrum system can be found in a co-pending patent application entitled l~DIFFER}~rIAL CORRELATOR FOR
SPREAD SPECTRUM COMMUNICATION SYSTEH-, serial number 271,614, filed Septemb~r 15, 1988 and assigned to the same assignee a~ the assignee of the present invention.
The ob~ect in any multiplex communication systeM (such as a frequency division multiplex syste~ or a time division multiplex system, as well as a code division multiplex system), is to provide ~or independenk communication paths between individual devices without interference to neighboring device~, i.e., to establish distinct chann~ls of coDmunication without mutual interference.
Code division multipl~x, or CDM, i8 a ~ethod for e~tablishing ~uch different distinct channels in a spread spectrum co~munlcation ~ystem. In a CD~ communication systen, different spreading code sequences are used to distinguish the different data communication channels.
Each spread spectrum recaiver correlates the received -2- DOCXET NO. 1016 ., .. , . . . , . .. _ . _ _ . _ _ . ~ .. _ .. ~ _ .. _ . . , . . . .. , .. . . ... , . .. . . . .. .
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~, - 2('~75S4 '-s. .lal vith a particular spreading code sequence, thereby establishing independent channels of communication, one channel for each distinct spread spectrum spreading code sequence used.
Su~ary Of The Inventio~
The present invention i8 embodied in a code division multipleY system in which a plurality of communication channels are created at the trans~itter encoder by selecting one of a plurality of different length spreading code seguences. At the receiver correlator, each of the sQparate ~pread spectru~ communication cbannel~ are distinguished and detected substanti~lly on th~ basis of the length of the received spreading code sequence.
Tho present invention is further embodied in a differential encoder wherein a spreading code cequenc~ of a given fixed lenqth is selected from a plurality o~ spreading code sequences ~hich have respective distinct lengths. The sQlacted ~pr0ading code ~equence is then differentially encoded in accordance with the input data. That is, each chip of th~ selected ~preading code sequence is in~erted, or not inverted, in accordance with the input data, relative to the spreading code sequence a fixed time delay previously, whi~h fixed time delay is also selectable at -3- DOCKET NO. 1016 _ ~ _ _ _ ~ . _ . .. _ . .... _ .. . _ _ . _ . . . .. . _ . _ . . .... . _ _ .. .. . . . _ . . . . _ .. _ _ . .
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t. en~oder, and is set substantially equal to the length of the selected spreading code sequence.
The present invention ifi further embodied in a spread spectrum receiver in which each received chip is compared with a chip received a ~electable fixed ti~e delay previou~ly, which time delay i8 set to be substantially equal to the length of the desired selected spreading code sequence. ~f the present received chip and the previously received chip (at the selected fixed time delay previously) are equal, then the received data i8 a logic 0. If the pre~ent received chip and the previously received chip are not equal, then received data i8 a logic 1.
Since the length of the spreading code sequence selected in the encoder is substantially equal to the ti~e delay s~lected in the recèiver correlator, t~e d~ta i~
recovered. For those receiver~ wherein the selected time delay does not match the lengt~ selected spreading code sequence in the encoder, the receiver correlator will produce ~n uncorreiat d noi6e like output. ~owever~ the extent of cod~ divi~ion ~ultiplex descrimination depends on the cross oorrelation propertie~ of the chosen plurality of spreading code sequance~.
SELECTABLE LENGTH SPREADING CODE SEQUENCES
F~L~ Of The Invention This invention relates to code d~vi~ion multiplex systems particularly for use in spread spectrum communication systems.
~ackcround Of the Invention Code div$~ion multiplexing in spread spectrum communication 8y8te~s is well known. In a spread spectrum communication sy~tem, a spreading code sequence i8 used to disperse the energy content of an original input data signal in the frequency spectrum. The individual bit~ of ~he spreading code sequence are called chips. In order to transmit each data bit in a spread spectru~ com~unication system, each individual data bit is first multiplied by the spreading codQ sequenco ln an exclusive OR gate. In a typical systemt for a data bit of zero, the spreading code sequence -~
itself i8 transmitted; while for a data bit of one, the inverse o~ the spreading code sequence is transmitted.
-1- DOC~ET NO. 1016 . ... . . ..
: - . . : ... . .
- , . .
. -. , - . ... . .
:. ~ .. . .
, . .
.: .. .. ..
. . - ~ .., ;
Z')~75S4 At the receiver, the spreading code sequence is detected by correlating the received spread spectru~ signal with knowledge o the original spreading oode sequence which was used at the transmitter. one method and apparatus for encoding transmitted data and correlating received data in a spread spectrum system can be found in a co-pending patent application entitled l~DIFFER}~rIAL CORRELATOR FOR
SPREAD SPECTRUM COMMUNICATION SYSTEH-, serial number 271,614, filed Septemb~r 15, 1988 and assigned to the same assignee a~ the assignee of the present invention.
The ob~ect in any multiplex communication systeM (such as a frequency division multiplex syste~ or a time division multiplex system, as well as a code division multiplex system), is to provide ~or independenk communication paths between individual devices without interference to neighboring device~, i.e., to establish distinct chann~ls of coDmunication without mutual interference.
Code division multipl~x, or CDM, i8 a ~ethod for e~tablishing ~uch different distinct channels in a spread spectrum co~munlcation ~ystem. In a CD~ communication systen, different spreading code sequences are used to distinguish the different data communication channels.
Each spread spectrum recaiver correlates the received -2- DOCXET NO. 1016 ., .. , . . . , . .. _ . _ _ . _ _ . ~ .. _ .. ~ _ .. _ . . , . . . .. , .. . . ... , . .. . . . .. .
. .. ~ _ _ _ _ _ .. . . . ..
, . , ,: ~
- . .. . . , - - - . , . . -... ~ . .. ~ - . . . . - .: -. .
'''''' '' .
.".. .. ..
.
~, - 2('~75S4 '-s. .lal vith a particular spreading code sequence, thereby establishing independent channels of communication, one channel for each distinct spread spectrum spreading code sequence used.
Su~ary Of The Inventio~
The present invention i8 embodied in a code division multipleY system in which a plurality of communication channels are created at the trans~itter encoder by selecting one of a plurality of different length spreading code seguences. At the receiver correlator, each of the sQparate ~pread spectru~ communication cbannel~ are distinguished and detected substanti~lly on th~ basis of the length of the received spreading code sequence.
Tho present invention is further embodied in a differential encoder wherein a spreading code cequenc~ of a given fixed lenqth is selected from a plurality o~ spreading code sequences ~hich have respective distinct lengths. The sQlacted ~pr0ading code ~equence is then differentially encoded in accordance with the input data. That is, each chip of th~ selected ~preading code sequence is in~erted, or not inverted, in accordance with the input data, relative to the spreading code sequence a fixed time delay previously, whi~h fixed time delay is also selectable at -3- DOCKET NO. 1016 _ ~ _ _ _ ~ . _ . .. _ . .... _ .. . _ _ . _ . . . .. . _ . _ . . .... . _ _ .. .. . . . _ . . . . _ .. _ _ . .
, - - . .~ ~ C7 .
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~ V .
., .
: Z')~7S5~
t. en~oder, and is set substantially equal to the length of the selected spreading code sequence.
The present invention ifi further embodied in a spread spectrum receiver in which each received chip is compared with a chip received a ~electable fixed ti~e delay previou~ly, which time delay i8 set to be substantially equal to the length of the desired selected spreading code sequence. ~f the present received chip and the previously received chip (at the selected fixed time delay previously) are equal, then the received data i8 a logic 0. If the pre~ent received chip and the previously received chip are not equal, then received data i8 a logic 1.
Since the length of the spreading code sequence selected in the encoder is substantially equal to the ti~e delay s~lected in the recèiver correlator, t~e d~ta i~
recovered. For those receiver~ wherein the selected time delay does not match the lengt~ selected spreading code sequence in the encoder, the receiver correlator will produce ~n uncorreiat d noi6e like output. ~owever~ the extent of cod~ divi~ion ~ultiplex descrimination depends on the cross oorrelation propertie~ of the chosen plurality of spreading code sequance~.
-4- DOCKET N0. 1016 - . .
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' ' ' `-` 2~ 554 ~e__ription of the Drawing Figure 1 i5 a topological map of plurality of local area networks embodying th~ present invention arrangedi in a plurality of cells.
Figure 2 i8 a bloc~ diagram of a spread spectru~ receiver and a spread spectrum transmitter in accordance with the pre~ent invention.
Figure 3 i8 a schematic diagra~, partially in blocX form, of a spread spectru~ encoder in accordance with the present invention.
Figure 4 i8 a schematic diagra~, partially in block form, of a spread spectrum correlator in accordance ~ith the pre~ent invention.
DetalL Description Figure 1 illustrates thie general situation presented in a multiplexed data communication environ~ient. In a given area 10, it i8 desired to provide for more than one non-intefering communication channel.
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' ' ' `-` 2~ 554 ~e__ription of the Drawing Figure 1 i5 a topological map of plurality of local area networks embodying th~ present invention arrangedi in a plurality of cells.
Figure 2 i8 a bloc~ diagram of a spread spectru~ receiver and a spread spectrum transmitter in accordance with the pre~ent invention.
Figure 3 i8 a schematic diagra~, partially in blocX form, of a spread spectru~ encoder in accordance with the present invention.
Figure 4 i8 a schematic diagra~, partially in block form, of a spread spectrum correlator in accordance ~ith the pre~ent invention.
DetalL Description Figure 1 illustrates thie general situation presented in a multiplexed data communication environ~ient. In a given area 10, it i8 desired to provide for more than one non-intefering communication channel.
-5- DOCKET N0. 1016 "
~ ", ~ , . , .~ ~ - . , ~ ` 2()075S4 S~ ificallyt a given area 10 may be divided into four cells each containing separate local area networks, i.e., LAN 1, LAN 2, LAN 3, and LAN 4. Within each of the four respective LAN cells, a separate data communication channel is used to communicate between local devices within each LAN cell. That is, printers, file server~ and the like are shared by individual computers and co~puter terminal~
within a LAN cell. However, it is desired that there be no interference with neighboring LANs using separate data communication channels in adjac~nt cell~.
In a CDM spread spectrum communication ~ystem, each of LAN
1, LAN 2, LAN 3, and LAN 4 typically uses a different spreading code sequence length so that the four LAN5 can coexist in an area 10 simultaneously using the sa~e portion of the frequency spectrum without ad~acent channel interference. In order to create the separate channels, LAN 1 use ~ first spreading code sequence length ~hile LAN
2, LAN 3, and LA~ 4 each u~e respective different 2nd, 3rd, and 4th spreading code sequence lengths~ The topological pattern o~ the four c811~ is repeated in ad~acent area~ so that the minimu~ distance between cell~ u~ing the same spreadiag cod~ sequence length is t~o.
~ ", ~ , . , .~ ~ - . , ~ ` 2()075S4 S~ ificallyt a given area 10 may be divided into four cells each containing separate local area networks, i.e., LAN 1, LAN 2, LAN 3, and LAN 4. Within each of the four respective LAN cells, a separate data communication channel is used to communicate between local devices within each LAN cell. That is, printers, file server~ and the like are shared by individual computers and co~puter terminal~
within a LAN cell. However, it is desired that there be no interference with neighboring LANs using separate data communication channels in adjac~nt cell~.
In a CDM spread spectrum communication ~ystem, each of LAN
1, LAN 2, LAN 3, and LAN 4 typically uses a different spreading code sequence length so that the four LAN5 can coexist in an area 10 simultaneously using the sa~e portion of the frequency spectrum without ad~acent channel interference. In order to create the separate channels, LAN 1 use ~ first spreading code sequence length ~hile LAN
2, LAN 3, and LA~ 4 each u~e respective different 2nd, 3rd, and 4th spreading code sequence lengths~ The topological pattern o~ the four c811~ is repeated in ad~acent area~ so that the minimu~ distance between cell~ u~ing the same spreadiag cod~ sequence length is t~o.
-6- DOCKET NO. 1016 . . ~ - .,. .' '' . . . .
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2~ 7SS4 A ~read spectrum co~unication system using selectable length spreading code sequences in accordance with the present invention is shown in figure 2.
Data input at terminal 20 i5 applied to spread spectrum encoder 22 which i~ in turn input to PSK modulator and RF
transmitter 24. The output of the R~ transmitter is applied to transmitter antenna 26. A~ter transmission through a suitable medium and reception by rec~iving antenna 28, the signal is applied to RF receiver and PSK
demodulator 30. The output of the PSR demodulator is applied to a spread speotrum correlator 32 to recover the original data at output tQrminal 34.
Th~ length of the spreading code sequence utilized i~ the transmitter spread spectrum encoder 22 i8 set by ~
transmitter seguence length select switch 23 (shown symbolically as a rotary sw~tch) which places an enabling signal on on~ of four ~equence length ~elect lines 36, 38, 40, or 42 connected to ~pread -Qprectrum encoder 22.
Similarly, at the r~ceiver the length of the spreading code sequenca utilized by the receiver spread spectrun correlator 32 i~ ~et by a receiver sequence length select ~witch 31 (also shown symbolically a~ a rotary switch) which place3 an enabling signal on one of four sequence length select lines 44, 46, 48, or 50 connected to spread sp~ctrum correlator 32.
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2~ 7SS4 A ~read spectrum co~unication system using selectable length spreading code sequences in accordance with the present invention is shown in figure 2.
Data input at terminal 20 i5 applied to spread spectrum encoder 22 which i~ in turn input to PSK modulator and RF
transmitter 24. The output of the R~ transmitter is applied to transmitter antenna 26. A~ter transmission through a suitable medium and reception by rec~iving antenna 28, the signal is applied to RF receiver and PSK
demodulator 30. The output of the PSR demodulator is applied to a spread speotrum correlator 32 to recover the original data at output tQrminal 34.
Th~ length of the spreading code sequence utilized i~ the transmitter spread spectrum encoder 22 i8 set by ~
transmitter seguence length select switch 23 (shown symbolically as a rotary sw~tch) which places an enabling signal on on~ of four ~equence length ~elect lines 36, 38, 40, or 42 connected to ~pread -Qprectrum encoder 22.
Similarly, at the r~ceiver the length of the spreading code sequenca utilized by the receiver spread spectrun correlator 32 i~ ~et by a receiver sequence length select ~witch 31 (also shown symbolically a~ a rotary switch) which place3 an enabling signal on one of four sequence length select lines 44, 46, 48, or 50 connected to spread sp~ctrum correlator 32.
-7- DOCKET N0. 1016 ... _ , . _ _ ~ _ _ .. . , ... ..... . _ _ . _ . _ ... , . _ . . . . . ... . . . _ . ., , .. ... , .
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~ 2~)7554 In operation, one of four different spreading code sequence lenqths in the transmitter i selected by setting the transmitter sequence length selec~ switch 23 to one of its four different settings. In the receiver, one of four different spreading code sequence lengths ~g selected by setting receiver sequence lengths ~elect switch 31 to one of its four different settings.
If the transmitter portion and receiver portion of figure 2 are in the same LAN cell, and are intended to communicate over a co~mon data ch~nel, then the lenqth of the selected ~preading code seguence in the transmitter i~ set equal to the length of the selected spreading cod~ sequence in the receiver. On the o~her hand, if the receiver portion of figure 2 i5 intended to operate in a different ~AN cell without lnterference fro~ the transmitter in the first LAN
cell, then the length of the spreading code sequence selected in the receiver is not egual to the length of the spreading code sequence selected in the transmitter.
In such manner, all of the spread spectrum encoders and spread spectrum correlators utilized within LAN 1 are ad~usted to use a spreading code sequence of a first length, while all of the respective spread spectrum encoders and spread spectrum correlators in adjacent LAN
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~ 2~)7554 In operation, one of four different spreading code sequence lenqths in the transmitter i selected by setting the transmitter sequence length selec~ switch 23 to one of its four different settings. In the receiver, one of four different spreading code sequence lengths ~g selected by setting receiver sequence lengths ~elect switch 31 to one of its four different settings.
If the transmitter portion and receiver portion of figure 2 are in the same LAN cell, and are intended to communicate over a co~mon data ch~nel, then the lenqth of the selected ~preading code seguence in the transmitter i~ set equal to the length of the selected spreading cod~ sequence in the receiver. On the o~her hand, if the receiver portion of figure 2 i5 intended to operate in a different ~AN cell without lnterference fro~ the transmitter in the first LAN
cell, then the length of the spreading code sequence selected in the receiver is not egual to the length of the spreading code sequence selected in the transmitter.
In such manner, all of the spread spectrum encoders and spread spectrum correlators utilized within LAN 1 are ad~usted to use a spreading code sequence of a first length, while all of the respective spread spectrum encoders and spread spectrum correlators in adjacent LAN
-8- DOCKET NO. 1016 _. ~_ _~, _ _,-- , . _ ._ _ .. . _ . . . _ . , .. . _ . . _. _ _ ._ _._ ..... _ _ .... . .. ..... .
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Z~ 7554 ce _s 2, 3, and 4, are selected to use respective spreading codQ sequences of a second, third, and fourth length.
Figure 3 ~ho~ a transmitter encoder in accordance with the present invention which ~ay be used to generate a spread spectrum signal having a selectab1e length spreading code sequence. Tha trans~itter encoder includes a differential encoder portion and a selectable length spreading code ~-sQquence q~nerator portion.
The differential encoder portion comprise~ a ~ultiple tap ~hift register 70, a 4 to 1 multipl~xer ~2, exclusive OR
gate 66, and exclu~iv~ OR gate 68. Nultiplexer 72 is connected for selecting one o~ tbe four ~ultiple tapc~ or output stages, of shift register 70 on one of four conductors 82, 84, 86, or 88, respectively in accordance with a trans~itter ~equenc~ length ~el~at signal input on input data buss 5~.
Input data buss 56 i8 a t~o bit data bu~s which controls multiplexer 72 80 ~ to select one of the four multiple taps of ~bi~t regi~ter 70 as one input to exclusive OR gate 66. Thu~, ~ultiplexer 72 i8 r~sponsive to the trans~itt~r sequence length select signal on input data buss 56 to control the effectiv~ length of shift register 70, the output of which i8 input to exclusive OR gate 66. The -9- DOCKET NO. 1016 .. ..
. . : .. . - . , . . -.: . . .
_ .. :,. . . - .. . . . -, , .~ -';
- , ` ` . Z ~ 3 ~3 7 5 S 4 ou_~ut of exclusive OR gate 66 is connected to one input of exclusive OR gate 68 and is also connected in a feedback configuration to the data input terminal of shift reqister 70. The transmitter chip cloc~ on terminal 54 i8 connected to the clock input of shift register 70 The selectable length spreading sequence generator portion of figure 3 co~prises a multiple tap sh1ft register 74, a 4 to 1 multiplexer 80, a 2 to 1 multiplexer 76, and a 2 to 1 multiplexer 78. A shift register run/load signal on t~rminal 58 is connected to the control terminals of the multiplexer~ 76 and 78. Multiple~er 80 i connected for selecting one of the four ~ultiple tap~, or output stages, Or shift rsqlster 74 on one of four conductors 90, 92, 94, or 96, respectively in accordance with the trans~itter sQquence length select signal on input data buss 56, d~cribed above. Thus, multiplexer 80 is responsive to the 8am~ transmitter seguence length select signal on input data buss 56 as i9 ~ultiplexer 72 so 28 to control the effective length of shift register 74 to be equal to the ~fective length of shift register 70. The output of multiplexer 80 is connected to one input of multiplexer 78, the output of which i~ connected to tha data input of shift regi3ter 74, thereby providing a data path to recirculate the data in shift reqister 74 through multiplexers 80 and 78.
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Z~ 7554 ce _s 2, 3, and 4, are selected to use respective spreading codQ sequences of a second, third, and fourth length.
Figure 3 ~ho~ a transmitter encoder in accordance with the present invention which ~ay be used to generate a spread spectrum signal having a selectab1e length spreading code sequence. Tha trans~itter encoder includes a differential encoder portion and a selectable length spreading code ~-sQquence q~nerator portion.
The differential encoder portion comprise~ a ~ultiple tap ~hift register 70, a 4 to 1 multipl~xer ~2, exclusive OR
gate 66, and exclu~iv~ OR gate 68. Nultiplexer 72 is connected for selecting one o~ tbe four ~ultiple tapc~ or output stages, of shift register 70 on one of four conductors 82, 84, 86, or 88, respectively in accordance with a trans~itter ~equenc~ length ~el~at signal input on input data buss 5~.
Input data buss 56 i8 a t~o bit data bu~s which controls multiplexer 72 80 ~ to select one of the four multiple taps of ~bi~t regi~ter 70 as one input to exclusive OR gate 66. Thu~, ~ultiplexer 72 i8 r~sponsive to the trans~itt~r sequence length select signal on input data buss 56 to control the effectiv~ length of shift register 70, the output of which i8 input to exclusive OR gate 66. The -9- DOCKET NO. 1016 .. ..
. . : .. . - . , . . -.: . . .
_ .. :,. . . - .. . . . -, , .~ -';
- , ` ` . Z ~ 3 ~3 7 5 S 4 ou_~ut of exclusive OR gate 66 is connected to one input of exclusive OR gate 68 and is also connected in a feedback configuration to the data input terminal of shift reqister 70. The transmitter chip cloc~ on terminal 54 i8 connected to the clock input of shift register 70 The selectable length spreading sequence generator portion of figure 3 co~prises a multiple tap sh1ft register 74, a 4 to 1 multiplexer 80, a 2 to 1 multiplexer 76, and a 2 to 1 multiplexer 78. A shift register run/load signal on t~rminal 58 is connected to the control terminals of the multiplexer~ 76 and 78. Multiple~er 80 i connected for selecting one of the four ~ultiple tap~, or output stages, Or shift rsqlster 74 on one of four conductors 90, 92, 94, or 96, respectively in accordance with the trans~itter sQquence length select signal on input data buss 56, d~cribed above. Thus, multiplexer 80 is responsive to the 8am~ transmitter seguence length select signal on input data buss 56 as i9 ~ultiplexer 72 so 28 to control the effective length of shift register 74 to be equal to the ~fective length of shift register 70. The output of multiplexer 80 is connected to one input of multiplexer 78, the output of which i~ connected to tha data input of shift regi3ter 74, thereby providing a data path to recirculate the data in shift reqister 74 through multiplexers 80 and 78.
-10- DOCXET NO. 1016 - . i . : . ., , ~
., ,: . , .' ~ .
, .
In operation, there i8 an initializing mode during which a spreading code sequence is loaded into shift register 74, followed by a run mode during which the previously loaded spreading code sequence is recirculated in shift register 74. The selected transmitter spreading code sequence on terminal 60 is serially loaded into shift register 74 through multiplexer 78. ~uring the initializing mode, the shift register run/load signal on ter~inal 58 conditions ~ultiplexer 76 to connect the load clock sign21 on terminal 62 to the clock input of shift register 74. The transmitter spreading sequence thus loaded into shift register 74 is the selected spreading code sequence which will be used in the transmitter encoder, and ~ay be provided from a suitable digital memory (not ~hown) which contains the plurality of the spreading codes sequences to be used in the present cod~ di~i~ion ~ultiplexing s~stem.
After ~ufficient load clock pulses h~ve elapsed to load the selected spreading sequence into shift register 74, the run ~ode i~ entered. ThQ ~hift reqi~ter run/load signal on termin~l 58 then condition~ multiplexer 76 to connect the transmitt~r chip clock ~ignal on terDinal 64 to the clock input of shift register 74. At the s2me time, the shift register run/load signal on ter~inal 58 condition.
~ultiplexer 78 to connect the output of multiplexer 80 on DOCXET N0. 1016 - . : . .
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` '~')~37554 con~uctor 81 to the data input terminal of shi~t register 74. Thus, the transmîtter spreading sequence previously loaded into shift register 74 will now recirculate from the selected output tap of ~hift register 74 to the data input terminal of shift register 74. The resulting signal on conductor 81 is the rapeating selectable length spreading code sequence which will be used to generate the output spread spectrum signal at terminal 69.
The intended purpose of the differential encoder portion of figure 3 is to invert, or not in~ert, the polarity of each chip of the selected spreading code ~equence, relative to the polarity of the corresponding chip of the selected spreading code sequence a selected fixed time delay pravioulsy, in accordance with the value of the input data.
Specifically, if the tran~mitter input data signal on terminal 52 is a logic 1, the polarity of the current chip of the selected spreading code sequence at output terminal 69 relative to the polarity of the ~elected spreading code aequence a selected fixed time delay previously, ~ill be inverted; if the tr~ns~itter input data ~ignal i5 a 0, the encoder of ~igure 3 will not invert tha polarity of the present chip of the selected spreading code sequence, relative to th~ polarity of the ~elected spreading code sequence a fixed ti~e delay previou~ly, at output terminal 69.
-12- DOCKET N0. 1016 -,. . . ~ . . . . -~ ' `` 2')~)7~54 Exclusive OR gate 68 unctions as a programmable inverter to invert or not invert each chip of the selected spreading code sequence on condutor 81 depending upon the value of an inversion control logic signal on conductor 67. Thu~, if the ~ignal on conductor 67 is a logic 1, the present chip of the selected spreading code sequence on conductor 81 is inverted at the output of exclusive OR gate 68 on terminal 69. Conversely, if the ~ignal on conductor 67 i8 a logic O, the present chip of the selected spreading code sequence on conductor 81 is not invertad in eYclusive OR gat~ 68 at output terminal 69.
The previous values of the inversion control 6ignal on conductor 67 are recorded in shift register 70 so that a previous inv~rsion control signal, specifically at a ~el~ctable time delay pr2viously, i~ input to exclusive OR
gate 66 at the output of multiplexer 72. If the transmitter data input ~ignal at ter~inal 52 is a logic 1, then exclu~ive OR gate 66 inverts the previous inversion control 8ignal to ~or~ th~ present i~ver~ion control signal at conductor 67, while if the trans~itter data input signal at tenminal 5~ logic 0, exclusive OR gate 66 does not invert the previous inversion control ~ignal stored in shift register 70 to form the present inversion control signal at conductoF 67.
~13- DOCKET NO. 1016 . ~ . _ __ . _ . _. , . . . ~ .. _ . .. . . .. _ _ _ ., . . . .. . _ .. . .... _ ... . ... ~ .. . . ..
_ , _ _ ....... ,_ .,. ,, - . . .
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~. - , . , 2')07~54 More speci~ically, i~ t~e previous chip (meaning the corresponding chip of the previous cycle of the selected spreading code sequence at output ter~inal 69) was inverted and the transmitted data input i8 a logic 1, then present chip is not inverted. If the previous chip was not inverted and the trans~itted data input i~ a logic 1, then the present chip at output terminal 69 i~ inverted. If the previous chip was inverted, and the trans~itted data input is a logic 0, then the present chip i5 also inverted. If the previous chip wa~ not inverted, and the transmitted data input is a logic 0, then the present chlp i~ al~o not inverted. In such manner, the selected spreading code sequence is differentially encoded at output terminal 69 in accordance with the tran~mitter input data at terminal 52.
Each of the selectable spreading code ~equences has unique longth which correspond to the ~el~ctable length~ of shi~t regist~rs 70 and 74. As a speci~ic exa~ple, ln the trans~itter encoder o~ figuro 3, shift registers 70 and 74 may be 18 bit shift r~gi~ters. The selectable taps 82, 84, 86, and 88 of shi~t r~gister 70 and the selectable taps 90, 92, 9~, and 96 ot ahi~t register 74 may correspond to selectable ~xed time d~lay~ or selectable length spreading code sequence~ of 14, 15, 17, or 1~ chips respectively. In ~uch ~anner, a spreading code sequence of 14, 15, 17, or 18 -14- DOCKET NO. 1016 .. . _ . .. ... , .. ... . ..... .. . . .. . . . . .. ., . .. . . . .. ... ... .. . . _ _ . . .
~ ~ .
. .
~, , ' . .
; Z~ 7Ss4 "s is selected. Tne input data in all cases, may be fixed at 16 chips per data bit.
A receiver correlator for recovering the data from a spread spectrum signal encoded in accordance with a selectable length spreading code sequence, is shown in figure 4. The correlator comprises a ~ultiple tap shift register 104; a 4 to 1 multiplexer 108, and an exclusive OR gate 106.
MultipleYer 108 is connected for selecting one of the four output stages of shift register 70 on conductor~ 110, 112, 114, or 116 for input to one input terminal of exclusive OR
gate 106. ~ultiplexer 108 is responsive to a recei~er sequence length select signal input on data bu~ 102. The two bit input at data bus~ 102 conditions ~ultiplexer 108 to select one of the plural output stages of shift register 104, thereby effectively controlling the total delay pro~ided by shift regi~ter 104.
~he receiver chip clock at terminal 101 is connected to the clock input of shift ragister 104. Methods for recovering th~ receiver chip clock ~ignal from the received ~pread ~pectru~ signal are well known to those skilled in the art and ~or- no part of th~ present invention.
-15- DOCXET NO. 1016 ... , . ~ . . . .. ... . . ... . .. . .... ... ... .. . .. ~ . . . . .. ..... . ... .. ... _ . .
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Z"~75S4 In peration, the shift register 104 stores the individual received chips of the spread spectrum signal received on terminal 100. The delay provided by shift register 104 and multiplexer 108, responsive to the receiver sequence length signal on data buss 102, is set equal to the length of the desired selected spreading code seguence. For example, if it ia desired to receive data from an encoder using ~ 14 chip spreading code sequence, multiplexer 108 is Qet to select conductor 110 at the output tap of shift register 104 corresponding to 14 stagQs. Similarly, output taps for 15, 17, and 18 chips are provided at conductors 112, 114, and 116, respectively.
The output of multiplexer 108 on conductor 109 i9 thus the correspondin~ chip of the previous spreading code ~equence. Now, exclu3ive OR gate 106 compares each received chip of ths presently rece~ved spreading code sequence with a corresponding chip of the previously raceived spreading cod~ ~equence. Either the pre~ently rece~ved chip of th- ~pre~ding eode sequence is the ~ame as the previously receive~ chip of the prev~ously received ~equence, in which cas~ the received data is a logic 0, or it i~ the opposit~ o~ such previously receiv~d chip, in wh1ch case the received data i~ a logic 1.
-16- DOCKET NO. 1016 , _ _ ,., . , .. , .. _ .. . _ _. _ . , .... . . _ . _ . _ . . . . . _ . .. . . _~._ .. .
..
., . .. .. : . . -, . . ' . ,, ' ' : :
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I, either event, the output of exclusive OR gate 106 atreceiver data output terminal 118, will be a ~eries of comparison~, sne comparison for each chip with a correspoding chip of the previously received spreading code sequence, the total number of comparisons being equal to the total number of chips per data bit.
Following the output of the data correlator of figure 4, is a ma~ority vote logic (not shown) in ord~r to determine whether the received data bit i8 a 1 or ~ O. Under ideal condition~, all of the output chip co~parisons of over one data bit interval fro~ exclusive OR gate 106 will be of the ~ame polarity. In the presence of noise, some of t~em will be in error. However, by a ~ajority vote of the output chip~ at terminal 118, improv~d com~unication~ reliability i~ achieved. In the present example, it i~ noted that the number of chips per data bit i~ always 16, even for dif~erent spreading code sequence lengt~, which simplifies system design and a~sure~ rel~tively uniform system performance parameter regardless of th~ chosen spreading code sequence length.
If the spreading cod~ sequence used to enccde the received spread spectru~ ~ignal on terminal 100 is of a different length than ~he length selected by shift register 104 and multlplexer 108, then th~ receiver data output at terminal -17- DOCRET NO. 1016 ., .,, ~ --: - ,.
... ~, ~ ~ - . . , . - - .
.
.
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118 will resemble an uncorrleated noise like signal.
Therefore, the correlator of figure 4 is responsive primarily to the length of the received spreading code sequence. Signals encoded with a spreading code sequence of a different length, relative to the selectable delay provided by shift register 104 and multiplexer 108,will be ignored.
Although it is only nece~sary that the plurality of spr~ading code sequences used in the cod~ divi~ion multiplex 8y8tem of the present invention differ only in th~ lQngth of the respective ~preading codQ 8equence8, it i~ preferabl~ to u~e ~preading code sequences ha~iDg low crosQ correlation properti~s, as well as different lengths, in order to improve system channel discrimination between the different length spreading code sequence~. Al~o, it is understood that the ~hift reqisters 70, 74, and 10~ used in the described emb2diment may be replaced with any other delay element providing a selectable time delay.
Thu~, a ~imple econouic~l data corr~lator and d~ta encoder u~ing sele~tablQ leng~h spreading code seguence~ for code division ~ultiplexing ha~ been de~cribed for u~e and con~unction with a spread spectru~ communication system.
-18- DOCgET NO. 1016 ~ ~ .. _ _ _ . . , , . _ _ _ . .. _ , _ . .. , .. . . . _ _ _ _ _ _ _ .. . ..... . .... . ...... . . _ . _ -, . ....
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In operation, there i8 an initializing mode during which a spreading code sequence is loaded into shift register 74, followed by a run mode during which the previously loaded spreading code sequence is recirculated in shift register 74. The selected transmitter spreading code sequence on terminal 60 is serially loaded into shift register 74 through multiplexer 78. ~uring the initializing mode, the shift register run/load signal on ter~inal 58 conditions ~ultiplexer 76 to connect the load clock sign21 on terminal 62 to the clock input of shift register 74. The transmitter spreading sequence thus loaded into shift register 74 is the selected spreading code sequence which will be used in the transmitter encoder, and ~ay be provided from a suitable digital memory (not ~hown) which contains the plurality of the spreading codes sequences to be used in the present cod~ di~i~ion ~ultiplexing s~stem.
After ~ufficient load clock pulses h~ve elapsed to load the selected spreading sequence into shift register 74, the run ~ode i~ entered. ThQ ~hift reqi~ter run/load signal on termin~l 58 then condition~ multiplexer 76 to connect the transmitt~r chip clock ~ignal on terDinal 64 to the clock input of shift register 74. At the s2me time, the shift register run/load signal on ter~inal 58 condition.
~ultiplexer 78 to connect the output of multiplexer 80 on DOCXET N0. 1016 - . : . .
. . ~ . - . ; - : - , -, : : ., - . . .
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.. . .
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` '~')~37554 con~uctor 81 to the data input terminal of shi~t register 74. Thus, the transmîtter spreading sequence previously loaded into shift register 74 will now recirculate from the selected output tap of ~hift register 74 to the data input terminal of shift register 74. The resulting signal on conductor 81 is the rapeating selectable length spreading code sequence which will be used to generate the output spread spectrum signal at terminal 69.
The intended purpose of the differential encoder portion of figure 3 is to invert, or not in~ert, the polarity of each chip of the selected spreading code ~equence, relative to the polarity of the corresponding chip of the selected spreading code sequence a selected fixed time delay pravioulsy, in accordance with the value of the input data.
Specifically, if the tran~mitter input data signal on terminal 52 is a logic 1, the polarity of the current chip of the selected spreading code sequence at output terminal 69 relative to the polarity of the ~elected spreading code aequence a selected fixed time delay previously, ~ill be inverted; if the tr~ns~itter input data ~ignal i5 a 0, the encoder of ~igure 3 will not invert tha polarity of the present chip of the selected spreading code sequence, relative to th~ polarity of the ~elected spreading code sequence a fixed ti~e delay previou~ly, at output terminal 69.
-12- DOCKET N0. 1016 -,. . . ~ . . . . -~ ' `` 2')~)7~54 Exclusive OR gate 68 unctions as a programmable inverter to invert or not invert each chip of the selected spreading code sequence on condutor 81 depending upon the value of an inversion control logic signal on conductor 67. Thu~, if the ~ignal on conductor 67 is a logic 1, the present chip of the selected spreading code sequence on conductor 81 is inverted at the output of exclusive OR gate 68 on terminal 69. Conversely, if the ~ignal on conductor 67 i8 a logic O, the present chip of the selected spreading code sequence on conductor 81 is not invertad in eYclusive OR gat~ 68 at output terminal 69.
The previous values of the inversion control 6ignal on conductor 67 are recorded in shift register 70 so that a previous inv~rsion control signal, specifically at a ~el~ctable time delay pr2viously, i~ input to exclusive OR
gate 66 at the output of multiplexer 72. If the transmitter data input ~ignal at ter~inal 52 is a logic 1, then exclu~ive OR gate 66 inverts the previous inversion control 8ignal to ~or~ th~ present i~ver~ion control signal at conductor 67, while if the trans~itter data input signal at tenminal 5~ logic 0, exclusive OR gate 66 does not invert the previous inversion control ~ignal stored in shift register 70 to form the present inversion control signal at conductoF 67.
~13- DOCKET NO. 1016 . ~ . _ __ . _ . _. , . . . ~ .. _ . .. . . .. _ _ _ ., . . . .. . _ .. . .... _ ... . ... ~ .. . . ..
_ , _ _ ....... ,_ .,. ,, - . . .
.: . . . . : : .
. , :
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. :
~. - , . , 2')07~54 More speci~ically, i~ t~e previous chip (meaning the corresponding chip of the previous cycle of the selected spreading code sequence at output ter~inal 69) was inverted and the transmitted data input i8 a logic 1, then present chip is not inverted. If the previous chip was not inverted and the trans~itted data input i~ a logic 1, then the present chip at output terminal 69 i~ inverted. If the previous chip was inverted, and the trans~itted data input is a logic 0, then the present chip i5 also inverted. If the previous chip wa~ not inverted, and the transmitted data input is a logic 0, then the present chlp i~ al~o not inverted. In such manner, the selected spreading code sequence is differentially encoded at output terminal 69 in accordance with the tran~mitter input data at terminal 52.
Each of the selectable spreading code ~equences has unique longth which correspond to the ~el~ctable length~ of shi~t regist~rs 70 and 74. As a speci~ic exa~ple, ln the trans~itter encoder o~ figuro 3, shift registers 70 and 74 may be 18 bit shift r~gi~ters. The selectable taps 82, 84, 86, and 88 of shi~t r~gister 70 and the selectable taps 90, 92, 9~, and 96 ot ahi~t register 74 may correspond to selectable ~xed time d~lay~ or selectable length spreading code sequence~ of 14, 15, 17, or 1~ chips respectively. In ~uch ~anner, a spreading code sequence of 14, 15, 17, or 18 -14- DOCKET NO. 1016 .. . _ . .. ... , .. ... . ..... .. . . .. . . . . .. ., . .. . . . .. ... ... .. . . _ _ . . .
~ ~ .
. .
~, , ' . .
; Z~ 7Ss4 "s is selected. Tne input data in all cases, may be fixed at 16 chips per data bit.
A receiver correlator for recovering the data from a spread spectrum signal encoded in accordance with a selectable length spreading code sequence, is shown in figure 4. The correlator comprises a ~ultiple tap shift register 104; a 4 to 1 multiplexer 108, and an exclusive OR gate 106.
MultipleYer 108 is connected for selecting one of the four output stages of shift register 70 on conductor~ 110, 112, 114, or 116 for input to one input terminal of exclusive OR
gate 106. ~ultiplexer 108 is responsive to a recei~er sequence length select signal input on data bu~ 102. The two bit input at data bus~ 102 conditions ~ultiplexer 108 to select one of the plural output stages of shift register 104, thereby effectively controlling the total delay pro~ided by shift regi~ter 104.
~he receiver chip clock at terminal 101 is connected to the clock input of shift ragister 104. Methods for recovering th~ receiver chip clock ~ignal from the received ~pread ~pectru~ signal are well known to those skilled in the art and ~or- no part of th~ present invention.
-15- DOCXET NO. 1016 ... , . ~ . . . .. ... . . ... . .. . .... ... ... .. . .. ~ . . . . .. ..... . ... .. ... _ . .
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. . .
Z"~75S4 In peration, the shift register 104 stores the individual received chips of the spread spectrum signal received on terminal 100. The delay provided by shift register 104 and multiplexer 108, responsive to the receiver sequence length signal on data buss 102, is set equal to the length of the desired selected spreading code seguence. For example, if it ia desired to receive data from an encoder using ~ 14 chip spreading code sequence, multiplexer 108 is Qet to select conductor 110 at the output tap of shift register 104 corresponding to 14 stagQs. Similarly, output taps for 15, 17, and 18 chips are provided at conductors 112, 114, and 116, respectively.
The output of multiplexer 108 on conductor 109 i9 thus the correspondin~ chip of the previous spreading code ~equence. Now, exclu3ive OR gate 106 compares each received chip of ths presently rece~ved spreading code sequence with a corresponding chip of the previously raceived spreading cod~ ~equence. Either the pre~ently rece~ved chip of th- ~pre~ding eode sequence is the ~ame as the previously receive~ chip of the prev~ously received ~equence, in which cas~ the received data is a logic 0, or it i~ the opposit~ o~ such previously receiv~d chip, in wh1ch case the received data i~ a logic 1.
-16- DOCKET NO. 1016 , _ _ ,., . , .. , .. _ .. . _ _. _ . , .... . . _ . _ . _ . . . . . _ . .. . . _~._ .. .
..
., . .. .. : . . -, . . ' . ,, ' ' : :
: . . -: , . . .
-; ~ , ~. .
: ' , ()q37554 .--- ' .
I, either event, the output of exclusive OR gate 106 atreceiver data output terminal 118, will be a ~eries of comparison~, sne comparison for each chip with a correspoding chip of the previously received spreading code sequence, the total number of comparisons being equal to the total number of chips per data bit.
Following the output of the data correlator of figure 4, is a ma~ority vote logic (not shown) in ord~r to determine whether the received data bit i8 a 1 or ~ O. Under ideal condition~, all of the output chip co~parisons of over one data bit interval fro~ exclusive OR gate 106 will be of the ~ame polarity. In the presence of noise, some of t~em will be in error. However, by a ~ajority vote of the output chip~ at terminal 118, improv~d com~unication~ reliability i~ achieved. In the present example, it i~ noted that the number of chips per data bit i~ always 16, even for dif~erent spreading code sequence lengt~, which simplifies system design and a~sure~ rel~tively uniform system performance parameter regardless of th~ chosen spreading code sequence length.
If the spreading cod~ sequence used to enccde the received spread spectru~ ~ignal on terminal 100 is of a different length than ~he length selected by shift register 104 and multlplexer 108, then th~ receiver data output at terminal -17- DOCRET NO. 1016 ., .,, ~ --: - ,.
... ~, ~ ~ - . . , . - - .
.
.
~ ', . ." ~'', ~' ' -` 2r)V755~ `
118 will resemble an uncorrleated noise like signal.
Therefore, the correlator of figure 4 is responsive primarily to the length of the received spreading code sequence. Signals encoded with a spreading code sequence of a different length, relative to the selectable delay provided by shift register 104 and multiplexer 108,will be ignored.
Although it is only nece~sary that the plurality of spr~ading code sequences used in the cod~ divi~ion multiplex 8y8tem of the present invention differ only in th~ lQngth of the respective ~preading codQ 8equence8, it i~ preferabl~ to u~e ~preading code sequences ha~iDg low crosQ correlation properti~s, as well as different lengths, in order to improve system channel discrimination between the different length spreading code sequence~. Al~o, it is understood that the ~hift reqisters 70, 74, and 10~ used in the described emb2diment may be replaced with any other delay element providing a selectable time delay.
Thu~, a ~imple econouic~l data corr~lator and d~ta encoder u~ing sele~tablQ leng~h spreading code seguence~ for code division ~ultiplexing ha~ been de~cribed for u~e and con~unction with a spread spectru~ communication system.
-18- DOCgET NO. 1016 ~ ~ .. _ _ _ . . , , . _ _ _ . .. _ , _ . .. , .. . . . _ _ _ _ _ _ _ .. . ..... . .... . ...... . . _ . _ -, . ....
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Claims (16)
1. A method for communicating an input data signal between a transmitter and a receiver in a spread spectrum code division multiplex system, said method comprising the steps of:
selecting a transmitter spread spectrum spreading code sequence of a given length at said transmitter;
generating said transmitter spread spectrum spreading code sequence of said selected given length;
differentially encoding said spread spectrum spreading code sequence in accordance with said input data signal;
transmitting said differentially encoded spread spectrum spreading code sequence as a spread spectrum signal; and at said receiver, receiving said differentially encoded spread spectrum spreading code sequence;
selecting a given length of a receiver spread spectrum spreading code sequence;
differentially correlating said received spread spectrum signal with said selected given length of said receiver spread spectrum spreading code sequence to recover said input data signal.
selecting a transmitter spread spectrum spreading code sequence of a given length at said transmitter;
generating said transmitter spread spectrum spreading code sequence of said selected given length;
differentially encoding said spread spectrum spreading code sequence in accordance with said input data signal;
transmitting said differentially encoded spread spectrum spreading code sequence as a spread spectrum signal; and at said receiver, receiving said differentially encoded spread spectrum spreading code sequence;
selecting a given length of a receiver spread spectrum spreading code sequence;
differentially correlating said received spread spectrum signal with said selected given length of said receiver spread spectrum spreading code sequence to recover said input data signal.
2, A method for encoding an input data signal in a code division multiplex spread spectrum system, said method comprising the steps of:
selecting one of a plurality of spread spectrum spreading code sequences, each of said plurality of spread spectrum spreading code sequences having a distinct unique length;
generating said selected spread spectrum spreading code sequence: and combining said generated spread spectrum spreading code sequence with said input data signal to form said spread spectrum signal.
selecting one of a plurality of spread spectrum spreading code sequences, each of said plurality of spread spectrum spreading code sequences having a distinct unique length;
generating said selected spread spectrum spreading code sequence: and combining said generated spread spectrum spreading code sequence with said input data signal to form said spread spectrum signal.
3. A method in accordance with claim 2 wherein said step of combining said generated spread spectrum spreading code sequence with said input data signal comprises differentially encoding said selected spread spectrum sp ?ding code sequence in accordance with said input data signal.
4. A method in accordance with claim 3 wherein said step of differentially encoding said selected spread spectrum spreading code sequence in accordance with said input data signal further comprises the steps of:
inverting the polarity of said generated spread spectrum spreading code sequence, relative to the polarity of said spread spectrum spreading code sequence a fixed time delay previously, if said present input data signal is a first logic level; and not inverting the polarity of said generated spread spectrum spreading code sequence, relative to the polarity of said generated spread spectrum spreading code sequence said fixed time delay previously, if said present input data signal is a second logic level;
wherein in said fixed time delay is substantially equal to the length of said selected spread spectrum spreading code sequence.
inverting the polarity of said generated spread spectrum spreading code sequence, relative to the polarity of said spread spectrum spreading code sequence a fixed time delay previously, if said present input data signal is a first logic level; and not inverting the polarity of said generated spread spectrum spreading code sequence, relative to the polarity of said generated spread spectrum spreading code sequence said fixed time delay previously, if said present input data signal is a second logic level;
wherein in said fixed time delay is substantially equal to the length of said selected spread spectrum spreading code sequence.
5. A method in accordance with claim 4 wherein in said method further comprises generating a present inversion control signal for controlling the inversion of said chip of said generated spread spectrum spreading code sequence, said method comprising the steps of:
storing at least some portion of the previous inversion control signal in a delay memory;
selecting the delay provided by said delay memory to be substantially equal to the length of said selected spread spectrum spreading code sequence;
calculating the exclusive OR of said present input data signal and said previous inversion control signal stored in said delay memory to form the present inversion control signal.
storing at least some portion of the previous inversion control signal in a delay memory;
selecting the delay provided by said delay memory to be substantially equal to the length of said selected spread spectrum spreading code sequence;
calculating the exclusive OR of said present input data signal and said previous inversion control signal stored in said delay memory to form the present inversion control signal.
6. In a code division multiplex spread spectrum communication system including a spread spectrum signal having a selected spread spectrum spreading code sequence differentially encoded in accordance with an input data signal, a method for correlating said data signal on said spread spectrum signal comprising:
selecting a time delay substantially equal to the length of said selected spread spectrum spreading code sequence;
determining whether the presently received chip of said spread spectrum signal and a previously received chip of said spread spectrum signal, said selected time delay previously, are substantially equal;
providing a first output signal indication when said chip of said presently received spread spectrum signal and said chip of said previously received spread spectrum signal are substantially equal: and providing a second output signal indication when said presently received chip of said spread spectrum signal and said previously received chip of said spread spectrum signal are substantially not equal.
selecting a time delay substantially equal to the length of said selected spread spectrum spreading code sequence;
determining whether the presently received chip of said spread spectrum signal and a previously received chip of said spread spectrum signal, said selected time delay previously, are substantially equal;
providing a first output signal indication when said chip of said presently received spread spectrum signal and said chip of said previously received spread spectrum signal are substantially equal: and providing a second output signal indication when said presently received chip of said spread spectrum signal and said previously received chip of said spread spectrum signal are substantially not equal.
7. A method for correlating a spread spectrum signal in accordance with claim 6 wherein said step of determining whether said chip of said presently received spread spectrum signal and said chip of said previously received spread spectrum signal, said selected time delay previously are substantially equal further comprises:
storing at least one chip of the previously received spread spectrum signal in a delay memory;
selecting the delay provided by said delay memory to be substantially equal to the length of said selected spread spectrum spreading code sequence; and calculating the exclusive OR of said chip of said presently received spread spectrum signal, and said stored previous chip of said previously received spread spectrum signal.
storing at least one chip of the previously received spread spectrum signal in a delay memory;
selecting the delay provided by said delay memory to be substantially equal to the length of said selected spread spectrum spreading code sequence; and calculating the exclusive OR of said chip of said presently received spread spectrum signal, and said stored previous chip of said previously received spread spectrum signal.
8. A code division multiplex spread spectrum communication system for communicating an input data signal between a transmitter and a receiver, said system comprising:
means for selecting a transmitter spread spectrum spreading code sequence of a given length;
means for generating said transmitter spread spectrum spreading code sequence of said given length;
means for differentially encoding said spread spectrum spreading code sequence in accordance with said input data signal;
means for transmitting said differentially encoded spread spectrum spreading code sequence as a spread spectrum signal;
means for receiving spread spectrum signal including said differentially encoded spread spectrum spreading code sequence;
means, at said receiver, for selecting a given length of a receiver spread spectrum spreading code sequence;
means for differentially correlating said received spread spectrum signal with said selected given length of said receiver spread spectrum spreading code sequence to recover said input data signal.
means for selecting a transmitter spread spectrum spreading code sequence of a given length;
means for generating said transmitter spread spectrum spreading code sequence of said given length;
means for differentially encoding said spread spectrum spreading code sequence in accordance with said input data signal;
means for transmitting said differentially encoded spread spectrum spreading code sequence as a spread spectrum signal;
means for receiving spread spectrum signal including said differentially encoded spread spectrum spreading code sequence;
means, at said receiver, for selecting a given length of a receiver spread spectrum spreading code sequence;
means for differentially correlating said received spread spectrum signal with said selected given length of said receiver spread spectrum spreading code sequence to recover said input data signal.
9. A differential spread spectrum data encoder for use in a code division multiplex spread spectrum system having a plurality of selectable length spread spectrum spreading code sequences, said encoder comprising:
an input terminal for receiving a input data signal;
an output terminal;
means for selecting a spread spectrum spreading code sequence of a given length from said plurality of spread spectrum spreading code sequences;
means for generating said selected spread spectrum spreading code sequence;
differential encoding means responsive to said spectrum spreading code generating means, and a id input data signal at said input terminal, for providing a spread spectrum signal at said output terminal;
said differential encoding means including means for inverting the polarity of said selected spread spectrum spreading code sequence, relative to the polarity of said spread spectrum spreading code sequence a fixed time delay previously at said output terminal, if said present input data signal is a first logic level; and said differential encoding means including means for not inverting the polarity of said selected spread spectrum spreading code sequence, relative to the polarity of said selected spread spectrum spreading code sequence said fixed time delay previously at said output terminal, if said present input data signal is a second logic level.
an input terminal for receiving a input data signal;
an output terminal;
means for selecting a spread spectrum spreading code sequence of a given length from said plurality of spread spectrum spreading code sequences;
means for generating said selected spread spectrum spreading code sequence;
differential encoding means responsive to said spectrum spreading code generating means, and a id input data signal at said input terminal, for providing a spread spectrum signal at said output terminal;
said differential encoding means including means for inverting the polarity of said selected spread spectrum spreading code sequence, relative to the polarity of said spread spectrum spreading code sequence a fixed time delay previously at said output terminal, if said present input data signal is a first logic level; and said differential encoding means including means for not inverting the polarity of said selected spread spectrum spreading code sequence, relative to the polarity of said selected spread spectrum spreading code sequence said fixed time delay previously at said output terminal, if said present input data signal is a second logic level.
10. A differential spread spectrum data encoder in accordance with claim 9, wherein said means for generating said selected spread spectrum spreading code sequence comprises:
a delay memory means having a selectable delay length, said delay memory means having respective input and output terminals; and means coupling the output terminal of said delay memory means to the input terminal of said delay memory means.
a delay memory means having a selectable delay length, said delay memory means having respective input and output terminals; and means coupling the output terminal of said delay memory means to the input terminal of said delay memory means.
11. A differential spread spectrum data encoder in accordance with claim 10, wherein said means for selecting a spread spectrum spreading code sequence of a given length comprises means for loading said delay memory means with said selected spread spectrum spreading code sequence.
12. A differential spread spectrum data encoder for use in a code division multiplex spread spectrum system having a plurality of selectable length spread spectrum spreading code sequences, said encoder comprising:
an input terminal for receiving a input data signal;
an output terminal;
a first exclusive OR gate having first and second input terminals and an output terminal, said first input terminal of said first exclusive OR gate being coupled to said input terminal;
selectable delay memory means having an input and an output terminal, said output terminal of said selectable delay memory means being connected to said second input terminal of said first exclusive OR gate, said input terminal of said selectable delay memory means being connected to said output terminal of said first exclusive OR gate;
a second exclusive OR gate having respective first and second input terminals and a respective output terminal;
means coupling said first input terminal of said second exclusive OR gate to the output terminal of said first exclusive OR gate;
means for selecting a spread spectrum spreading code sequence of a given length from said plurality of spread spectrum spreading code sequences;
means for generating said selected spread spectrum spreading code sequence;
means coupling said second input terminal of said second exclusive OR gate to the output of said selected spread spectrum spreading code sequence generater means;
and means coupling said output terminal of said second exclusive OR gate to said output terminal.
an input terminal for receiving a input data signal;
an output terminal;
a first exclusive OR gate having first and second input terminals and an output terminal, said first input terminal of said first exclusive OR gate being coupled to said input terminal;
selectable delay memory means having an input and an output terminal, said output terminal of said selectable delay memory means being connected to said second input terminal of said first exclusive OR gate, said input terminal of said selectable delay memory means being connected to said output terminal of said first exclusive OR gate;
a second exclusive OR gate having respective first and second input terminals and a respective output terminal;
means coupling said first input terminal of said second exclusive OR gate to the output terminal of said first exclusive OR gate;
means for selecting a spread spectrum spreading code sequence of a given length from said plurality of spread spectrum spreading code sequences;
means for generating said selected spread spectrum spreading code sequence;
means coupling said second input terminal of said second exclusive OR gate to the output of said selected spread spectrum spreading code sequence generater means;
and means coupling said output terminal of said second exclusive OR gate to said output terminal.
13. A differential spread spectrum data encoder in accordance with claim 12, wherein said selectable delay memory means comprises:
a shift register having an input terminal and a plurality of output terminal taps; and a plural input to single output multiplexer, wherein said plural output taps of said shift register are connected to respective ones of said plural input to said multiplexer.
a shift register having an input terminal and a plurality of output terminal taps; and a plural input to single output multiplexer, wherein said plural output taps of said shift register are connected to respective ones of said plural input to said multiplexer.
14. In a code division multiplex spread spectrum communication system including a spread spectrum signal having a selectable length spread spectrum spreading code sequence differentially encoded in accordance with an input data signal, a data correlator comprising:
an input terminal for receiving said sprecturm signal;
an output terminal;
a selectable time delay means connected to said input terminal;
differential decoding means, coupled to said input terminal for determining whether the presently received chip of the presently spread spectrum spreading code sequence at said input terminal and a previously received chip of a previously received spread spectrum spreading code sequence said selectable time delay previously, are substantially equal;
said differential decoding means further providing a first logic level output at said output terminal when said present chip of said presently received spread spectrum spreading code sequence and said previous chip of said previously received spread spectrum spreading code sequence ? ?d selectable time delay previously, are substantially equal; and said differential decoding means further providing a second logic level output at said output terminal when said present chip of said presently received spread spectrum spreading code sequence and said previous chip of said previously received spread spectcrum spreading code sequence said selectable time delay previously are substantially not equal.
an input terminal for receiving said sprecturm signal;
an output terminal;
a selectable time delay means connected to said input terminal;
differential decoding means, coupled to said input terminal for determining whether the presently received chip of the presently spread spectrum spreading code sequence at said input terminal and a previously received chip of a previously received spread spectrum spreading code sequence said selectable time delay previously, are substantially equal;
said differential decoding means further providing a first logic level output at said output terminal when said present chip of said presently received spread spectrum spreading code sequence and said previous chip of said previously received spread spectrum spreading code sequence ? ?d selectable time delay previously, are substantially equal; and said differential decoding means further providing a second logic level output at said output terminal when said present chip of said presently received spread spectrum spreading code sequence and said previous chip of said previously received spread spectcrum spreading code sequence said selectable time delay previously are substantially not equal.
15. In a code division multiplex spread spectrum communication system including a spread spectrum signal having a selectable spread spectrum spreading code sequence differentially encoded in accordance with an input data singal, a data correlator comprising:
an input terminal for receiving said spread spectrum signal;
an exclusive OR gate having first and second input terminals and an output terminal, said input terminal for receiving said spread spectrum signal being coupled to said first input terminal of said exclusive OR gate;
selectable delay memory means having input and output terminals, said input terminal, of said selectable delay memory means being coupled to said input terminal for receiving said spectrum signal, said output terminal of said selectable delay memory means being coupled to the second input terminal of said exclusive OR gate; and an output terminal coupled to said output terminal of said exclusive OR gate.
an input terminal for receiving said spread spectrum signal;
an exclusive OR gate having first and second input terminals and an output terminal, said input terminal for receiving said spread spectrum signal being coupled to said first input terminal of said exclusive OR gate;
selectable delay memory means having input and output terminals, said input terminal, of said selectable delay memory means being coupled to said input terminal for receiving said spectrum signal, said output terminal of said selectable delay memory means being coupled to the second input terminal of said exclusive OR gate; and an output terminal coupled to said output terminal of said exclusive OR gate.
16. A data correlator in accordance with claim 15, wherein said selectable delay memory means comprises:
a shift register having an input terminal, and plurality of output terminal taps; and a plural input to single output multiplexer, wherein;
said plurality of output taps of said shift register are connected to respective ones of said plurality of input terminals of said multiplexer.
a shift register having an input terminal, and plurality of output terminal taps; and a plural input to single output multiplexer, wherein;
said plurality of output taps of said shift register are connected to respective ones of said plurality of input terminals of said multiplexer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/297,412 | 1989-01-13 | ||
| US07/297,412 US4930140A (en) | 1989-01-13 | 1989-01-13 | Code division multiplex system using selectable length spreading code sequences |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2007554A1 true CA2007554A1 (en) | 1990-07-13 |
Family
ID=23146212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002007554A Abandoned CA2007554A1 (en) | 1989-01-13 | 1990-01-11 | Code division multiplex system using selectable length spreading code sequence |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4930140A (en) |
| EP (1) | EP0378417A3 (en) |
| JP (1) | JPH02290344A (en) |
| CA (1) | CA2007554A1 (en) |
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-
1989
- 1989-01-13 US US07/297,412 patent/US4930140A/en not_active Expired - Fee Related
-
1990
- 1990-01-11 EP EP19900300332 patent/EP0378417A3/en not_active Withdrawn
- 1990-01-11 CA CA002007554A patent/CA2007554A1/en not_active Abandoned
- 1990-01-12 JP JP2006079A patent/JPH02290344A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02290344A (en) | 1990-11-30 |
| EP0378417A3 (en) | 1992-08-05 |
| US4930140A (en) | 1990-05-29 |
| EP0378417A2 (en) | 1990-07-18 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued | ||
| FZDE | Discontinued |
Effective date: 19920711 |