CA1323443C - Fault tolerant digital data processor with improved bus protocol - Google Patents

Abstract

ABSTRACT

A fault-tolerant digital data processor includes a peripheral device controller for communicating with one or more peripheral devices over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing information. Each peripheral device includes a device interface for transferring information signals between the associated peripheral device and the peripheral bus. The peripheral device controller includes a strobe element connected with the first and second input/output buses for transmitting thereon duplicative, synchronous and simultaneous strobe signals. These strobe signals define successive timing intervals for information transfers along the peripheral bus. Information transfers are normally effected by the transmission of duplicate information signals synchronously and simultaneously on the first and second input/output buses. A transfer cycle element includes a scanner cycle element to determine an operational state of at least one of the peripheral devices connected to the peripheral bus; a command cycle element for executing a command cycle for controlling operation of an attached peripheral device; a read cycle element for effecting the transfer of data signals from the peripheral device to the input/output controller; and a write cycle element for transferring data signals from the input/output controller an attached peripheral device.

Description

The invention relates to fault tolerant digital data processing and, particularly, to 5 apparatus and methods for providing fault tolerant communications with peripheral devices.
Faults in diqital computer systems are inevitable and are due, at least in part, to the complexity of the circuits, the associated 10 electromechanical devices, and the process control software. To permit system operation even after the occurrence of a fault, ~he art has developed a number of fault-tolerant designs. Among these is Rennels, ~Architecture for Fault-Tolerant Spacecraft 15 Computers,~ Proceedings of the I.E.E.E., Vol. 66, No.
10, pp. 1255-12~8 (1975), disclosing a computer system having independent self-checking computer modules (SCCM~s). In the event of failure of a module, the SCCM is taken off-line.
An improved fault-tolerant digital data processing system is currently available from the assignee hereof, Stratus Computer Company, of Marlboro, Massachusetts. ~his system employs redundant functional unit pairs, e.g., duplicative 25 central processing units, duplicative memory units, and duplicative peripheral control units, interconnected for information transfer by a common system bus.
The aforementioned system bus includes two 30 duplicative buses, the A Bus and the B Bus, as well as a control bus, the X Bus. During normal operation, signàls transferred along the A Bus are duplicated through simultaneous transmission along the B Bus. Signals transferred along the X Bus, a~

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, 1 323~43 including timing, status, diagnostics and fault-responsive signals, and are not duplicated.
~ ithin the Stratus System, control of and communications with peripheral devices are effected 5 by peripheral control units. One such unit, the communication control unit, routes control and data signals to attached peripheral devices by way of a communication buso With this backqround, an object of this 10 invention is to provide an improved digital data processing system. More particularly, an object of this invention is to provide a system for improved fault-tolerant communication with, and control of, peripheral devices.
lS A further object of this invention is to provide an improved fault-tolerant bus structure for use in digital data processing apparatus and, particularly, for use in communications with data processor peripheral units.
Yet another object of this invention is to provide an input/output controller for controlling and communicating with plural peripheral devices over a common peripheral bus structure.
Other objects of the invention are evident 25 in the description which follows.

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SUMMARY OF THE INVENTION

The aforementioned objects are attained by the invention which provides, in one aspect, an 5 improved fault-tolerant digital data processing system having a first input/output controller which communicates with at least one peripheral device over a peripheral device bus. The peripheral bus means includes first and second input~output buses, each 10 includinq means for carrying data, address, control, and timing signals.
The input/output contrôller includes an element for applying duplicate information signals synchronously and simultaneously to the first and 15 second input/output buses for transfer to the peripheral device. That is, upon applying information signals to the first input/output bus, the inputfoutput controller simultaneously applies those same siqnals to the second input/output bus.
2Q In a further aspect, the invention provides a fault-tolerant diqital data processing system of the type described above in which the input~output controller includes a bus interface element for receiving, in the absence of fault, duplicative ~5 information signal synchronousIy and simultaneously from the first and second input/output buses.
Still further, the invention provides a digital data processor of the type describe above in which the input~output controller includes clocking 30 elements for generating and transferring on the first and second input/output buses strobe signals~
indicati~e of the timing of associated inormat;on transfers along those buses.

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The aforementioned input/output controller can also include a scanner element for polling the peripheral devices which are connected along the peripheral device bus. By this polling, the scanner 5 can determine the current operational status of each peripheral device. Using this scanning element, the input/output controller can determine, for example, whether a peripheral is active and awaiting instruction, whether it requires interrupt 10 processing, or whether it has become unexpectedly inactive.
According to another aspect of the invention, a digital data processor having a first input/output controller communicates with one or more 15 peripheral devices over a peripheral device bus having first and second input/output buses for carrying, respectively, first and second input signals. In the absence of fault, these first and second signals are identical and are transmitted 20 synchronously and simultaneously along those buses.
The aforementioned input/output controller can include first and second processing sections, each for processing signals recei~ed on the peripheral device bus. During the course of normal 25 operation, the first and second processing sections receive identical input signals from the peripheral bus and produce identical output signals.
Further, a first bus interface element can be coupled with the processing sections and with said 30 peripher~l bus for receiving the first and second input signals and for applying at least one of those ~nput signals identically, i.e., synchronously and simultaneously, to ssid first and second processing sections.

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1 3234D,3 A digital data processor of the type described above can also include a second peripheral controller which is coupled with the peripheral device bus for receiving the first and second input 5 signals identically with the first peripheral controller. In this aspect, a second device interface element serves to apply at least one of those input signals to said second input/output controller.
In order to coordinate operations of the first and second processing sections, the data processor can include a flash circuitry element that is coupled to the first and second bus interface.
This circuitry is responsive to operational states of 15 the bus interface elements for generating a signal indicative of the synchronous receipt of identical copies at least one of the first and second input signals by each of said first and second bus interface elements.
Thus, the flash circuitry provides a mechanism by which the digital data processor can insure that the first and second bus interface sections are simultaneously applying duplicative and synchronous information signals to the first and 25 second processing sections of the ~irst peripheral controller, as well as to the second peripheral controller.
In still another aspect, a digital data processor as described above can utilize bus 30 interface elements for applying duplicative output signals synchronously and simultaneously to the first and second input~output buses. Within such a processor, flash circuitry can be advantageously employed to monitor those transmissions.

, , ' - 6 - 1323~43 According to this asp~ct of tha invention, the flash circuitry can generate a timing signal, which itself is transmitted along the first and second input~output buses, indicative of the timing 5 of information transfer cycles along the bus.
Consequently, for e~ample, a peripheral device at~ached to the bus can employ an interface for inputting transferred signals only at the time of receipt of the transmitted strobe signal. Through 10 this mechanism, the peripheral avoids the processing of non-duplicative or asynchronous information signals.
The flash circuitry of a digital data processor as described above can include, further, 15 strobe delay element which responds to differing operational states of the first and second bus interface elements for delaying generation of the aforementioned STROBE signal. This delay element can be employed to facilitate continuous operation 20 notwithstanding a slight delay in the receipt of either of the first and second information signals along the peripheral bus structure.
The flash circuitry can also employ an element for periodically and repeatedly comparing the 25 operational states of the first and second bus interface elements in order to detect the concurrence of the first and second information signals. In the event those signals do not agree after a specified time period, the processing sections can initiate an 30 error detection se~uence to determine the source of ault.
Another aspect of the invention provides a fault-tolerant digital data processing system having a first input/output controller which communicates B`

7 ~ 323443 with at least one peripheral device over a peripheral device bus, which ;ncludes first and second input/output buses~ As above, each of these buses can carry data, address, control, and timing signals 5 from the input/output controller to the peripheral device.
According to this aspect of the invention, a device interface is coupled to said irst and second input/output buses means and to an associated 10 peripheral device for transferring information between said the bus~s and the associated peripheral device. In normal operation, the de~ice interface applies duplicate information signals synchronously and simultaneously to the input/output buses for 15 transfer to said input~output controller.
In a related aspect of the invention~ the device interface includes a bus interface section for receiving, in the absence of fault, duplicative inormation signal synchronously and simultaneously 20 from the first and second input/output buses.
The interface can include a fault detection element that is coupled to said bus interface for detecting faulty information transmission and for responding thereto to generate a fault signal.
25 According to this aspect of the invention, the device interface can respond to a first selected type of transmission error, e.g., a single-bit error, occurring on one of the buses for accepting data only from the other bus. Similarly, the device interface 30 can respond to a second selected error type, e.g., a multi-bit error, occurring on either bus for initiating a diagnostic testing seguence.
The a~orementioned testing sequence can include the timed generation of various diagnostic B

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- 8 - ~ 3~4 43 testing signals, which are intended to facilitate the identification of the source of error. By way of example, subsequent to the detection of a multi-bit error, a transmitter portion of the device interface 5 can apply nassert~ signals ~ e., all one's or zero~s -- to the peripheral bus data and function code conductors for a specified time interval.
Concurrently, a receiver portion of the interface can monitor the bus to determine whether all the incoming 10 signals retain their asserted values.
In another aspect, the invention is directed to a protocol for communications over the peripheral device bus of a digital data processor. The apparatus includes a peripheral device controller for 15 communicating with one or more peripheral devices over a peripheral device bus which includes first and second input/output buses, each carryin~ data, address, control, and timing information. Each peripheral device can include a device interface 20 element for transferring information signals between the associated peripheral device and the peripheral bus.
According to the aforementioned aspect of the invention, the peripheral device controller 25 includes a strobe element connected with the first and second input/output buses }or transmitting thereon duplicative, synchronous and simultaneous strobe signals. These strobe signals define the successive timing intervals for information transfers 30 along the peripheral buses.
Further~ the peripheral device controller can include an element for executing an information transfer cycle which normally, i.e., in the absence of fault, involves the transmission of duplicate 9 1 ~23443 --information signals synchronously and simultaneously on said first and second inputfoutput buses. This transfer cycle element can include a scanner cycle element to determine an operational state of at least 5 one of the peripheral devices connected to said peripheral bus; a command cycle element for e~ecuting a command cycle for controlling operation of an attached peripheral device; a read cycle element for effecting the transfer of data signals from the 10 peripheral device to tha input/output controller; and a write cycle element for transferring data signals from the input/output controller an attached peripheral device.
Each of the aforementioned scanner cycle, 15 command cycle, read cycle, and write cycle elements can include, further, a cycle initiation section for initiating an information transfer cycle. In this aspect, the cycle initiation section includes an element for transmitting, during a first timing 20 interval, a SELECT signal indicative of cycle initiation. This SELECT signal is transferred duplicatively and synchronously on said first and second input/output buses. Concurrently, the cycle initiation section transmits on both buses a SLOT-ID
25 signal indicative of at leas~ one said peripheral device to be addressed during the information transfer cycle.
In an apparatus constructed according to this aspect o~ the invention, an addressed peripheral 30 device responds to a selected SLOT-ID signal to transmit a signal representative of the operational status of the peripheral device ~including its associated bus interface element). This status signal is transmitted in a second, subsequent timing .
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lo - 1 ~3443 interval, During that time interval, a receiving element within the cycle initiation section receives, in absence of error, the status signal on both the first and the second buses.
In related aspects, the invention is directed to a digital data processor of the type described above in which the command cycle element transmits duplicative command signals along the first and second buses in a third timing interval.
Alternatively, the processor can utilize either of the read or write cycle elementæ to transmit addressing information during the third, fourth, and fifth timing intervals. According to these aspects of the invention, a write cycle element 15 can thereafter transmit duplicative WRITE signals, along with duplicative write data, to an addressed peripheral device. Similarly, a read cycle element can transmit duplicative READ signals to invoke the duplication transfer of read data from the addressed 20 peripheral device.
In yet further aspects, the invention is directed to a peripheral device interface for responding to and participating in the bus protocol defined by the actions of the peripheral device 25 controller discussed above.
In still further aspects, the invention is directed to methods of operating a digital data processor in accord with the functioning of the apparatus described above.
These and other aspects of the invention are evident in the drawings and the detailed description below.

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BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of the invention may be obtained ~y reference to the drawings, in which:
S Figure 1 illus~rates a digital data processing system including a fault tolerant peripheral i~o system constructed according to a preferred practice of the invention;
Figure 2 illustrates an i/o con~roller 10 constructed in accord with a preferred practice of the invention;
Figure 3 illustrates a flash circuitry element constructed in accord with a preferred practice of the invention;
Figure 9 illustrates a preferred configuration of circuitry used to generate pre-strobe signals;
Figures 5A and 5B illustrate preferred circuitry for generating strobe signals;
Figures 6A and 6B illustrate prefsrred circuitry for generating bus obey signals;
Figure 7 illustrates one preferred circuitry for generating bus and time-out error signals:
Figure 8 illustrates a timing sequence for 25 preferred command and scanner cycles;
Figure 9 depicts a timing sequence for a preferred peripheral i/o write cycle;
Figure 10 depicts a timing sequence for a preferred peripheral i~o read cycle;
Figure 11 illustrates a timing sequence for two normal peripheral bus interface cycles;
Figure 12 illustrates a timing sequence for a peripheral bus interface cycle including two peripheral-bus/flash-bus comparisons; ~
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, ,, ~, . ., Figure 13 depicts a timing sequence for a preferred bus interface in which the i/o controller switches bus obey modes;
Figure 1~ illustrates a time-out sequence in 5 a preferred i/o controller constructed according to the invention;
Figure 15 depicts preferred circuitry for interfacing a peripheral device with the peripheral bus;
Figures 16 and 17 illustrate preferred bus interface circuitry for preferred gate arrays constructed in accord with the invention;
Figure 18 depicts preferred circuitry for generating strobe tracking s~qnals in a device 15 interface constructed according to the invention;
Figure 19 illustrates a preferred circuit for detecting faults in incoming data signals in a device interface constructed according to the invention:
Figure 20 illustrates a preferred circuit for comparing function code signals received by partnered gate arrays;
Figure 21 illustrates a preferred circuit for comparing data signals received by partnered gate 25 arrays;
Figure 22 illustrates preferred circuitry for checking data and function code signals received during the stages of the gate array error checking se~uence;
Figure 23 illustrates pre~erred circuitry or extracting peripheral device address inormation rom the peripheral bus data signals in a d~vice interface constructed according to the invention;

- 13 ~ 43 Figure 24 depicts preferred circuitry for generating signals for initiating an error seguence in a device interface constructed according to the invention;
Figure 25 illustrates preferred circuitry for extracting peripheral device adaptor command signals in a device interface constructed according to the invention;
Figure 26 illustrates preferred circuitry 10 for evaluating slot-id signals received from the i/o controller;
Figures 27 and 28 illustrate preferred circuitry for generating gate array state signals in a device interface constructed according to the 15 ;nvention;
Figure 2~ illustrates a preferred circuit for generating peripheral adaptor control signals in a device interface constructed according to the invention;
Figure 30 illustrates preferred circuitry for generating timing signals in a device interface constructed according to the invention;
Figure 31 illustrates a preferred circuit for generating adaptor address and data signals in a 25 device interface constructed according to the invention;
Figure 32 illustrates preferred circuitry for comparinq peripheral bus data signals generated by partnered qate arrays;
Figures 33 and 34 illustrate pre erred circuitry for generating interrupt-related and obey siqnals in a device interface constructed according to the invention; ~ -.

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- 14 - ~ 323443 Figure 35 illustrates preferred circuitry for generating start-up signals in a device interface constructed according to the invention Figure 36 illustrates a preferred circuit 5 for generating timer siqnals;
Figure 37 illustrates preferred circuitry for driving data and status signals onto the adaptor bus in a device interface constructed according to the invention; and Figure 38 illustrates preferred circuitry for generating early read and write signals.

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DESCRIPTION OF TH~ ILLUSTRATED EMBO~IMENT

Figure 1 depicts a digital data processing system 5 having a fault tolerant peripheral 5 input/output system constructed according to a preferred practice of the invention. The system 5 includes partnered central processing units 10, 12, partnered random access memory unites 14, 16, and partnered input~output controllers 18, 20, connected 10 for communications over system bus 22.
The i/o controllers 18, 20, which are coupled via flash bus 19, control the transfer of information and control signals between the system bacXplane, represented by system bus 22, and one or 15 more peripheral devices 24, 26, 28. These periphsral devices can include permanent storage media, e.g., disk and tape drives, communications controllers, network interfaces, and the like.
Peripheral device control and information 20 signal transfers occur over peripheral bus 30, which includes dual input/output buses 30A, 30B. Signals carried over these buses are routed to the peripheral devices 24, 26, 28 via gate arrays 32, 34, 36, 38, 40, 42 and adaptors 44, 46, 48. As shown in the 25 illustration, each peripheral device, e.g., device 24, is associated with a gate array pair, e.g., arrays 32, 34, and an adaptor, e.g., adaptor 44. The paired gate arrays, e.g., arrays 32, 34, are interconnected by a communications line, as 30 illustrated; e.g., see line 50. Moreover, each gate array is connected to its associated adaptor by an adaptor bus; see lines 56A, 56B, 58A, 58B, 60~, 6~B.
In turn, the adaptors 44, 46, 48 are coupled to ~heir ` ' `': ' . ` . `

respective associated peripheral devices 24, 26, 28 via local peripheral lines, as illustrated.
The peripheral bus 30 and, particularly, first and second i~o buses 30A, 308, are terminated 5 by terminators 62, 64.
The illustrated central processing units 10, 12, the random access memory units, and the system bus 22 are constructed according to the teachings of the aforementioned Canadian patents, to wit, Canada 10 Patent Nos. 1,178,374; 1,178,712; and 1,180l453; the aforementioned EPO patent application, to wit, EPO
Application No. 87 30 7179.9; and the aforementioned United States patents, to wit, United States Patent Nos. 4,953,215; 4,597,084; and 4,816,990.
According to a preferred practice, i/o buses 30A and 30B serve as redundant signal carriers. That is, the buses 30A, 30B carry duplicative information signals synchronously and simultaneously. This arrangement facilitates the detection of transmission 20 faults and permits the system to provide continuous, uninterrupted, processing and communication over the non-faulty bus.
According to a preferred practice, each bus 30A, 30b, includes data, control, parity, strobe, and 25 ~wait" signal conductors. Physically, the bus 30 can be implemented using two cables of 30 twisted pairs each. Such an implementation permits redundant 8-bit trans~ers at 4 megahertz using one cable or, alternatively, redundant 16-~it transfers at 4 30 megahert~ using both cables. Information trans~ers along bus 30 occur at a cycle rate of 250 nanoseconds, thus providing 8-bit transfers at four ~' megabytes per second and 16-bit transfers at eight megabytes per second.
The data, control, parity and wait signal lines of each i~o bus 30A, 30B are open collector 5 conductors and are driven, for example, by Motorola 26S10 transceivers. Two strobe lines are provided in each bus 30A, 30B. These paired lines serve as a differential signal carriers driven at the i/o controller 14, 20 and received at terminators 62, 64.
The gate array pairs, which may reside on a single board, are inserted in slots of an adaptor chassis ~not shown). Each slot is associated with a slot-id which defines the address of the associated peripheral device. In one embodiment, the chassis 15 maintains sixteen such addressable slots, with the far end terminators 62, 64 occupying the final two slots.
Figure 2 depicts an i/o controller 18 constructed in accord with a preferred practice of 20 the invention. The i/o controller 18 includes a peripheral bus interface section 18A, a first processing sections 18B, a second processing section 18C, and a system bus interface section 18D. The peripheral bus interface section 18A provides an 25 interface for receiving, transmittinq, and checking information transfers betwean the i/o controller 18 and devices attached to first and second i/o buses 30~, 30B. The system bus inter~ace section 18D
provides intarface for receiving, transmitting, and 30 checkinq in~ormation transers between the ifo controller 18 and those functional units (e.
central process~ng units 10, 12 an~ ran~om a~ce~
` ~ memory units 14, 16) attached along the system bus 22. The first and second processing sections 18B, * Trade Mark ;

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18C serve as redundant processing for signals received by the i/o c~ntroller from system and peripheral buses~
The peripheral bus eontrol section 18A is 5 composed of two dupli~ative interface sections: the ~drive~ section shown in the upper-left portion of Figure 2; and the Ncheck~ section shown in the lower-left portion of Figure 2. The drive section is primarily associated with both the first i/o bus 30A
10 (hereinafter referred to as the ~P bus~ and the first processing section 18B. That is, in the absence of fault, the drive section couples the P Bus ~OA with the first processing section 18B.
Similarly, the check section is primarily associated 15 with the second i/o bus 30B (hereinafter referred to as the "Q bus") and the second processing section 18C.
With particular reference to Figure 2, it is seen that the drive section of the peripheral bus interface 18A includes transceiver 66A, input data 20 multiplexor 68A, output data multiplexor 70A, paripheral bus interface control 72A, function code loop-back comparator 74A, data loop-back comparator 76A, and peripheral scanner 78A.
Transceiver 66A receives incoming data from 25 the P bus and makes this data available to the controller 18 on line 82A. The transceiver also monitors ~unction code signals on the P bus, via line 80A, for loopback comparison. Data generated for output by the controller 18 is passed to the ~0 transceiver via line 86A for transmission along the P
bus, while function codes generated for output by the controller 18 are passed to 66A via line 8~A for transmission along the P bus.

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Incoming drive section data signals are routed ~o multiplexor 68A, along with data signals received from the check 3ection transceiver 66B, as shown. Data selected by multiplexor 68A is routed 5 along line 90A to the ~irst processing section dat~
bus 92A.
In the absence o~ ~ault, as where duplicate data signals are received from P bus and Q bus synchronously and simultaneously, the multiplexor 68A
10 will selec~ P bus data signals, received along line 82A, for routing to first processing section data bus 92A. ~ot~ever, if the P bus data is detected as faulty, the multiplexor will select Q bus data signals, received along line 82s, for routing to the 15 first processing section data bus 92A.
Outgoing data signals generated by the scanner 78A, the first processing data bus 92A, and the first processing address bus 94A, are routed through output multiplexor 70A, which acts under the 20 control of controller 72A. Signals from the multiplexor 70A are transmitted to the P bus via line 86A, while simultaneously being routed to loop-back comparator 76A.
The bus interface control 72A generates a 25 function code signal along line 84A for output by the transceiver 66A. This function code signal is also routed to the check section for output along the Q
bus v~a line 84B and transceiver 66B. Function code s~gnals generated by control 72A are compared with 30 incoming function code signals, routed on line 80A, by loop-back comparator 74A.
As shown in Figure 2, the check side of ~he peripheral bus interface section l~A is o similar construction to the drive side of that section.

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Accordingly, operation of the check side of the peripheral bus ;nter~ace section 18A will be understood by reference to the discussion above.
With further reference to Figure 2, the 5 peripheral bus interface 18A is seen to include function code comparator 96. This comparator compares function code signals produced by both the drive side interface control 72A and the check side interface control 72B to produce a signal indicating 10 whether these ma~ch. The interface 18A further includes output data comparator 98 and input data comparator 100. The output data comparator 98 is arranged for comparing data signals selected by the drive side multiplexor 70A with those selected by 15 check side multiplexor 70B, while the input data comparator is arranged for comparing data selected by multiplexor 68A with that selected by check side multiplexor 68B.
In addition to the drive and check sides, 20 discussed above, the peripheral bus interface section 18A includes circuitry for transmitting local data and operational status signals to partner controller 20. This circuitry, termed ~flash~ circuitry, also compares data and status signals received from the 25 partner controller 20.
According to the illustrated embodiment, the flash circuitry includes transceiver 102, comparator 104, and strobe generator 106~ The transceiver 102 transmits data signals from the drive side of the 30 interface 18A to the flash bus 19. The transceiver also transmits operational status signals to the flash bus 19, as indicated by the signal line denoted MY STATE. Data receiYed from the flash bus is transferred from the transceiver 102 to the .~ .

comparator 104, as shown. There, the data is compared with check side data routed on line 90B.
State information received from the flash bus is passed along line 108 to strobe generator 106. If 5 this information compares favorably with local operational status signals, or if it is determined that strobe signals must otherwise be generated, e.g., during an error detection sequence, the strobe generator 106 generat~s strobe information for 10 routing to the P and Q buses via lines 110, 88A, and 888.
With further reference to Figure 2, the first processing section 18B includes processor ll~A, timer 116A, EEPROM 118A, map section 120A, and 15 control 1~2A. As indicated in the illustration, each of these elements is coupled to the data bus 92A for transmitting and receiving data signals, while the later four of the elements are coupled to the address bus 94A for receiving addressing signals. The 20 processor 112A is arranged for driving addressing signals onto the address bus 94A.
Interrupt signals ~enerated by the scanner 78A, the timer 116A, and the control 122A are transferred via line 124A to the processor.
25 Similarly, an error siqnal designated BERR generated by the map section is transferred via line 126A ~o the processor 112A.
The second processing section 18C is constructed similarly to the irst processing section 30 18B, as shown in the drawing.
The controller 18 also includes circuitry which is shared by the first and second processing sections 18B, 18C. To wit, a random access memory module 128 accepts addressing information from both -~
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1 3234~3 address buses 94A, 94B, as illustrated. The module is also connected for receiving and transmitting data to and from the local data buses 92A, 92B, as shown in the illustration. The illustration also depicts 5 the transfer of paging information to the memory module 128 from map sections 120A, 120B.
According to a preferred embodiment, data comparators 130, 132 monitor signals received from the local data buses 92A, 92B to identify 10 discrepancies between them. A further comparator 134 monitors signals received from the local address buses 94A, 94B, as well as si~nals generated by map sections 120A, 120B, to identify differences therebetween.
The system bus interface section 18D
includes address multiplexor 136, data multiplexor 138, as well as standard interface control 140. The address multiplexor 136 transfers output address signals from the map section 120A and the address bus 20 94~ to the system bus 22 and, more particularly, to the duplicative buses 22A and 22B. The data multiplexor 138 transfers output data signa~s from the local data bus 92A to the duplicative buses 22A
and 22B, as shown in the illustration. As further 25 depicted in Figure 2, address and control information received by the address and data multiplexors 136, 138 is routed to the standard interface control 190.
From there, this incoming lnformation may be route~
via line 142 to controls 122A and 122B. A preferred 30 construction of bus interface section 18D is provided in the aforementioned related patents and patent applications.

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- ' ` ' ` ' . ' '. , ' ' IfO Controller Peripheral Bus Interface According to one preferred practice, i~o controller 18 can be connected with the peripheral bus 30, via transceivers 66A, 66B, to send andfor 5 receive the signals identi~ied below. ~ereinafter, the i/o controller is referred to as the IOPn, while a gate array~adaptor combination, e.g., gate arrays 32, 34 and adaptor 44, is referred to as an ~interface~ or IOA~.
10 Signal Name Description Siqnal Direçtion Data 0 P Bus P Data Bit O IOP to/from IOA
Data 1 P Bus P Data Bit 1 IOP to/from IOA
Data 2 P Bus P ~ata Bit 2 IOP to/from IOA
15 Data 3 P Bus P Data Bit 3 IOP to~from IOA
Data 4 P Bus P Data Bit 4 IOP to/from IOA
Data 5 P Bus P Da~a Bit 5 IOP to/from IOA
Data 6 P Bus P Data Bit 6 IOP toffrom IOA
Data 7 P Bus P Data Bit 7 IOP to/from IOA
20 Data Parity P Bus P Data Parity IOP to/from IOA
Data 0 Q Bus Q Data Bit 0 IOP to/from IOA
Data 1 Q Bus Q Data Bit 1 IOP to~from IOA
Data 2 Q Bus Q Data Bit 2 IOP to/from IOA
25 Data 3 Q Bus Q Data Bit 3 IOP to~from IOA
Data 4 Q Bus Q Data Bit 4 IOP to/from IOA
Data 5 Q Bus Q Data Bit 5 IOP to/from IOA
~ata 6 Q Bus Q Data Bit 6 IOP to/from IOA
Data 7 Q Bus Q Data Bit 7 IOP to/from IOA
30 Data Parity Q 8us Q Data Parity IOP to/from IOA
Func 0 P Bus P Function Code IOP to IOA
Bit 0 Func 1 P Bus P Function Code .IOP to IOA
3S Bit 1 Func 2 P Bus P Function Code IOP to IOA
Bit 2 Func Parity P Bus P Function Code IOP to IO~
Parity Func 0 Q Bus Q Function Code IOP to I9A
Bit 0 Func 1 Q Bus Q Function Code IOP to IOA
Bit 1 ~;

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Siqnal Nam~ Descripti~n Sianal DirectiQn Func: 2 Q Bus Q Function Code IOP to IOA
Bit 2 5 Func Parity Q Bus A Function Code IOP to IOA
Parity Strobe P Bus P Strobe IOP to IOA
positive conductor of differential pair Strobe P~ Bus P Strobe IOP to IOA
negative conductor of differential pair Strobe Q Bus Q Strobe IOP to IOA
positive conductor of differential pair Strobe Q* Bus Q Strobe IOP to IOA
negative conductor of differential pair Wait P Bus P Wait IOh to IOP
Wait Q Bus Q Wait IOA to IOP
According to a preferred practice, i~o 3Q controller 18 transmits and receives on the flash bus 19 the signals listed below, wherein the first i~o controller, e.g., controller 18, is r~ferred to as "IOP lN, and the second i/o controller, e.g., controller 20~ is referred to as ~IOP 2n. An "~" in 35 the signal name indicates that the signal is inverted. The flash ~us 19 is a wire QR'ed open-collector. The controllers IOP 1 and IOP 2 concurrently present a signal level on the bus 19, with the ~low" level prevailing and being received by 40 both controllers.
Signal Name De~cri~tion Siqnal Direction FDATA 0* Flash Bus Data Bit 0 IOP 1 to/from ' . ~ , ' ` .

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~ 323443 Siqnal Name Description Siqnal Direc~iQn FDATA 1~ Flash Bus Data Bit 1 IOP 1 to/from 5 FDATA 2* Flash Bus Data Bit 2 IOP 1 to/from FDATA 3* Flash Bus Data Bit 3 IOP 1 to/from FDATA 4~ Flash Bus Data Bit 4 IOP 1 to/from IOP ~
FDA~A 5* Flash BUS Data Bit 5 IOP 1 to/from FDATA 6* Flash Bus Data Bit 6 IOP 1 to/from 15 FDATA 7* Flash Bus Data Bit 7 IOP 1 to/from WE STRB* IOP to issue STROBE IOP 1 to/from 20 WE HOLD STRB* IOP to hold STROBE IOP 1 to/from because of WAIT IOP 2 CF NEQ* Check side data does IOP 1 to/from not equal flash data IOP 2 CD NEQ~ Check side data does IOP 1 to/from 2~ not equal drive side IOP 2 data P NOK~ Failure detected in IOP 1 to~from Bus P IOP 2 Q NOK~ Failure detected in IOP 1 to/from Bus Q IOP 2 Memory Allocation The i/o controller 18 and its circuitry is 35 allocated in a virtual memory configuration as follows:
Address Ç~a~n~
000000x - BDFFFFx User mapped virtual memory 40 BE0000x - BEFFFFx PROM telements 118A, 118B), also residing at 000000x -00ffff~ when PROM is not high BF0000s - BF7FFFs Not used BF8000~ - BF8FFFs Sync paqe 45 BF9000~ - BF9FFFx P Bus DMA (direct memory access) select/P Bus command page '' ' ' '' ' ' "

, Address Cont~~
BFAOOOx - BFAFFF~ Supervisor control (incl., control registers for P bus, timer elements 116A, 116B), scanner (elements 78A, 78B, and scanner list) BFBOOO~ - BFBFFF~ Privileged control BFCOOOx - BFFFFF~ Map (elements 120A, 120B) 10 COOOOO~ - FFFFFF~ P Bus pro~rammed i/o space, providing a 4 MByte window into the selected adaptor Within the DMA select/interface command 15 page, address space is arranged as follows:
A~Q~ Access Content BF9002Xwrite word Select Adaptor for PIO
command Bits 15-08 Slot/subchannel 07 ~lu 06-00 Command number BFsoo4-006 write long Select peripheral adaptor for DMA write Bits 31-24 Slot/subchannel 21-16 Upper six adaptor address bits 15-00 Lower sixteen adaptor address bits 35 BF9008- write long Select peripheral adaptor BF9OOA for DMA read Bits 31-24 Slot/subchannel 23-22 n 21-16 Upper si~
~o adaptor address bits 15-00 Lower sixteen adaptor address bits BF9OOC write long Select Adaptor for DMA
Verify Bits 31-24 slot/subchannel B~
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, Addres~ Access Con~ent 21-16 up 6 peripheral adaptor address bits 15-00 lower 15 adaptor address bits 10 Su~ervisorY Control Pa~e Supervisory control page accesses are made at virtual page BFA000x. The timer, peripheràl bus and scanner control, including the scanner list, are addres~ed in this page. USER and CODE accesses to 15 this page cause the ~eneration of BERR~ along line 126A. The page also maintains selected interrupt, privilege, and scanner interrupt status information.
All control accesses to the supervisory control page, except for accesses to timer 116A
20 require no wait states. Unlatched control pulses are initiated by the rising edge of a first timing signal and terminated by the falling edqe of a subsequent timing signal. Control bits for the standard bus interface and P bus are synchronized to a 4 MHz clock 25 signal.
Within the supervisory control command page, i/o address space is allocated as follows:
~EÇQ~ Access ~Cont~nt 30 BFA000 Read Timer Data Word BFA002 Timer Status Word Bits 15-00 BFA000 Write Timer Data Word 35 BFA002 Timer Command/Data Pointer Words ` Bits 15-00 BFA400 Read Checksum Word Bits~15-00 .

- 28 - 13234~3 Address Ac~es~ Conten~
BFA400 Write PUBS~SCANNER/DEV CONTROL
WORD
Bit 15 ~1 to set/0 to clear) Bits 02-01-00 1 1 1 PBUS ~nable Bit (active hi) 1 1 0 Set PBUS-BERR
Enable Bit ~active hi~
1 0 1 Scanner on (active hi~
1 0 0 Run Scanner ~active hi~
0 1 1 Timer Interrupt Mask~Clear (masked off lo~
0 1 0 Level 1 Interrupt ~active hi) 0 0 1 Privileged Bit ~active low) 0 0 0 PBUS Lock ~active low) BFA800 Read Scanner Interrupt Status Word ~to be read only if a scanner interrupt is pending) Bits 15-00 Bit 15 Adaptor ~ e ~active hi) Bit 14 Adaptor Interrupt (active hi) Bit 13 Adaptor Obeying P
Bit 12 Adaptor Obeyinq Q
Bits 11-8 Adaptor Interrupt Code or Subchannel Bits 7-4 Slot number Bits 3-0 TBD tsubchannel) BFA801 write PTO Slot Select Address Byte Bits 7-4 Slot number :
Bits 3-0 TBD (subchannel) -. . . - :
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Address Access Content BFAC01- Read ~Odd Scanner Slot Select ~FADFF Addresses) Address Byte Bits 7-4 Slot number Bits 3-0 TBD (subchannel BFAC01- wri~e (Odd Scanner Slot Select BFADFF Addresses) Address Byte BitS 7-4 Slot nu~ber Bits 3-0 TBD ~subchannel) Privilege Control Page Privileqe control page accesses are made at 15 virtual address BFB000~. The controller 18 privileged-only status and control registers are stored in this virtual page. Additionally, the standard bus interface 122A control resides in this page. Accesses to the privilege control page require 20 no wait states.
Within the privileged control page, i/o ~address space is arranged as follows:
Address Access Content 25 BFB000 Read Board Status Word ~note:
if one, a mask bit allows the interrupt for the specified condition) Bit 15 BROKEN
Bit 14 BROKEN TWO
Bit 13 MEMORY BROKEN --Parity/Data Bit 12 MEMORY BROKEN --Compare Bit 11 TIMER INTERRUPT MASK
(enabled if 1) Bit 10 PK COMPARE ~Hi=OK) Bit 09 COM~5AND PENDING
Bit 08 STATUS CHANGE
Bit 07 Side C = 1, D = ~ROM
HI -- read only Bit 06 INTERRUPT PENDING
(~rom IOP on Str?ata-BUS) Bit 05 PARTNERED bit Bit 04 ZOUT ~T

B

_ 30 - ~3443 Addres~ Access Content Bit 03 LEVELl INT
Bit 02 PROM HI -- when this bit is cleared, P~O~
addresses start at 0 and RAM addresses below 8000 are not available.
When prom is h;gh, S;de D
is also high. When prom îs not high, Side is low.
Bit 01 INTERRUPT MASK for Bit 09 (CMD PENDING) being 1 (Level 4) Bit 00 INTERRUPT MASK for all ~onditions and levels tBitS 00-05 are 0 after a ~ESET . ) sF8000 Write Board Status Word Bit 15 (1 to set/0 to clear) Bits 02-01-00 1 1 1 P PBUS Enabled 251 1 0 Q PBUS Enabled 0 1 PARTNERED bi t 1 0 0 OUTPUT ~RANT bit 0 1 1 PBUS OB~Y FORCE
bit 300 1 0 PROM HI bit for ~CMD PENDING) Level 4 O O O INTERRUPT MASK
for all conditions and levels BFB401 Read Standard Interface Command Register Bytes BFBg05 Bits 07-00 for all 4S BFB400 write Board Control Word Bits 15--02-01-00 (only used by PROM code) :
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', Addres~ A~ces~ Content O 1 1 0 CLEAR BROKEN TWO, CLEAR MæMoRy~
PARITY ERROR, CLEAR MEMORY
COMPARE ERROR, CLEAR INTERRUPT
LEVELS 2-3, CLEAR
PK CO~PARE ERROR, CBEAR
WAIT-TIMEOUT
ERROR, CLEAR PBUS
OBEY ERROR

O 1) 1 1 SET INTERRUPT
REQUEST

PENDING

CHANGE
25 BFB801 Read Standard Interface Pointer Register Bytes BFB805 Bits 07-00 for all BFB801 Write Standard Interface VOS
Vector Byte BitS 07-00 VeCtor Number 35 BFBC00 Read Pbus Status Word Bit 15 VERIFY 9K
Bit 14 DMA WRITE
~it 13 DMA READ
Bit 12 SCANNER INTERRUPT
~active low) Bit 11 SCANNER SET TO RUN
(active low3 Bit 10 PBUS OBEY FORCED
Bit 9 P PBUS ENABLED Sync Bit 8 Q PBUS E~A~LED Sync Bit 7 PBUS WAIT-TIMEOUT
ERROR ~ activ~ low) Bit 6 PBUS OBEY ERROR
(active low) :

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B
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: ' , Address Acces~ Content B i t 5 PBUS SELECT ERROR
( act ive low) Bi t 4 PBUS SELECT BERR
ENABLED (active hi) Bit 3 PBUS ENABLED Sync Bit 2 PBUS LOCK (locked if low) Bit 1 OBEY P
Bit 0 OBEY Q
BFBC00 Write CHECKSUM TEST WORDfBYTE
Bits 15-8 Add byte (if asserte~) to checksum for test Bits 7-0 Add byte (if asserted) to checksum for test The MaP Element In a preferred embodiment, the map 120A
includes four pages of 24 bit map entries, each ~5 having sixteen physical address translation bits, one i~o bit, one interlock bit, three access control bits, one local/main memory bit, one DMA thread bit, and one spare bit. The translation address bits are aligned on even word boundaries, while the control 30 bits occupy a bytes aligned on odd word boundaries.
The access control bits are allocated to de~ine the following access types:
no access:
any access - write only memory:
any sccess - read data/execute:
any access - read data/write data;
privileged access - no access;
privileged access`- write only memoryî
privileged access - read datafexecute; and privileged access - read data/write data.
According to one preferred embodiment, the ollowing memory access control violations will cause assertion of BERR~ on line 126A~

B
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1) an unprivileged access to a privileged pa~e;
2) an execute access to a wr~te accessible page;
3) a write access to a non-write accessible page; and 4) a read access to a non-read accessible page.
Moreover, the following local virtual access violations can also cause assertion of BERR, as above:
1) a code access to the local virtual pages, except prom 118A;
2) an unprivileged write access to the privileged control page;
3) a user access to ths supervisor control page;
4) a write to prom 118A;
S) an overranye durinq local memory access;
6) a read to the sync selection page;
7) a peripheral bus time-out error occurring during a peripheral bus access;
8) a peripheral bus obey error occurring during a non-DMA peripheral bus access, except when bus obey is forced;
9) a peripheral bus obey error occurring during a DMA cycle; and 10) a CPU (112A) write during a DMA cycle.
In the illustrated embodiment, a peripheral bus select error will be generated under the ~ollowing circumstances:
1) a peripheral bus access to an empty or broken peripheral bus device adaptor slot in the adaptor chassis, except when peripheral bus select errors are disables;
2) a peripheral bus DMA with either addressing bit 1 or data bit 7 asserted;
3) a peripheral bus command with address bit 1 de-asserted;
4) a peripheral bus select when the peripheral bus is defined as locXed;

5) a peripheral bus access when the peripheral bus is turned o~f, .

, ~ 323443 Local Memory Acce~s The illustrated controller 18 utilizes a 12 MHz Motorola 68010 processor 112A which executes instructions out o~ local memory 128 with no wait 5 states, unless a memory re~resh is aemanded~
With regard to operation of the memory 128, a row strobe signal RRAS* is issued on every cycle of the local processor 112A. If the cycle is a local memory access, and (i) a refresh is not demanded, 10 and tii) a LOCAL VIRTUAL or an IACK cycle is not decoded, strobe signal RCAS* will be issued;
otherwise, RRAS* A~ORT will be issued, thereby terminatinq RRAS*.
Terminating RRAS* allows a free refresh to 15 occur, so long as a refresh is requested after the signal AS* is asserted during a CPU bus cycle having 3 or more wait states. It is necessary to be able to perform a refresh while AS* is asserted so that during synchronization of partnered ifo controllers 20 18, 20, memory refresh times are not violated while the local CPU 112A is waiting, with AS~ asserted, for the other board to catch up.
Most refresh cycles occur by demand, i.e., the refresh cycle begins before AS* is asserted, 25 regardless of the type of the next cycle. If the neYt cycle is a local memory access, the refresh cycle will add 3 wait states; otherwise, no wait states will be added.
A signal RAS PRECHARGE* is clocked by the 30 risiny edge of RRAS* to prevent any reassertion of RRAS*. ~ssertion of RAS PRECH~RGE* also prevents a reresh cycle from occurring before the RAM has had t~me to recover from a RAM access abort or a late ne~ation of AS*.

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~23~43 Addresses to the RAMs are selected by a signal SELCOL*, w~ich follows RR~S* by 15 nsec. Row addresses to the RAMs are the low order address bits of the CPU ll~A and do not have a map translation 5 delay. Some of the column addresses are part of the mapped address area and have map translation delay.
The first processing sec~ion 18~ employs a Motorola 74F521 to determine whether the local memory access being made is within the range of the local memory 10 space. If not, the signal OVERRANGE is asserted.
A refresh cycle occurs synchronously with the 12MHz clock signal. A refresh request is generated as a result of the falling edge of timer clock, which is synchronized to the rising edge of 15 the 12MHz CLK, every 15.25 microseconds.

Map Access Access to map unit 120 occurs with no wait states. The map 120A, when used for address 20 translation, is 4K long by 24 bits wide, including 16 physical address bits and eight control bits. Map entries reside on word or long word boundaries, with byte accesses being unallowable. Even addressed words store the 16 bits of translation information.
25 The upper eight bits of the odd addressed word are the control bits, including read access, write access, privileged access, local memory, interlock, i/o, dma, and spare ~it signals. The lower eight bits o the odd-address words are not use.
~0 The map 120A virtual page access are privileged only/data only access; an unprivileged or code access will cause 8ERRt to be asserted. These pages are also write protected from the unprivileged access.

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Timer The timer 116A, including its associated jiffy counters, is synchronized with the 12 MHz clock signal. The timer has a period of 15.25 microseconds 5 which is asserted for 1.3 microseconds and unasserted for 13.9 microseconds. Timer signals are re-synchronized to the 12 MHz CLK after the counters reach a selected value. A signal, TIMER STA~E*, is negated 1.3 microseconds before the rising edge of 10 the timer clock signal, while beinq asserted 1.3 microseconds after that rising edge to prevent accessing the TIMER too close to its clock edge. The timer 116A addresses are stored within the supervisory control virtual page as noted above. The 15 timer 116A may only be accessed at word boundaries.
Such accesses add from 1 to 31 wait states to the CPU
112A bus cycle depending on the state of a signal TIMER* STABLE when the access is made. For the timer 116A to interrupt the processor 112A, the interrupt 20 masX TIMER IMSK must be set to one. Upon servicing a TIMER INTERRUPT, TIMER IMSX must be set to zero to clear the condition~ and then set to one to re-enable interrupts from the TIMER.

25 Interrupt Acknowle~qe The processor 118A provides an interrupt acknowledge cycle, IACK, requiring no wait states.
On any interrupt acknowledge, the lower three address bits on local address buses 92A, 92B indicate which 30 level interrupt the process is servicing. These three bits are returned to the processor in an interrupt vector byte, with the high order bit of the byte as asserted. The interrupt levels are as follows~

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Interrupt Level Devicç

LEVEL 3 PBUS TIME OUT or OBEY E~ROR

S~anner The illustrated scanner 78A runs as a parallel processor to the main board CPU. If enabled and set to run, it will scan the adaptors in the 15 adaptor chassis in a software assignable order for interrup~s and lack o~ alive status. The scanner takes advantage of the select mechanism of the adaptors by using an aborted select to retrieve adaptor status. This allows a 750 nanosecond scan 20 cycle for each entry in the scan list.
A scanner table entry is one byte long, including four bits designating a peripheral slot number and four bits designating a subchannel number~
The software controlled scan list forces the 25 scanner 78A to check only those slots which are occupied. The scanner may be utilized to compensate for different interrupt service requirements of different adaptors by including selected adaptor slots more than once in the scan list. The scan list 30 consists of 256 entries. All en~ries must be contiguous, starting at the first entry. However, the entire scan list does not have to be filled. A
~return to zero" entry is employed by the scanner 78A
to scan the active terminators in the adaptor 35 chassis. An interrupt from such a scan to the terminator indicates a bulk power supply failure, fan .

failure, powe~ synchronization failure, or a terminator failure.
The scanner 78A, upon finding a slot with the interrupt bit set or the alive bit cleared, will 5 ~top at that entry and interrupt the~ processor 117A.
When reading back the scanner interrupt status word, the processor 112A reads the adaptor status in one byte and the contents of the scan list entry in the other. The scanner interrupt status is not read 10 unless there is an interrupt or the scanner is not set to run.
The scanner 78A runs when it is enabled and there are no processor 112A pending on the peripheral bus 30. The processor 112A cycles have priority;
15 accordingly, the scanner 79A will stop while during those cycles and restart only after the first idle cycle during which the processor 112A does not access the bus. The scanner 78A stops completely when an adaptor is selected for DMA and restarts when DMA
20 enable is cleared.

Fla~h Circuitry Figure 3 depicts a preferred construction ~or the flash circuitry of an i~o controller 18. The 25 circuitry includes AND gates 142A, 142B, 142C, 142D, NOR gates 144A, 144B, 144C, inverters 146A, 146B, NAND gates 148, NAND gate 150, OR gate 152, and bu~fer 154. The flash circuitry provides, as output from NAND gates 148, controller operational state 30 signals which are OR'ed cnto the open collector flash bus 19.
The AND gates 142A accepts the following input signals:

, , ,' ~ ': ~ '; ' , Siqnal Description PDATA PAR O~ D~ validity of data signal parity at transceiver 66A
PDATA EN* i/o controller enabled to drive data onto the peripheral bus 30 OBEY P i/o controller enabled to send~receive on the P bus WAIT IN P i~o controller receiving W~IT signal on the P bus 30A
FC LB OK P* function code loopback comparator 74~ output DATA LB OK P* data loopback comparator 76A output PDATA EN D i~o controller drive side 18B enabled to drive data onto peripheral bus 30 Logical AND's of the above signals are qenerated by AND gates 142A in the manner indicated in the illustration. Outputs of the array 19~a are passed to NOR gate 144a to produce a binary signal, 25 ~ P NOK~, representa~ive of the validity of information transfer signals received from the P bus 30A. In particular, MY P NOK* has an assertive state indicating that signals received from the P bus by the i/o controller, e.g., controller 18, contain 30 errors. While, MY P NOK* has a non-assertive state indicating that no obvious fauIt has occurred in the signals received from the P bus. The signal~MY P
NOK* is routed through inverter 146a.
In a similar manner, the AND gates 142b and 35 NOR gate 144b produce a binary signal, MY Q NOK~, representative of the validity of information transfer signals received from the ~ bus 30B. The signal MY Q NOK* is routed through inverter 146b.
The AND gates 142C, 142D and NOR GATE~144C
40 are arranged to generate an I WAIT* signal, hav~ing a~n :: :

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assert-ve stat~ indicating that the controller is to delay generation of the strobe signal.
The NAND gate 150 is arranged to generate a binary siqnal, PK ONLINE~, as a boolean NAND of the 5 followinq input signals:
Siqnal DescriptiQn BROKEN BUF~
PK COr~lARE
PBUS ENS D
The PK ONLINE* signal, which has an assertive ~tata indicating that the associated i/o controller is onl~ns, is negated by neqated-input OR
15 gate 152, as shown. The resulting signal PK ONLINE
is tied through resistor 156 to potential +VCC and, further, is coupled to an input of each of the NAND
qates in array 148. The output of gate 152 is also retained in buffer 154 to provide the buffered signal 2 0 BUE PK ONL INE.
With further reference to Figure 3, outputs of each of inverters 146a and 14~b, as well as each of the signals listed below, is provided as a second input to individual NAND gates in array 148.
Siqnal Description MY CD EQ* output of comparator 100 MY FLASH EQ~ output of comparator 104 STRB HOLD D drive side of i/o controller delaying strobe signal generation STRB HOLD C check side of ifo controller delaying strobe signal generation STROBE D drive side regenerate of strobe STROBE C check side regenerate o~
strobe :
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- 41 - 1323~43 The output of ~he NA~D qates of array 148 are passed to the open collector conductors of flash bus 19 as shown in the illustration.

5 StrQbe Signal GeneratiQn Figure 9 depicts one preferred configuration of circuitry used to generate pre-STROBE siqnals in i~o controller 18, 20. The illustrated circuitry includes counter 158, flip-flops 160, 162, 164, 166, 10 NAND gates 167, 168, 170, 172, OR gates 174, 176, 178, NOR gate 180, and buffers 182, 184.
The counter 158 is driven by a 1 MH~ clock signal provided in the drive side of the i/o controller. A clear input to the counter 158 is 15 provided by the output of NAND gate 167, having at its negated inputs, a WE HOLD STROBE* signals and a timing siqnal, designated T5 D~. The fourth output bit of the timer 158 is coupled to "D~ input of flip-flop 162, as shown.
The flip-flop 162 is arranged for generating a WAIT TO signal, reflecting that a time out is required in order to permit error checking. As shown in the illustrated e~bodiment a delay of eight microseconds, resulting from assertion by one or~more 25 peripherals of a WAIT signal on the peripheral bus, causes the aforementioned time out. The negated output of flip-flop 162 is routed to provide an input t~ OR gate 176.
A second input to OR gate 176 is provided by 30 the SET STROBE output of NAND gate 168. Inputs to gate 168 include PNOK*, QNOK, CDNEQ~, WE HOLD STRB*, PK OX, FD~TA CLK D (an output of the drive side flash data clock), F~ATA CLK C ~an output of the check side flash data clock), T0 D (tbe~drive side primary~

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timiny signal for the peripheral bus transfer cycle), T0 C (the corresponding si~nal generated on the check side), WAIT TO~, PBO error (indicating a bus obey error), and BUF PK ONLINE
The SET STRB* output of NAND gate 168 is also provided as the ~j~ input to flip-flop 166. A
clear input to that flip-flop is pro~ided as an output of the gates 170, 172, and 174, as shown in the illustration. The flip-flop 166 provides as 10 output the ERROR CLX and ER~OR CLK* signals, which provide timing signals for the error se~uenc~
initiated by the i~o processor during the time out.
As shown at the top of Figure 4, a FORCE
STRB* signal is generated by the combined actions of 15 flip-flop 160 and NOR gate 180. This FORCE STRB*
serves as a preset to flip-flop 164, which serves to generate a STROBE OUT signal at its ~Q'~ output. The clear input to that flip-flop is provided by a STROBE
CLR* signal. A 16 MHz clock signals generated by the 20 check side drives the flip-flop 164.
As further shown in the illustration, the STROBE OUT output of flip-flop lS4 is retained in buffers 182 and 184, providing STROBE D and STROBE C
signals, respectively.
Figure 5A depicts a preferred circuit for generating a STROBE P signal for transmission along P
bus 30A. The circuit includes a AND gate, having as its inputs the STROBE OUT signal (see Fi~. 4) and a BU~ PK ONLINE signal (see Fig. 33~ The output of the 30 AND gate 186 is output to the STROBE P pin of the bus ~OA via diode 188, resistors 190a, 190b, 190c, 190d, and transistor lg2, as shown.
Figure 5B depicts a preferred circuit for generating a STROBE P* siqnal for output along P bus R
,: ` . ` .

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30A. The circuit includes an AND gate array 194a, 194b, 194c, 194d~ and inverters 196a, 196b implemented in combination with resistor 198 as shown in the illustration.
Figure 6A depicts one preferred confiquration of circuitry utilized in i/o controller 18, 20 f~r generatin~ an OBEY P si~nal, conditioning the controller is to respond only to those peripheral bus signals received on the first i/o bus 30A. The 10 illustrated circuitry includes OR gate 200, NAND gate 202, and flip flop 204.
The OR ~ate 200 produces a TOGGLE P signal representative of a boolean logic OR of the P NOK*
siqnal and the ONE BUS* signal (indicating that the 15 i/o controller is currently conditioned to receive signals on only one of the i/o buses 30A, 30B). The TOGGLE P signal is routed to provide the ~j n and "k~
inputs to flip-flop 204.
The negated preset signal for flip-flop 2Q4 20 is provided by the FORCE P* signal output of NAND
gate 202. The FORCE P* signal results from the boolean NAND function of the PK FORCE D signal (indicating that the i/o controller is conditioned to respond on the drive side) and the P ENS D signal 2S (indicating that the P bus is enabled).
A clock input to~flip-flop 204 is provided by a TOGGLE OBEYS~ signal, resulting from a ~oolean NAND of the ERROR CLX signal (see Figure 4) and a PBO
ERROR* signal (see Fiqure 7).
The flip-flop 204 provides the aforementioned OBEY P signal at its "q~ output, while providing the inverse signal, OBEY P~, as the negated output.

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'' '''. ",' ,'. ''" '' ~ ' .' ~ ' Figure 6B depicts one preferred confiq~lration of circuitry utilized in i/o controller 18, 20 for generating an OBEY Q signal, conditioning the controller is to respond only to those peripheral 5 bus signals received on the second i/o bus 30B~ The circuit is constructed similarly to that shown above in Figure 6A.
Figure 7 depicts one preferred configuration of circuitry utilized in i~o controller 18, 20 for 10 generating bus and time-out error signals. The circuitry includes counter 206, AND gate array 208, NOR gate 210, flip-flops 212, 214, and NOR gates 216, 218.
As shown at the left of the illustration, 15 the clear input of the counter is provided by the T0 D~, the inverse of the drive side 18B T0 clock signal. A clock input to the counter 206 is provided by the ERROR CLK* signal (see Figure 4). The second output bit of counter 206 drives a TOGGLED OUT
20 signal, which serves as an input to AND gate array 208. The AND gate array 208 also accepts as input TOGG~E P (Figure 6A), TOGGLE Q (Figure 6B), ONE BUS*
(the inverse of a boolean exclusive OR of the OBEY P
and OBEY Q signals), PR FORCE D, PK FORCE D, OBEY P
25 (Fiqure 6A), OBEY Q (Figure 6B), P NOK*, and Q NOK~
signals.
Output of AND gate array 208 is routed to NOR gate 210, as shown in the illustration. This ga~e produces a SET PBO ERR~ signal, which p~ovides 30 an input to NOR gate 211. As illus~rated, a secon~
input to gate 211 is provided by the non-inverting output o~ flip-flop 212. The output of NO~ gate 211 ~rives the ~D~ input of flip flop 212, as shown~ In operation, once PBO ERROR* is see~: it is held by the ~`
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NOR gate 211 until cleared by the CLR MEM ERR~
signal. The clock input for that flip-flop is provided by the ERROR CL~ signal~ while the preset is driven by the CLR MEM ERR* signal ~indicating that 5 the error signal i~ to be cleared). At its non-inverting output, the flip-flop 212 driYes a PBO
ERROR siqnal, indicating that a peripheral bus error has occurred.
As further shown in Figure 7, the flip-flop 10 214 has a clock input which is driven by the WAIT TO*
signal ~Figure 4), and a clear input driven by the CLR MEM ERR* signal. At its in~erting output, the flip-flop 214 drives a TO ER~* signal, indicating that a time-out error has occurred.
The PBO ERROR* and TO ERR* signal are routed to inverting inputs of NOR gates 216 and 218, as shown. Output of these gates provide PBUS ERROR D*
and PBUS ERROR C* signals, indicating a peripheral bus error has been detected in each of the drive and 20 check sections of the i/o controller.
Figure 8 depicts a timing-sequence for two information transfer cycle types -- a command cycle and a scanner cycle -- executed by an i/o controller acting according to a preferred embodiment of the 25 invention. Durinq a scanner cycle, the i/o controller, under control of its scanner units ~Figure 2, elements 124A, 124B), interrogates peripheral units and their respective interfaces, i.e., qa~e arrays and peripheral adaptors, to 30 determine the operational state thereof. In a command cycle, on the other hand, the i/o controller sends a one-byte command to a selected peripheral device.

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Referring to Figure 8, wave forms transmitted on the strobe conductors of each of the first and second i/o buses, i.e., the STROBE signal, are shown on wave form line 220. Falling edges of 5 the STROBE signal define information transfer timing intervals, as shown by consecutively numbered time intervals at the top o the illustration. Line 222 represents the content of signals transferred on the function code conductors of each of the first and 10 second i/o buses, while line 224 represents the content of signals transferred on the data conductors of those buses.
As indicated by line 222 in Timing Interval 0, the system is in an idle state, with an IDLE
15 function code being asserted on the i/o bus function code conductors. Concurrently, as shown by line 224, all one's are asserted on the data conductors.
In Timing Interval 1, the i/o controller commences a command cycle. Particularly, the SELECT
20 function code is asserted on the function code conductors -- see line 222 -- while a peripheral selection addressing byte is transmitted on the data conductors -- see line 224. This peripheral selection addressing byte can include, as in the ~5 preferred embodiment, four SLOT ID b;ts and four "subchannel" bits. Gate arrays (Figure 1, elements 32, 34 . . . 42) can be conditioned to respond to ~elected channel/subchannel bit patterns to determine whether the command cycle is directed to the gate 30 array, its associated adaptor, and/or its associated peripheral device.
In Timing Interval 2, the i~o controller asserts IDLE on the function code conductors of the i~o buses while monitoring the data conductors of those buses to receive a response from the addressed peripheral device or interface~ In absence of fault, the i/o controller will expect to receive an ALIVE
signal -- e.g., an asserted seventh bit in an 5 otherwise non-asserted transmission byte -- on the data conductors, indicating that the addressed peripheral is operational. The addressed peripheral and interface can also respond, during the Timing Interval 2, with a signal indicating that an 10 interrupt is pending, or with signals indicating which i~o buses are being obeyed. Absent error, the command cycle continues in Timing Interval 3 with the transmission of a peripheral/interface command signal. In one embodiment, that signal can represent 15 one of six commands and have the following format:
Command Bit Pattern Reset "100.~X000"
Clear Interrupt "100XX001~
Togqle Obey P* UlOOXXO10"
Toggle Obey Q* NlOOXXOll~
Clear Broken UlOOXXlOON
Set Broken "lOOXX101~
Set Interrupt ~lOOXXllO"
CLR CPU Reset ~100XXlll~
-- the designation ~X~ represents an unused bit ~ Following transmission of the 30 periphera Vadaptor command signal, the illustrated system re-enters the idle state, with the transmission of an IDLE signal on the function code conductors o~ the i/o buses; see Timing Interval 4.
With further reference to Figure 4, Timing 35 Intervals 5-6, and 7-8 illustrate the e~ecution of two scannsr cycles. More particularly, as shown in Timing Interval 5, the i/o controller 18 initiates a scanner cycle by transmission, on the function code .
` ` ' :

,' ~ .
-. ' : . :

- 48 - ~323443 conductors of the i/o buses, a S~LECT signal te.g., having a unigue bit pattern ~001~). Concurrently, the i/o controller transmits on the data conductors a peripheral selection addressing byte directed to the 5 peripheral/adaptor being polled~
In the subsequent interval, i.e., Timing Interval 6, the i~o controller transmits an IDLE
signal on the function code conductors, while monitoring the data conductors for a 10 periphera Vadaptor response. According to one preferred embodiment, a response signal constitutes a one byte transmission having the following format:
~ Conten~
07 ALIVE -- peripheral is operation or "alive~
06 INTERRUPT -- peripheral~interface signalling an interrupt 05 Obey P~ -- interface not rec~iving signals on the P bus 06 Obey Q~ -- interface not receiving signals on the Q bus 03-10 intPrrupt code As indicated by line 222, the i~o controller enters the idle state in Timing Interval 7, following receipt of the periphera Vinterface response.
A further scanner cycle is shown in timing 30 intervals 8-9, proceeding in the same manner as the cycle discussed a~ove.
Figure 9 depicts a timing sequence for a peripheral i/o (PIO) write cycle. As noted above, this information transfer cycle provides a mechanism 35 throuqh which the ifo controller can transfer a data word to an attached peripheral device.
As above, the timing se~uence for the PIO
write cycle is shown by way of a stro~e line 226, a B ~ ~ :

.
- .

49 1 3~3`4~3 function code phase line 228, and a data phase line 230. ~oreover, the falling edqes of the strobe line 226 -- representing the STROBE signal -- define the PIO write cycles timing intervals. Nu~bering for 5 these intervals is given at the top of the illustration.
In accord with function code phase line, the i/o controller is in its idle state in time interval 0. At time interval 1, the controller commences the 10 PIO write cycle. Particularly, during that timing interval, the controller transmits a SELECT signal, accompanied by a peripheral selection address byte, on the function code and data conductors of the i/o buses; see function code phase line 228, data phase lS line 230. As above, the controller awaits a response from the addressed unit in time interval 2.
Assuming no error or interrupt signal is received during the response interval, the i/o controller transmits the data write address the next 20 three timing intervals. Particularly, during time interval 3, the controller asserts a WRITE signal on the function code conductors, while asserting the high-order byte of the write address on ~he data conductors. During time interval 4, the controller 25 continues assertion of the WRITE signal, while asserting the middle-order byte of the write address on the data conductors. Further, during time interval 5, the controller transmits the low-order byte of the write address on the data conducts, while 30 continuing assertion of the WRITE signal on the function code conductor.
As shown by function code phase linq 228, the iJo controller sends write data on the peripheral bus subsequent to transmission of the write data B`` ~

.` ` ` ` ` ` . .- . . .
.` ` - "'' ':' ''` ' ` ' :

~ ~23~43 address~ Specifically, the controller transmits the high-ordar byte of write data on the data conductors during time interval 6 and transmits the low-order byte of write data on the data conductors during time 5 interval 7. The controller maintains assertion of the WRITE signal of the function code controllers during these intervals.
Subsequent to transmission of the write data, the i~o controller re-enters the idle state, 1~ with transmission of the IDLE si~nal of the function code conductors; see function coda phase line 228.
Figure 10 depicts a timing sequence for a peripheral i~o (PIO) read cycle. Thi~ information transfer cycle provides a mechanism through which the 15 i/o controller 18 requests the transfer of a read data word from an attached peripheral device. As above, timing for the cycle is indicated through strobe line 232, function code phase line 234, and data phase line 236. Timing intervals, defined by 20 the falling edge of the strobe line 232, are shown across the top of the illustration.
The i~o controller 18 initiates a PIO read cycle in a manner similar to that of the PIO write cycle, to wit, the controller selects a peripheral 25 unit and transmits three bytes of address information. In this instance, however, that address information indicates the location from which data is to be read~. See function code and data phase lines 234, 238.
Following transmission of the read data address information, the controller 18 asserts IDLE
on the function code conductors. This signals the addressed unit that a read cycle -- as opposed to a write cycle -- has commenced. The unit accordingly - Sl 1323443 reads the addressed data locations and begins data transmissionO More particularly, in Time Int~rval 7, the addressea unit sends a first byte of read data, while in Time Int~rval 8, the unit sends the 5 remaining byte of data.
Apart from the first data byte, the i/o controller signals the addressed unit to continue read data transmission through successive assertions of the READ signal on the function code conductors.
10 Thus, for example, the controller asserts the READ
signal during Time Interval 7 in order to effect the transmission of a byte of read data in Time Interval 8. The controller's assertion of IDLE, e.g., during Time Interval 9, effects completion of the cycle.
15 That is, no further data is transmitted by the addressed unit subsequent to assertion of the IDLE
signal.

Peripheral 8us Selection and Control Loqic As noted above, the i/o controller 18 and, more particularly, processor 112A is arranged for two types of data access son the peripheral bus: direct memory access ~DMA) and programmed i/o access (PIO).
The PIO access moves only a single word on the bus 25 30, treating the peripherals as bank selected memory. The DMA, on the other hand, is designed for moving a continuous s~ream of bytes to a selected peripheral. In e~ecuting a DMA access, the controllsr 18 utilizes hardware assist which permit 30 the processor 112A to move each read or writs word of data in a single cycle. This hardware also calculates a checksum for every transferred word, in addition to permitting data verification ~a verify cycle) for data writ~en to the peripherals.

' .

- 52 - 132~443 Peripheral Bus Timinq The peripheral bus timing, as shown in Figure 11, is based on the falling edge of the 16 ~z~ system backplane clock, provided along line 22C
5 by a clock element (not shown). To maintain a substantially synchronous relationship between the 12 ~z processor 112A and the peripheral bus timing, controller 18 cycles only start on the leadinq edge of the interval 8 MH~ clock.
The first 8 MHz edge after c~cle commencement clocks T0. The next falling edge of 16 MH2* clocks interval T2, which would clock out data onto tha peripheral bus during a write. The ne~t falling edge of 16 MHz~ clocks FDATA C~K, capturing 15 data signals from the peripheral bus. The next rising edge of 16 MHz~ clocks interval T5.
If the proper conditions are met as a result of comparisons of the captured data, the signal SET
STROBE~ is asserted, and the next falling edge of the 20 16 ~z~ clock signal will cause STROBE. If SET
STROBE* is not asserted, as shown in FigurP 12, then that edge will only clear FDATA CLK. The next falling edge of 16 MH~ signal will clock FDATA CLK
again, which will clock RETRY if the PBUS is not 25 waiting.
The new data is then run through the comparisons and if SET STROBE~ is asserted~ STROBE
will occur on the next falling edge of the 16 MHz*
clock signal. If SET STROBE* is not asserted, then 30 ERROR CLK will occur on the next falling edge of the 16 MH2* clock signal.
If STROBE does occur, then CLR T0 will be asserted until T7 at the next rising edge of the 16 MHz* clock signal. The deassertion of T0 clears T2 Bi - 53 - ~323~43 and T5. STROBE deasserting on the ne~t falling edge of 16 P~z* clears T7. TO can be reasserted by this same edge, starting a new cycl~.

5 Peripheral Bus Accesses Processor 112A accesses to the peripheral bus are initiat~d by the signal S4 SYNC which is the result of the first 8 MHz clock signal edge following S4 SYNC. S4 SYNC will be taken on the next STROBE
10 into the peripheral bus interface select path and the cycle will begin.
A PIO cycle (address C00000x-FFFFFF~) is initiated as follows. In the list, the designation ~^" indicates assertion of the corresponding signal 5 STATE -> SELECT (0-0-1) on STROBE^ (If previous state was IDLE) FCODE -~ SELECT (0-0-1) on T0^
DATA SOURCE -~ PIO SLOT ADDR (1-0-0) on T0^
20 PDATA EN -> ASSERTED on T0^
STATE -> STATUS ~0-1-0) on STROBE^
FCODE -> IDLE ~0-0-0) on T0^
DATA SOURCE -> XXX on T0^
25 PDATA EN -> DE-ASSERTED on T0^
STATE -> WRADRl (0-1-1) on STROBE^
FCODE -~ WRITE (0-1-0`) on $0^
DATA SOURCE -> PIO ADR BYTE 1 (1-0-1) on T0^
3Q PDATA EN -> ASSERTED on T0^
STATE -> WRADR2 (1-0-0) on STROB~^
FCODE -> WRITE (0-1-0) on T0^
DATA SOURCE -> PIO ADR BYTE 2 (1-1-0) on T0^
35 PDATA EN -> ASSERTED
STATE -> WRADR3 (1-O-1) on STROBE^
FCODE -> WRITE (0-1-0) on T0^
DATA SOURCE -> PIO ADR BYTE 3 (1-1-1) on T0^
40 PDATA EN -> ASSERTED
STATE -> SELECT OK for PIO ~1-1-0) on STROBE^

.

-.. ' - ' ' .
, . ,;

~ 323443 A PIO WRITE cycle proceeds from initiation as follows:
FCODE -> WRITE ~0-1-0) on T0^
DATA SOURCE -> UPPER DATA BYTE 1 (0-1-0~ on TO^
~if UDS asserted~
PDATA EN -> ASSERTED
STATE -~ SELECT OK for PIO (1-1-0) on STROBE^
10 FCODE -> WRITE (0-1-0) on TO^
DATA SOURCE -> LOWER DATA BYTE 1 ~0-1-1) on T0^
(if LDS asserted) PDATA EN -> ASSERTED
STATE -> IDLE (0-0-0) on STROBE^
FCODE -~ IDLE (0-0-0) on T0^
DATA SOURCE -> ALL ASSERTED (0-0-0) on T0^
PDATA EN -> DE-ASSERTED on T0^
STATE -> IDLE (0-0-0) or SELECT ~0-0-1~ on STROBE^
A PIO READ cycle proceeds from initiation as follows:
FCODE -> IDLE (0-0-0) on T0^
25 DATA SOURCE -~ UPPER DATA BYTE 1 (0-1-0) on T0^
(if UDS asserted) PDATA EN -> DE-ASSERTED
STATE -> SELECT OK for PIO (1-1-0) on STROBE^
FCODE -> READ (0-1-1) on T0^
DATA SOURCE -> UPPER DATA BYTE 1 (0-1 0) on T0^
PDATA EN -> DE-ASSERTED
STATE -> SELECT OK for PIO (1-1-0) on STROBE^
FCODE -> READ (0-1-1) on T0^
DATA SOURCE -~ UPPER DATA BYTE 1 (0-1-0) on T0^
~if UDS asserted) 40 PDATA EN -~ DE-ASSERTED
STATE -> IDLE (0-0-0) on STROBE^ (first data byte latched) FCODE -> IDLE (0-0-0) on T0^
45 DATA SO~RCE -> LOWER DATA BYTE ~0-1-1) on T0^ (if LDS asse~ted) PDATA EN -> DE-ASSERTED
STATE -> IDLE (0-0-0~ on $TROBE^ (second data byte latched~

, ' .

_ 55 - 1323~43 FCODE -> IDLE (0-0-0) on T0^
DATA SOURCE -~ ALL ASSERTED (0-0-0) on T0^
PDATA EN -~ DE-ASSERTED
STATE -> IDLE (0-0-0) or SELECT (0-0-1) on STROBE^
If processor makes a word access (with the upper data select signal, UDS, and the lower data select si~nal, LDS, asserted~, then the control logic 10 will access two consecutive bytes from the peripheral bus 30 during the one select. If th~ processor makes a long word operation, whi~h is actually two word operations, then the control logic will maXe two peripheral bus selects, each time moving two bytes 15 prior to de-selecting~
If the processor 112A makes a long word write to address BF9004~, BF9008x, or BF900Cx, then the cycle will be a DMA SELECT as follows:
STATE -> SELECT (0-0-1) on STROBE^ ~If previous state was IDLE) FCODE -~ SELECT (0-0-1) on T0^
DATA SOURCE -> UPPER DATA BYTE (0-1-0) on T0^
PDATA EN -> ASSERTED on T0^
25 STATE -> STATUS (0-1-0) on STROBE^
FCODE -> IDLE (0-0-0) on T0^
DATA SOURCE -> XXX on T0^
PDATA EN -> DE-ASSERTED on T0^
30 STATE -~ WRADRl (0-1~1) on STRO~E^
FCODE -> WRITE (0-1-0) on T0^
DATA SOURCE -> LOWER DATA BYTE (0-1-1) on T0^
PDA~A EN -> ASSERTED on T0^
35 STATE -> WRADR2 (1-0-0) on STROBE^
FCODE -> WRITE (0-1-0) on T0^
DATA SOURCE -> UPPER DATA BYTE ~0-1-0) on T0^
PDATA EN -> ASSERTED
40 STATE -> `WRADR3 ~1-0-1) on STROBE^
FCODE -> WRITE ~0-1-0) on T0^
DATA SOURCE -> LOWER DATA BYTE (O-1-1) on T0^
PDATA EN -> ASSERTED

' `` ` ` ~ . ':~
' ~
, :. .

STATE -> SELECT OK for DMA ~1-1-1) on STROBE^
The adaptor is now SELECTED for READ or 5 WRITE or VERIFY. If the SELECT was for WRITE, then the select is complete and no more STROBE signals will ~e asserted until the processor actually wants to move DMA data. If the SELECT was for either READ
or VERIFY, then two more cycles will occur as follows:
10 FCODE -~ IDLE (0-0-0) on T0^
DATA SOURCE -> UPPER DATA BYTE 1 ~0-1-0) on T0^
(if UDS asserted~
PDATA EN -> DE-ASSERTED
STATE -~ SELECT OK for DMA (1-1-1) on STROBE^
FCODE -> READ ~O-l-l~ on T0^
DATA SOURCE -> UPPER DATA BYTE 1 (0-1-0) on T0^
PDATA EN -> DE-ASSERTED
20 ST~TE -> SELECT OK for DMA (1-1-1) on STROBE^
At this point, the first data byte will be on the peripheral bus 30 waiting to be latchea in.
25 It cannot be latched until the processor 112A makes its first DMA CYCLE access so that the first byte can be properly placed in either the upper or lower latch, depending on the states of UDS and LDS.
It will be appreciated that during a DMA
30 cycle the processor 112A performs a cycle for each data transfer to or from the buffers; however, it does not move the data itself. The direction of the tran~fer is considered to have previously bee~ set by the address of the selection. Accordinqly, the 35 processor 112A merely provides the virtual memory address Of a page marked for the DMA access.
That iS, where processor 112A performs a read to a virtual page marked for D~A while~the:
controller 18 has selected a peripheral for DMA, then :

B`
..

- . . ~ ~ .

- 57 - ~3~3~4~`

data will be transferred in the d;rection set by the selection address, to or from the physical page as mapped. A write to a DMA marked page while the controller 18 has selected a peripheral for DMA will 5 cause a processor exception, BERR.
The illustrated controller 18 advantageously employs a programmable array logic chip, the BUFFER
MANAGER PAL, to control the peripheral bus cycles once a peripheral has been selectad. If selected for 10 DMA write, then the BUFFER MANAGER PAL fills the outb~und data buffers asynchronously when they are empty and the processor 112A has data ready f~r them during a D~A CYCLE. Once filled, the BUFFER MANAGER
PAL starts peripheral bus cycles and empties the 15 buffers synchronously with T2, as each byte is presented on the peripheral bus. When the buffer is empty, then the BUFFER MANAGER PAL stops requestinq cycles until the processor 112A returns with more data.
When the processor 112A starts the next DMA
cycle and S4 SYNC is asserted, then the BUFFER
MANAGER PAL will return a buffer load signal P~VF RDY
when the buffers needed for this cycle are empty.
After PBUF RDY iS asserted, the processor 112A cycle 25 can complete when the data is valid and ready to latch into the outbound buffers.
If selected for a DMA read, then the BUFFER
MANAGER PAL requests cycles to fill the inbound data buffers when empty. This data is latched in the 30 buffers synchronous with STROBE. When the buffers are full, and the processor 112A performs a DM~
cycle, then the BUFFER MANAGER PAL will issue a PBUF
RDY, resulting in the signal DTACR being asserted and ' `. ' .' ' ~
' , - 58 - ~3~3~43 either a local memory or a standard bus interface write commencing.
The illustrated controller 18 is also capable of performing a ~verifyN operation to insure 5 that data written to the permanent storage media, e.q., disk drives, is valid. Selecting for a verify cycle is a hybrid operation of the read and write cycle. The logic on the controller 112A, except for the function code, is performing a write without the 10 data enable signal PDATA EN being asserted. Here, peripheral bus interface logic selects a peripheral for a read, ending ~he select phase as in a normal read cycle, with the first data byte waiting on the bus for the processor 112 to return with the first 15 D~ cycle.
Subsequently, when the first DMA cycle occurs, data is read out of either main or local memory, depending on the DMA mapped page, and written into the outbound data buffers as in a DMA write 20 cycle. The BUFFER MANAGER PA~, detecting a full buffer, commences a peripheral bus cycle with the assertion of T0. At timing interval T2, a data byte ou~ of the buffer is latched into the output register, which would otherwise result in the 25 placement of data on the peripheral bus, where, ~or example, PDATA EN was asserted. Since it is not, however, when FDATA CLK iS asserted, data from the peripheral is latched into input registers. The result of the loopback comparator 76A is used to -~0 determine if the data otherwise being written is the same as the data byte being read back. If it is the same, ~he verify data is deemed valid; otherwise, the verify data is invalid.

- :
' : ' 1 3234~3 Figures 11 - 14 illustrate the internal operation of a preferred i/o controller 18, 20 constructed in accord with the invention. More particularly, the illustrations depict a controller's 5 peripheral bus interace cycle, i.e., the cycle during which the i/o controller takes data ~rom the peripheral bus.
Figure 11 illustrates a timing sequence for two normal peripheral ;nterface cycles. That is, the 10 illustration depicts the wave forms occurring during two cycles in which error-free, duplicated signals are received on the first and second i/o buses 30A, ~OB by the partnered i/o controllers 18, 20.
In the illustration, the waveforms are 15 defined as follows-Sianal Definition 16 MHz* Inverse of the si~teen megahertz clock signal 8 MHz Eight megahertæ timing signal derived from 16 MHz clock signal TO Timing signal having a leading edge which defines the start of a peripheral interface cycle T2 Timing signal derived from TO
having a leading edge which rises 125 nanoseconds after TO and having a trailing edge which falls with TO
F CLK Flash clock signal defining instants at which the flash circuitry compares operational states of the first i/o controller 18 and its partner, i/o controller ~5 20: the signal is generated at the non-inverting output of a:
flip-flop having its HJn input driven by SET STRB~, its l~" input tied to its non-inverting output, it~ clock input driven by 16 MHz~, its clear input driv~n by T2.

.

i~

;
. - . : :.
.
.

'. ' - ' . ' ';
, :

~ 3~3~4~

Sinnal Definition SET STRB Timing signal for setting the strobe flip-flop; see Figure 4, element 176 STROBE* Timing signal deining peripheral bus interface cycles CLR T0* Signal for clearing T0 T7~ Timing siqnal for seventh interval E CLK Error clock signal; see Figuse 4, element 166 In Figure 11, the first of the illustrated peripheral interface cycles begins with the first 15 rise of wave form T0 and ends with the first fall of wave form STROBE. The second of the cycles begins with the second rise of wave form T0 and ends with the fall of wave form STROBE.

20 P~ripheral Bus Error Handling Peripheral bus data signals are captured by the i~o controller 18 at F CLR and cumpared by drive and check sides, as well as between partner controllers 18, 20. The results of these comparisons ~5 are shared between partners so tha~ all peripheral bus obey/error decisions are made identically between boards even if only one board saw an error.
If the results of the comparisons indicate that the data captured by both boards agrees and is 30 of good parity, then the bus interface cycle continues with the issuing of STROBE on the next falling edge of 16 MHz*. If the data captured at F
CLK does not agree between boards (as indicated by the WE signals), then a RETRY F CLK i5 issued 35 capturing data on the bus again. The same comparisons are made with the cycle continuing if the boards agree.

' ' : ~.

1 323~43 Figure 12 illustrates a timing sequence for a peripheral bus interface cycle in which the peripheral p~rforms two peripheral bus/flash bus comparisons (hereinafter, refexred to as ~bu~
5 comparisons~) to determine that duplicative data is received synchronously and simultaneously by the first and second processing sections 18A, 18s of the first and second peripheral controller 18, 20.
In the illustration, the peripheral bus 10 interface cycle commences with the rise of the leading edge of wave form T0. A bus comparison is performed during the first interval in which the wave form F CLR is high; see corresponding FDATA CLK D and FDATA CL~ C signals providing inputs to element 168 15 of Figure 4.
As a result of the flash circuitry's detection of an improper condition during the first bus comparison -- indicated by the failure of SET
STRB to become asserted -- the i~o controller 20 performs a second bus comparison. This second comparison occurs during the second interval in which F CLK is shown to be asserted. As indicated by the illustration, this second interval begins 125 nanoseconds after the first interval ends.
As indicated by the rise of SET STRB, the second bus comparison results in a finding that the first and second processing sections 18A, 18B o~ the first and second i~o controller 18, 20 received duplicative information signals from the peripheral 30 bus. Following tha rise of SET STRB, the STROBE
signal is asserted. With the fall of that signal, the illustrated cycle ends.
Figure 13 depicts a timing sequence for a preferred bus interface cycle where, in conse~uence , . .

to detecting an error, the ifo controller switches from a mode in which it obeys one of the i/o buses to a mode in which it obeys the other i/o bus. When this occurs, an ERROR CLK siqnal will be asserted 5 instead of STROBE. The assertion of ERROR CLK will change the state of the obey signals as follows:
CVRRENT STATE NEXT STATE

10 OBEY P O~EY Q P OK O OK ERROR CLK OBEY P OBEY Q P BERR

T T T T asserted T T T
T T T F asserted T F F
T T F T asserted F T F
15 T T F F asserted F F T
T F F T asserted F T F
F T T F asserted T F F
In addition to the signals def;ned above, the 20 illustration presents the following wave forms:
Siqnal De~inition RETRY Signal defining onset of retry interval for rechecking signals received from the i/o buses PB OBEY ERR Peripheral bus obey error;
see Figure 7, element 212 TOGGLE* indicates upon assertion that the each side of the i~o controller te-9-, the drive and check sides) is enabled to toggle from its current obey stat~ (e.g, obeying the P bus) to a new obey state (e.g., obeying the Q bus~ depending upon the status of P NOK~, Q
NOK*, OBEY P*, and OBEY Qx OBEY P Signal indicating that the i/o controller is processing signals received on the P bus 1 3234~3 Si~nal Definition OBEY Q Signal indicating that the i~o controller i~
processing signals received on the Q bus P NO~* Signal indicating that the P bus is not fault Q NOK~ Signal indicating that the Q bus is not faulty With particulax reference to Figure 13, the illustrated bus interface cycle be~ins with the rise of the T0 siqnal. At the outset, the i~o controller 15 is obeying the Q bus, but not the P bus. That i~, the controller is processing signals received on the Q bus, while ignoring those signals received on the P
bus. This is indicated by the OBEY Q sîgnal, which is in its assertive state at the be~inning of the ~0 cycle, while the OBEY P signal is initially in its non-assertive state.
As indicated by the F CLK wave form, upon the first tick of the flash clock, signals received by the i/o controllerts) 18, 20 from the Q bus are 25 detected as faulty; see the deassertion of Q NOK~.
With the second tick of F CLK, the RETRY
siqnal is asserted. This si~nal can be generated at the non-inverted output of a f lip-f lop having F CLR
as it clocked input, having its non-inverting output 30 coupled to its "K" input, and having its clear input driven by the NOR of T2 C~ and WE HOLD STRB.
As shown earlier (see Figure 4, elements lfi6 and 174), the ERRO~ CLK signal is ~enerated in lieù
of STROBE after RETR~ is set and while SET STRB is ~ ~ -35 not asserted. The ERROR CLK si~nal provides an input to a NAND gate, alon~ with the PB OBEY ERR* signal (see Figure 7, element 2123 to cause TO~GLE to become : ~ :
::

~:
' ~ . .
' ' . ' . ,, , ~ -'.''' . ', ' ' ' -.
.

- 64 1323~

asserted. This assertion enables the OBEY P and OBEY
Q signals to chan~e state.
At the time of the third illustrated flash clock ~- see the F CLK wave form -- the i/o 5 controller has switched from obeying the Q bus tO
obeying the P bus. The third illustrated flash clock forces a bus comparison (i.e., a comparison of the flash and peripheral bus signals~ which reveals no error (sea Figure 1~. Accordingly, SET STRB and 10 STROBE are asserted, completing the bus interface cycle.
Figure 14 illustrates a time out sequence in a preferred i~o controller constructed according to the invention. As noted above, those active 15 peripheral devices which are attached to the peripheral bus constantly monitor and compare siqnals received on the first and second i/o buses. Whenever one of the peripherals detects an erroneous bus transmission, e.g., data signals received on the 20 first i~o bus which do not match data si~nals received on the second i~o bus, the peripheral asserts WAIT on the corresponding conductors of the peripheral bus.
The i/o controller responds to brief 25 assertions of WAIT by delaying until WAIT is deasserted any subsequent assertions of STROBE on the peripheral bus. In other terms, brief assertions of WAIT delay completion o~ a current bus interface cycle. This proves advantageous insofar as the delay 30 permits the peripheral which wàs asserting WAIT to recheck incoming signals, which may have merely required extra time to settle or to rid themselves of interference.

'' ' '. : ~ , , 1 3~3443 However, in the event the i/o controller detects excessively lengthy assertions of WAIT, it enters an error checking sequence which allow it, as well as the peripheral devices, to locate the source 5 of error. According to one embodiment of the inventions, the i/o controller will enter this error checking sequence if WAIT is asserted for more than eight microseconds.
In addition to those waveforms define above, 10 Figure 14 includes the following:
Signal Definition WAIT TO Wait time out siqnal; see Figure 4, element 162 ERR SEQ Signal defining onset of i/o controller sequence or identifying a source of error TO ERR Signal defining a time out error YOU WAIT wait-related signal defined as a boolean AND of the WAIT TO and ERR
SEQ* signals With particular reference to Figure 14, if an attached peripheral detects an erroneous 25 transmission on the peripheral bus, it asserts WAIT, which inhibits the i/o controller from asserting STROBE or RETRY. The assertion of WAIT
simultaneously presets WE HLD STRB, so that the timing logic (Figure 4) strobes only F CLX.
In addition to asserting WAIT, the ~ault-detecting peripheral can back-drive signals on `
the fun~tion code and data conducts o~ the first and second i~o buses. The function code loo~back comparator ~Figure 2, element ~4A, 74~) will, thu~, 35 indicate errors on both i/o buses. The data loopback comparators ~Figure 2, elements 76A, 76B) may also indicate errors if the i/o controller is driving~d~ata.

, . . . . .
., . : . -: ' - ' , ' ' , . . .
. . . .

.

1 3~3443 More particularly, if WE HLD STRB remains set for eight microseconds, the i~o controller 18 enters its time-out error sequence on the next strobe of F CLK.
The signal WAIT TIME-OUT is set by FDATA CLK
and causes assertion of STROBE on the next falling edge of the timing si~nal 16 M~z*. The assertion of WAIT-TIME OUT also causes the controller 18 to assert WAIT back to the adaptors to insure that all adaptors 10 enter the ERROR T2 sequence. This assertion of STROBE also clears the states of the peripheral bus selection loqic, as well as clocking the adaptor asserting WAIT to deassert the WAIT conductor, the function code conductors and data conductors.
The rising edge of STROBE clears WAIT
TIME-OUT, whose falling edge then sets the error signal TIME-OUT ERROR. With the function code states at IDLE, the BUFFER MANAGER PAL asserts the cycle initiation signal BCYC START regardless of the type 20 of cycle the board was performin~ at the time of the assertion of WAIT TIME-OUT. The next rising edge of the 8 MHz starts the ne~t part of the time-out cycle by asserting T0.
The assertion of T0 clocks the peripheral 25 bus control logic into its time-out error sequence.
Particularly, following the first assertion of T0 after the error signal TIME-OUT ERROR iS asserted causes the controller 18 to assert all function codes conductors as well as selecting the data multiplexors 30 70A, 70B to assert all data conductors.
Simultaneously, the controller 18 asserts the opposite data parity on the parity conductors. A
STROBE for this cycle will normally occur if W~IT has been deasserted; however, if WAIT has not been ' `' " : ' . ~ -` . . ~ , .

- 67 - 13~34~3 deasserted and another WAIT TIME-OUT occurs, then another FORCED STROBE occurs along with an ERROR
CLK. ThiS ERROR C~K will change the buses as follows:
WAIT P WAIT O OBEY P OBEY Q OBEY P OBEY O

F T T ~r F T
T F F T -~
F T T T T F
T F T F F T
10 lF T T F --~
While the description above relates generally to the first i/o controller 18 and, more particularly, to the first processing section 18~, it 15 will be appreciated that the second i/o controller 20, as well as the second processing section 18C, are constructed and operate similarly to the apparatus described above.

20 Peripheral De~ice Interface The i/o controllers 18, 20 communicate with the peripheral devices 24, 26, 28 via the peripheral bus 30. As noted above, the controllers 18, 20 address ~ach peripheral device using the chassis slot 25 number of the associated interface card, which includes the gate arrays and adaptors for the peripheral.
Referring to the drawings, Figure 15 depicts preferred circuitry for interfacing a peripheral 30 device 24 with the peripheral bus 30 and, more particularly, the first and second i~o buses 30A, 30B. The interface includes gate arrays 32, 34, adaptor 44, adaptor bus 56, inverters 238A, 238B, 238C, 238D, and registered multiplexors 240A, 240B.
AS shown in the illustration, input signals receivad on the P bus 30A are routed through inverter '. : ~ ` ' , . - : -`' - , , ,' . . . .
.
.

238B to both registered multiple~ors 240A, 240B, while input signals received on the Q bus 30B are routed through inverter 238D to ths multiplexors.
From the registered multiplexors 290A, 240B, the 5 input signals are routed on lines 242A, 242B to both gate arrays 3~, 34, where the signals are checked and processed. Output signals produced by gate array 32 are routed via line 244 to the P bus and the Q bus via inverters 238A, 238C, respectively.
The bus interface logic is presented in greater detail in Figures 16 and 17. More particularly, Figure 16 illustrates the circuitry interconnecting the peripheral bus 30 and the gate arrays 32, 34. Specifically, that illustration 15 depicts circuitry which makes up inverters 238A, 2~8B, and multiple~or 240A (Figure 15). On input, this circuitry routes data, function, and strobe signals from the P bus 30A to its principle associated gate array 32, i.e., the Udrive~ side 20 array, as well as to the partner array 34. on output, this circuitry routes data, function, and WAIT signals from the gate axrays 32, 3~ to both i/o buses, i.e., P bus 30A and Q bus 30B.
Similarly, Figure 17 illustrates circuitry 25 interconnecting the peripheral bus 30 and the gate arrays 32, 34. Specifically, the illustration depicts circuitry making up inverters 238C, 238D, and multiplexor 240B (Figure 15~. The illustrated circuit routes data between the Q bus (30B) and its 30 principle associated gate array 34, i.e., the Ucheck"
side array, as well as to its partner gate array 32.
Figure 18 depicts circuitry for generating strobe tracking signals TRACK P D and TRACX Q D, as well as inverted forms thereof. This circuitry is B : :
:

.. .. : ~

. `
`, ` - 69 1 3~ 3 443 used in combinati~n with the circuitry depicted in Figure 16 (at bot~om) for generating the STROBE IN D~
signal, representative of the timing of information signal transfers received by the drive side gate 5 array 32. A si~ilar circuit, not illustrated, i~
provided for genera~ing the tracking signals used in combination with the c;rcuitry depicted in Fiqure 17 or generating the STROBE I~ C* signal, representative of the timing of information signal 10 transfers at the check side array 34.
A full appreciation of the operation of the circuit shown in Figure 18 may be obtained by reference to aforementioned EPO Application No.
88 10 2650.4, filed February 23, 1988.

With particular reference to the interface circuitry of Figure 16, four Motorola 26S10 transceivers provide access to eiqht bits of data and four bits of function code on the P bus 30A, along with their associated parity bits and with the WAIT
line. The transceivers function in receive mode to produce DATA IN P and FC IN P signals. The Q BUS
counterparts functioning similarly to receive and produce DATA IN Q siqnals.
The DATA IN P and FC IN P signals, and their associated parity bits, are routed to a set of latched multiplexers. The outputs of these latched multiplexors are the PDATA IN D and PFC IN C
siQnals~ An OBEY P* signal determines whether those outputs drive signals received from the P Bus 30A or from the Q Bus 30B. Latching occurs on the first falling edge of ST~O~ IN D*.
The OBEY P and OBEY Q lines are conditioned so that the latches arsociated w~th the drive side ~ ! :

B

- .

- 7n - 1323443 array 32 normally provide data obtained from the P
Bus, while the latches associated with the check side array 34 normally provide data obtained from the Q
bus.
Figures 19-20 illustrate circuitry for checking data and function code signals received by the drive side array 32. More particularly, Figure 19 illustrates a preferred circuit for detecting faults in incoming data and for generating in 10 response thereto WAIT and MAKE ERROR Tl signals. The fi~ure provides circuitry for checking the parity o data and unction code signals (i.e., MY DAT~ IN and MY FC IN) received by the gate arrays 32, as well as that of similar signals (i.e., HIS DATA IN and HIS FC
15 IN) received in the partner gate array 34.
Figure 20 illustrates a preferred circuit for comparing function code signals (MY FC IN) received in a gate array 32 with those (HIS FC IN) received by the partner gate array 34. The circuit 20 generates resultant signal FC IN EQ* having an assertive value indicating that the function code signals are equal.
Figure 21 illustrates a preferred circuit for comparing data signal (MY DATA IN) received by a 25 gate array 32 with those (HIS DATA IN) received by the partner gate array 34. The circuit generates resultant signal DATA IN EQ~ having an assertive value indicating that the compared signals are equal.
Figure 22 illustrates preferred circuitry 30 for checking data and function code signals received durin~ all stages of the peripheral bus 30 error checking sequence, discussed~below.
Figure 23 illustrates preferred circuitry for e~tracting periphèral device;address information B`

.
.. . . .
.... . . : .
. . :

.

- 71 - 13234~3 from input data signals. The circuit accepts input data signals from bo~h gate arrays, i.e., signals MY
DATA IN and HIS DATA IN to produce addressing output siynals, PADDR. The circuit also selects, from those 5 incoming data signals, data signals (SAFE DATA) which will be utilized during further processing by the qate array.
Figure 24 depicts preferred circuitry for generating error sequence initiatinq signal ERROR Tl l0 and for generating a DRIVE* signal or controlling operation of the attached peripheral device adaptor 44. The circuitry also includes elements for selecting, from the incoming funct;on code signals (MY FC IN and HIS FC IN), those function code siqnals 15 (SAFE FC0, SAFE FCl, . . . SAFE FC3~ which will be used for further processing by the gate array 32.
With respect to Figure 23, the trailing edge of STROBE* effects the storage of the data signal parity in the drive side latch. If that parity is 20 ok, the MAKE SAFE DATA signal is asserted, causinq the multiplexor shown at bottom left of Figure 23 to select the PDATA IN D leads as the source of SAFE
DATA for the drive side of the interface. On the other hand, if the parity stored in the drive latch 25 proved unacceptable, the MAKE SAFE DATA signal would not be generated, thereby causing the selection of the check side latch data siqnals, PDATA IN C.
Figure 24 presents logic utilized in determining whether to assert MAKE SAFE FC and 30 thereby effect selection of drive side function code siqnal, as opposed to check side function code siqnal. That logic is used similarly to the MAKE
SAFE DATA is determining function code signal selection.

B

^ 72 ~323443 The circuitry of Figure 19 compares the ~unction code parity check signals, PFC PAR OK, generated by the drive and check sides to determine whether both side received valid function code 5 signals. This check is important insofar as a fault could result where one side of the interface, i.e., check side array 34, interprets the incomin~ signals as de~ining a read or select operation, while the other array, e.g., array ~2, interprets those signals 10 as defining an idle or write operation.
Particularly, in the event the arrays 32, 34 disaqree whether the requested function is a read or select operation, they may not simultaneously place data or status signals on the bus. If one side is 15 late in so doing, the i/o controllers 18, 20 might receive erroneous data. Alternatively, in the event the the arrays disagree whether the requested function is a write operation, the transmission of read or status signal may interfere with the receipt 20 of valid write data.
To circumvent these possible sources of error, the gate array 32, 34 generates and transmits to the i/o controllers 18, 20 a WAIT signal which delays the generation of subsequent STROBE signals on 25 the peripheral bus. Logic for generating the WAIT
signal in response to a disagreement of parity siqnals -- i.e., single bit errors perceived within the received signals -- is presented in Figure 19.
Specifically, attention is directed to the logic ~or 30 generat~ng the ~AIT OUT signal.
Figure 19 also presents circuitry for generating the MAXE ERROR Tl signal in the event a mùltibit error i5 detected. Specifically, the illustrated logic generates that signal where both B : ~
.

the drive and check side latches have incorrect data parity; where both the drive and check side latches have correct data parity, ~ut differing data s~gnals;
where both the drive and check latches hava incorrect 5 function code parity; and where the drive and check latches have correct function code parity, but differing function code signals.
The generation of MAXE ERROR Tl causes the gate array logic to enter an error handling sequence, 10 beginning with the assertion of WAIT.
Figures 25 throuqh 36 present further circuitry of preferred gate array 32. In particular, Figure 25 illustrates pre~errea circuitry for extracting, from the high order bits of the 15 peripheral address signal PADDR, peripheral dev;ce adaptor 44 command signals CLR UP RESET, PINT TO
DEV*, SET BROKEN, CLR BROKEN, TOGGLE OBEY Q, TOGGL~
OBEY P, CLR INT, and DO RESET*.
Figure 26 illustrates preferred circuitry 20 for comparing slot-id signals ~SAFE DATA bits 4-7 received from the i/o controller with the slot-id signals (SID) assigned to the gate array 32 ~o determine whether the gate array has been addressed (ME SAFE) and selected ~STATUS SEL). The circuitry 25 also provides elements for interpreting the function code signals (SAFE FC0, SAFE FCl, SAFE FC2, and SAFE
FC3, ànd the respective inverted forms) to determine whether a read operation has been requested.
Figures 27 and 28 illustrate preferred 30 circuitry for generating state signals N~W ME, ~Q~D
HI, LOAD MæD, ~OAD LW, SELECTED, ERROR SEQUENCE, ERROR T3, ~RROR T2, OBEY ME, and LP0 . . . LP7, as well as inverted and latched forms thereof.
:

Bt , .

Figure 2g illustrated a preferred circuit for generating peripheral adaptor 44 control signals GET CYC* and I WANT CYC, as well as inverted forms thereof.
Figure 30 illu~trates preferred circuitry for generating timing signals LCLKl, LCLK2, as well as state signals RAM CYC DEL, RAM CYC, ADDR OE, ADDX
EN, and PENDING CYC, as well as inverted forms thereof.
Figure 31 illustrates a preferred circuit for generating address (ADP ADDR) and data (ADP DATA
OUT) signals for output to the adaptor 44. The circuit also includes elements for generating internal data signals (ADP DATA O) and ~ADP DATA 1) 15 from data signals (ADP DATA IN) received from the adaptor.
Figure 32 illustrates preferred circuitry for comparing peripheral bus data signals (MY PDATA
OUT) output by the gate array 32 with those signals 20 (HIS PDATA OUT) output by the partner gate array 34 to generate the COMPARE OK* signal. The figure also illustrates circuitry for generating the signals MY
BROKEN and BROKEN TWO, as well as inverted forms thereof.
Figure 33 illustrates preferred circuitry for generating interrupt-related signals GET INT* and I WANT INT, as well as gate array 32 status signals (STATUS OUT).
Figure 34 illustrates a preferred circui~
30 for generating further interrupt related signals INT
FROM IOP, INT FROM TIMER.
Fiqure 35 illustrates preferred circuitry for generating error-related signals CLX BROKEN;TWO, ' ' ' - '- , .

.

SET BROKEN and synchroniziny signals RESET INSYN
STROBE and PRE RIS, as well as inverted forms thereof.
Figure 35 illustrates a preferred circuit for generating timer signals LOAD TIMER~ and TIMER
5 OUT.
Fiyure 37 illustrates preferred circuitry for driving data and status sig~als ~ADP DATA and STATUS OUT) onto the adaptor bus 56, as well as circuitry for receiving data signals (MY PDATA OUT) 10 from that bus.

B~s Protocol The peripheral device interEace and, particularly, the gate arrays 32, 34 and adaptor 44 15 receive signals from the peripheral bus 30 according to the protocol defined above. Unlike the i/o controller 18, 20 which ends each bus interface cycle with the generation of a strobe signal, the gate arrays 32, 34 begin each cycle upon receipt of the 20 strobe signai. This aspect, among others, of the operation of the interface is described below. It will be appreciated that this description qenerally applies to all of the illustrated gate arrays 32, 34, . . . 42.
Generally, each gate array 32, 34, 36, 38, 40, 42 monitors both the first and second iio buses and compares information received from both of them.
Normally, of course, the comparisons reveal that the signals are ok -- i.e., that duplicate signals have 30 been received synchronously and simultaneously on the buses. Accordingly, the the gate array passes signal received on the assigned, or obeyed, bus.
~ s described above, an information transfer cycle begins with the transmission along the .

.

peripheral bus 30 o a select command and slot id.
The interface associated with the peripheral to which this select command is directed normally responds with an ALIVE signal, as described above. The next 5 three cycles invol~e the transfer of the address to be read or written to the adaptor. The final cycles are the reads or writes, and the i/o controller 18, 20 may continue with additional reads or writes if it wishss a sequence of transfers.
As shown in Figure 26, four XOR gates compare a hard-wired slot ~D associated with the chassis slot with bits 4-7 of the SAFE DATA to create a signal called ME SAFE. While this signal may be asserted immediately after receipt of unsafe data, 15 only after assertion of MAKESAFE DATA will ME SAFE be used by the drive side array 32. The signal arrives slightly after the safe function code, but sufficiently before the rising edge of STROBE.
The SAFE FC signals are used as inputs to 20 programmable array logic of the drive side array 32 which controls all of the data transfers on the D-side of the interface. The SAFE FC signals include the following function codes:
ooo0 Idle 0001 Select 0010 Write 0011 ~ead Responding to the~e function codes, the 30 drive side array 32 acts as a finite state machine havinq states described below. It will be apprecia~ed that the check side array 34 is normally acting identically to the drive side array 32 and, therefore, is expected to enter the states 35 simultaneously with its partner array. In the .. : , . .. .

.

description of states, the de~ignation "PALN is used in reference to those elements which provide the finite state logic unctionO

5 Enterinq Selection State SAFE FUNCTION CODE: SELECTION
SAFE DATA: SLOT NUMBER (first part of cycle~
~ATA PLACED ON BUS: STATUS (last part of cycle) PAL STATE BEFORE STROBE: Nothing 10 PAL STATE AFTER STROBE: NEW ME
All data transfers begin with a safe function code for Selection (0001), while the device address is present on safe address leads 4-7. The ME
15 SAFE signal is decoded and presented to the drive side array 32 logic.
The PAL logic implements a state machine which decodes the fact that ME SAFE has been asserted, the fact that a Select function code is 20 present, and the fact that the logic itself is not asserting any of its outputs, to create a state called NEW ME, which it enter on the rising edge of the next STROB~.

25 Accçp~ing the High Byte of Address SAFE FUNCTION CODE: IDLE
SAFE DATA: Status that devices was driving (stored in multiplexors ~40A and 240~) PAL STATE BEFORE STROBE: NEW ME
30 ~A~ STATE AFTER STROBE: LD ~I
With reference to Figure 24, when the rising edge of STROBE occurs, the PAL enters the ~D HI
state, asserting a signal called LOAD HI*. This 35 signal causes SAFE DATA 0-7 to be recorded on the rising edge of the next STROBE, i.e., the one that terminates the LD HI state.

,~ .

- 78 - 13234~

The lower four bits of the binary counter have outputs A16-Al9 and are part of the 23-bit address for data transfers, although bits A16-A18 have another purpose which will be described shortly.
The upper four bits of the counter are called A20-A~2 and P CONT~OL. If outputs Al9, A20, A21, A22, and P CONTROL contain the code 001, a decoder shown in Figure 25 is enabled. This decoder decodes address bits A16-A18 to create SET BROKEN*, 10 CLR BROKEN*, TOGGLE OBEY Q*, TOGGLE QBEY P*, CLEAR
INTERRUPT~, and DO RESET*. The set and clear of BROKEN go to the BROKEN flip-flop (see Figure 32).
If the device 24 associated with this interface has set the Interrupt Reguest bit (by 15 asserting SET INT), a processor 10, 12 can clear that by sending a "P CONTROL COMMAND" that will assert CLEAR INTERRUPT*. When CLEAR INTERRUPT~ has been asserted (low), the ne2t rising edge of STROBE will clear the STATUS OUT 6 (Interrupt Request) 20 flip-flop. The flip-flop is arranged so that it will not be cleared unless it is already set. This prevents a race condition in which issuance of CLEAR
INTERRUPT~ might clear the flip-flop as it was in the process of being set.
The DO RESET* signal clears a binary shifter, as illustrated in Figure 35. RESET~ will be asserted (low) until three more STROBE assertions have been received. The shi~ter is then disabled until the next occurrence of DO RESET~.
.Ac~p~ing the Middle Bvte of Address SAFE FUNCTION CODE: WRITE
SAFE DATA: Hiqh Address Byte : .: ' .

_ 79 _ 1323443 PAL STATE BEFORE STROBE: LD HI
PAL STATE AFTER STROBE: LD MID
Assuming that a P CONTROL operation did not 5 occur, the PAL state machine of Figure 27 w;ll continue processing the data transfer. (~n the cases of RESET and SET BROKEN, the hardware will not step to LD MID. In the other cases, the function codes normally used in those cases are inappropriate for LD
10 MID.
The PAL determines that it is in the LD HI
state, not in any other state, and that a WRITE
functi~n code (0010) i~ present. From these conditions it will enter the LD MID state on the 15 rising edge of STROBE.
When the rising edge of STROBE occurs, the logic records the high address information in latches that were conditioned during LD HI state. The logic enters the LD MID state, asserting a signal called LD
20 MID*. This signal prepares two binary counters to record SAEE DATA 0-7 on the rising edge of the next STRQBE, i.e., the one that terminates the LD MID
state.

~5 Acceptinq the Low Byte of Address SAFE FUNCTION CODE: WRITE
SAFE DA~A: Middle Address Byte PAL STATE BEFORE STROBE: LD MID
PAL STATE AFTER STROBE: LD LOW
The logic determines that it is in the LD
MID state, and that a WRITE function code ~0010) is present. From these conditions, it will enter the LD
LOW state on the rising edge o~ STR9BE.
When the rising edge of STROBE occurs, this records the middle address information in the $

- 80 - 1323~43 aforementioned latches, which were conditioned during LD MID state. The logic enters the LD LOW
state, assertin~ a signal called LD LOW*. This siqnal prepares two binary counters to record S~FE
5 DATA 0-7 on the rising edge of the next ST~OBE, i.e., the one that terminates the LD LOW state.

Achievinq the "SELECTED~ State SAFE FUNCTION CODE: WRITE
10 SAFE DATA: Low Address Byte PAL STATE BEFORE STROBE: hD LOW
PAL STATE AFTER STROBE: NEW ME AND SELECTED
The logic determines that it is in the LD
15 LOW state, and that a WRITE function code (0010) is present. From these conditions, it will enter the NEW ME and SELECTED state on the rising edge of STROBE.
The function code and data sequence common 20 to all data transfers is now complete. The STROBE
that causes the logic to enter the NEW ME and SELECTED states also records the low byte of address information into the latches, which were conditioned during the LD LOW state.
2~
Preparation for Data Reads and Writes SAFE FUNCTION CODE: WRITE (Write operation) or IDLE
(Read operation) SAFE DATA: Data to be written (Write operation) or 30 Nothing ~Read operation) PAL STATE BEFORE STRO~E: NEW ME AND SELECTED
PAL STATE AFTER STROBE: SELECTED
The PAL to remain in the SELECTED state a 35 long as it is in the NEW ME and SELECTED state (only), MAXE ERROR Tl is not asserted, and a IDLE or WRITE function code is present.

.

~ '` ` ` ' .

1 323~3 The STROBE that causes the PAL to change from the NEW ME and SELECTED state to only the SELECTED state increments the address counter indicating that the supplied data has been recorded 5 (WRITE cycle) or that the desired data has been obtained (READ cycle). In the case of the READ
cycle, the desired data will be placed on the bus during the ne~t cycle.

l0 Data Reads and Writes SAFE FUNCTION CODE: WRITE (Write operation) or READ
(Read operation) SAFE DATA: Data to be written into device (Write operation, or 15 DATA PLACED ONTO BUS: Data obtained from device on previous cycle (Read operation) PAL STATE BEFORE STROBE: SELECTED
PAL ~TATE AFTER STROBE: SELECTED
Once the PAL is no longer in the joint NEW
ME / SELECTED state, an additional term in the PAL
equation for SELECTED permits the device to stay in the SELECTED state so long as READ (00ll) or WRITE
(00l0) function codes occur and no error states are 25 entered.
STROBE records the SAFE DATA received from the P BUS or Q BUS during writes and changes the data gated out to the P BUS and Q ~US during reads.

30 Enterinq the ~rror Stat~ -If upon the assertion of STROBE, the latched P and Q data and~or function codes are of correct par~ty, but dif~er~n~ values, or if neither P nor Q
produced correct parity, logic which detects this on 35 the ~rive side array 32 or check ~ide array 34 will assert ~AKE ERROR Tl~ or MAKE ERROR Tl C*

:: :

.
' ~ ' -.

1 323~43 respectively. The assertion of MAKE E~ROR Tl~ will cause a WAIT ~equest to be assert~d on the bus. The WAIT request allows the STROBE pulse to complete at the normal ~ime, but the nest rising edge of STROBE
5 is delayed for 16 microseconds.
The following table shows the conditions that can lead to the assertion of MAKE E~ROR Tl* and ~XE ERROR Tl C*:
D-Latch C-Latch D-Latch 10 Parity Parity C-Latch S~atus ~ Comp2~e ~Ç~IQ~
Fail Fail ---- MAKE ERROR Tl*
Pass Pass Fail MAKE ERROR Tl~
(---- = don't care) If BROXEN* is not asserted, the trailing edge of the STROBE w;ll record the assertion of MAKE
20 ERROR Tl* to create a "sub-state" that will last until the next trailing edge of STROBE. This sub-state is called E~ROR Tl, and will be fairly long because of the assertion of WAIT.
ERROR Tl places an all-l's pattern on both 25 the P bus data and the P bus function code lines. It accomplishes this as follows:
1. ERROR Tl and NOT ~ROKEN create DRIVE*
enabling PDATA OUT 0-7 D to the P bus 30A, 2. ERROR Tl causes SEND DATA* to be high, causing DATA OUT 0-7 to be connected to PDATA OUT 0-7.
3. ERROR Tl brings DATA OUT 0-7 to the all-l's state.
4. ERROR Tl, combined with the all-l's data will cause the ~EVEN~ output of the parity generator to be LOW, causing the associated 74F02 output to be ~IGH
when DRIVE* is asserted, causing an , - . ' . .

- 83 - 1323~3 assertion of the DATA PARITY ~it on the P Bus 30A as long as the interface is not BROKEN.
5. ERROR Tl enables a transceiver on Figure 16 to directly place an all-l's condition onto the P bus function code leads.

6. ERROR Tl is used as a direct input in~o the transceiver which will place a 1 on the Function Code Parity line of the P
bus 30A as long as the interface isn't BROKEN.
The ne~t assertion of STROBE will latch new data (all l's) into the drive and check latches of Figure 16, and will place the drive side array 32 PAL in the ERROR SEQUENCE state, since MAKE ERRO~ Tl*
20 is still asserted based on the data stored in the Drive and Check latches at the time of the STROBE.
The ERROR Tl sub-state still exists because it is clocked on the trailing edge of STROBE.
During the transition to the ERROR
25 SEQUENCE/ERROR T3 state, the controller 18, 20 continues to place an all l's pattern on the P bus.
This will continue until part way through the ERRO~
SEQUENCE i ERROR T3 state.
The next assertion of STRO~E will place the 30 driYe side array 32 PAL in a null state, with only OBEY P* possibly asserted.

Normal Operation ~Including Bad Parity on One Side PAL equation: OBEY_P = OBEY_P ~ /MAKE ERROR
Tl * ~ERR_SEQ * ~ESET (See Appendi~ 2 - Differences between PAL notation and text notation).
The D-Side o~ the interface is arranged ~o 40 prefer to get its data from the P BUS. The C-Side o D

.

, :

- 8~ -the interface is arranged to prefer to get its data from the Q BUS. Continuing to use the drive side array 32 as an example, the control P~L on the drive side array 32 usually asserts OBEY P*, a signal 5 which keeps the ~rive Latch connected to the P BUS.
In normal operation, the drive side array 32 control PAL will continue to assert OBEY P as long as MAKE
ERROR Tl, ERROR SEQU~NCE, and RESET~ are not asserted.
The following table outlines normal 10 operation and the cases where the D-latch or the C-latch have bad parity~
D-Latch C-Latch D-Latch Parity C-Latch Parity OBEY P* SourcQ Status OBEY O* Source _tatus ACTION
Assert P BUS OK Assert QBUS OK MAKESAFE
D = D
C = C
0 Assert P BUS Fail Assert QBUS OK MAKESAFE
D = C
C = C
~ssert P BUS OK Assert QBUS Fail MAKESAFE
D - D
C = D
~The table does not mention data and function code separately, but the MAKESAFE determination is made 0 separately, as was discussed previously.) Data Inteqrity Checks During th~ Erro~-Handling SequencQ
As was indicated previously, circumstances beyond a simple parity error on one side of the interface will cause the assertion of MAKE ERROR Tl*, MAKE ERROR Tl C* signals which will cause the interace to step through the error-handling seguence 40 described.

- ' ` ` .

- 85 - 1 32 3 4 4 ~
O~ three occasions during the error-handling sequence, test pattern data will be placed on the bus:
1. In preparation for the STROBE that occurs at the beginning of ERROR
S SEQUENCE (i.e., during ERROR Tl) 2. In preparation for the STROBE that occurs at the beginning of E~ROR T3.
3. In preparation for the STRO~E that occurs at the end o ERROR T3.
In the first case, the interface is placing all-l's on the bus. In the second case, the i/o 15 controllers 18, 20 is placing all-l~s on the bus. In the last case, no one is placing anything on the bus, and it should be all-0's.
When an assertion of STROBE occurs, the PAL
may enter a new "OBEY" condition, based on the 20 results of the test.

Checking for the All-Ones Condition During ERR~R Tl Sequen~e 25 PAL: OBEY_P - ERR_Tl_DEL D * CHK_OK P ~ WAIT I~ P *
/RESET
OBEY_Q = ERR_Tl_DEL C ~ CHK_OK Q ~ WAIT_IN Q
/RESET
The illustrated circuitry checks:for an all l's condition when the interface is not in the ERRO~
T3 state.
If both OBEY P~ and OBEY Q* were asserted, both buses were in use and an error occurred. If the 35 P bus ~ail~ its check, the first equation above will not allow continued operation of OBEY P*. ~If the Q ~ :
bus fails its check, the second eqùation above~will not allow continued operation of OBEY Q~
If only OBEY P~ was asserted, only the:~P bus 40 was in use. Therefore, the first:equation w~ fail ~ ~ :

:

.

- , - . . . . ~ , , - ~6 - 1323443 because OBEY Q~ was not asserted. The second equation will check the Q bus to see if OBEY Q*
should be asserted such that data transfer now uses the Q bus.
If only O~EY Q* was asserted, only the Q bus was in use. Therefore, the second equation will fail because OBEY P~ was not asserted. The first eguation will check the P BUS ~o see iÇ OBEY pe should be asserted such that data transfer now uses thP P BUS.
In each of the a~ove equations, the CHECK OX
test is performed during the ERROR Tl time (MAKE
ERRO~ Tl and NOT ERROR SEQUENCE) for the side of the interface appropriate to the bus being checked.
If neither bus passes its test, neither OBEY
15 will be asserted on the next assertion of STROBE, and the interface will then go BROKEN.

Checking for the All-Ones Condition Durin~ the Error T2 Sequence PAL equations: OBEY_P = OBEY_P * CHK_OK P * ERR SEQ
D * /WAIT_P * /RESET 2 ERR_T2 D
OBEY_Q = OBEY_Q ~ CHK_OK Q * ERR_SEQ
C ~ /WAIT_Q ~ ~RESET ~ ERR T2 C
There are two data checks performed during ERROR SEQUENCE. An all-l's check at the mid-point (which is the beginnin~ of ERROR SEQUENCE / ERROR T3) and an all-0's check at the end.
Each data check is performed by the check circuitry located in the illustration. The l's check takes place at the time of the STROBE which will take the inter ace into E~RO~ T3 state.

~ . .,; . :

.
- . . . :. -' ,,.
, - 87 - 13234~3 Checking for the All-Zeros Condition During the Error T3 SeqUence PAL Equations: OBEY_P = OBEY_P * CHECK_OK P ~
ERR_SEQ D ~ /WAIT_P * /RESET *
ERR_T3 D
OBEYQ = OBEYQ * CHECK_OX Q ~
ERR_SEQ C * ~WAIT_Q * /RESET *
ERR_T3 D
The 0's check takes place at the time of the STROBE which will take the interface out of the ERROR
T3 state. In each case, if the check is OK, and the WAIT signal is negated (it was supposed to be turned 15 off at the end of ERROR Tl, the OBEY output assertions of the PALS remains unchanged when the next assertion of STROBE occurs.

Other Ways in Which NBus Obedience" Get Chanqed 20 PAL Equations: OBEY_P = /OBEY_P * TOGGLE * ~RESET
OBEY_P = ~OBEY_P ~ /OBEY Q ~ /RESET
OBEY_Q = /OBEY_Q * TOGGLE * /RESET
OBEY_Q = /OBEY Q * /OBEY P * /RESET
The drive side array 32 control PAL
monitors the OBEY P*, OBEY Q* and TOGGLE OBEY P* for the following additional conditions (assuming no RESET):
1. If the OBEY P* signal is not presently asserted, and a toggle request occurs, OBEY P* qets asserted on the next assertion of STROBE.
2. If the OBEY P* signal is not presently asserted, and OBEY Q* isn't asserted either, OBEY P* gets asserted on the next assertion of STROBE.

40 Driving Data onto the P BUS and QBUS
Data is driven onto the bus when DRIVE* is low. The DRIVE* signal is low when the folIowing conditions are true:

::

Error Tl AND Not sroken or: Fu~ction Code 0011 (Read) AND Selected AND Not Broken or: Function Code 0001 ~Select~ AND Me The first term is used to place all l's on the bus during ERRO~ Tl state. The second term is the normal data reading case. The third term is the status reportins case immediately after transfer 10 begins.

Broken The BROKEN signal is generated by latching COMPARE OK* on the leading ~falling) edge of 15 STROBE*. The signal COMPARE OK~ is asserted if any of the following conditions becomes true:
1 The XOR of Data Out 0-7 with Data Out 2 or: the XOR of Drive D* with Drive C*
3 or: the XOR of Error Tl D* with Error Tl C*
4 or: the XOR of Error Tl D with Error Tl C
or: the XOR of PDATA PAR OUT D with PDATA
PA OUT C
6 or: the XOR of WAITOUT D with WAITOUT C

7 or: (the XOR of OBEY P* with OBEY Q*) AND
(PFC IN EQ* or PDATA IN EQ*~ .

8 or: OBEY P~ AND OBEY Q*

9 or: GIOC (controller 18, 20) SET BROKEN
or: DEVICE GO BROXEN
Term 1: If the data that the drive side array 32 of the interface would like to put on the bus and the data which the check side array 34 would like to put on the ~us do not agree, the interface is BROKEN.
T~rm 2: If one side of the interface would like to drive data onto the bus, but the ot~er side would not, the interface is BROKEN, Terms 3 and 4: If the ~wo sides of the interface disagree as to whether or not they are in the ERROR Tl sub-state, the interface is BROKEN.
4~

~' ` ' .

Term 5: If the parity of the data tha~ the drive side array 32 of the interface would like to put on the bus and the parity of the data which the check side array 34 would like to put on the bus do not agree, the interface is BROKEN.
Term h: If one side of the in~erface is requesting a bus WAIT, but the other is not, the interface is BROKEN.
Term 7: If only one of the OsEY signals is asserte~, the data is all being received from one bus. If the data or func~ion code information received from that bus is inconsistent on the two sides of the interface, the interface must be BROKEN.
Term 8: If neither OBEY signal is asserted, the interface is BROKEN. This situation is usually the result of complete test failure during an ERROR SEQUENCE.
Term 9: If the controll~r 18, 20 to which the interface connects desires to take the interface off-line, it can do so by asserting this signal.
Term 10: If the device to which the interface connects desires to take the interface off-line, it can do so by asserting this signal.

Appendices A and B, submitted with copending, commonly assigned application Serial No. 6n~anh~Attorney Doc~et No~ SCM-041CA, ~iled on the same day herewith, provide further hardware and software specifications for the fault-tolerant 40 peripheral cont`rol system described above and, particularly, for the i/o controllers 18, 20, the gate arrays 32, 34, and the adaptors q4.

f~

,` .. . ~.
: ~ . ;~ .: , .

. . ~

- : , -- ,' , . ' , ' '. :

It will thus be seen that the objects set forth above, among those made apparent rom the preceding description, are efficiently attained. It will be understood that changes may be made in the 5 above constructions and in the foregoing sequences of operation without departing from the scope of the invention. It is accordingly intended that all matter contained in the above description or shown in the accompanying drawing be interpreted as 10 illustrative rather than limiting in sense.

B
, . . - ` .

:
.
. . . .
.

Claims (48)

1. In a digital data processor having a peripheral device controller for communicating with one or more peripheral devices connected along a common peripheral device bus, wherein each said peripheral device can include device interface means for transferring information-representative signals between the associated peripheral device and the peripheral bus means, the improvement wherein A. said peripheral bus includes first and second input/output buses each for carrying information-representative signals, including at least one of data, address, control, and timing signals, B. said peripheral device controller includes strobe means connected with said first and second input/output buses for normally transmitting thereon duplicative, synchronous and simultaneous strobe signals, said strobe signals defining successive timing intervals for information-representative signal transfers along said first and second input/output buses, C. said peripheral device controller includes controller transfer cycle means, coupled to said first and second input/output buses, for controlling the execution of information transfer cycles for transferring information-representative signals between said peripheral device controller and said peripheral devices on said first and second input/output buses, D. said controller transfer cycle means including controller cycle initiation means connected with said first and second input/output buses for initiating said information transfer cycles, said controller cycle initiation means including means for normally transmitting during a first said timing interval, duplicatively and synchronously on said first and second input/output buses, a first status signal indicative of cycle initiation, E. said controller cycle initiation means further including means for normally transmitting during said first timing interval, duplicatively and synchronously on said first and second input/output buses, a second status signal indicative of at least one said peripheral device to be addressed during the information transfer cycle, F. said one or more peripheral devices including means for detecting a selected fault condition during execution of said information transfer cycle and for generating a WAIT signal in response thereto, and G. said peripheral device controller including means responsive to said WAIT signal for delaying transmission of further information-representative signals, including strobe signals, by said peripheral device controller along said first and second input/output buses.

2. In a digital data processor according to claim 1, the further improvement wherein said controller transfer cycle means includes i. controller scanner cycle means, coupled to said peripheral device bus, for executing a scanner cycle to determine an operational state of at least one said peripheral device connected to said common peripheral bus, ii. controller read cycle means, coupled to said peripheral device bus, for executing a read cycle to effect the transfer of data signals from the peripheral device to the peripheral device controller, iii. controller write cycle means, coupled to said peripheral device bus, for executing a write cycle to effect the transfer of data signals from the peripheral device controller to at least one said peripheral device, and iv. controller command cycle means, coupled to said peripheral device bus, for executing a command cycle for controlling other selected operations of at least one said peripheral device connected to said common peripheral bus.

3. In a processor according to claim 1, the further improvement wherein said controller cycle initiation means includes means for receiving, in absence of error and during a second said timing interval, duplicatively and synchronously on said first and second input/output buses, a third status signal, said second timing interval being subsequent to said first timing interval, said third status signal including at least one of i) a signal indicative of an operational state of a peripheral device addressed in said first timing interval, ii) a signal indicative of a request associated with the addressed peripheral device, and iii) a bus status signal indicative of fault detected in at least one of said first and second input/output buses.

4. In a processor according to claim 3, the further improvement wherein said controller command cycle means includes means for transmitting duplicatively and synchronously on said first and second input/output buses a command signal during a third timing interval, said third timing interval being subsequent to said second timing interval.

5. In a processor according to claim 4, the further improvement wherein said controller write cycle means includes means for transmitting duplicatively and synchronously on said first and second input/output buses and during said third timing interval at least a portion of a data write address, said data write address portion being transmitted in lieu of said command signal.

6. In a processor according to claim 5, the further improvement wherein said controller write cycle means includes means for transmitting synchronously and duplicatively on said first and second input/output buses peripheral device write data during one or more timing intervals subsequent to said third timing interval, said controller write cycle means further including means for concurrently transmitting synchronously and duplicatively on said first and second input/output buses a write signal during each timing interval in which write data is transmitted.

7. In a processor according to claim 3, the further improvement wherein said controller read cycle means includes means for transmitting synchronously and duplicatively on said first and second input/output buses at least a portion of a data read address during said third timing interval, said read data address portion being transmitted in lieu of said command signal.

8. In a processor according to claim 7, the further improvement wherein said controller read cycle means includes means for receiving, in absence of error, synchronously and duplicatively on said first and second input/output buses read data from said peripheral device during one or more timing intervals subsequent to said third timing interval, said controller read cycle means further including means for transmitting synchronously and simultaneously on said first and second input/output buses one or more read signals, each normally being associated with the transmission of data by the addressed peripheral device in a subsequent timing interval.

9. In a processor according to claim 8, the further improvement wherein i) said second timing interval immediately follows said first timing interval, ii) said third timing interval immediately follows said second timing interval, iii) said controller write cycle means includes means for transmitting synchronously and duplicatively on said first and second input/output buses remaining portions of said write data address during fourth and fifth timing intervals, said write cycle means further including means for beginning transmission of said one or more write data signals during a sixth timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and iv) said controller read cycle means includes means for transmitting synchronously and simultaneously on said first and second input/output buses remaining portions of said read data address during fourth and fifth timing intervals, said read cycle means further including means for beginning transmission of said one or more read signals during a seventh timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and said seventh following sixth.

10. In a processor according to claim 7, the further improvement wherein each of said first and second input/output buses includes a data signal conductor set and a control signal conductor set, and wherein i) said controller cycle initiation means includes means for transmitting said first status signal on said control signal conductor set and includes means for transmitting said second status signal on said data signal conductor set, ii) said controller cycle initiation means further includes means for receiving said STATUS
signal on said data signal conductor set, iii) said controller command cycle means includes means for transmitting said command signal on said data signal conductor set, and iv) said controller write cycle means and said read cycle means include means for respectively transmitting said write signals and said read signals on said control signal set and further include means for respectively transmitting said write data and receiving read data on said data signal conductor set.

11. In a processor according to claim 1, the further improvement wherein said strobe means includes strobe delay means responsive to assertion of a wait signal received on at least one of said first and second input/output buses for delaying generation of said strobe signal.

12. In a processor according to claim 11, the further improvement wherein said peripheral device controller includes error handling means responsive to assertion of said wait signal for a time period greater than a designated time period for entering an operational state for identifying a source of bus transmission error.

13. In a processor according to claim 12, the further improvement wherein said error handling means comprises means for transmitting synchronously, simultaneously and duplicatively on said first and second input/output buses during a designated error-handling time interval an error-checking data signal.

14. In a digital data processor according to claim 1, the further improvement wherein A. each said peripheral device includes an associated peripheral device adaptor providing an interface between the peripheral device and the peripheral device bus, and wherein said peripheral device adaptor includes adaptor transfer cycle means, coupled to said first and second input/output buses, for normally transferring and receiving information-representative signals synchronously, simultaneously and duplicatively on said first and second input/output buses, B. said adaptor transfer cycle means including adaptor cycle initiation means connected with said peripheral device bus for receiving, in absence of error, during said first timing interval duplicatively, synchronously, and simultaneously on said first and second input/output buses said first status signal, C. said adaptor cycle initiation means including means for receiving, during said first timing interval and in absence of fault, duplicatively, synchronously, and simultaneously on said first and second input/output buses, said second status signal.

15. In a digital data processor according to claim 14, the further improvement wherein said adaptor transfer cycle means includes i. adaptor scanner cycle means, coupled to said peripheral device bus, for executing an adaptor scanner cycle for effecting the transfer of a signal representative of an operational state of a selected peripheral device connected, ii. adaptor command cycle means, coupled to said peripheral device bus, for executing a adaptor command cycle to accept peripheral device control information-representative signals from the first and second input/output buses, iii. adaptor read cycle means, coupled to said peripheral device bus, for executing an adaptor read cycle to effect the transmission data from the associated peripheral device to the first and second input/output buses, iv. adaptor write cycle means, coupled to said peripheral device bus, for accepting write data from the first and second input/output buses.

16. In a processor according to claim 14, the further improvement wherein said adaptor cycle initiation means includes means for transmitting during a second said timing interval, duplicatively, synchronously, and simultaneously on said first and second input/output buses, a third status signal, said third status signal including at least one of i) a signal indicative of an operational status of said associated peripheral device, ii) a signal indicative of a pending interrupt, and iii) a bus status signal indicative of fault detected in at least one of said first and second input/output buses.

17. In a processor according to claim 16, the further improvement wherein said adaptor command cycle means includes means for receiving, in absence of error, duplicatively, simultaneously, and synchronously on said first and second input/output buses a command signal during a third timing interval.

18. In a processor according to claim 17, the further improvement wherein said adaptor write cycle means includes means for receiving, in absence of error, duplicatively, synchronously, and simultaneously on said first and second input/output buses at least a portion of a data write address, said data write address portion being received during said third timing interval and in lieu of said command signal.

19. In a processor according to claim 18, the further improvement wherein said adaptor write cycle means includes means for receiving, in absence of fault, synchronously, simultaneously, and duplicatively on said first and second input/output buses peripheral device write data during one or more timing intervals subsequent to said third timing interval, said adaptor write cycle means further including means for concurrently receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses a WRITE signal during each timing interval in which write data is received.

20. In a processor according to claim 19, the further improvement wherein said adaptor read cycle means includes means for transmitting, synchronously, simultaneously, and duplicatively on said first and second input/output buses read data from said peripheral device, said read data being transmitted during one or more timing intervals subsequent to said third timing interval, said adaptor read cycle means further including means for receiving, in absence of error, synchronously, duplicatively, and simultaneously on said first and second input/output buses one or more read signals, each normally being associated with the transmission of read data in a subsequent timing interval.

21. In a processor according to claim 20, the further improvement wherein i) said second timing interval immediately follows said first timing interval, ii) said third timing interval immediately follows said second timing interval, iii) said adaptor write cycle means includes means for receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses remaining portions of said write data address during fourth and fifth timing intervals, said adaptor write cycle means further including means for beginning transmission of said one or more write data signals during a sixth timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and iv) said adaptor read cycle means includes means for receiving, in absence of error, synchronously, duplicatively, and simultaneously on said first and second input/output buses remaining portions of said read data address during fourth and fifth timing intervals, said adaptor read cycle means further including means for beginning transmission of said one or more read signals during a seventh timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and seventh following sixth.

22. In a processor according to claim 18, the further improvement wherein said adaptor read cycle means includes means for receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses at least a portion of a data read address during said third timing interval, said data read address portion being received in lieu of said command signal.

23. In a processor according to claim 22, the further improvement wherein each of said first and second input/output buses includes a data signal conductor set and a control signal conductor set, and wherein i) said adaptor cycle initiation means includes means for receiving said first status signal on said control signal conductor set and includes means for receiving said second status signal on said data signal conductor set, ii) said adaptor cycle initiation means further includes means for transmitting said third status signal on said data signal conductor set, iii) said adaptor command cycle means includes means for receiving said command signal on said data signal conductor set, and iv) said adaptor write cycle means and said adaptor read cycle means include means for respectively receiving said write signals and said READ signals on said control signal set and further include means for respectively receiving said write data and transmitting read data on said data signal conductor set.

24. In a processor according to claim 14, the further improvement comprising fault detection means comprises means responsive to selected fault for transmitting synchronously, simultaneously, and duplicatively on said first and second input/output buses at least one of an error-checking data signal and an error-checking control signal.

25. In a method for operating a digital data processor having a peripheral device controller for communicating with one or more peripheral devices connected along a common peripheral device bus, wherein each said peripheral device can include device interface means for transferring information-representative signals between the associated peripheral device and the peripheral bus means, the improvement comprising the steps of A. providing first and second input/output buses each for carrying information-representative signals, including at least one of data, address, control, and timing signals, between said peripheral device controller and said one or more peripheral devices, B. transmitting on said first and second input/output buses duplicative, synchronous and simultaneous strobe signals, said strobe signals defining successive timing intervals for information-representative signal transfers along said first and second input/output buses, and C. transferring, in the absence of selected fault, information-representative signals synchronously, simultaneously and duplicatively on said first and second input/output buses, D. initiating said information transfer cycles by normally transmitting during a first said timing interval, duplicatively and synchronously on said first and second input/output buses, a first status signal indicative of cycle initiation, E. normally transmitting during said first timing interval, duplicatively and synchronously on said first and second input/output buses, a second status signal indicative of at least one said peripheral device to be addressed during the information transfer cycle, F. detecting a selected fault condition during said transfer of information-representative signals on said peripheral bus means and generating a WAIT signal in response thereto, and G. responding to said WAIT signal for at least temporarily delaying the continued transmission of information-representative signals, including strobe signals, by said peripheral devices controlled on said first and second input/output buses.

26. In a method according to claim 25, the further improvement comprising the step of executing at least one step selected from the steps of A. a scanner cycle step for determining an operational state of at least one said peripheral device connected to said common peripheral bus, B. a read cycle step for effecting the transfer of data signals from the peripheral device to the peripheral device controller, C. a write cycle step for effecting the transfer of data signals from the peripheral device controller to at least one said peripheral device, and D. a command cycle step for controlling other selected operations of at least one said peripheral device connected to said common peripheral bus.

27. In a method according to claim 26, the further improvement wherein each of said scanner cycle, command cycle, read cycle, and write cycle steps comprising the steps of A. transmitting, during a first timing interval, duplicatively and synchronously on said first and second input/output buses a first status signal indicative of cycle initiation, and B. transmitting, in the absence of error and during said first timing interval, duplicatively and synchronously on said first and second input/output buses, a second status signal indicative of at least one said peripheral device to be addressed during the information transfer cycle.

28. In a method according to claim 25, the further improvement wherein said command cycle step comprises the step of transmitting duplicatively and synchronously on said first and second input/output buses a command signal during a third timing interval, said third timing interval being subsequent to said second timing interval.

29. In a method according to claim 28, the further improvement wherein said write cycle step comprises the step of transmitting duplicatively and synchronously on said first and second input/output buses and during said third timing interval at least a portion of a data write address.

30. In a method according to claim 29, the further improvement wherein said write cycle step comprises the steps of A. transmitting synchronously and duplicatively on said first and second input/output buses peripheral device write data during one or more timing intervals subsequent to said third timing interval, and B. transmitting synchronously and duplicatively on said first and second input/output buses a write signal during each timing interval in which write data is transmitted.

31. In a method according to claim 25, the further improvement wherein said read cycle step comprises the step of transmitting synchronously and duplicatively on said first and second input/output buses at least a portion of a data read address during said third timing interval, said read data address portion being transmitted in lieu of said command signal.

32. In a method according to claim 31, the further improvement wherein said read cycle step comprises the steps of A. receiving, in absence of error, synchronously and duplicatively on said first and second input/output buses read data from said peripheral device during one or more timing intervals subsequent to said third timing interval, and B. transmitting synchronously and simultaneously on said first and second input/output buses one or more read signals, each normally being associated with the transmission of data by the addressed peripheral device in a subsequent timing interval.

33. In a method according to claim 32, wherein said second timing interval immediately follows said first timing interval, and said third timing interval immediately follows said second timing interval, the further improvement wherein A. said write cycle step comprises the additional step of transmitting synchronously and duplicatively on said first and second input/output buses remaining portions of said write data address during fourth and fifth timing intervals, and initiating transmission of said one or more write data signals during a sixth timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and wherein B. said read cycle step comprises the additional step of transmitting synchronously and simultaneously on said first and second input/output buses remaining portions of said read data address during fourth and fifth timing intervals, and initiating transmission of said one or more read signals during a seventh timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and said seventh following sixth.

34. In method according to claim 31, wherein each of said first and second input/output buses includes a data signal conductor set and a control signal conductor set, the further improvement comprising the steps of A. transmitting said first status signal on said control signal conductor set and transmitting said second status signal on said data signal conductor set, B. receiving said STATUS signal on said data signal conductor set, C. transmitting said command signal on said data signal conductor set, and D. transmitting said write signals and said read signals on said control signal set and transmitting said write data and receiving read data on said data signal conductor set.

35. In a method according to claim 25, the further improvement comprising the step of responding to assertion of a wait signal received on at least one of said first and second input/output buses for delaying generation of said strobe signal.

36. In a method according to claim 35, the further improvement comprising the step of responding to assertion of said wait signal for a time period greater than a designated time period for entering an operational state for identifying a source of bus transmission error.

37. In a method according to claim 36, the further improvement comprising the step of transmitting synchronously, simultaneously and duplicatively on said first and second input/output buses during a designated error-handling time interval an error-checking data signal.

38. In a method according to claim 25, the further improvement comprising the steps of A. receiving, in absence of error, during said first timing interval duplicatively, synchronously, and simultaneously on said first and second input/output buses said first status signal, and B. receiving, during said first timing interval and in absence of fault, duplicatively, synchronously, and simultaneously on said first and second input/output buses, said second status signal.

39. In a method according to claim 38, the further improvement wherein said information cycle executing step comprises at least one step selected from the steps of A. an adaptor scanner cycle step for effecting the transfer of a signal representative of an operational state of a selected peripheral device connected, B an adaptor command cycle step for accepting peripheral device control information-representative signals from the first and second input/output buses, C. an adaptor read cycle step for effecting the transmission data from the associated peripheral device to the first and second input/output buses, and D. an adaptor write cycle step for accepting write data from the first and second input/output buses.

40. In a method according to claim 38, the further improvement wherein each of said adaptor scanner, command, read, and write cycle steps comprises the step of transmitting during a second said timing interval, duplicatively, synchronously, and simultaneously on said first and second input/output buses, a third status signal, said third status signal including at least one of i) a signal indicative of an operational status of said associated peripheral device, ii) a signal indicative of a pending interrupt, and iii) a bus status signal indicative of fault detected in at least one of said first and second input/output buses.

41. In a method according to claim 40, the further improvement wherein said adaptor command cycle step comprises the step of receiving, in absence of error, duplicatively, simultaneously, and synchronously on said first and second input/output buses a command signal during a third timing interval.

42. In a method according to claim 41, the further improvement wherein said adaptor write cycle step comprises the step of receiving, in absence of error, duplicatively, synchronously, and simultaneously on said first and second input/output buses at least a portion of a data write address, said data write address portion being received during said third timing interval.

43. In a method according to claim 42, the further improvement wherein said adaptor write cycle step comprises the steps of A. receiving, in absence of fault, synchronously, simultaneously, and duplicatively on said first and second input/output buses peripheral device write data during one or more timing intervals subsequent to said third timing interval, B. receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses a write signal during each timing interval in which write data is received.

44. In a method according to claim 43, the further improvement wherein said adaptor read cycle step comprises the steps of A. transmitting, synchronously, simultaneously, and duplicatively on said first and second input/output buses read data from said peripheral device, said read data being transmitted during one or more timing intervals subsequent to said third timing interval, and B. receiving, in absence of error, synchronously, duplicatively, and simultaneously on said first and second input/output buses one or more read signals, each normally being associated with the transmission of read data in a subsequent timing interval.

45. In a method according to claim 44, wherein said second timing interval immediately follows said first timing interval, said third timing interval immediately follows said second timing interval, the further improvement wherein A. said adaptor write cycle step comprises the steps of receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses remaining portions of said write data address during fourth and fifth timing intervals, initiating transmission of said one or more write data signals during a sixth timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and wherein B. said adaptor read cycle step comprises the steps of receiving, in absence of error, synchronously, duplicatively, and simultaneously on said first and second input/output buses remaining portions of said read data address during fourth and fifth timing intervals, initiating transmission of said one or more read signals during a seventh timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and seventh following sixth.

46. In a method according to claim 42, the further improvement wherein said adaptor read cycle step comprises the step of receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses at least a portion of a data read address during said third timing interval.

47. In a method according to claim 46, wherein said first and second input/output buses each include a data signal conductor set and a control signal conductor set, the further improvement comprising the steps of A. receiving said first status signal on said control signal conductor set and includes means for receiving said second status signal on said data signal conductor set, B. transmitting said third status signal on said data signal conductor set, C. receiving said command signal on said data signal conductor set, and D. receiving said write signals and said read signals on said control signal set and further include means for respectively receiving said write data and transmitting read data on said data signal conductor set.

48. In a method according to claim 38, the further improvement comprising the step of responding to selected fault for transmitting synchronously, simultaneously, and duplicatively on said first and second input/output buses at least one of an error-checking data signal and an error-checking control signal.