CA1314106C - Programmable logic system for filtering commands to a microprocessor - Google Patents
Programmable logic system for filtering commands to a microprocessorInfo
- Publication number
- CA1314106C CA1314106C CA000575359A CA575359A CA1314106C CA 1314106 C CA1314106 C CA 1314106C CA 000575359 A CA000575359 A CA 000575359A CA 575359 A CA575359 A CA 575359A CA 1314106 C CA1314106 C CA 1314106C
- Authority
- CA
- Canada
- Prior art keywords
- force
- commands
- signal
- microprocessor
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
Abstract
PROGRAMMABLE LOGIC SYSTEM FOR FILTERING
COMMANDS TO A MICROPROCESSOR
ABSTRACT
A system utilizing one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined criteria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a key-board controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.
COMMANDS TO A MICROPROCESSOR
ABSTRACT
A system utilizing one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined criteria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a key-board controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.
Description
131410~
COMW:116 PROGRAMMABLE LOGIC SYSTEM FOR FILTERING
COMMANDS TO A MICROPROCESSOR
This invention relates to regulating the operations of a microprocessor by the use of one or more programmable logic arrays or gate arrays for filtering of certain commands to the microprocessor. More particularly, it relates to the use of programmable logic arrays or gate arrays for monitoring commands to a keyboard controller in a personal computer based on either the INTEL 80286 or 80386 microprocessor, and intercepting certain of those commands relating to the FORCE-A20 and CPU-RESET signals.
In many popular personal computers based on the INTEL
80286 or 80386 microprocessor, there is a need for uti-lizing both real-address mode ("real mode") and protected mode. Real mode is used for initialization when first powered up, and mimicking of older 16-bit microprocessors, such as the INTEL 8086 family of microprocessors. In real mode, the 80286 or 80386 microprocessor uses segment and offset registers in the same way as the 8086 family to access the same one megabyte of memory. In real mode, the 16-bit instruction set, the segmented programming model, addressing mechanism, and one megabyte physical memory limitations are identical to those provided by the 8086.
~rA l ~
$
131410 ~
Thus the 80286 and 80386 microprocessors are compatible with the addressing scheme of the 8086 family.
In protected mode, the 80286 or 80386 microprocessor adds a series of features that allow it to safely and reliably expand the number of programs the computer can be working on at one time. This is accomplished through four main facilities: protection, extended memory, virtual memory, and multi-tasking. Protection allows the operat-ing system to erect barriers to prevent a program frominterfering with the operation of other programs or of the operating system itself. Extended memory greatly in-creases the amount of working memory beyond the 640 KB
actually available to the software. Virtual memory allows the computer to go further beyond the installed physical memory limitations by shifting data to and from remote memory, such as hard disk. Finally, with multi-tasking supported by the hardware, the 80286 or 80386 can swiftly and reliably switch among several programs that are running at the same time.
A basic difference between protected mode and real mode is that the protected mode segment register is no longer a real (i.e., physical) address. Instead, in protected mode, the 80286 or 80386 uses the upper (most significant) 14 bits of the segment register to look up a 24-bit base address (with the 80286) or a 32-bit base address (with the 80386) stored in a descriptor table in memory.
Additionally, with protected mode, segment registers define the way that memory is organized between tasks.
Each task has its own descriptor table describing the segments for that task. Since physical addresses are stored in the descriptor table rather than in the segment 131~10~
registers, the operating system can move memory around without application programs being affected.
Protected mode is so named because segments belonging to one task are protected from being corrupted by another task. Tasks are organized in privilege levels, and certain machine-code instructions are prohibited to lower privilege levels. In a well-designed protected mode operating system, a single program can neither crash the whole system nor get itself into an unrecoverable state.
Many personal computers based on the 80286 or 80386 microprocessors implement the "FORCE-A20" function. This function is necessary to maintain compatibility with software designed for systems based on the 8086 family of microprocessors.
The compatibility issue arises from the different memory address sizes available on the 8086, 80286, and 80386 chips. The 8086 had a one megabyte address range, with twenty address lines (A0-Al9) driven by the micro-processor. The total range was 2 raised to the 20th power, or 1,048,576 possible addresses (one megabyte). In contrast, the 80286 has 24 address lines, giving 16 megabytes of address range (2 raised to the 24th power);
the 80386 has 32 address lines, giving 4096 megabytes of address range (2 raised to the 32nd power).
The 8086 microprocessor uses a segmented memory addressing scheme. The effect of this scheme is to allow a software program to access only a 64 KB "window" out of the one megabyte total range. To access memory outside this window, the window's location must change, and this operation takes time.
13141~ ~
To access memory near the top of the one megabyte address space as well as memory near the bottom of the 8086's one megabyte address space, without moving the window, some software takes advantage of "memory wrap-around". This feature on the 8086 may be used when thebase of the 64 KB window is less than 64 KB from the 'op of the one megabyte address range, so the top of the window would extend beyond the highest possible address location. When the window is in such a position, these impossibly high addresses are simply "wrapped around" to low addresses, much in the same way that an odometer goes from 99,999 to 00,000 miles. Thus, software could access very high as well as very low addresses in the same window.
Since the 80286 and 80386 microprocessors have more than one megabyte of address range, these microprocessors do not wrap around memory addresses at one megabyte.
Instead, accesses to the part of the window above one megabyte are put out as actual addresses greater than one megabyte.
The difference between the old 8086 "wrapped around"
low addresses and the new 80286/80386 high addresses is that the new 80286/80386 microprocessors have extra address lines beyond Al9 (much like having extra digits on an odometer, so it doesn't wrap around after 99,999 miles). The first of these address lines on the 80286 or 80386 is A20, and it is set high for all addresses in the range from one megabyte to two megabytes (in the absence of the FORCE-A20 command). The A20 line is set low for addresses below one megabyte.
In real mode, the 80286 and 80386 microprocessors behave as much as possible like the 8086 microprocessors.
131~
Thus, in real mode the 80286 and 80386 cannot access memory above one megabyte. Because the 80286 or 80386 have more than one megabyte address range, the wrap-around feature of the 8086 family of microprocessors does not work on the 80286 or 80386 (in real mode) unless the A20 line is low. When the A20 line is low, the 80286 or 80386 can simulate the wrap-around feature.
To allow software with wrap-around windows to operate on the 80286 or 80386 microprocessors, the prior art has employed various techniques to intercept the A20 line from the microprocessor and force it low. Forcing the A20 line low makes addresses put out by the microprocessor in the range of between one and two megabytes result in an address one megabyte lower. The signal that causes the A20 line to stay low is called "FORCE-A20".
When the 80286 or 80386 microprocessor returns from real mode back to protected mode, the FORCE-A20 signal must be turned off, so that the software has the ability to use the full address range (beyond one megabyte) available to the microprocessor.
The FORCE-A20 signal does not actually cause the microprocessor to switch between protected and real mode.
The actual switching of modes is accomplished either by executing special instructions in the microprocessor or by resetting the microprocessor. Setting the FORCE-A20 signal is simply something that must be done by the software program to insure the wrap-around feature will not prevent proper functioning of the program.
In the prior art, the FORCE-A20 signal was controlled by an extra output pin on the 8042 keyboard controller.
This prior art solution was chosen because the extra ~31~0~
output pin was not otherwise needed, and because at the time nobody foresaw any need to switch between real and protected mode more than occasionally. The problem, however, of putting the FORCE-A20 signal under the control of the 8042 keyboard controller was that access to the signal was possible only by sending a command to the 8042, which then executed a routine to alter the state of the output pin. This process typically takes approximately 200 microseconds. The delay was found to be undesirable in many applications.
Many of the protected mode software programs utilizing the 80286 or 80386 microprocessors must disable the FORCE-A20 signal before switching to protected mode, and then enable it after returning to real mode. The prior art has controlled the FORCE-A20 signal by sending commands to the 8042 keyboard controller. Some of the newer software has needed to switch between protected and real mode very frequently, so that the delay for switching (approximately 200 microseconds) caused by the 8042 keyboard controller became a significant part of the program's execution time.
The present invention solves the delay problem resulting from utilizing the 8042 to control the FORCE-A20 signal, so that all existing software that calls on the 8042 to change the FORCE-A20 signal is not obsolete and the delay caused by the 8042 is reduced substantially.
The prior art has attempted to solve this delay problem by installing an additional, separate hardware port for the FORCE-A20 signals. This attempted solution, however, is incompatible with much of the existing soft-ware which utilizes the existing port on the 8042.
Therefore, a need exists for implementing the FORCE-A20 131~10 ~
command without delay by the 8042 keyboard controller, in a system compatible with existing software.
Many personal computers based on the 80286 or 80386 microprocessors also implement the "RESET-CPU" function.
The RESET-CPU command activates the RESET-CPU signal, which addresses the 80286 or B0386 microprocessor reset input. When the signal is activated, it causes the microprocessor to stop whatever it is doing and start its initialization sequence.
One use for the RESET-CPU command is to switch from protected mode to real mode in a system based on the 80286. When the 80286 microprocessor is reset, it de-faults to real mode. The RESET-CPU command, however, is not generally used by application software because it may cause the system to reboot. The system does provide that control can be returned to a program already residing in memory even after the CPU has been reset. Thus, if a protected mode program wishes to switch to real mode on an 80286 microprocessor, the program must reset the CPU, then regain control after the reset occurs.
It should be noted that the 80386 microprocessor, unlike the 80286, provides a specific instruction to switch from protected to real mode. However, software developed for the 80286 does not utilize this 80386-specific instruction.
If a software program switches from protected to real mode frequently, then it must reset the CPU frequently.
The RESET function is a strobe or pulse typically con-trolled by the 8042 keyboard controller. In the prior art, the command to change the CPU~RESET signal has utilized the extra pin on the 8042, just as the FORCE-A20 ~ 3 ~
signal utilized that pin. In the prior art, the 8042 RESET-CPU command holds that signal active for a short period of time; i.e., about five microseconds. The RESET-CPU signal resets the CPU, and then allows it to restart. However, since the 8042 hardware controls this function, the software program must wait for the rela-tively slow 8042 to respond during every RESET. Because the signal utilizes the extra pin on the 8042, there is typically a delay of approximately 200 microseconds for the 8042 to respond to the command; i.e., from the time that the CPU-RESET strobe command is sent to the 8042 until the time the 8042 starts the strobe. This addi-tional 200 microsecond delay was found to be undesirable in many applications.
Attempted solutions to this delay problem include installing an additional, separate hardware port for the CPU-RESET signal, but this attempted solution is incom-patible with much of the existing software. Another alternative method is to cause a CPU-RESET from software without using the 8042. This alternative is called a "triple fault". The triple fault is done by intentionally causing an execution error while in protected mode. When this happens, the CPU will automatically begin executing an error handling routine. If there is also an error in the first routine, the CPU goes to a second error handling routine. If there is an error in the second error handling routine, the CPU resets itself. Although this triple fault sequence is faster than the 8042 hardware reset, this approach has not been utilized by existing software applications. Therefore, the need exists for implementing the CPU-RESET signal, compatible with exist-ing software and without delay inherent in the 8042 keyboard controller.
131~
SUMMARY OF THE INVENTION
The present lnventlon resldes ln a programmable system for fllterlng commands to a mlcroprocessor, lncludlng at least one gate array or programmable loglc array for allowlng all lnput commands to pass dlrectly through to the mlcroprocessor except a deslgnated sequence of lnput commands. The present lnventlon ls particularly well suited to select and process commands relatlng to swltchlng between real and protected mode ln a personal computer based on the INTEL 80286 or INTEL 80386 mlcroprocessor.
Such personal computers lnclude those manufactured by IBM and COMPAQ.
In a preferred embodlment, the present invention resldes ln the use of one or more programmable loglc arrays or gate arrays to monltor the commands to the INTEL 8042 keyboard controller and lntercept certaln of those commands relatlng to the FORCE-A20 and CPU-RESET slgnals. One or more programmable loglc arrays or gate arrays allow all commands to pass dlrectly through to the 8042 except the speclfic sequence of commands relatlng to the slgnals necessary for FORCE-A20 and CPU-RESET. The slgnals, which prevlously came from the 8042 relatlng to the FORCE-A20 and CPU-RESET slgnals, accordlng to the present lnventlon, are controlled by the programmable loglc arrays or gate arrays as a hardware patch around the 8042. The result of the programmable loglc array or gate array lmplementatlon ls that programmable hardware ls used to reduce the time delay for implementing the FORCE-A20 and CPU-RESET ~lgnals.
In accordance wlth the present lnventlon there is provided a method for filterlng the commands avallable to a 131~
9a 72159-14 mlcroprocessor, comprlslng the steps of: (a) monltorlng all lnput commands to the mlcroprocessor; (b) lnterceptlng a predetermlned sequence of input commands matchlng programmable crlterla; (c) processlng sald lntercepted commands accordlng to programmable loglc to compute output slgnals; and (d) outputtlng sald computed slgnals correspondlng to sald predetermlned sequence of lnput commands.
In accordance wlth the present lnventlon there ls also provlded a programmable system for fllterlng lnput commands to a control devlce functlonally attached to lnput llnes of a mlcroprocessor, sald system comprlslng: (a) at least one programmable loglc array means for monltorlng lnput. llnes to sald control devlce and allowlng all lnput commands to pass dlrectly through to said control devlce except a deslgnated sequence of lnput commands~ and (b) output means for outputtlng a slgnal from sald programmable loglc array means to sald lnput llnes of sald mlcroprocessor, sald output slgnal correspondlng to sald deslgnated sequence of lnput commands.
In accordance wlth the present lnventlon there ls further provlded a system for selectlng and processlng deslgnated 2 commands relatlng to the FORCE-A20 slgnal and CPU-RESET slgnal for a keyboard controller functlonally attached to an INTEL 80286 or INTEL 80386 mlcroprocessor, sald system comprlslng, ~a) lnput means for monltorlng all lnput commands to sald keyboard controller; (b) flrst programmable loglc array means for allowlng all lnput commands to pass dlrectly through to sald keyboard controller except the command sequence relatlng to the FORCE-A20 slgnal; (c) second programmable loglc array means for allowlng all A
1 3 1 4 ~ o !~
9b 72159-14 lnput commands to pass dlrectly through to sald keyboard controller except the command sequence relatlng to the CPU-RESET
slgnal; and (d) output means for outputtlng the FORCE-A20 slgnal from sald flrst programmable loglc array means and the CPU-RESET
slgnal from sald second programmable loglc array means, sald output slgnal functlonally connected to sald INTEL 80286 or INTEL
80386 mlcroprocessor.
FIG. 1 ls a Block Diagram of the Programmable Loglc Array System for Fllterlng Commands to a Mlcroprocessor accordlng to the present lnventlon.
A
1 3 ~ b A preferred embodiment of the present invention comprises the use of at least one programmable logic array or gate array to monitor the commands to the 8042 keyboard controller and intercept certain of those commands re-lating to the FORCE-A20 and CPU-RESET signals. Each programmable logic array is an array of AND/OR gates and registers that can be interconnected in a combinational logic design. A gate array is simply a large number of gates placed on the chip in fixed locations that can be interconnected during the final stages of semiconductor manufacture. Essentially, a programmable logic array or gate array is a programmable, function-specific hardware component. Throughout the disclosure, the terms pro-grammable logic array, gate array and "PAL" will be used interchangeably. The term "PAL" as used in this dis-closure is a registered trademark of Monolithic Memories, Inc., 2175 Mission College Blvd., Santa Clara, California 95054, referring to certain species of programmable logic arrays.
The PAL or gate array described in this invention controls the FORCE-A20 and CPU-RESET signals in personal computers based on the INTEL 80286 and 80386 microprocessors. According to the prior art, these signals are controlled by the 8042 keyboard controller.
The PAL implementation enhances performance for software applications that do frequent switching between real mode and protected mode.
The A20 address line allows or disallows one megabyte wraparound memory, a feature necessary for implementing certain software designed for the 8086 family of microprocessors. The FORCE-A20 signal is used to force the A20 address line low. Forcing the A20 address line low is one of the several steps necessary to successfully ~ .:'`' , .
1 3 ~
--ll--switch the 80286 or 80386 microprocessor from protected to real mode. Through the use of an AND gate or similar logic, the A20 output is held low if the FORCE-A20 line goes low. When FORCE-A20 drives the A20 line low, the wrap-around feature is simulated. If the FORCE-A20 line is high, the A20 line is unaffected, that is, the A20 line remains low or high.
In the prior art, the FORCE-A20 line was instructed via the 8042 output port. There was a two-step command, described in more detail below, which was designed to set all eight bits on the 8042 output port. The FORCE-A20 line is just one bit of those eight bits. As there was no need to set the other seven bits, the two-step command became associated solely with setting the A20 line.
The FORCE-A20 and CPU-RESET PAL or gate array takes over the function of controlling the FORCE-A20 and CPU-RESET signals that were previously controlled by the 8042 keyboard controller 30. The PAL monitors all the commands to the 8042 keyboard controller. If the PAL sees a command to change either the CPU-RESET or the FORCE-A20 line, then the PAL does not allow the 8042 to see that command, but updates the signals itself. The signals are sent to a designated port on the microprocessor.
As shown in FIG. 1, a preferred embodiment of the present invention comprises two PALs, which will be referred to as the PORCE-A20 PAL 10 and the CPU-RESET PAL
20. It should be understood, however, that the present invention may comprise a single programmable logic array, gate array or PAL performing the functions of both the FORCE-A20 and CPU-RESET PAL. It also will be understood that the particular logic sequence for the present invention (i.e., passing a signal first through the 131410~
-FORCE-A20 PAL, then through the CPU-RESET PAL) may be varied without departing from the present invention.
To filter the commands to the 8042 keyboard con-troller 30, the Write Command ("WC") input 11 to the 8042 is intercepted by the PAL or gate array. An output of the PAL, WC 8042, is sent to the 8042. The WC 8042 output 41 is active when the WC line is active, but goes inactive when a FORCE-A20 or CPU-RESET command is detected. If a FORCE-A20 or a CPU-RESET command is detected, the WC 8042 line is held inactive. In such a case, the PAL sends the FORCE-A20 signal 12 or CPU-RESET signal 22 to the 80286 or 80386 microprocessor.
The FORCE-A20 and CPU-RESET lines 12 and 22 are connected so that they are driven from the PRLs instead of from the 8042. The 8042 write command 11 goes first through the FORCE-A20 PAL 10, and then through the CPU-RESET PAL 20. The command can be blocked by either PAL.
The FORCE-A20 line 12 is set and reset by a two-byte command sequence. The first byte, which indicates that the FORCE-A20 line is to be changed, is a write of the command word "Dl" to port 64h of the microprocessor. This write command indicates that a write to port 60h of the microprocessor is to follow. The second byte, which indicates the state that the FORCE-A20 line will go to, is the actual data to be sent to the output port. The data is written to port 60h. Bit 1 of the second byte is the new FORCE-A20 line status. Both commands are masked out of the 8042 by the FORCE-A20 PAL. The FORCE-A20 PAL will always mask a write of Dlh to port 64h from the 8042.
The FORCE-A20 PAL has two basic states: the "RESET"
state and the "AFTER-Dl" state. The FORCE-A20 PAL nor-l3l~10 i3 mally is in the "RESET" state. After every write of Dlhto port 64h, the FORCE-A20 PAL goes into the "AFTER-Dl"
state. In this state, the FORCE-A20 PAL will mask any data write command to port 60. If a write command to port 60h occurs, the FORCE-A20 is set to the value of bit one of the input data. When the PAL is in the "RESET" state, any write command to the 8042 except a Dlh write command to port 64h will leave the FORCE-A20 PAL in the "RESET"
state. When the PAL is in the "AFTER-Dl" state, the next state of the FORCE-A20 line (if it is a write to port 60) is determined by bit l of the input data.
Thus the FORCE-A20 PAL lets all the commands through to the 8042 until the sequence of commands to toggle the FORCE-A20 line comes through. The line FORCE-A20 command sequence is switched out of the 8042 and the PAL takes over the operation and toggles the command line. The FORCE-A20 PAL drives the FORCE-A20 line directly.
There are four input commands to the FORCE-A20 PAL in addition to the 8 data lines. The first command, "RST", goes active during a system reset and it resets the PALs.
"WC", as mentioned previously, is the write command line to the 8042 that is intercepted by the FORCE-A2Q PAL.
"CS" is a chip select signal that selects the 8042 on the I/O bus. The PALs do not respond to a write on the bus unless the "CS" command is present. "A2" is the address line used by the PALs to determine whether a write command is to port 60h or to port 64h.
The present invention utilizes at least one flip-flop to indicate whether the FORCE-A20 is in the RESET or AFTER-Dl state. In a preferred embodiment, the FORCE-A20 PAL includes four flip-flops: Q0, Ql, Q2, and Q3. One of the state flip-flops, Q0, is always set to the value of WC
1314 1~ ~
* CS, and as a result, Q0 gives a synchronous version of the write command signal. The FORCE-A20 PAL switches between the "RESET" state and the "AFTER Dl" state only between write cycles and not during them. The information about whether the FORCE-A20 PAL is in the "RESET" state or the "AFTER Dl" state is stored in the Ql flip-flop. The information about which state the FORCE-A20 PAL will go to after the current write cycle is stored in the Q2 and Q3 flip-flops, and this information is transferred to the Ql flip-flop after the write cycle is completed.
The CPU-RESET PAL monitors the WC 8042I line 21 from the FORCE-A20 PAL. The WC 8042I signal transfers information from the FORCE-A20 PAL to the CPU-RESET PAL;
it is the 8042 write command signal after the FORCE-A20 commands have been filtered out, but before the CPU-RESET
commands have been filtered out. If the WC 8042I line 21 is active after the FORCE-A20 commands are filtered out, the CPU-RESET PAL outputs the WC 80420 signal 31 unless there is an "FE" write to port 64h of the microprocessor (in which case the 8042 does not see the command). The FE
write to port 64h triggers the CPU-RESET signal delay logic.
Of course, if the WC 8042I line to the CPU-RESET PAL
is inactive, the current command will be a FORCE-A20 related signal (FF or Dl). The CPU-RESET PAL can deter-mine if an FE write to port 64 is happening by looking at the FF-FE-Dl signal and the DO signal. The FF-FE-Dl signal transfers information from the FORCE-A20 PAL to the CPU-RESET PAL. This signal tells the CPU-RESET PAL that the FORCE-A20 PAL has decoded the current 8042 data to be either OFFh, OFEh, or ODlh.
It has been found that the CPU-RESET signal executes properly if there is some delay from the strobe command until the activation of the CPU-RESET signal. In a preferred embodiment, a delay of approximately 14 micro-seconds is built into the CPU-RESET PAL, along with an active strobe period of approximately 5 microseconds.
To achieve these delays, the CPU-RESET PAL registers are set up as a 6 bit counter. The counter counts the pulses provided by the FORCE-A20 PAL to the CPU-RESET PAL.
The CPU-RESET PAL output is activated when the two high order bits of the counter are both active, during the last quarter of the count cycle. Thus, where the pulses are 3.58 MHZ, there is a 13.41 microsecond delay until the strobe starts, and the strobe is active for 4.47 microseconds. This total of 17.88 microseconds corre-sponds to 26/3.58 MHZ. After the counter reaches its maximum value, it returns to the reset state.
Attached is Appendix A, which is incorporated by reference to the disclosure of the present invention.
Appendix A provides a PAL state diagram and PAL timing diagram for the FORCE-A20 PAL and the CPU-RESET PALl as well as a schematic for the FORCE-A20/CPU-RESET test board. Also included in Appendix A is the PAL design specification for the FORCE-A20 PAL and CPU-RESET PAL.
Appendix B also is attached and incorporated by reference. Appendix B is a computer program listing for the FORCE-A20 and CPU-RESET PALs.
Although a preferred embodiment of the present invention is intended for use with a personal computer based on the INTEL 80286 or 80386 microprocessor, with an INTEL 8042 keyboard controller, it will be realized that 131~10~
the present invention is not intended to be so limited.
Instead, the present invention is intended to cover a system for allowing all input commands to pass directly through to the control device (such as the 8042 keyboard controller) except a designated sequence of input commands tsuch as the commands relating to the FORCE-A20 and CPU-RESET signals). Thus, although variations in the embodi-ment of the present invention may not each realize all of the advantages of the invention, certain features may become more important than others in various applications.
The invention, accordingly, should be understood to be limited only by the scope of the appended claims.
`- 131410~
A P P 1~ N D I ~ A
li . .
=~~ a --T ~ __ ~ D 1 ¦ ~ 1~
131~106 ~
_ . _ -- z : N
_ ~ I C _ _ c I _ ~ I m I c ~14 ~ . 0 6 ~ ~ hl lo 1- . I lll~ ~ 1~1 1 , ~ 1 ~ ] : I ~ ~
~ S
n~ ~D
_ a I ~ 1 m I c _ lq - a I o I ~ ¢ 131 ~10 6 , , _ _ g S ~ r ' ~
_ ~ ~ _ _ _ _ . _ _ ._ _ -- e~ c 5 _ ~ ~ ~c ~ ~. ~ ~
1~ .......... ....... ...... ............ ...... ...... ......... ............. .....
......... ....... ........ , _ .
......... _~.. ......... ....... ....... ............ ......... ...... ..... ............. ........ ......... ......... .....
.~ ~ - r Ll ~ ~ r - 1 ~ ~ i l l l z ~D
---- ~1 l ~ l l a ~
w ~ 1 1 - L~ . r ~ E _ r- ~ ~ 1~ ~ 1 - r ~ r.
[ ~ ~ , E ~ E
~ x ~ O ~ ~ - O c ~ ~ ~ 151 _ ,, C, ~ ~ I C _ ..~
o~
: - ~ l c -~ c _ ~ ~ 1 4 1 0 6 ,, 1-_ r o w --~5¦rn~rl~~ ro~lN~ ol~l_l l ~. ~ u, _ ~ D U, 7 D U' ~ rO N _ _ N N ~ N ~ Vl Lll ~ r~r L'~
m m _ --Q ~ I C _ ~a-P~L20R6 _ P~L L~C~ N SPEI_ I F I C;AT I ON
~VF--~4 JOHN TH~YEfi 2/23/87 ~04 ~20 LINE FIX PAL WITH LONCi t:PU FESET STRtlr~E
CI~PYF;I~HT COMPA~ COMPUTER HCllJSTON, TEXAS 1~)S7 t Lk'; /R5T /C;S A2 /WC: ~15 I:IC) Cl1 Cl_~ D:~: rl4 ~Nrl /OC ~17 /FF_FE_~ C /~: /6!7 /4!1 /~ /HLFCLK /wl~C:04~' D/:~ VCC
C.!O : = /RST * WC; * t ~: ; 6!(:) FClLLOWS WC:, CLE~fiErl ClN REC;ET
6!1 : = C!l * Q---: ; SET TLl ZERO IF STATE C)1IC) + 6!1 */C!2 + 1~!1 * 6!0 + /C.!_: * /C~!;2 * /C!I * /C'!O ; SET T0 ONE IF ST~TE C)C)(~
fi:-;T ; 5ET TCI CINE ON fi'E5ET
l.'!~' : = ; ~;ET IF STATE OC)11 ~ND ~;7 ~NLI r,l ~
/F;ST * /l;~:~ * /1~!~ * ~!1 * 6!(:) *~_'*rJ7*rl~ */~ *rl4*/~l~*f~l ~*/r,l *~c, ;~:EEP SET I F .'.TQTE = C 1 1 C) C,F (1111 + ~R'-;T * f6!:_: * C!2 * 6!l ;~:EEP SET I F STATE = 01(:)-~ C(fi 1 10(:) + /fi'ST * 6!2 * /li!l * /6!
;~EEP C;ET IF STATE = IIC)I
+ /RST * 1~ ' * Q:~ * /6!1 * 4!() C:LEAk IF STATE Cl1O1 ~NLl NClT (A_~ ANrl Crl1::~) ~STAY ONLY IF QNIITHER
;r11 W~ITE TO ~4H~
+ /fi':~T * /~: * ~ ' * /~!1 * 6!0 * ~_'*n7*l~ */rl.ci*rl4*/rl:_:*/rl~r*/rll*rl-.
f!:-: := SET IF STATE 0-.)11 ANrl NOT (A_~ ANrl cr~
; SET IF _;T~TE C)0l 1 ANrl ~ NCIT A~
;T * /Q:~; * /6!:~ * (`!1 * I.!~) * /f~_ ;SET IF STQTE ~011 ANrl NCIT cr, + /fi':_:T * /C!~ * /1~!..' * C!l * QC) * /FF_FE_rll ~ /RC;T * /l~!:3 * /6!7 * 6!1 * 1~!0 * rl7*rl~*~l5*D4*D_:*D2*rl1*rlC) + /R~CJT * /Q--: * /6!7 * Ql * C~!() * ~l7*r)~*rl'~*rl4*rl:--:*r~2*rll*/D(:) + /RC'.T * l~ * /l~ * C!~. * ~!
;CET I F .;TATE O1CI1 ANrl Q_' AN~I Crl I ;~
+ /RST * /6!~ * I~!-' * /I.~!1 * I.!(:I*~ *r(7*rl~*/rl5*~l4*/rl~*/~ */rll*~ll) ;SET IF STATE 11-:)1 + /kST * 1~!3 * Q:2 * /C`! 1 *
/~(:) := ;INVERSE r-(F A2(:I FUNCTIIIN
;CL.EA~ IF 5TATE (l1C!I AN~ (:) WRITE AN~I rll I:-; LCIW
sr * /C!-~: * C! * /l:!l * ~.!I:) * /1~ J * /~l ; OTHEh'W ISE FEE~ 3AC:k::
+ /R~C;T * C!--: * /~''0 /R:~T * /l~!_ * /~
/R~.T * Ql * /1~
+ ~R~T * ~C~ * /A~O
/RST * A2 * /A20 HLFC L~ = ; HALF CLOI~k:: SF EECt OUTPUT F~ iESET P~L T I MEF;
/HLFCLI'.
FF_FE_DI = IJ7--~ 5~C~4f D::~ Cl2~ C~ C~C~
131~106 + D7*~.*/D5*~4~13*/D~*/[1I*[1(~
1 D7*~6* ~5*D4* ~3* ~'2* Cll*/[/O
WCSC)4~ = ;NO D1 WRITE YET~
;~IC1N~T FILTER IF WRITE IS TCI 60H
~C * C:S * WC * ~l * /A~
;DON~T FILTEk IF WkITE IS TCI ~.4H ~ND NOT C~ ,CFE::~ C1fi CFF::~
+ ,~, * ~c, * W1~ * ~1 * /FF_FE_Dl ~ IC1N~T FILTEk IF WklTE IS TC1 ~.4H ~Nrl IS CFE~
+ 1~ * ~ ; * W1~ * ~l * /~
;~FTEk Dl WRITE
;DON'T FILTEk IF WkITE I.C; TCIr'.4HhN~lNl_lTC~, CFE::> qR CFF~
t: * C:S * W13 * /1.!l * Q~ * /FF_FE_rll ,D1-1N~T FILTEk IF WRITE IS TLI~.4H~N~lI'_; CFE~
+ I~'.!C) * I_:C: * Wl_: * /1;~1 * ~q.Lr * /~1(3 F1JN1-:TIC1N T~LE
/1:11:: CL~ ;T 1~17 L1~ 14 r,:: D_ Lll Ll':
1~!3 1.!-~ C`!l ~!': FF_FE_~ C) WC::3C14~ HLFC:L~:
; F WH
F CL
~ : F
; C R R ~ O 1-:
;CILc;~WA~l~lrlrl~l~lrl~l C!l..!l!l!~ 4L
;C: ~ T S C: ~ 7 6 5 4 :-: ~ l C 3 ~ l C~ 1 C) ~
__________________________________________________________________________ LXXXXXHHHHHHH H X X X X HXXX ; TE-;l- FF_C!F;_~1l LXXXXXHHLHLLLH XXXXHXXX
LXXXXXLLHHLLL H X X X X LXXX
;
L~HXXXXXXXXXXX LLHLXHLX; RESET
;
LCLHLXXXXXXXXX LLHLX H LX;/:.4 WRITE NL1T (~ll C1fi FF~
LC:LHHHLLLLLLLL LLH H LHHX
LCLHHHLLLLLLLL HLHHLHHX
LCLHHHLLLLLLLL HLHHLHHX
LCLHLHLLLLLLLL HLHLLHLX
LCLXLXXXXXXXXX LLHLXHLX
Ll:LHLXXXXXXXXX LLHL.XHLX ~-.4WR ITE FF
LC:LHHHH H H H H HH H L LHHHHLX
LC:LHHHHHHHHHHH HLHHHHLX
LCLHHHHHHHHHHH HLHHHHLX
LCLHLHHHHHHHHH HlHLHHLX
LC:LXLXXXXXXXXX LLHLXHLX
LC:LHLXXXXXXXXX LLHLXHI_X /:CI Wfi I TE
LCLHHLXXXXXXXX LLHHXHHX
LC:LHHLXXXXXXXX HLHHXHHX
LCLHHLXXXXXXXX HLHHXHHX
LCLHLLXXXXXXXX HLHLXHLX
L~LXLXXXXXXXXX LLHLXHLX
LC:HXXXXXXXXXXX LLHLXHLX; fi'ESET
;
LCLHLXXXXXXXXX LLHLXHLX C:LEAk ~O
LCLHHHHHLHLLLH LLHHHHLX ;~.4 WfiITE ~ll L~LHHHHHLHLLLH LHHHHHLX
~ It LC HHHHHLHLLLH LHHHHHLX
LC_HLHHHLHLLLH LHHLHHLX
LCLXLXXXXXXXXX LHLLXHLX
LCLHLXXXXXXXXX LHLLXHLX ;~OWRITETOCLE~
LCLHHXXXXXXXLX LHLHXHLX L~TCH
LCLHHXXXXXXXLX LLLHXLLX
LCLHHXXXXXXXLX LLLHXLLX
LCLHLHXXXXXXLX LLLLXLLX
LCLXLXXXXXXXXX LLHLXLLX
LCLHLXXXXXXXXX LLHLXLLX;~ET~
LCLHHHHHLHLLLH LLHHHLLX ;~:.4W~ITE~ll L~LHHHHHLHLLLH LHHHHLLX
LCLHHHHHLHLLLH L.HHHHLLX
LI~LHLHHHLHLLLH L HHLHLLX
LCLXLXXXXXXXXX LHLLXLLX
LC:LHLXXXXXXXXX LHLLXLLX~:4 WF~ITE Cll LCLHHHHHLHLLLH LHLHHLLX
LCLHHHHHLHLLLH HHLHHLLX
LCLHHHHHLHLLLH HHLHHLLX
LCLHLHHHLHLLLH HHLLHLLX
LCLXLXXXXXXXXX LHL.LXI_LX
LCLHLXXXXXXXXX LHLLXLLX ;/:.OWhITETOSET
LCLHHXXXXXXXHX LHLHXLLX ;L~TCH
LCLHHXXXXXXXHX LLLHXHLX
LCLHHXXXXXXXHX LLLHXHLX
LCLHLHXXXXXXHX LLLLXHLX
LCLXLXXXXXXXXX LLHLXHLX
LCHXXXXXXXXXXX LLH L X HLX;~E-;ET
LC:LHLXXXXXXXXX L L HLXHLX;[llTHENFF,E~TBI-lTH
LCLHHHHH L HLLLH LLHHHHLX ~.4WF~ITE~ll LCLHHHHHLHLLLH LHHHHHLX
LCLHHHHHLHLLLH LHHHHHLX
LCLHLHHHLHLLLH LHHLHHLX
LCLXLXXXXXXXXX LHLLXHLX
LC:LHLXXXXXXXXX LHLLXHLX;~4WF; ITE FF
LCLHHHHHHHHHHH LHLHHHLX
LCLHHHHHHHHHHH LLLHHHLX
LCLHHHHHHHHHHH LLLHHHLX
LC:LHLHHHHHHHHH LLLLHh L X
L l_ L X L X X X X X X X X X L L HlXHLX
LCLHLXXXXXXXXX LLHLXH L X;1:1l THEN ~:.4 WF~ITE, E~TI~NLY 1~1 LC:LHHHHHLHLLLH LLHHHHLX ;~.4 WRITE[I
LCLHHHHHLHLLLH LHHHHHLX
LCLHHHHHLHLLLH LHHHHHLX
L~LHLHHHLHLLLH LHHLHHLX
LCLXLXXXXXXXXX LHLLXHLX
LC:LHLXXXXXXXXX LHLLXHLX;6 4 WF~ ITE-:)O
LCLHHHLLLLLLLL LHLHLHHX
LCLHHHLLLLLLLL LLLHLHHX
L~ HHHLLLLLLLL LLLHLHHX
LCLHLHLLLLLLLL LLLLLHLX
~ .
, ~ 1314106 L 1~ ~- X L X X X X X X X X X L L H L X H L X
DESI~R I PT I ON
~ G
~3~410~
PAL ~fi6 . PAL ~iÉ :lCiN ;FEI-IFIC~.TION
A20 ~_5:3 .JOHN THhYEk 2-/ 23 / 37 8042 CP-l RE';ET STkO~E FIX FOR USE W I TH LOWA20 P I CiCiYBhC K PAL
COPYRIÇHT COI~lPhl~ C.OMPUTEfi H4U :TCN TEXhS 1537 CLK /kST h~ X~lO /WC:3l:\4_I /FF_FE_rll I 5 I~:. HLFCLK C.NC
~OC ~WCC:0421_1 /C4 /C3 /C:~ /C:l /CO /C:5 /CPURE5 VCI_ ; rll3N ~T 1`1A~.K NClN FF FE ~11 rlhTA
WC3C)420 = WC::S04-~i * /CC) * /C1 * /C2 * /C:-: * /C:4 * /C.5 * /FF_FE_rl1 lN-~T 1~1ASk:: FF ~11 {lATh I WC:;~ )4~I * /C:O * /L-:l * /C: * /kC-: * /C:4 * /C: 5 * X~10 ; ClCIN T r1ASK PClRT t.OH WR I TE =i + WC:~:04_I * /C:O * /l-1 * /C2 * /C-: * /C:4 * /C:5 * /A-~
CPURES = C:4 * C:5 ~ h.--;5EkT C:Pl_l REC;ET ;IciNhL Cl!`lLY ;lUF;INC. LA-;T l-!UAfiTEfi CIF CCll_lNT
ClELAY 1 . 1~1 I C:RLl~;ECl-lNLl.-; TCI -;TAF~T ClF 5 1~1 I CRCI =;El_:l_lNrl PlJL.-;E
; C;l-~qR~ IF FE TCI ~4 CO : = /kiT * WC~:042I * FF_FE_Cl1 * /XrlO * A- * /CO*/C1*/ -:2*/r:--:*/l 4*/C:S
+ /R5T * HLFCLI. * /C:I:) * C:1 TCll3~1iLE WHEN RE5ET AC:TIVE
+ /R_;T * HLFCLK * /C:O * C
/RC;T * HLFC:LK * /C:O * C:3 + /R5T * HLFCLK * /CCI * C4 + /RST * HLFC:L~ * /CO * C:5 + /R5T * /HLFC:LkK * CO
~; C1 := /fi~_;T * /r:1 * C:O * HLFCL~:: FrlRM HICiHER C:l3UNTER BITi + / RST * C 1 * / C:O
+ /R5T * C 1 * /HLFCL~
1 C 7 : = /fi5T * /C: ~ * C 1 * C C) * HLFCLk::
+ /RST * C2 * /Cl + /R5T * C:2 * /1,0 + /R~T * C2 * /HLFC:LK
C3 := /R5T * /C3 * C2 * C:1 * CO * HLFC:LkK
+ /R_;T * C:3 * /C_ + /RST * C3 * /Cl + /R_;T * C_: * /C:O
+ /RC-;T * C3 * /HLFCLK
C:4 : = /R.-;T * /C:4 * C:3 * C2 * C 1 * C:Cl * HLFC:LK
+ /R5T * C4 * /C 3 + /R5T * C:4 * /L-:-~
+ /RC;T * C:4 * /C:1 /RST * C:4 * /CO
+ /R5T * C4 * /HLFCLIC
CS : = ~RC;T * /C5 * C.4 * C3 * C2 * C 1 * t C~ * HLFCLK
+ /F~e.T * C5 * /C4 + /RST * t5 * /C3 + /RST * C5 * /C2 + /R5T * C'. * /Cl + XR5T * C5 * /CCI
+ /R5T * C5 * /HLFC~LK
F UNC T I ON Th.BLE
13141~6 ., /C~r-LI~kSTWC~042I~2X~I0FF_FE_r~1HLFCL~C
C5.~C3C2C1C0WC804~0CPIJfiES
W W
C FH C:C
COMW:116 PROGRAMMABLE LOGIC SYSTEM FOR FILTERING
COMMANDS TO A MICROPROCESSOR
This invention relates to regulating the operations of a microprocessor by the use of one or more programmable logic arrays or gate arrays for filtering of certain commands to the microprocessor. More particularly, it relates to the use of programmable logic arrays or gate arrays for monitoring commands to a keyboard controller in a personal computer based on either the INTEL 80286 or 80386 microprocessor, and intercepting certain of those commands relating to the FORCE-A20 and CPU-RESET signals.
In many popular personal computers based on the INTEL
80286 or 80386 microprocessor, there is a need for uti-lizing both real-address mode ("real mode") and protected mode. Real mode is used for initialization when first powered up, and mimicking of older 16-bit microprocessors, such as the INTEL 8086 family of microprocessors. In real mode, the 80286 or 80386 microprocessor uses segment and offset registers in the same way as the 8086 family to access the same one megabyte of memory. In real mode, the 16-bit instruction set, the segmented programming model, addressing mechanism, and one megabyte physical memory limitations are identical to those provided by the 8086.
~rA l ~
$
131410 ~
Thus the 80286 and 80386 microprocessors are compatible with the addressing scheme of the 8086 family.
In protected mode, the 80286 or 80386 microprocessor adds a series of features that allow it to safely and reliably expand the number of programs the computer can be working on at one time. This is accomplished through four main facilities: protection, extended memory, virtual memory, and multi-tasking. Protection allows the operat-ing system to erect barriers to prevent a program frominterfering with the operation of other programs or of the operating system itself. Extended memory greatly in-creases the amount of working memory beyond the 640 KB
actually available to the software. Virtual memory allows the computer to go further beyond the installed physical memory limitations by shifting data to and from remote memory, such as hard disk. Finally, with multi-tasking supported by the hardware, the 80286 or 80386 can swiftly and reliably switch among several programs that are running at the same time.
A basic difference between protected mode and real mode is that the protected mode segment register is no longer a real (i.e., physical) address. Instead, in protected mode, the 80286 or 80386 uses the upper (most significant) 14 bits of the segment register to look up a 24-bit base address (with the 80286) or a 32-bit base address (with the 80386) stored in a descriptor table in memory.
Additionally, with protected mode, segment registers define the way that memory is organized between tasks.
Each task has its own descriptor table describing the segments for that task. Since physical addresses are stored in the descriptor table rather than in the segment 131~10~
registers, the operating system can move memory around without application programs being affected.
Protected mode is so named because segments belonging to one task are protected from being corrupted by another task. Tasks are organized in privilege levels, and certain machine-code instructions are prohibited to lower privilege levels. In a well-designed protected mode operating system, a single program can neither crash the whole system nor get itself into an unrecoverable state.
Many personal computers based on the 80286 or 80386 microprocessors implement the "FORCE-A20" function. This function is necessary to maintain compatibility with software designed for systems based on the 8086 family of microprocessors.
The compatibility issue arises from the different memory address sizes available on the 8086, 80286, and 80386 chips. The 8086 had a one megabyte address range, with twenty address lines (A0-Al9) driven by the micro-processor. The total range was 2 raised to the 20th power, or 1,048,576 possible addresses (one megabyte). In contrast, the 80286 has 24 address lines, giving 16 megabytes of address range (2 raised to the 24th power);
the 80386 has 32 address lines, giving 4096 megabytes of address range (2 raised to the 32nd power).
The 8086 microprocessor uses a segmented memory addressing scheme. The effect of this scheme is to allow a software program to access only a 64 KB "window" out of the one megabyte total range. To access memory outside this window, the window's location must change, and this operation takes time.
13141~ ~
To access memory near the top of the one megabyte address space as well as memory near the bottom of the 8086's one megabyte address space, without moving the window, some software takes advantage of "memory wrap-around". This feature on the 8086 may be used when thebase of the 64 KB window is less than 64 KB from the 'op of the one megabyte address range, so the top of the window would extend beyond the highest possible address location. When the window is in such a position, these impossibly high addresses are simply "wrapped around" to low addresses, much in the same way that an odometer goes from 99,999 to 00,000 miles. Thus, software could access very high as well as very low addresses in the same window.
Since the 80286 and 80386 microprocessors have more than one megabyte of address range, these microprocessors do not wrap around memory addresses at one megabyte.
Instead, accesses to the part of the window above one megabyte are put out as actual addresses greater than one megabyte.
The difference between the old 8086 "wrapped around"
low addresses and the new 80286/80386 high addresses is that the new 80286/80386 microprocessors have extra address lines beyond Al9 (much like having extra digits on an odometer, so it doesn't wrap around after 99,999 miles). The first of these address lines on the 80286 or 80386 is A20, and it is set high for all addresses in the range from one megabyte to two megabytes (in the absence of the FORCE-A20 command). The A20 line is set low for addresses below one megabyte.
In real mode, the 80286 and 80386 microprocessors behave as much as possible like the 8086 microprocessors.
131~
Thus, in real mode the 80286 and 80386 cannot access memory above one megabyte. Because the 80286 or 80386 have more than one megabyte address range, the wrap-around feature of the 8086 family of microprocessors does not work on the 80286 or 80386 (in real mode) unless the A20 line is low. When the A20 line is low, the 80286 or 80386 can simulate the wrap-around feature.
To allow software with wrap-around windows to operate on the 80286 or 80386 microprocessors, the prior art has employed various techniques to intercept the A20 line from the microprocessor and force it low. Forcing the A20 line low makes addresses put out by the microprocessor in the range of between one and two megabytes result in an address one megabyte lower. The signal that causes the A20 line to stay low is called "FORCE-A20".
When the 80286 or 80386 microprocessor returns from real mode back to protected mode, the FORCE-A20 signal must be turned off, so that the software has the ability to use the full address range (beyond one megabyte) available to the microprocessor.
The FORCE-A20 signal does not actually cause the microprocessor to switch between protected and real mode.
The actual switching of modes is accomplished either by executing special instructions in the microprocessor or by resetting the microprocessor. Setting the FORCE-A20 signal is simply something that must be done by the software program to insure the wrap-around feature will not prevent proper functioning of the program.
In the prior art, the FORCE-A20 signal was controlled by an extra output pin on the 8042 keyboard controller.
This prior art solution was chosen because the extra ~31~0~
output pin was not otherwise needed, and because at the time nobody foresaw any need to switch between real and protected mode more than occasionally. The problem, however, of putting the FORCE-A20 signal under the control of the 8042 keyboard controller was that access to the signal was possible only by sending a command to the 8042, which then executed a routine to alter the state of the output pin. This process typically takes approximately 200 microseconds. The delay was found to be undesirable in many applications.
Many of the protected mode software programs utilizing the 80286 or 80386 microprocessors must disable the FORCE-A20 signal before switching to protected mode, and then enable it after returning to real mode. The prior art has controlled the FORCE-A20 signal by sending commands to the 8042 keyboard controller. Some of the newer software has needed to switch between protected and real mode very frequently, so that the delay for switching (approximately 200 microseconds) caused by the 8042 keyboard controller became a significant part of the program's execution time.
The present invention solves the delay problem resulting from utilizing the 8042 to control the FORCE-A20 signal, so that all existing software that calls on the 8042 to change the FORCE-A20 signal is not obsolete and the delay caused by the 8042 is reduced substantially.
The prior art has attempted to solve this delay problem by installing an additional, separate hardware port for the FORCE-A20 signals. This attempted solution, however, is incompatible with much of the existing soft-ware which utilizes the existing port on the 8042.
Therefore, a need exists for implementing the FORCE-A20 131~10 ~
command without delay by the 8042 keyboard controller, in a system compatible with existing software.
Many personal computers based on the 80286 or 80386 microprocessors also implement the "RESET-CPU" function.
The RESET-CPU command activates the RESET-CPU signal, which addresses the 80286 or B0386 microprocessor reset input. When the signal is activated, it causes the microprocessor to stop whatever it is doing and start its initialization sequence.
One use for the RESET-CPU command is to switch from protected mode to real mode in a system based on the 80286. When the 80286 microprocessor is reset, it de-faults to real mode. The RESET-CPU command, however, is not generally used by application software because it may cause the system to reboot. The system does provide that control can be returned to a program already residing in memory even after the CPU has been reset. Thus, if a protected mode program wishes to switch to real mode on an 80286 microprocessor, the program must reset the CPU, then regain control after the reset occurs.
It should be noted that the 80386 microprocessor, unlike the 80286, provides a specific instruction to switch from protected to real mode. However, software developed for the 80286 does not utilize this 80386-specific instruction.
If a software program switches from protected to real mode frequently, then it must reset the CPU frequently.
The RESET function is a strobe or pulse typically con-trolled by the 8042 keyboard controller. In the prior art, the command to change the CPU~RESET signal has utilized the extra pin on the 8042, just as the FORCE-A20 ~ 3 ~
signal utilized that pin. In the prior art, the 8042 RESET-CPU command holds that signal active for a short period of time; i.e., about five microseconds. The RESET-CPU signal resets the CPU, and then allows it to restart. However, since the 8042 hardware controls this function, the software program must wait for the rela-tively slow 8042 to respond during every RESET. Because the signal utilizes the extra pin on the 8042, there is typically a delay of approximately 200 microseconds for the 8042 to respond to the command; i.e., from the time that the CPU-RESET strobe command is sent to the 8042 until the time the 8042 starts the strobe. This addi-tional 200 microsecond delay was found to be undesirable in many applications.
Attempted solutions to this delay problem include installing an additional, separate hardware port for the CPU-RESET signal, but this attempted solution is incom-patible with much of the existing software. Another alternative method is to cause a CPU-RESET from software without using the 8042. This alternative is called a "triple fault". The triple fault is done by intentionally causing an execution error while in protected mode. When this happens, the CPU will automatically begin executing an error handling routine. If there is also an error in the first routine, the CPU goes to a second error handling routine. If there is an error in the second error handling routine, the CPU resets itself. Although this triple fault sequence is faster than the 8042 hardware reset, this approach has not been utilized by existing software applications. Therefore, the need exists for implementing the CPU-RESET signal, compatible with exist-ing software and without delay inherent in the 8042 keyboard controller.
131~
SUMMARY OF THE INVENTION
The present lnventlon resldes ln a programmable system for fllterlng commands to a mlcroprocessor, lncludlng at least one gate array or programmable loglc array for allowlng all lnput commands to pass dlrectly through to the mlcroprocessor except a deslgnated sequence of lnput commands. The present lnventlon ls particularly well suited to select and process commands relatlng to swltchlng between real and protected mode ln a personal computer based on the INTEL 80286 or INTEL 80386 mlcroprocessor.
Such personal computers lnclude those manufactured by IBM and COMPAQ.
In a preferred embodlment, the present invention resldes ln the use of one or more programmable loglc arrays or gate arrays to monltor the commands to the INTEL 8042 keyboard controller and lntercept certaln of those commands relatlng to the FORCE-A20 and CPU-RESET slgnals. One or more programmable loglc arrays or gate arrays allow all commands to pass dlrectly through to the 8042 except the speclfic sequence of commands relatlng to the slgnals necessary for FORCE-A20 and CPU-RESET. The slgnals, which prevlously came from the 8042 relatlng to the FORCE-A20 and CPU-RESET slgnals, accordlng to the present lnventlon, are controlled by the programmable loglc arrays or gate arrays as a hardware patch around the 8042. The result of the programmable loglc array or gate array lmplementatlon ls that programmable hardware ls used to reduce the time delay for implementing the FORCE-A20 and CPU-RESET ~lgnals.
In accordance wlth the present lnventlon there is provided a method for filterlng the commands avallable to a 131~
9a 72159-14 mlcroprocessor, comprlslng the steps of: (a) monltorlng all lnput commands to the mlcroprocessor; (b) lnterceptlng a predetermlned sequence of input commands matchlng programmable crlterla; (c) processlng sald lntercepted commands accordlng to programmable loglc to compute output slgnals; and (d) outputtlng sald computed slgnals correspondlng to sald predetermlned sequence of lnput commands.
In accordance wlth the present lnventlon there ls also provlded a programmable system for fllterlng lnput commands to a control devlce functlonally attached to lnput llnes of a mlcroprocessor, sald system comprlslng: (a) at least one programmable loglc array means for monltorlng lnput. llnes to sald control devlce and allowlng all lnput commands to pass dlrectly through to said control devlce except a deslgnated sequence of lnput commands~ and (b) output means for outputtlng a slgnal from sald programmable loglc array means to sald lnput llnes of sald mlcroprocessor, sald output slgnal correspondlng to sald deslgnated sequence of lnput commands.
In accordance wlth the present lnventlon there ls further provlded a system for selectlng and processlng deslgnated 2 commands relatlng to the FORCE-A20 slgnal and CPU-RESET slgnal for a keyboard controller functlonally attached to an INTEL 80286 or INTEL 80386 mlcroprocessor, sald system comprlslng, ~a) lnput means for monltorlng all lnput commands to sald keyboard controller; (b) flrst programmable loglc array means for allowlng all lnput commands to pass dlrectly through to sald keyboard controller except the command sequence relatlng to the FORCE-A20 slgnal; (c) second programmable loglc array means for allowlng all A
1 3 1 4 ~ o !~
9b 72159-14 lnput commands to pass dlrectly through to sald keyboard controller except the command sequence relatlng to the CPU-RESET
slgnal; and (d) output means for outputtlng the FORCE-A20 slgnal from sald flrst programmable loglc array means and the CPU-RESET
slgnal from sald second programmable loglc array means, sald output slgnal functlonally connected to sald INTEL 80286 or INTEL
80386 mlcroprocessor.
FIG. 1 ls a Block Diagram of the Programmable Loglc Array System for Fllterlng Commands to a Mlcroprocessor accordlng to the present lnventlon.
A
1 3 ~ b A preferred embodiment of the present invention comprises the use of at least one programmable logic array or gate array to monitor the commands to the 8042 keyboard controller and intercept certain of those commands re-lating to the FORCE-A20 and CPU-RESET signals. Each programmable logic array is an array of AND/OR gates and registers that can be interconnected in a combinational logic design. A gate array is simply a large number of gates placed on the chip in fixed locations that can be interconnected during the final stages of semiconductor manufacture. Essentially, a programmable logic array or gate array is a programmable, function-specific hardware component. Throughout the disclosure, the terms pro-grammable logic array, gate array and "PAL" will be used interchangeably. The term "PAL" as used in this dis-closure is a registered trademark of Monolithic Memories, Inc., 2175 Mission College Blvd., Santa Clara, California 95054, referring to certain species of programmable logic arrays.
The PAL or gate array described in this invention controls the FORCE-A20 and CPU-RESET signals in personal computers based on the INTEL 80286 and 80386 microprocessors. According to the prior art, these signals are controlled by the 8042 keyboard controller.
The PAL implementation enhances performance for software applications that do frequent switching between real mode and protected mode.
The A20 address line allows or disallows one megabyte wraparound memory, a feature necessary for implementing certain software designed for the 8086 family of microprocessors. The FORCE-A20 signal is used to force the A20 address line low. Forcing the A20 address line low is one of the several steps necessary to successfully ~ .:'`' , .
1 3 ~
--ll--switch the 80286 or 80386 microprocessor from protected to real mode. Through the use of an AND gate or similar logic, the A20 output is held low if the FORCE-A20 line goes low. When FORCE-A20 drives the A20 line low, the wrap-around feature is simulated. If the FORCE-A20 line is high, the A20 line is unaffected, that is, the A20 line remains low or high.
In the prior art, the FORCE-A20 line was instructed via the 8042 output port. There was a two-step command, described in more detail below, which was designed to set all eight bits on the 8042 output port. The FORCE-A20 line is just one bit of those eight bits. As there was no need to set the other seven bits, the two-step command became associated solely with setting the A20 line.
The FORCE-A20 and CPU-RESET PAL or gate array takes over the function of controlling the FORCE-A20 and CPU-RESET signals that were previously controlled by the 8042 keyboard controller 30. The PAL monitors all the commands to the 8042 keyboard controller. If the PAL sees a command to change either the CPU-RESET or the FORCE-A20 line, then the PAL does not allow the 8042 to see that command, but updates the signals itself. The signals are sent to a designated port on the microprocessor.
As shown in FIG. 1, a preferred embodiment of the present invention comprises two PALs, which will be referred to as the PORCE-A20 PAL 10 and the CPU-RESET PAL
20. It should be understood, however, that the present invention may comprise a single programmable logic array, gate array or PAL performing the functions of both the FORCE-A20 and CPU-RESET PAL. It also will be understood that the particular logic sequence for the present invention (i.e., passing a signal first through the 131410~
-FORCE-A20 PAL, then through the CPU-RESET PAL) may be varied without departing from the present invention.
To filter the commands to the 8042 keyboard con-troller 30, the Write Command ("WC") input 11 to the 8042 is intercepted by the PAL or gate array. An output of the PAL, WC 8042, is sent to the 8042. The WC 8042 output 41 is active when the WC line is active, but goes inactive when a FORCE-A20 or CPU-RESET command is detected. If a FORCE-A20 or a CPU-RESET command is detected, the WC 8042 line is held inactive. In such a case, the PAL sends the FORCE-A20 signal 12 or CPU-RESET signal 22 to the 80286 or 80386 microprocessor.
The FORCE-A20 and CPU-RESET lines 12 and 22 are connected so that they are driven from the PRLs instead of from the 8042. The 8042 write command 11 goes first through the FORCE-A20 PAL 10, and then through the CPU-RESET PAL 20. The command can be blocked by either PAL.
The FORCE-A20 line 12 is set and reset by a two-byte command sequence. The first byte, which indicates that the FORCE-A20 line is to be changed, is a write of the command word "Dl" to port 64h of the microprocessor. This write command indicates that a write to port 60h of the microprocessor is to follow. The second byte, which indicates the state that the FORCE-A20 line will go to, is the actual data to be sent to the output port. The data is written to port 60h. Bit 1 of the second byte is the new FORCE-A20 line status. Both commands are masked out of the 8042 by the FORCE-A20 PAL. The FORCE-A20 PAL will always mask a write of Dlh to port 64h from the 8042.
The FORCE-A20 PAL has two basic states: the "RESET"
state and the "AFTER-Dl" state. The FORCE-A20 PAL nor-l3l~10 i3 mally is in the "RESET" state. After every write of Dlhto port 64h, the FORCE-A20 PAL goes into the "AFTER-Dl"
state. In this state, the FORCE-A20 PAL will mask any data write command to port 60. If a write command to port 60h occurs, the FORCE-A20 is set to the value of bit one of the input data. When the PAL is in the "RESET" state, any write command to the 8042 except a Dlh write command to port 64h will leave the FORCE-A20 PAL in the "RESET"
state. When the PAL is in the "AFTER-Dl" state, the next state of the FORCE-A20 line (if it is a write to port 60) is determined by bit l of the input data.
Thus the FORCE-A20 PAL lets all the commands through to the 8042 until the sequence of commands to toggle the FORCE-A20 line comes through. The line FORCE-A20 command sequence is switched out of the 8042 and the PAL takes over the operation and toggles the command line. The FORCE-A20 PAL drives the FORCE-A20 line directly.
There are four input commands to the FORCE-A20 PAL in addition to the 8 data lines. The first command, "RST", goes active during a system reset and it resets the PALs.
"WC", as mentioned previously, is the write command line to the 8042 that is intercepted by the FORCE-A2Q PAL.
"CS" is a chip select signal that selects the 8042 on the I/O bus. The PALs do not respond to a write on the bus unless the "CS" command is present. "A2" is the address line used by the PALs to determine whether a write command is to port 60h or to port 64h.
The present invention utilizes at least one flip-flop to indicate whether the FORCE-A20 is in the RESET or AFTER-Dl state. In a preferred embodiment, the FORCE-A20 PAL includes four flip-flops: Q0, Ql, Q2, and Q3. One of the state flip-flops, Q0, is always set to the value of WC
1314 1~ ~
* CS, and as a result, Q0 gives a synchronous version of the write command signal. The FORCE-A20 PAL switches between the "RESET" state and the "AFTER Dl" state only between write cycles and not during them. The information about whether the FORCE-A20 PAL is in the "RESET" state or the "AFTER Dl" state is stored in the Ql flip-flop. The information about which state the FORCE-A20 PAL will go to after the current write cycle is stored in the Q2 and Q3 flip-flops, and this information is transferred to the Ql flip-flop after the write cycle is completed.
The CPU-RESET PAL monitors the WC 8042I line 21 from the FORCE-A20 PAL. The WC 8042I signal transfers information from the FORCE-A20 PAL to the CPU-RESET PAL;
it is the 8042 write command signal after the FORCE-A20 commands have been filtered out, but before the CPU-RESET
commands have been filtered out. If the WC 8042I line 21 is active after the FORCE-A20 commands are filtered out, the CPU-RESET PAL outputs the WC 80420 signal 31 unless there is an "FE" write to port 64h of the microprocessor (in which case the 8042 does not see the command). The FE
write to port 64h triggers the CPU-RESET signal delay logic.
Of course, if the WC 8042I line to the CPU-RESET PAL
is inactive, the current command will be a FORCE-A20 related signal (FF or Dl). The CPU-RESET PAL can deter-mine if an FE write to port 64 is happening by looking at the FF-FE-Dl signal and the DO signal. The FF-FE-Dl signal transfers information from the FORCE-A20 PAL to the CPU-RESET PAL. This signal tells the CPU-RESET PAL that the FORCE-A20 PAL has decoded the current 8042 data to be either OFFh, OFEh, or ODlh.
It has been found that the CPU-RESET signal executes properly if there is some delay from the strobe command until the activation of the CPU-RESET signal. In a preferred embodiment, a delay of approximately 14 micro-seconds is built into the CPU-RESET PAL, along with an active strobe period of approximately 5 microseconds.
To achieve these delays, the CPU-RESET PAL registers are set up as a 6 bit counter. The counter counts the pulses provided by the FORCE-A20 PAL to the CPU-RESET PAL.
The CPU-RESET PAL output is activated when the two high order bits of the counter are both active, during the last quarter of the count cycle. Thus, where the pulses are 3.58 MHZ, there is a 13.41 microsecond delay until the strobe starts, and the strobe is active for 4.47 microseconds. This total of 17.88 microseconds corre-sponds to 26/3.58 MHZ. After the counter reaches its maximum value, it returns to the reset state.
Attached is Appendix A, which is incorporated by reference to the disclosure of the present invention.
Appendix A provides a PAL state diagram and PAL timing diagram for the FORCE-A20 PAL and the CPU-RESET PALl as well as a schematic for the FORCE-A20/CPU-RESET test board. Also included in Appendix A is the PAL design specification for the FORCE-A20 PAL and CPU-RESET PAL.
Appendix B also is attached and incorporated by reference. Appendix B is a computer program listing for the FORCE-A20 and CPU-RESET PALs.
Although a preferred embodiment of the present invention is intended for use with a personal computer based on the INTEL 80286 or 80386 microprocessor, with an INTEL 8042 keyboard controller, it will be realized that 131~10~
the present invention is not intended to be so limited.
Instead, the present invention is intended to cover a system for allowing all input commands to pass directly through to the control device (such as the 8042 keyboard controller) except a designated sequence of input commands tsuch as the commands relating to the FORCE-A20 and CPU-RESET signals). Thus, although variations in the embodi-ment of the present invention may not each realize all of the advantages of the invention, certain features may become more important than others in various applications.
The invention, accordingly, should be understood to be limited only by the scope of the appended claims.
`- 131410~
A P P 1~ N D I ~ A
li . .
=~~ a --T ~ __ ~ D 1 ¦ ~ 1~
131~106 ~
_ . _ -- z : N
_ ~ I C _ _ c I _ ~ I m I c ~14 ~ . 0 6 ~ ~ hl lo 1- . I lll~ ~ 1~1 1 , ~ 1 ~ ] : I ~ ~
~ S
n~ ~D
_ a I ~ 1 m I c _ lq - a I o I ~ ¢ 131 ~10 6 , , _ _ g S ~ r ' ~
_ ~ ~ _ _ _ _ . _ _ ._ _ -- e~ c 5 _ ~ ~ ~c ~ ~. ~ ~
1~ .......... ....... ...... ............ ...... ...... ......... ............. .....
......... ....... ........ , _ .
......... _~.. ......... ....... ....... ............ ......... ...... ..... ............. ........ ......... ......... .....
.~ ~ - r Ll ~ ~ r - 1 ~ ~ i l l l z ~D
---- ~1 l ~ l l a ~
w ~ 1 1 - L~ . r ~ E _ r- ~ ~ 1~ ~ 1 - r ~ r.
[ ~ ~ , E ~ E
~ x ~ O ~ ~ - O c ~ ~ ~ 151 _ ,, C, ~ ~ I C _ ..~
o~
: - ~ l c -~ c _ ~ ~ 1 4 1 0 6 ,, 1-_ r o w --~5¦rn~rl~~ ro~lN~ ol~l_l l ~. ~ u, _ ~ D U, 7 D U' ~ rO N _ _ N N ~ N ~ Vl Lll ~ r~r L'~
m m _ --Q ~ I C _ ~a-P~L20R6 _ P~L L~C~ N SPEI_ I F I C;AT I ON
~VF--~4 JOHN TH~YEfi 2/23/87 ~04 ~20 LINE FIX PAL WITH LONCi t:PU FESET STRtlr~E
CI~PYF;I~HT COMPA~ COMPUTER HCllJSTON, TEXAS 1~)S7 t Lk'; /R5T /C;S A2 /WC: ~15 I:IC) Cl1 Cl_~ D:~: rl4 ~Nrl /OC ~17 /FF_FE_~ C /~: /6!7 /4!1 /~ /HLFCLK /wl~C:04~' D/:~ VCC
C.!O : = /RST * WC; * t ~: ; 6!(:) FClLLOWS WC:, CLE~fiErl ClN REC;ET
6!1 : = C!l * Q---: ; SET TLl ZERO IF STATE C)1IC) + 6!1 */C!2 + 1~!1 * 6!0 + /C.!_: * /C~!;2 * /C!I * /C'!O ; SET T0 ONE IF ST~TE C)C)(~
fi:-;T ; 5ET TCI CINE ON fi'E5ET
l.'!~' : = ; ~;ET IF STATE OC)11 ~ND ~;7 ~NLI r,l ~
/F;ST * /l;~:~ * /1~!~ * ~!1 * 6!(:) *~_'*rJ7*rl~ */~ *rl4*/~l~*f~l ~*/r,l *~c, ;~:EEP SET I F .'.TQTE = C 1 1 C) C,F (1111 + ~R'-;T * f6!:_: * C!2 * 6!l ;~:EEP SET I F STATE = 01(:)-~ C(fi 1 10(:) + /fi'ST * 6!2 * /li!l * /6!
;~EEP C;ET IF STATE = IIC)I
+ /RST * 1~ ' * Q:~ * /6!1 * 4!() C:LEAk IF STATE Cl1O1 ~NLl NClT (A_~ ANrl Crl1::~) ~STAY ONLY IF QNIITHER
;r11 W~ITE TO ~4H~
+ /fi':~T * /~: * ~ ' * /~!1 * 6!0 * ~_'*n7*l~ */rl.ci*rl4*/rl:_:*/rl~r*/rll*rl-.
f!:-: := SET IF STATE 0-.)11 ANrl NOT (A_~ ANrl cr~
; SET IF _;T~TE C)0l 1 ANrl ~ NCIT A~
;T * /Q:~; * /6!:~ * (`!1 * I.!~) * /f~_ ;SET IF STQTE ~011 ANrl NCIT cr, + /fi':_:T * /C!~ * /1~!..' * C!l * QC) * /FF_FE_rll ~ /RC;T * /l~!:3 * /6!7 * 6!1 * 1~!0 * rl7*rl~*~l5*D4*D_:*D2*rl1*rlC) + /R~CJT * /Q--: * /6!7 * Ql * C~!() * ~l7*r)~*rl'~*rl4*rl:--:*r~2*rll*/D(:) + /RC'.T * l~ * /l~ * C!~. * ~!
;CET I F .;TATE O1CI1 ANrl Q_' AN~I Crl I ;~
+ /RST * /6!~ * I~!-' * /I.~!1 * I.!(:I*~ *r(7*rl~*/rl5*~l4*/rl~*/~ */rll*~ll) ;SET IF STATE 11-:)1 + /kST * 1~!3 * Q:2 * /C`! 1 *
/~(:) := ;INVERSE r-(F A2(:I FUNCTIIIN
;CL.EA~ IF 5TATE (l1C!I AN~ (:) WRITE AN~I rll I:-; LCIW
sr * /C!-~: * C! * /l:!l * ~.!I:) * /1~ J * /~l ; OTHEh'W ISE FEE~ 3AC:k::
+ /R~C;T * C!--: * /~''0 /R:~T * /l~!_ * /~
/R~.T * Ql * /1~
+ ~R~T * ~C~ * /A~O
/RST * A2 * /A20 HLFC L~ = ; HALF CLOI~k:: SF EECt OUTPUT F~ iESET P~L T I MEF;
/HLFCLI'.
FF_FE_DI = IJ7--~ 5~C~4f D::~ Cl2~ C~ C~C~
131~106 + D7*~.*/D5*~4~13*/D~*/[1I*[1(~
1 D7*~6* ~5*D4* ~3* ~'2* Cll*/[/O
WCSC)4~ = ;NO D1 WRITE YET~
;~IC1N~T FILTER IF WRITE IS TCI 60H
~C * C:S * WC * ~l * /A~
;DON~T FILTEk IF WkITE IS TCI ~.4H ~ND NOT C~ ,CFE::~ C1fi CFF::~
+ ,~, * ~c, * W1~ * ~1 * /FF_FE_Dl ~ IC1N~T FILTEk IF WklTE IS TC1 ~.4H ~Nrl IS CFE~
+ 1~ * ~ ; * W1~ * ~l * /~
;~FTEk Dl WRITE
;DON'T FILTEk IF WkITE I.C; TCIr'.4HhN~lNl_lTC~, CFE::> qR CFF~
t: * C:S * W13 * /1.!l * Q~ * /FF_FE_rll ,D1-1N~T FILTEk IF WRITE IS TLI~.4H~N~lI'_; CFE~
+ I~'.!C) * I_:C: * Wl_: * /1;~1 * ~q.Lr * /~1(3 F1JN1-:TIC1N T~LE
/1:11:: CL~ ;T 1~17 L1~ 14 r,:: D_ Lll Ll':
1~!3 1.!-~ C`!l ~!': FF_FE_~ C) WC::3C14~ HLFC:L~:
; F WH
F CL
~ : F
; C R R ~ O 1-:
;CILc;~WA~l~lrlrl~l~lrl~l C!l..!l!l!~ 4L
;C: ~ T S C: ~ 7 6 5 4 :-: ~ l C 3 ~ l C~ 1 C) ~
__________________________________________________________________________ LXXXXXHHHHHHH H X X X X HXXX ; TE-;l- FF_C!F;_~1l LXXXXXHHLHLLLH XXXXHXXX
LXXXXXLLHHLLL H X X X X LXXX
;
L~HXXXXXXXXXXX LLHLXHLX; RESET
;
LCLHLXXXXXXXXX LLHLX H LX;/:.4 WRITE NL1T (~ll C1fi FF~
LC:LHHHLLLLLLLL LLH H LHHX
LCLHHHLLLLLLLL HLHHLHHX
LCLHHHLLLLLLLL HLHHLHHX
LCLHLHLLLLLLLL HLHLLHLX
LCLXLXXXXXXXXX LLHLXHLX
Ll:LHLXXXXXXXXX LLHL.XHLX ~-.4WR ITE FF
LC:LHHHH H H H H HH H L LHHHHLX
LC:LHHHHHHHHHHH HLHHHHLX
LCLHHHHHHHHHHH HLHHHHLX
LCLHLHHHHHHHHH HlHLHHLX
LC:LXLXXXXXXXXX LLHLXHLX
LC:LHLXXXXXXXXX LLHLXHI_X /:CI Wfi I TE
LCLHHLXXXXXXXX LLHHXHHX
LC:LHHLXXXXXXXX HLHHXHHX
LCLHHLXXXXXXXX HLHHXHHX
LCLHLLXXXXXXXX HLHLXHLX
L~LXLXXXXXXXXX LLHLXHLX
LC:HXXXXXXXXXXX LLHLXHLX; fi'ESET
;
LCLHLXXXXXXXXX LLHLXHLX C:LEAk ~O
LCLHHHHHLHLLLH LLHHHHLX ;~.4 WfiITE ~ll L~LHHHHHLHLLLH LHHHHHLX
~ It LC HHHHHLHLLLH LHHHHHLX
LC_HLHHHLHLLLH LHHLHHLX
LCLXLXXXXXXXXX LHLLXHLX
LCLHLXXXXXXXXX LHLLXHLX ;~OWRITETOCLE~
LCLHHXXXXXXXLX LHLHXHLX L~TCH
LCLHHXXXXXXXLX LLLHXLLX
LCLHHXXXXXXXLX LLLHXLLX
LCLHLHXXXXXXLX LLLLXLLX
LCLXLXXXXXXXXX LLHLXLLX
LCLHLXXXXXXXXX LLHLXLLX;~ET~
LCLHHHHHLHLLLH LLHHHLLX ;~:.4W~ITE~ll L~LHHHHHLHLLLH LHHHHLLX
LCLHHHHHLHLLLH L.HHHHLLX
LI~LHLHHHLHLLLH L HHLHLLX
LCLXLXXXXXXXXX LHLLXLLX
LC:LHLXXXXXXXXX LHLLXLLX~:4 WF~ITE Cll LCLHHHHHLHLLLH LHLHHLLX
LCLHHHHHLHLLLH HHLHHLLX
LCLHHHHHLHLLLH HHLHHLLX
LCLHLHHHLHLLLH HHLLHLLX
LCLXLXXXXXXXXX LHL.LXI_LX
LCLHLXXXXXXXXX LHLLXLLX ;/:.OWhITETOSET
LCLHHXXXXXXXHX LHLHXLLX ;L~TCH
LCLHHXXXXXXXHX LLLHXHLX
LCLHHXXXXXXXHX LLLHXHLX
LCLHLHXXXXXXHX LLLLXHLX
LCLXLXXXXXXXXX LLHLXHLX
LCHXXXXXXXXXXX LLH L X HLX;~E-;ET
LC:LHLXXXXXXXXX L L HLXHLX;[llTHENFF,E~TBI-lTH
LCLHHHHH L HLLLH LLHHHHLX ~.4WF~ITE~ll LCLHHHHHLHLLLH LHHHHHLX
LCLHHHHHLHLLLH LHHHHHLX
LCLHLHHHLHLLLH LHHLHHLX
LCLXLXXXXXXXXX LHLLXHLX
LC:LHLXXXXXXXXX LHLLXHLX;~4WF; ITE FF
LCLHHHHHHHHHHH LHLHHHLX
LCLHHHHHHHHHHH LLLHHHLX
LCLHHHHHHHHHHH LLLHHHLX
LC:LHLHHHHHHHHH LLLLHh L X
L l_ L X L X X X X X X X X X L L HlXHLX
LCLHLXXXXXXXXX LLHLXH L X;1:1l THEN ~:.4 WF~ITE, E~TI~NLY 1~1 LC:LHHHHHLHLLLH LLHHHHLX ;~.4 WRITE[I
LCLHHHHHLHLLLH LHHHHHLX
LCLHHHHHLHLLLH LHHHHHLX
L~LHLHHHLHLLLH LHHLHHLX
LCLXLXXXXXXXXX LHLLXHLX
LC:LHLXXXXXXXXX LHLLXHLX;6 4 WF~ ITE-:)O
LCLHHHLLLLLLLL LHLHLHHX
LCLHHHLLLLLLLL LLLHLHHX
L~ HHHLLLLLLLL LLLHLHHX
LCLHLHLLLLLLLL LLLLLHLX
~ .
, ~ 1314106 L 1~ ~- X L X X X X X X X X X L L H L X H L X
DESI~R I PT I ON
~ G
~3~410~
PAL ~fi6 . PAL ~iÉ :lCiN ;FEI-IFIC~.TION
A20 ~_5:3 .JOHN THhYEk 2-/ 23 / 37 8042 CP-l RE';ET STkO~E FIX FOR USE W I TH LOWA20 P I CiCiYBhC K PAL
COPYRIÇHT COI~lPhl~ C.OMPUTEfi H4U :TCN TEXhS 1537 CLK /kST h~ X~lO /WC:3l:\4_I /FF_FE_rll I 5 I~:. HLFCLK C.NC
~OC ~WCC:0421_1 /C4 /C3 /C:~ /C:l /CO /C:5 /CPURE5 VCI_ ; rll3N ~T 1`1A~.K NClN FF FE ~11 rlhTA
WC3C)420 = WC::S04-~i * /CC) * /C1 * /C2 * /C:-: * /C:4 * /C.5 * /FF_FE_rl1 lN-~T 1~1ASk:: FF ~11 {lATh I WC:;~ )4~I * /C:O * /L-:l * /C: * /kC-: * /C:4 * /C: 5 * X~10 ; ClCIN T r1ASK PClRT t.OH WR I TE =i + WC:~:04_I * /C:O * /l-1 * /C2 * /C-: * /C:4 * /C:5 * /A-~
CPURES = C:4 * C:5 ~ h.--;5EkT C:Pl_l REC;ET ;IciNhL Cl!`lLY ;lUF;INC. LA-;T l-!UAfiTEfi CIF CCll_lNT
ClELAY 1 . 1~1 I C:RLl~;ECl-lNLl.-; TCI -;TAF~T ClF 5 1~1 I CRCI =;El_:l_lNrl PlJL.-;E
; C;l-~qR~ IF FE TCI ~4 CO : = /kiT * WC~:042I * FF_FE_Cl1 * /XrlO * A- * /CO*/C1*/ -:2*/r:--:*/l 4*/C:S
+ /R5T * HLFCLI. * /C:I:) * C:1 TCll3~1iLE WHEN RE5ET AC:TIVE
+ /R_;T * HLFCLK * /C:O * C
/RC;T * HLFC:LK * /C:O * C:3 + /R5T * HLFCLK * /CCI * C4 + /RST * HLFC:L~ * /CO * C:5 + /R5T * /HLFC:LkK * CO
~; C1 := /fi~_;T * /r:1 * C:O * HLFCL~:: FrlRM HICiHER C:l3UNTER BITi + / RST * C 1 * / C:O
+ /R5T * C 1 * /HLFCL~
1 C 7 : = /fi5T * /C: ~ * C 1 * C C) * HLFCLk::
+ /RST * C2 * /Cl + /R5T * C:2 * /1,0 + /R~T * C2 * /HLFC:LK
C3 := /R5T * /C3 * C2 * C:1 * CO * HLFC:LkK
+ /R_;T * C:3 * /C_ + /RST * C3 * /Cl + /R_;T * C_: * /C:O
+ /RC-;T * C3 * /HLFCLK
C:4 : = /R.-;T * /C:4 * C:3 * C2 * C 1 * C:Cl * HLFC:LK
+ /R5T * C4 * /C 3 + /R5T * C:4 * /L-:-~
+ /RC;T * C:4 * /C:1 /RST * C:4 * /CO
+ /R5T * C4 * /HLFCLIC
CS : = ~RC;T * /C5 * C.4 * C3 * C2 * C 1 * t C~ * HLFCLK
+ /F~e.T * C5 * /C4 + /RST * t5 * /C3 + /RST * C5 * /C2 + /R5T * C'. * /Cl + XR5T * C5 * /CCI
+ /R5T * C5 * /HLFC~LK
F UNC T I ON Th.BLE
13141~6 ., /C~r-LI~kSTWC~042I~2X~I0FF_FE_r~1HLFCL~C
C5.~C3C2C1C0WC804~0CPIJfiES
W W
C FH C:C
;XCk4 XEC 4k ;~ILS~ID~ CCCC:CC2E
;Ch~TI~CI1~ 544210CIS
_______________________________________________________________ L C H X X X X X L L L L L L X L ;F;ESET
LCLLXXXX LL~LLLLL Nl-lSELECT
L C L H L X X X L L L L L L H L ; PCI~T 6C)---- PASC; THfilJ
L C L H X H X X L L L L L L H L FF Clfi [11---- F'~C;S THF;U
L C L H X X L X L L L L L L H L NCITFF, FE 7 0k~11-- F'~ S THfiU
L C L H H L H H L L L L L H L L FE WkITETOF\-IkT~4--C:T~fiTfiECETC;EI2I-IENCE
;
L C: L X X X X L L L L L L H L L ST~fiTC:IIUNT~
LCLXXXXH LLLLHLLL
LCLXXXXL LLLLHLLL
L C: L X X X X H L L L L H HLL
L C L X X X X L L L L L H HLL
LCLXXXXH LLL H L L L L
LCLXXXXL LLLHLLLL
¦ L~LXXXXH LLLHLHLL
LCLXXXXL LLLHL H L L
LCLXXXXH LLL H H L L L
: LCLXXXXL LLLHHLLL
LC~XXXXH LLL H H H L L
LCLXXXXL LLLHHHLL
LCLXXXXH LLHLLLLL
LCLXXXXL LLHLLLLL
LCLXXXXH LLHLLHLL
L C L X X X X L L L H L L H L L
LI_LXXXXH LLHL H L L L
L C. L X X X X L L L H L H L L L
LCLXXXXH LL H L HHLL
LCLXXXXL LLHLHHLL
LC.LXXXXH LLHHLLLL
LCLXXXXL LLHHLLLL
LC:LXXXXH LL H H L H L L
LC:LXXXXL LLH H L H L L
LCLXXXXH LLHHHLLL
LCLXXXXL LLHHHLLL
LCLXXXXH LLHHHHLL
LCLXXXXL LLHHHHLL
LCLXXXXH LHLLLLLL
LCLXXXXL LHLLLLLL
L C L L X X X H L L L L L L L L ; F;ET~IRN TO NClfi'~1f`.L
W W
C F CC
; 4 F 4F' ; 0 F OIJ
;/Ck4 XE 4k 131~106 A P P E N D I X B
f~
131~1~6 Couand Proce~60r lpseudocode) S~ARS
DO
DO
ll~lt OII~IL l~lrlte to couand lnput port or data input port is detected IRDDO
rlte Ul to data port~ ~RER
call routine to ~end the data ln the data lnput port to teyboard ~LSe Rar~e coDand:
le ~data in coDand pott egual~ Dlh~ sHeR
DO
~ l~it URTIL (~Irlte to couand input port or data input port i~ detected) IRDDO
Il (ulte ~la6 to data input port~ IlleR
copy content6 of data lnput port to output port 12 eLse GOTO Ru-e cou~and:
IRDII
ILSI 11 Iulue ln co and lnput ~ort egual~ ~h 1~ Don t care ~lt~l~ SReR
aa~e eontent~ of output ~ort R2 in urlz~le Oldoutreg logicall~ ARD the content6 of output regi6ter ~2 ~ith the ulue in the Input couand port and copy the re6ult to the output regi~ter R2 ait S nlcrosecond6 copy the ~alue of Oldootreg to utput port 12 ILSe proce~ other coDand~ not related to IORCE-A20 or ReSe~-C~U
IRDII
IRDII
e~eA~ Ifore~er~
IRDDO
3 o
;Ch~TI~CI1~ 544210CIS
_______________________________________________________________ L C H X X X X X L L L L L L X L ;F;ESET
LCLLXXXX LL~LLLLL Nl-lSELECT
L C L H L X X X L L L L L L H L ; PCI~T 6C)---- PASC; THfilJ
L C L H X H X X L L L L L L H L FF Clfi [11---- F'~C;S THF;U
L C L H X X L X L L L L L L H L NCITFF, FE 7 0k~11-- F'~ S THfiU
L C L H H L H H L L L L L H L L FE WkITETOF\-IkT~4--C:T~fiTfiECETC;EI2I-IENCE
;
L C: L X X X X L L L L L L H L L ST~fiTC:IIUNT~
LCLXXXXH LLLLHLLL
LCLXXXXL LLLLHLLL
L C: L X X X X H L L L L H HLL
L C L X X X X L L L L L H HLL
LCLXXXXH LLL H L L L L
LCLXXXXL LLLHLLLL
¦ L~LXXXXH LLLHLHLL
LCLXXXXL LLLHL H L L
LCLXXXXH LLL H H L L L
: LCLXXXXL LLLHHLLL
LC~XXXXH LLL H H H L L
LCLXXXXL LLLHHHLL
LCLXXXXH LLHLLLLL
LCLXXXXL LLHLLLLL
LCLXXXXH LLHLLHLL
L C L X X X X L L L H L L H L L
LI_LXXXXH LLHL H L L L
L C. L X X X X L L L H L H L L L
LCLXXXXH LL H L HHLL
LCLXXXXL LLHLHHLL
LC.LXXXXH LLHHLLLL
LCLXXXXL LLHHLLLL
LC:LXXXXH LL H H L H L L
LC:LXXXXL LLH H L H L L
LCLXXXXH LLHHHLLL
LCLXXXXL LLHHHLLL
LCLXXXXH LLHHHHLL
LCLXXXXL LLHHHHLL
LCLXXXXH LHLLLLLL
LCLXXXXL LHLLLLLL
L C L L X X X H L L L L L L L L ; F;ET~IRN TO NClfi'~1f`.L
W W
C F CC
; 4 F 4F' ; 0 F OIJ
;/Ck4 XE 4k 131~106 A P P E N D I X B
f~
131~1~6 Couand Proce~60r lpseudocode) S~ARS
DO
DO
ll~lt OII~IL l~lrlte to couand lnput port or data input port is detected IRDDO
rlte Ul to data port~ ~RER
call routine to ~end the data ln the data lnput port to teyboard ~LSe Rar~e coDand:
le ~data in coDand pott egual~ Dlh~ sHeR
DO
~ l~it URTIL (~Irlte to couand input port or data input port i~ detected) IRDDO
Il (ulte ~la6 to data input port~ IlleR
copy content6 of data lnput port to output port 12 eLse GOTO Ru-e cou~and:
IRDII
ILSI 11 Iulue ln co and lnput ~ort egual~ ~h 1~ Don t care ~lt~l~ SReR
aa~e eontent~ of output ~ort R2 in urlz~le Oldoutreg logicall~ ARD the content6 of output regi6ter ~2 ~ith the ulue in the Input couand port and copy the re6ult to the output regi~ter R2 ait S nlcrosecond6 copy the ~alue of Oldootreg to utput port 12 ILSe proce~ other coDand~ not related to IORCE-A20 or ReSe~-C~U
IRDII
IRDII
e~eA~ Ifore~er~
IRDDO
3 o
Claims (10)
1. A method for filtering the commands available to a microprocessor, comprising the steps of:
(a) monitoring all input commands to the microprocessor;
(b) intercepting a predetermined sequence of input commands matching programmable criteria;
(c) processing said intercepted commands according to programmable logic to compute output signals;
and (d) outputting said computed signals corresponding to said predetermined sequence of input commands.
(a) monitoring all input commands to the microprocessor;
(b) intercepting a predetermined sequence of input commands matching programmable criteria;
(c) processing said intercepted commands according to programmable logic to compute output signals;
and (d) outputting said computed signals corresponding to said predetermined sequence of input commands.
2. The method of claim 1 wherein programmable logic array means is used to determine said programmable cri-teria and process said intercepted commands.
3. The method of claim 1 wherein gate array means is used to determine said programmable criteria and process said intercepted commands.
4. The method of claim 1 wherein the microprocessor is a keyboard controller.
5. A programmable system for filtering input commands to a control device functionally attached to input lines of a microprocessor, said system comprising:
(a) at least one programmable logic array means for monitoring input lines to said control device and allowing all input commands to pass directly through to said control device except a desig-nated sequence of input commands; and (b) output means for outputting a signal from said programmable logic array means to said input lines of said microprocessor, said output signal corresponding to said designated sequence of input commands.
(a) at least one programmable logic array means for monitoring input lines to said control device and allowing all input commands to pass directly through to said control device except a desig-nated sequence of input commands; and (b) output means for outputting a signal from said programmable logic array means to said input lines of said microprocessor, said output signal corresponding to said designated sequence of input commands.
6. The system of claim 5 wherein said designated sequence of input commands relate to switching between real address mode and protected mode in an INTEL 80286 or INTEL 80386 microprocessor.
7. The system of claim 6 wherein said designated sequence of input commands relates to the FORCE-A20 signal and the CPU-RESET signal.
8. A system for selecting and processing designated commands relating to the FORCE-A20 signal and CPU-RESET
signal for a keyboard controller functionally attached to an INTEL 80286 or INTEL 80386 microprocessor, said system comprising:
(a) input means for monitoring all input commands to said keyboard controller;
(b) first programmable logic array means for allow-ing all input commands to pass directly through to said keyboard controller except the command sequence relating to the FORCE-A20 signal;
(c) second programmable logic array means for allowing all input commands to pass directly through to said keyboard controller except the command sequence relating to the CPU-RESET
signal; and (d) output means for outputting the FORCE-A20 signal from said first programmable logic array means and the CPU-RESET signal from said second pro-grammable logic array means, said output signal functionally connected to said INTEL 80286 or INTEL 80386 microprocessor.
signal for a keyboard controller functionally attached to an INTEL 80286 or INTEL 80386 microprocessor, said system comprising:
(a) input means for monitoring all input commands to said keyboard controller;
(b) first programmable logic array means for allow-ing all input commands to pass directly through to said keyboard controller except the command sequence relating to the FORCE-A20 signal;
(c) second programmable logic array means for allowing all input commands to pass directly through to said keyboard controller except the command sequence relating to the CPU-RESET
signal; and (d) output means for outputting the FORCE-A20 signal from said first programmable logic array means and the CPU-RESET signal from said second pro-grammable logic array means, said output signal functionally connected to said INTEL 80286 or INTEL 80386 microprocessor.
9. The system of claim 8 wherein said FORCE-A20 signal is set and reset by a two-byte command sequence, said sequence comprising:
(a) a first byte indicating that the FORCE-A20 line is to be changed; and (b) a second byte indicating whether the FORCE-A20 line will be high or low.
(a) a first byte indicating that the FORCE-A20 line is to be changed; and (b) a second byte indicating whether the FORCE-A20 line will be high or low.
10. The system of claim 8 wherein said CPU-RESET signal comprises:
(a) a predetermined delay time before activating said CPU-RESET signal; and (b) a strobe signal activated for a designated time period.
(a) a predetermined delay time before activating said CPU-RESET signal; and (b) a strobe signal activated for a designated time period.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US088,093 | 1987-08-21 | ||
| US07/088,093 US5226122A (en) | 1987-08-21 | 1987-08-21 | Programmable logic system for filtering commands to a microprocessor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1314106C true CA1314106C (en) | 1993-03-02 |
Family
ID=22209343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000575359A Expired - Lifetime CA1314106C (en) | 1987-08-21 | 1988-08-22 | Programmable logic system for filtering commands to a microprocessor |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US5226122A (en) |
| CA (1) | CA1314106C (en) |
Families Citing this family (74)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5870602A (en) * | 1987-11-03 | 1999-02-09 | Compaq Computer Corporation | Multi-processor system with system wide reset and partial system reset capabilities |
| US5483646A (en) * | 1989-09-29 | 1996-01-09 | Kabushiki Kaisha Toshiba | Memory access control method and system for realizing the same |
| US5283889A (en) * | 1989-12-29 | 1994-02-01 | Zenith Data Systems Corporation | Hardware based interface for mode switching to access memory above one megabyte |
| US5872967A (en) * | 1989-12-29 | 1999-02-16 | Packard Bell Nec | Method for warm boot from reset |
| US6009495A (en) * | 1989-12-29 | 1999-12-28 | Packard Bell Nec | Protected address range in an electrically erasable programmable read only memory |
| US5822601A (en) * | 1989-12-29 | 1998-10-13 | Packard Bell Nec | Apparatus to allow a CPU to control the relocation of code blocks for other CPUs |
| US5519873A (en) * | 1990-08-31 | 1996-05-21 | International Business Machines Corporation | Apparatus for switching digital command execution between a general purpose microprocessor and dedicted execution logic |
| JP2677719B2 (en) * | 1991-05-08 | 1997-11-17 | 富士通株式会社 | Information processing device |
| US5389952A (en) * | 1992-12-02 | 1995-02-14 | Cordata Inc. | Low-power-consumption monitor standby system |
| US5821924A (en) * | 1992-09-04 | 1998-10-13 | Elonex I.P. Holdings, Ltd. | Computer peripherals low-power-consumption standby system |
| US5509139A (en) * | 1993-03-22 | 1996-04-16 | Compaq Computer Corp. | Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode |
| US5537576A (en) * | 1993-06-23 | 1996-07-16 | Dsp Semiconductors Ltd. | Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space |
| US5448717A (en) * | 1993-07-06 | 1995-09-05 | Intel Corporation | Transparently inserting wait states into memory accesses when microprocessor in performing in-circuit emulation |
| US5867655A (en) * | 1993-12-08 | 1999-02-02 | Packard Bell Nec | Method to store privileged data within the primary CPU memory space |
| US5596713A (en) * | 1993-12-08 | 1997-01-21 | Zenith Data Systems Corporation | Method to prevent data loss in an electrically erasable read only memory |
| US5752063A (en) * | 1993-12-08 | 1998-05-12 | Packard Bell Nec | Write inhibited registers |
| US5742841A (en) * | 1993-12-08 | 1998-04-21 | Packard Bell Nec | Alternate I/O port access to standard register set |
| US6161162A (en) * | 1993-12-08 | 2000-12-12 | Nec Corporation | Multiprocessor system for enabling shared access to a memory |
| US5666522A (en) * | 1994-01-28 | 1997-09-09 | Micron Electronics, Inc. | Variable speed controller |
| US5987618A (en) * | 1994-03-25 | 1999-11-16 | Packard Bell Nec | Programmable hardware timer including two programmable hardware downcounters wherein the second downcounter counts in multiples of the first downcounter |
| US5764995A (en) * | 1994-03-25 | 1998-06-09 | Packard Bell Nec | Write once read only registers |
| US5692189A (en) * | 1994-07-05 | 1997-11-25 | Microsoft Corporation | Method and apparatus for isolating circuit boards in a computer system |
| US5574943A (en) * | 1994-12-09 | 1996-11-12 | Ast Research, Inc. | Gate-A20 and CPU reset circuit for mircroprocessor-based computer system |
| US6006030A (en) * | 1995-02-17 | 1999-12-21 | Vlsi Technology, Inc. | Microprocessor with programmable instruction trap for deimplementing instructions |
| US5758170A (en) * | 1995-03-20 | 1998-05-26 | Dell Usa, L.P. | System for preventing corruption during CPU reset |
| US5878246A (en) * | 1995-07-05 | 1999-03-02 | Sun Microsystems, Inc. | System for linking an interposition module between two modules to provide compatibility as module versions change |
| US5724502A (en) * | 1995-08-07 | 1998-03-03 | International Business Machines Corporation | Test mode matrix circuit for an embedded microprocessor core |
| US5862370A (en) * | 1995-09-27 | 1999-01-19 | Vlsi Technology, Inc. | Data processor system with instruction substitution filter for deimplementing instructions |
| US5857116A (en) * | 1995-10-27 | 1999-01-05 | Compaq Computer Corporation | Circuit for disabling an address masking control signal when a microprocessor is in a system management mode |
| US5943242A (en) | 1995-11-17 | 1999-08-24 | Pact Gmbh | Dynamically reconfigurable data processing system |
| KR0180680B1 (en) * | 1995-12-08 | 1999-05-15 | 윤종용 | Reset apparatus of central processing unit and method thereof |
| US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
| US5784625A (en) * | 1996-03-19 | 1998-07-21 | Vlsi Technology, Inc. | Method and apparatus for effecting a soft reset in a processor device without requiring a dedicated external pin |
| DE19651075A1 (en) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like |
| US6338106B1 (en) | 1996-12-20 | 2002-01-08 | Pact Gmbh | I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures |
| DE19654593A1 (en) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | Reconfiguration procedure for programmable blocks at runtime |
| DE19654595A1 (en) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures |
| DE19654846A1 (en) | 1996-12-27 | 1998-07-09 | Pact Inf Tech Gmbh | Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.) |
| EP1329816B1 (en) | 1996-12-27 | 2011-06-22 | Richter, Thomas | Method for automatic dynamic unloading of data flow processors (dfp) as well as modules with bidimensional or multidimensional programmable cell structures (fpgas, dpgas or the like) |
| DE19704044A1 (en) * | 1997-02-04 | 1998-08-13 | Pact Inf Tech Gmbh | Address generation with systems having programmable modules |
| US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
| DE19704728A1 (en) | 1997-02-08 | 1998-08-13 | Pact Inf Tech Gmbh | Method for self-synchronization of configurable elements of a programmable module |
| DE19704742A1 (en) | 1997-02-11 | 1998-09-24 | Pact Inf Tech Gmbh | Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort |
| US5964853A (en) * | 1997-03-07 | 1999-10-12 | National Semiconductor Corp. | Interface controller including hardware mechanism to handle PS/2 interface |
| US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
| DE19861088A1 (en) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Repairing integrated circuits by replacing subassemblies with substitutes |
| DE19807872A1 (en) | 1998-02-25 | 1999-08-26 | Pact Inf Tech Gmbh | Method of managing configuration data in data flow processors |
| US6625649B1 (en) | 1998-06-08 | 2003-09-23 | Hewlett-Packard Development Company, L.P. | Rapid network access computer system |
| EP1228440B1 (en) | 1999-06-10 | 2017-04-05 | PACT XPP Technologies AG | Sequence partitioning in cell structures |
| ATE476700T1 (en) | 2000-06-13 | 2010-08-15 | Richter Thomas | PIPELINE CT PROTOCOLS AND COMMUNICATIONS |
| US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
| US7595659B2 (en) | 2000-10-09 | 2009-09-29 | Pact Xpp Technologies Ag | Logic cell array and bus system |
| US6990555B2 (en) * | 2001-01-09 | 2006-01-24 | Pact Xpp Technologies Ag | Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) |
| US7581076B2 (en) | 2001-03-05 | 2009-08-25 | Pact Xpp Technologies Ag | Methods and devices for treating and/or processing data |
| US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
| US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
| WO2005045692A2 (en) | 2003-08-28 | 2005-05-19 | Pact Xpp Technologies Ag | Data processing device and method |
| US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
| US7210129B2 (en) | 2001-08-16 | 2007-04-24 | Pact Xpp Technologies Ag | Method for translating programs for reconfigurable architectures |
| JP2004533691A (en) | 2001-06-20 | 2004-11-04 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Methods for processing data |
| US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
| US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
| US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
| US7577822B2 (en) | 2001-12-14 | 2009-08-18 | Pact Xpp Technologies Ag | Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization |
| WO2003060747A2 (en) | 2002-01-19 | 2003-07-24 | Pact Xpp Technologies Ag | Reconfigurable processor |
| AU2003214003A1 (en) | 2002-02-18 | 2003-09-09 | Pact Xpp Technologies Ag | Bus systems and method for reconfiguration |
| US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
| AU2003286131A1 (en) | 2002-08-07 | 2004-03-19 | Pact Xpp Technologies Ag | Method and device for processing data |
| US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
| JP4388895B2 (en) | 2002-09-06 | 2009-12-24 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Reconfigurable sequencer structure |
| TWI233564B (en) * | 2003-08-12 | 2005-06-01 | Ene Technology Inc | Keyboard controller |
| EP1974265A1 (en) | 2006-01-18 | 2008-10-01 | PACT XPP Technologies AG | Hardware definition method |
| WO2011005890A2 (en) * | 2009-07-07 | 2011-01-13 | Kuity Corp. | A hardware command filter matrix integrated circuit with restricted command enforcement capability |
| US20110167496A1 (en) * | 2009-07-07 | 2011-07-07 | Kuity Corp. | Enhanced hardware command filter matrix integrated circuit |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3970989A (en) * | 1974-03-06 | 1976-07-20 | Ontel Corporation | Data transfer error check |
| JPS5444535B2 (en) * | 1975-01-31 | 1979-12-26 | ||
| US4050098A (en) * | 1975-11-17 | 1977-09-20 | Gulf & Western Industries, Inc. | Self-addressing modules for programmable controller |
| US4367524A (en) * | 1980-02-07 | 1983-01-04 | Intel Corporation | Microinstruction execution unit for use in a microprocessor |
| US4438492A (en) * | 1980-08-01 | 1984-03-20 | Advanced Micro Devices, Inc. | Interruptable microprogram controller for microcomputer systems |
| US4434461A (en) * | 1980-09-15 | 1984-02-28 | Motorola, Inc. | Microprocessor with duplicate registers for processing interrupts |
| US4459662A (en) * | 1980-09-29 | 1984-07-10 | Texas Instruments Incorporated | Microcomputer having ROM mass memory for downloading main RAM memory with microcomputer instructions |
| US4402043A (en) * | 1980-11-24 | 1983-08-30 | Texas Instruments Incorporated | Microprocessor with compressed control ROM |
| US4556938A (en) * | 1982-02-22 | 1985-12-03 | International Business Machines Corp. | Microcode control mechanism utilizing programmable microcode repeat counter |
| US4519033A (en) * | 1982-08-02 | 1985-05-21 | Motorola, Inc. | Control state sequencer |
| US4493034A (en) * | 1982-10-14 | 1985-01-08 | Honeywell Information Systems Inc. | Apparatus and method for an operating system supervisor in a data processing system |
| US4488230A (en) * | 1982-12-08 | 1984-12-11 | At&T Bell Laboratories | Programmed logic array with external signals introduced between its AND plane and its OR plane |
| US4613936A (en) * | 1983-02-25 | 1986-09-23 | International Business Machines Corporation | Centralized generation of data transfer acknowledge pulses for microprocessors |
| US4562538A (en) * | 1983-05-16 | 1985-12-31 | At&T Bell Laboratories | Microprocessor having decision pointer to process restore position |
| JPS6017539A (en) * | 1983-07-11 | 1985-01-29 | Hitachi Ltd | Emulation system |
| US4598356A (en) * | 1983-12-30 | 1986-07-01 | International Business Machines Corporation | Data processing system including a main processor and a co-processor and co-processor error handling logic |
| JPS60181866A (en) * | 1984-02-29 | 1985-09-17 | Toshiba Corp | Key data emulation system |
| US4617479B1 (en) * | 1984-05-03 | 1993-09-21 | Altera Semiconductor Corp. | Programmable logic array device using eprom technology |
| US4745574A (en) * | 1984-10-15 | 1988-05-17 | Motorola, Inc. | Microcode testing of PLA's in a data processor |
| US4695945A (en) * | 1985-02-28 | 1987-09-22 | International Business Machines Corporation | Processor I/O and interrupt filters allowing a co-processor to run software unknown to the main processor |
| US4779187A (en) * | 1985-04-10 | 1988-10-18 | Microsoft Corporation | Method and operating system for executing programs in a multi-mode microprocessor |
| CA1234224A (en) * | 1985-05-28 | 1988-03-15 | Boleslav Sykora | Computer memory management system |
| DE3584446D1 (en) * | 1985-06-18 | 1991-11-21 | Ibm | MICROPROCESSOR. |
| US4747040A (en) * | 1985-10-09 | 1988-05-24 | American Telephone & Telegraph Company | Dual operating system computer |
| US4875186A (en) * | 1986-02-28 | 1989-10-17 | Prime Computer, Inc. | Peripheral emulation apparatus |
| US4749991A (en) * | 1986-07-05 | 1988-06-07 | Motorola, Inc. | Turn off protection circuit |
| US4787032A (en) * | 1986-09-08 | 1988-11-22 | Compaq Computer Corporation | Priority arbitration circuit for processor access |
| US4849875A (en) * | 1987-03-03 | 1989-07-18 | Tandon Corporation | Computer address modification system with optional DMA paging |
| US4928237A (en) * | 1987-03-27 | 1990-05-22 | International Business Machines Corp. | Computer system having mode independent addressing |
| US4926322A (en) * | 1987-08-03 | 1990-05-15 | Compag Computer Corporation | Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management |
| US5018062A (en) * | 1987-10-23 | 1991-05-21 | A.I. Architects, Inc. | Method and apparatus for overriding a ROM routine in response to a reset |
| US4868822A (en) * | 1988-02-19 | 1989-09-19 | John Fluke Mfg. Co., Inc. | Memory emulation method and system for testing and troubleshooting microprocessor-based electronic systems |
-
1987
- 1987-08-21 US US07/088,093 patent/US5226122A/en not_active Expired - Lifetime
-
1988
- 1988-08-22 CA CA000575359A patent/CA1314106C/en not_active Expired - Lifetime
-
1993
- 1993-06-30 US US08/084,632 patent/US5381530A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5381530A (en) | 1995-01-10 |
| US5226122A (en) | 1993-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1314106C (en) | Programmable logic system for filtering commands to a microprocessor | |
| US5027273A (en) | Method and operating system for executing programs in a multi-mode microprocessor | |
| US4825358A (en) | Method and operating system for executing programs in a multi-mode microprocessor | |
| US4779187A (en) | Method and operating system for executing programs in a multi-mode microprocessor | |
| US5125087A (en) | Method of resetting sequence of access to extended memory disrupted by interrupt processing in 80286 compatible system using code segment register | |
| US5263168A (en) | Circuitry for automatically entering and terminating an initialization mode in a data processing system in response to a control signal | |
| CN1208718C (en) | Computer system including memory access controller for using non-system memory storage resources during system boot time | |
| US6157979A (en) | Programmable controlling device with non-volatile ferroelectric state-machines for restarting processor when power is restored with execution states retained in said non-volatile state-machines on power down | |
| US4095268A (en) | System for stopping and restarting the operation of a data processor | |
| US6865636B1 (en) | Multitasking processor system for monitoring interrupt events | |
| JPH06242987A (en) | Method and equipment for making host computer execute succession of normal processing of microprocessor in computer unit | |
| US5696957A (en) | Integrated circuit comprising a central processing unit for executing a plurality of programs | |
| US8464016B2 (en) | Method and device for switching over in a memory for a control device | |
| US5842012A (en) | Efficient soft reset in a personal computer | |
| US4486833A (en) | Microprocessor peripheral control circuit | |
| EP0575171B1 (en) | Enhanced system management method and apparatus | |
| EP1652079A2 (en) | Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set | |
| US6182207B1 (en) | Microcontroller with register system for the indirect accessing of internal memory via auxiliary register | |
| KR20140135796A (en) | Microcontroller with context switch | |
| JPH08255476A (en) | Apparatus and method for memory extended stack in data-processing system | |
| WO1995034905A1 (en) | Computer system with peripheral control functions integrated into host cpu | |
| JPS60214044A (en) | Microcomputer | |
| Cates et al. | An ASIC RISC-based I/O processor for computer applications | |
| JP3616649B2 (en) | Method and apparatus for enabling address lines to access upper memory areas | |
| KR970004866B1 (en) | Memory for common devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |