CA1304153C - Video signal synchronization system as for an extended definitionwidescreen television signal processing system - Google Patents

Abstract

RCA 85,065 ABSTRACT OF THE DISCLOSURE
Apparatus and a method of synchronizing the component signals of a multi-component augmented television signal between its generation reception are disclosed. The disclosed apparatus includes circuitry which generates a training signal that indicates the position of the first pixel in each horizontal line interval of the video signal.
This training signal is inserted into one horizontal line interval of the active video signal for transmission. The receiver includes circuitry which separates the training signal and derives a timing signal from it. The timing signal is used to define the pixel positions of various decoded components of the received video signal to facilitate their combination. The timing signal is also used to align the color subcarrier signal and to generate other carrier and subcarrier signals used in the decoding process. Two training signals are disclosed: a pseudo-random noise sequence and a time-reversed, all-pass filtered, raised-cosine 2T pulse.

Description

l;~G~ 3 -1- RCA 85,065 VIDEO SIGNAL SYNCHRONlZATION SYSTEM AS lFOR AN
EXTENDIl!~G DEFINITION WIDESCRE~EN ~LEVISIO~
SIGNAL PROOESSING SYSTEM

This invention relates to apparatus and a method for synchronizing various component signals of an augmented television signal so that they may be properly recomb;ned at a receiver to reproduce an enhanced image.
A conventional television rcceiver, such as a receiver in accordance with ~TSC broadcast standards adopted in the United States and elsewhere, has a 4:3 aspect ratio (the ratio of the width to the height of a displayed image). Recently, there has been interest in using higher aspect ratios for television receiver systems, such as 2:1, 16:9 or 5:3, since such higher aspect ratios more nearly approximate or e~ual the aspec~ ratio of the human eye than does the 4:3 aspect ratio of a conventional television receiver. Video images having a 5:3 aspect ratio have received particular attention since this ra~io approximates that of motion picture film. However, widescreen television systems which 2 0 simply transmit signals having an increased aspect ratio as compared to conventional systems are incompatible with conventional aspect ratio receivers. This makes widescreen adoption of widescreen systems difficult.
It is therefore desirable to have a widescreen system 2 5 which is compatible with conventional television receivers. One - such system is disclosed in U.S. Patent 4,816,899 of C. H. Strolle et al., titled "Compatible Widescreen Television System".
It is even more desirable to have such a compatible widescreen system with provisions for enhancing or extending the 3 0 definition of the displayed image so as to provide extra image detail. For example, such widescreen EDTV (extended definition television) system may include apparatus for providing a progressively scanned image.

:, :

'~
, -:13(~gl.'1S3 -2- RCA 85,065 .
EDTY systems have been proposed which include provisions for inserting a signal representing the more detailed areas of an image into a portion of the video spectrum which is currently unused or which is not used efficiently under current 5 television standards. One of these proposals is set forth in U~S.
Patent No. 4,660,072 issued in the name of T. Fukinuki on April 21, 1987. A second proposal is presented in an article by Y. Yasumoto et al. "An Ex~ended Definition Television System Using Quadrature Modulation of the Video Carrier with Inverse 10 Ny~quist Filter" I~EE Transactions on Consumer Electronics, August, 1987, pp. 173~180. A third proposal is presented in an article by M. A. Isna~di et al. entitled "Decoding Issues in the ACTV System", IEEE Transactions on Consumer Electronics, ~ebruary 1988, pp.
1 1 1-120.
In the Fukinuki proposal, relatively high frequency informatioll is separated from an original high definition video signal, frequency converted to occupy a lower band of frequencies and then modulated onto an alternate subcarrier signal which is within the frequency spectrum of a conventional video signal.
2 0 This alternate subcarrier signal, like the chrominance subcarrier signal of a conventional composite video signal, is an odd multiple of one-half the horizontal line frequency but, unlike the chrominance subcarrier signal, it switches in phase by 180 from field to field. This modulated alternate subcarrier signal may be 2 5 substantially recovered at the receiver.
In the receiver, the high resolution signal is recovered from the modulated alternate subcarrier, restored to its original band of frequencies and added to the conventionally decoded luminance signal to produce a high definition luminance signal.
The Yasumoto et al. proposal uses an enhancement signal which may represent either high frequenGy luminance information or side-panel information needed to expand the . f,~, . .

~3~ S3 -3- RCA 85,065 aspect ratio of a transmitted image from 4 3 to, for example, 5.3. This enhancement si~nal is frequency converted to occupy a lower band of freguencies and then modulated onto a carrier which is in ~uadrature phase relative to the picture carrier signal of the transmitted video signal.
At the receiver, this enhancement signal is recovered by synchronous demodulation of the video signal.
The recovered sig~al is then frequency converted to occupy its original band of frequencies and com~ined with the conventionally processed video signal to produce an enhanced (high de~inition or widescreen) video image.
The Isnardi et al. proposal compresses side panel low frequency information of a widescreen image into the horizontal overscan region o a compatible NTSC Television signal. The high frequency information for the side panels and high freguency information for the entire widescreen image are quadrature modulated onto an interlaced carrier which changes phase by 180 from field to field. A fourth signal component, which is used to recons~ruct a progressive scan image from the in~erlace scan si~nal, is mo~ulated in quadrature with the combined first three component~ onto the video carrier signal.
At the receiver, a combination o s~nchronous demodulation and intra-frame processing is used to recover the four components. These components are combined to produce an extanded definition television signal.
In any of the systems described above, slight timing errors may occur in the signals used for frequency-converting the enhancement signals at the transmitter and at the receiver, or in signals used to determine relative pixel locations of the side panel and center panel information for the extended definition and/or enhanced aspect ratio image. These timing errors may distort the reproduced enhanced image causing, for example, dark areas of detailed in~ormation ~o appear erroneously bright or causing visible seams where the side panel and ~3~153 -4- RCA 85,065 center panel regions of a wide aspect ratio image are joined.
The present invention is embodied in apparatus for synchronizing the various components of an augmented vid~o signal after it is received. The apparatus includes circuitry in a video signal generation system for producing a training signal which is indicative of an instant in time and circuitry for adding the training signal to the augmented video signal. In the receiver, the apparatus includes circuitry for processin~ the training signal componen~ of the augment~d video signal t~ d~velop a reference time signal and circuitry for aligning components of said augmented video signal to the reference time signal.
FIGURE 1 illustrates a general overview of a compatible wid~screen EDTV encoder system in accordance with the present in~ention;
FIGURE la shows a detailed block diagram of the encoder for the disclosed system;
FIGURES lb-le contain diagrams helpful in understanding the operation of the disclosed system;
FIGURES 2-5 depict signal waveforms and diagrams helpful in understanding th~ operation of the disclosed system;
FIGURE 13 shows a block diagr~m o~ a portion of a - widescreen EDTV receiver including decoder apparatus in accordance with the present invention; and FIGURES 6-12 and 14-27 illustrate aspects of the disclosed system in greater detail.
In the drawings, single line arrows may represent busses for con~eying multiple bit parallel digital signals, or signal paths for conveying analog signals or single bit digi~al signals. The type of signal conveyed by a bus or signal path is made clear in the context in which it is discussed. As will be appreciate~ ~y those skilled in the art, apparatus for providing compensating delays may be required in certain of the signal paths. Such delay apparatus is not shown to simplify the description.

~3(~4~LS3 -5- R~A 85,065 The system shown in FIGURE 1 is sub~tantially the same as the encodex set for~h in the abo~e-referenced article by Isnardi et al.
In this system, elements which are common to ~he more detailed s~stem of FIGURE la are identified by the same reference number. As shown in Figure 1, an original widescreen progressive-sca~ signhl with left, right and center panel information is processed so as to develop four separate encoding components. These four components are illustrated generally in Figure 1 in the context of an imag~ display. Processing of the first component, which contains time expanded center panel pixel data and time compressed side panel pixel data, is such that the reæulting luminance bandwidth does not exceed the NTSC
luminance bandwidth of 4.2 MHz. This signal i5 color encoded in standard NTSC format, and the luminance and chrominance components of ~his signal are suitably pre-filtered (e.g., using field comb filters~ to provide improved luminance-chrominance separation at both standard NTSC and widescreen receivers. In proressing signals which represent the first component, the relative timing of the portions of the signal which represent the side and center panels is important. Even a slight error in the relative timin~ of these components may produce a visible seam in the reproduced image.
The second component, which includes side panel high frequency information, is time expanded ~o reduce its horizontal bandwidth to about 1.1 MHz. This component is spatially uncorrelated with the main signal (the first component), and special precautions are taken to mask its visibility on standard NTSC receivers. These precautions are described below. The relative timing of the side and center panel siynal components is important for the second component as well. In addition, sinc~, as described below, component 2 i~ guadrature modulated with componen~ 3 onto an alternate subcarrier. The alternate subcarrier is desirably kept in strict phase alignment between the transmitter and the receivex.

~3~

-6 RCA 85,065 The 5.O to 6.2 M~z e~tended high-frequency luminance information for th~ center panel region is contained in the third component. This component is first heterodyned to occupy a frequency range of 0 to 1.2 MHz and then mapped into the standard 4:3 format. The mapping operation spati~lly correlates the third component with the main signal ~the first component) to mask its visibility on standard NTSC receivers. The compressed sid~ panel information of the third component exhibits a bandwidth which is one-sixth that of the center information ~0-1.2 M~z). For the third component, the relative timing of the side and center panel signals, the phase of the alternate subcarrier signal and the frequency and phase ~f the S M~z signal used to shift the frequency spectrum of the third 15 component between 5-6.2 MHz and 0-1.2 MHz are all of great importance.
It is contemplated that the processing of the component 3 signals may be simplified by compressing an entire field of component 3 signal into the center panel region instead of expanding the center panel portion and compressing the side panel portion as shown. This alternative technique could produce slightly lower center panel resolution, improved side panel resolution and would simplify the circuits used to decode the component 3 si~nal at the r~ceiver. This modification would also make the circuits which process the compone~t 3 signals less sensitive to the relative timing of the signals representing the side and center panel portions of the image.
The fourth component is a vertical-temporal helper signal which is used to convert the received interlace scan signal i~to a progressive scan format. This signal is mapped into standard 4;3 format to correlate it with ~he main signal component and thereby mask its visibility on standard NTSC receivers. The horizontal bandwidth of the v~rtical-temporal helper signal is limited to 750 K~Z.

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~3~

-7- RCA 85,065 In FIGURE 1, the first, second, and third components are processed by respective intxaframe averagers 38, 64, and 76 (a type of vertical-temporal (V-T) filter~
to eliminate V-T crosstalk between khe main and auxiliary signal components at a widescreen receiver. The first component is intraframe averaged only above 1.5 MHz. The second and third intraframe averaged components, identified as X and Z, are non-linearly amplitude compressed and then used to quadrature modulate, in a block 80, a 3.108 MHz alternata subcarrier signal ASC, ha~ing a phase which alternates by 180 from line to-line and from field to field. A modulated signal ~M3 from block 80 is added to the intraframe averaged first component (N) in an adder 40.
The output signal produced by the adder 40 is a 4.2 M~z bandwidth baseband signal ~NTSCF). To aid in synchronizing the receiver to the signal provided by the transmitter, a composite synchronizing signal and a training signal which specifies the timing of the first pixel on each horizontal line of a field are inserted into the sig~al ~TSCF as described below. The signal NTSCF and a 750 R~z low pass filtered fsur~h component (YTN) from a filter 79, are used to quadrature modulate an RF picture carrier in a block 57 to produce an NTSC compati~le R~ signal. This signal can be transmitted to a standard NTSC receiver or a widescreen Progressive scan receiver via a single, standard bandwidth, broadcast channel.
When received by a standard NTSC receiver, only the center panel portion of the main signal ~he first component) is seen. The ~econd and third components may create a low amplitude interference pattern that is not perceived at normal viewing distances and at normal picture control settings. The fourth component is removed completely in receivers with synchronous video detectors.
In receivers with envelope de~ec~ors~ the four~h component is processed but not perceived because it is correlated with the main signal.
Figure lb illustrates ~he RF spectrum of the disclosed EDTV widescre~n system, including the auxiliary -~- RCA 85,065 information, compared to the RF spectrum of a standard NTSC
system. In the spectrum of the disclosed system the side panel highs and the extra high frequency horizontal luminance detail information extend approximately 1.1 M~
on either side of the 3.108 M~z alternate subcarrier (ASC~
fr~quency. The V-T helper signal information (component 4) extends 750 KHz on either side of the main signal picture carrier frequency.
A widescreen Progressive scan receiver includes apparatus for reconstructing the original widescreen Progressive scan signal. Compared to a standard NTSC
signal, the reconstructed widescreen signal has left and right side panels with standard NTSC resolution, and a 4:3 aspect ratio center panel with superior horizontal and vertical luminance detail, particularly in stationary portions of an image.
Two basic considerations govern the signal processing associated with the development and processiny of the first, second, third, and fourth signal components.
These considerations are compatibility with e~isting receivers, and recoverability at the receiver.
Full compatibility implies receiver and transmitter compatibility such that existing standard xeceivers can receive widescreen EDTV signals and produce a standard display without special adaptors. Compatibility in this sense requires, for example, tha~ the transmitter image scanning format is substantially the same as, or within the tolerance of, the receiver image scan~ing format. Compatibility also means that extra non-standard sig~al components are desirably phy~icially or perceptually hidden in the image produced on a standard receiver. To achieve compatibility in the latter sense, the disclosed system uses techniques described below to hide the auxiliary components.
Recovery of components 1, 2, and 3 at a widescreen progressive scan receiver is aided by -~he use o~
intrafr~me averaging at ~he tr~nsmitter and receiver.
Intraframe averaging is one signal conditioning technigue ~3~1S~
-9 RCA 85,065 that prepares two signals which are to be combined so that they can be recovered efficiently and accurately afterwards. The type of signal conditioning employed for this purpose essentially involves making two signals identical on a field ba~is. Intra~rame averaging is a convenient technique for achieving this objective, but - other techniques can also be used. Intraframe averaging is basically a linear, time varying digital pre-filtering and post-filtering process.
The process of intraframe averaging in the time domain is illustrated generally by FIGU~E lc, wherein pairs of fields are made identical by averaging pairs pixels (A, B and C,D) that are 262~ apart. The average value replaces both of the original values of eAch pair. FIGURE ld illustrates the process of intraframe averaging in the context of the system of ~igure 1. Starting with components 2 and 3, pairs of pixels Spicture elements) 262H
apart are averaged, and the average value (e.g., X1, X3 and Z1, Z3) replaces the original pixel values. This V-T
`~ 20 averaging only occurs within a frame, it does not cross frame boundaries. In the case of component 1, intraframe averaging is performed only on information above approximately 1.5 MH~ so as not to affect lower frequency vertical detail information. In ~he case o~ components 1 and 2, intraframe averaging is performed on a composite signal including luminance (Y) and chrominance (C) components throughout the chrominance band. The chrominance component of the composite signal survives intrafra~e averaging because pixels 262H apart are "in phase" with respect to the color subcarrier. The phas~
of the new alternate subcarrier is controlled so that it is exactly out of phase for pixels 262~ apax~. Thus when components 2 and 3 (after guadrature modulation) are added to component 1 in uni~ 40~ pi~els 26~ apart have the form (M ~ A) and (~ - A), where M is a sample of the main composite signal above 1.5 M~2, and A is a sample of the auxiliary modulated signal.

.
~, :, ;3 -10- RCA 85,065 With intraframe averaging, V-T crosstalk is virtually eliminated, even in the presence o~ motion. At the receiver it is a simple matter to recover the main and auxiliary signals exactly, i.e., free from crosstalk, by averaging and differencing pixel samples 262H apart within a frame as described below. Also at the receiver, components 2 and 3 are separated by quadrature demodulation and component 4 is recovered by quadrature demodulation using a synchronous RF detector.
In a widescreen E~TV receiver, after the training signal and the four video signal component6 have been recovered, the composite signals are NTSC decoded and separated into luminance and chrominance components. Using timing data obtained from the training signal, inverse mapping is performed on all components to recover the widescreen aspect ratio, and th~ side panel highs are combined with the lows to recover full side panel resolution. The extended high freguency luminance detail information is shifted to its original frequency range and added to the luminance signal, which is converted to a progressively scanned ~ormat using temporal interpolation assisted by the helper signal. The chrominance signal is converted to progressive scan format using unassisted temporal interpolation. Finally, the progressive scan luminance and chrominance signals are converted to analog form and matrixed to produce R, G, and B color image signals for diæplay by a widescreen progressively ~canned display device.
Before discussing the compatible widescreen encoding system of Figure la, reference is made to si~nal waveforms A and B of Figure 2. Si~nal A is a 5:3 aspect ratio widescreen si~nal that is to be co~verted to a standard NTSC compatible signal with a 4:3 aspect ratio as depicted by signal B. Widescreen siynal A includes a center panel portion associated with primary image information occupying an interval TC, and left and right side panel portions associated with secondary image information and occupying intervals TS. In this example ~3~
RCA 85,065 ~he left and right side panels exhibit substantially equal aspect ratios, less than that of the center panel which is centered therebetween.
The widescreen EDTV encoding system is shown in greater detail in FIGURE la. Referring to FIGURE la, an exemplary widescreen progressive scan camera 10 which is synchronized by a composite synchronization signal, CCPS, pro~ided by a studio timing si~nal generator 2, provides a 525 line/field, 60 field/second widescreen color signal with ~, G, B components and an aspect ratio of 5:3. The widescreen camera 10 has a greater aspect ratio and a greater video bandwidth than a standard NTSC camera.
The color video signal processed by the encoder system of Figure 1 contains both luminance and chrominance signal components. The luminance and chrominance signals contain both low and high frequency in~oxmation, which in the following discussion will be referred to as "lows" and "highs", respectively.
; The wide bandwidth widescreen progressive scan color video signals from camera 10 are matrixed in a unit 12 to derive a luminance component, Y, and color difference signal components I, and Q, from the R, G, B color signals.
The wideband signals Y, I, Q are sampled at 8 x fsc, eight-times, the chrominance subcarrier fre~uency, sc and are converted from analog to disital (binary) form individually by separate analog-to-digital converters (ADCs) in an ADC unit 14. The digital Y, I and Q siqnals are then filtered by separate vertical-temporal (V-T) low pass filters in a filter unit 16 to produce filtered signals YF, IF and QF. These signals are each of ~he form indicated by waveform A in Figure 2. The separate V-T
- filters axe linear time invariant filters of the ~ype shown in Figure lOd as will be discussed. These filters reduce vertical-temporal resolution sli~htly, particularly diagonal V-T re~olution, to prevent unwan~ed interlace artifacts (such as flicker, jagged edges, and other aliasing related e~fects~ in th~ main siynal after progressive to interlace scan conver~ion. The filters .

~3~
-12~ RCA 85,065 maint in nearly full vertical resolution in stationary portions of th~ image.
In the filter shown in FIGURE lOd, a sample of a progressively scanned signal T3 is averaged with corresponding samples of signals representing the pravious and subsequent horizontal lines of the image (T4 and T2 respectively) and with corresponding samples of signals representing the previous and subsequent imaga frames (T5 and Tl, respectively) to produce a sample of a progressively sc~nned output signal. The weighting factors for the samples of the sig~als Tl, T2~ T3, T~ and T5 are /8, l/Q, 1/2, 1/8, and 1/8 respectively.
The progressive scan signals from filter network 16 exhibit a bandwidth of 0-14.32 MHz and are respectively converted into 2:1 interlaced signals by means of progressive (P) to interlace (I) scan converters 17a, 17b and 17c. Examplary P to I scan converters for the luminance signal, YF, (17C~ and for the color difference signals IF and QF ~17a and 17b) are shown in FIGU~ES 22 and 23, respectively. FIGURE 22 also shows a diagram of a portion of a progressiYely scanned input signal YF with samples A~ B, C and X in a ver~ical (V) and tem~oral (T3 plane as indicated. In ~he converter shown in figure 22, the signal YF is subjected to consecu~ive time d21ays of 525H via elements 2210 and 2212 for producing ~amples X and A which are delayed relative to sample B. Samples B and A, which are separated by two field in~ervals, are summed by an adder 2214 and the resultant sum i5 applied to a divide by-two network 2216. A~ output signal from network 2216 is subtracted ~rom the sample X in a network 2218 to produce a signal YT. This signal is applied to one input of a switch 2220. Another input of witch 2220 receives delayed signal ~F from the output of delay 2210. The switch 2220 operates at twice the interlaced horizont21 line scanning rate and applias an ou~put signal to a dual port memory 2222. The memory 2222 is conditioned by read and write control signals (READ and WRITE) to store sample values provid~d by the switch 2220 at an 8 x fsc rate and ~4~
-13- RCA 85,065 to provide samples YF' and YT in parallel at a 4 x fsc rate. The signals READ and WRITE may be, for example, 4xfsc and 8xfsc signals provided by the studio timing signal generator 2.
The converter in FIGURE 22 includes an error prediction network. One output of the memory 2222, YF', is the interlaced subsampled version of the prefiltered progressive scan luminance component. Another output signal of the network shown in FIGURE 22, YT, comprises vertical-temporal information derived from image frame difference information and represents ~ temporal prediction error between act~al and predicted values of luminance samples which are deleted in the P to I conversion process.
Signal YT is a lumina~ce "helper" signal that assists to reconstruct the progressive scan signal at th~ receiver.
Essentially, the signal YT compensates for an error that the receiver is expected to make wi~h respect to non-stationary image signals. In ~tationary portions of an image the error is zero, since the pixel values in a region of the image do not change from frame to frame. FIGURE ~a illustrates the algorithm used to develop helper signal YT.
It has been found that a chrominance helper si~nal is not needed as a practical matter since the human eye is less sensitive to a lack of chrominance vertical or temporal detail.
In FIGURE 23 a progressivly scanned color difference signal IF (or QF) is applied to a 525H delay element 2310 before being applied ~o a dual port memory 2312. Alternate lines of samples are written into the 30 memory 2312 at an 8 x fsc rate and read from the memory at a 4 x fsc rate to produce an inte~laced outpu~ signal IF' ~or QF').
Also shown in FIGURE 23 are waveforms illustrative of the proscan inpu~ signal with first and second lines associated with samples C and X, and the interlace output signal (~he first line with ~ample C
stretched at a ~ rate). Dual port memory 2312 ou~puts :

~L3~ S3 -14- RCA 85,065 only ~he first line sample ~C) of the input signal, in stretched form.
The QUtpUt sig~als IF', QF' and YF' from converters 17a-17c exhibit a bandwidth of 0-7.16 M~z since the horizontal scanning rate for interlace scan signals is half that of progressive scan signals. In the conversion process, the progr~ssive scan signal is subsampled, -taking half the available pixel samples to produce the 2:1 ; interlaced main signal. Specifically, each pro-scan signal is converted to 2:1 in~erlaced forma~ by retaining either the odd or even lines in each field and reading out the retained pixels at a 4 x fsc rate (14.32 ~Hz). All subsequent digital processing of the interlaced signals occurs at ~he 4 x fsc rate.
Referring to FIGURE la, the helper signal, ~T, provided by the network 17C, is applied to a fonmat encoder 78 which compresse~ the pixel values corresponding to the image side panel regions a~d expands the pi~el values corresponding to the center panel region to correlate the component 4 helper signal to the component 1 main signal.
The sisnal provided by the format encoder 78 iæ lowpass filtered horizontally by means of 2 750 KHz low pass filter, 79, and conveyed as helper signal YTN.
i Bandlimiting of the helper signal to 750 KH2 i9 desirable to prevent this signal from interfering wi~h the nex~ lower RF channel in the broadcast spectrum when this signal is modulated onto the RF picture carrier.
Referring to FIGURE la, interlaced widescreen signal~ IF', QF' and YF' from con~erters 17a-17c are respectively filtered by hori20ntal lowpass filters l~a, l9b and l9c to produce sig~als IF" and QF" each with a bandwidth of 0-600 KHz, and a signal YF;' with a bandwidth of 0-5 MHz. These signals are next subjected ~o a format encoding process which encodes each o~ these signals into a 4:3 format by means of format encoding apparatus associated with a side-center signal separator and processor unit 18.
Exemplary circuitry for use as the processor unit 18 is shown in figure 6.

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~3~4~LS3 -15- RCA 85,065 In FIGUR~ 6, the ~ignal YF" is applied to a horizontal low pass filter 610 having a pa~sband rom 0 to 700 KHz to produce a low frequency luminance signal YL.
The signal YL is applied to the subtrahend input of a subtrac~ive combiner 612. The signal YF" is also applied to a delay element 614 which compensates for the processing delay through the filter 610. The delayed YF" signal provided by the delay element 614 is applied to the minuend input port of the subtractive combiner 612. The output.
si~nal of the combiner 612 is a luminance signal Y~O whi~h occupies a band of frequencies from 700 KHz to 5 MHz.
Delayed signal YF" and signals YHO and YL are applied to separate inputs of de-multiplexing apparatus 616, which includes de-multiplexing (DEMUX) units 618, 620 and 621 for respectively processing signals YF", YH0 and YL. The details of de-multiplexlng apparatus 616 are described below in reference to Figure 8. DEMUX units 618, 620 and 621, respectively, derive full bandwidth center panel signal YC, side panel highs signal YH, and side panel lows signal YL' as illustrated in Figures 3 and 4.
Signal YC is time expanded by a time expander 622 to produce signal YE. Signal YC is time expanded with a center expansion fac~or sufficient to leave room for the left and right horizontal overscan regions. The center expansion factor (1.19~ is the ratio of the intended width of signal YE ~pixels 15-740) to the width of signal YC
(pixels 75-680) as shown in Figure 3.
Signal YL' is compressed with a side compression factor by a time compressor 628 to produce si~nal Y0. The side compression factor ~6.0) is the ratio of the width of the corresponding portion of signal YL' (e.g. left pixels 1-84) to the in~ended width of signal Y0 (e.g. left pixels 1-14) as shown in ~igure 3. The time expander 622 and time compressor 628 can be of the type shown in Figure 12, described below.
Signals IE, IH, I0 and QE, QH, QO are respectively developed from signals IFI' and QF" in a manner similar to that by which signals YE, Y~ and ~0 are ~3~ 3 --16-- RCA l35, 065 developed by the apparatus of Figure 6. In this regard reference is made to Figure 7, which illustrates apparatus for developing signals IE, IH and I0 from signal IF".
Signals QE, QH and Q0 are developed from signal QF" in the 5 same manner. The circuitry shown in FIGURE 7 is the same as that shown in FIGURE 6 e~cept that the low~pass filter 710 has a passband from 0 to 83 KHz instead of from 0 to 7Q0 KHz for the corresponding filter 610 in FIGURE 6.
Figure 8 illustrates a DEMUX apparatus 816 such as can be used fox apparatus 616 of Fiyure 6 and 716 of Figure 7. The apparatus of Figure 8 is illustrated in the context of DEMUX 616 of Figure 6. Input signal YF"
contains 754 pixels defining the image information. Pixels 1-84 define the left panel, pixels 671-754 define the right panel, and pixels 75-680 define the center panel which overlaps the left and right panels slightly. Signals IF"
and QF" exhibit similar overlap. As will be discussed, such panel overlap has been found to facilitate combining (splicing) the center and side panels at the receiver to substantially eliminate boundary artifacts.
DEMUX apparatus 816 includes first, second and third de-multiplexer units 810, 812 and 81g respectively associated with left, center and right panel information.
Each DEMUX unit has an input l'A" to which signals YH, YF"
and YL are respectively applied, and an input l'B'I to which a blanking si~nal (BLK) is applied. The blanking signal may be, for example, a level which is reproduced as a black image (i.e., 0 IRE). Unit 810 extracts output signal YH, containing the left and right highs, from input signal YH
as long as a signal select input (SEL~ of unit 8lO receives a first control level from a count comparator 817. This level indicates the presence of left panel pixel elements 1-84 and right panel pixel elements 671 75~. At other times, a second co~trol level from count comparator 817 cau~es the BLK signal at input B rather than signal YH at input A to be coupled to the output of unit 810. Unit 814 and a count comparator 820 operate in a similar fashion for deriving side panel lows signal YL' from signal Y1. Unit ~3~S;~
-17- RCA 85,065 812 couples signal YF" from its input A to its output to produce center panel signal YC only when a control signal from a count comparator 818 indicates the presence of center panel pixels 75-680.
Count comparators 817, 818 and 820 are synchronized to video signal YF" by means of a count value output signal from a counter 822 which responds to a clock signal at four times the chrominance subcarrier fxequency (4 x fsc), and to a synchronizing pulse signal H provided by the studio timing signal generator 2. Each output count value from counter 822 corresponds to a pi~el position along a horizontal line. The signal H is a time reference signal which resets the counter 822 one pixel interval prior to ~he occurrence of pixel 1. To prevent visible seams at the junction of the side and center panels in the reproduced image, it is desirable for the signal H to be synchronized to the processed video signals. The apparatus for developing the signal H is described below in reference to FIGURE 25.
FIGURE 12 illustrates raster mapping apparatus which can be used for the time expanders and compressors of Figures 6 and 7. In this regard, reference is made to the waveforms of Figure 12a which illustrates the mapping process. Figure 12a shows an input signal waveform S wi~h 25 a center portion between pixels 75 and 680 which is intended to be mapped into pixel locations 15-740 of an output waveform W by means of a time expansion process.
End point pixels 75 and 680 of waveform S map directly into end point pixels 15 and 740 of waveform W. Intermediate pixels do not map directly on a 1:1 basis due to the time expansion, and in many cases do not map on an integer - basis. The latter case is illustrated when, for example, pixel location 76.67 of input waveform S corresponds to integer pixel location 17 of output waveform W.
In FIGURE 12, a pixel counter operating at a 4 x fsc rate provides an outpu~ WRITE ADDRESS signal ~l representative of pixel locations (1...754) on an output raster. Sign~l M is applied to PROM IProgrammable Read .

~3~15i3 RCA 85,065 Only Memory) 1212 which includes a look-up table containing programmed values depending upon the nature of raster mapping to be performed, e.g~, compression or expansion.
In response to signal M, PROM 1212 provides an ou~put READ
5 ADDRESS signal N representing an integer number, and an output signal DX representing a fractional number equal to or greater than zero but less than unity. In the case of a 6-bit signal DX = 2~ = 64, si~nal DX exhibits fractional parts 0, 1/64, 2/64, 3/64...63/64.
To achieve signal expansion, for example, PROM
1212 is arranged to produce signal N which increases in value at a rate slower than that of signal M. Cor~versely, to achieve signal compression, PROM 1212 provides signal N
which increases in value at a rate greater than that of signal M.
Video input signal S which may be one of the Q ~ L ~ IL or QL ~ is delayed by cascaded pixel delay elements 1214a, 1214b and 1214c to produce video signals S(N+2), S(N+l~ and S~N) which are mutually delayed versions of the video input signal These signals are applied to video signal input terminals of respective dual port memories 1216a - 1216d, as are known. Signal M
is applied to a write address input of each of memories 1216a - 1216d, and signal N is applied to a read address input of each of memories 1216a - 1216d. Signal M
determines where incoming video signal information will be written into the memories, and signal N determines which values will be read out of the memories. The memories can write into one address while simultaneously reading out of another address.
Signal~ S(N-l), S(N~, S(~+l) and S(N+2) from memories 1216a ~ 1216d are proces~ed by a four-point linear interpolator including peaking filters 1220 and 1222, a PROM 1225 and a two poin~ linear in~erpolator 1230, details of which are shown in FIGURES 12b and 12c. Peaking filters 1220 and 1222 receive three signals from the grou~ of signals including signals S~N-l), S(N~, S(N~l) and S(N+2), as shown, and a peaking signal PX. The value of peaking ii3 -19- RCA 85,065 signal PX varies from zero to unity as a function of th~
value of signal DX, as shown in FIGURE 12d, and is provided by P~OM 1225 in response to signal DX. PROM 1225 includes a look-up table and is programmed to produce a given value of PX in response to a give value of DX.
Peaking filters 1220 and 1222 respectively provide peaked mutually delayed video signals S'(N) and S'(N~l) to the two-point linear interpolator 1230 which also receives signal DX. Interpolator 1230 pro~ides a (compressed or expanded3 video output signal, where output signal W is defined by the expression W = S'(N) ~ DX [S'(N+1) - S'(N)]
The described two-point interpolator and peaking function advantageously approximates a (sin X)/X interpolation function with good resolution of high frequency detail.
FIGURE 12b shows details of peaking filters 1220 and 1222, and interpolator 1230. In FIGURE 12b, signals S(N-1), S(N) and S(N+1) are applied to a band-pass filter : 1240 in peaking f.ilter 1220 where these signals are respectively weighted by coe~ficients ~1/4, 1/2 and -1/4 and summed as shown in Figure 12c. The output signal of the filter 1240 is multiplied by signal PX in multiplier 1243. The signal provided by the multiplier 1243 is summed : with signal S(N) in adder 1244 to produce peaked signal S'(N). Peaking filter 1222 has the same structure and ` operation.
In two point interpolator 1230, signal S'(N) is subtracted from signal S'(N~1) in a subtractor 1232 to ~- pxoduce a differen~e signal which is multiplied by signal DX in a multiplier 1234. The output signal from multiplier 1234 is summed, in an adder 1236 with si~nal S'(N), which has been delayed by a delay element 1235 to compensate for the processing time through the multiplier 1234, to produce output signal W.
Referring to ~IGURE la, the signals YE, IE, QE
and YO, IO, QO produced by the en~oder 18 are combined by a side-center signal combiner 28, e.g. a time multiplexer, to produce signals YN, IN and QN with an NTSC compatible 13~
-20- RCA 85,065 bandwidth and a 4:3 aspeck ratio. These signals are of ~he form of signal YN shown in FIGURE 3. To produce these signals, the combiner 28 is responsive to a pixel counter (not shown) which may be the same a~ the counter 822 shown in FIGURE 8. In response to counter output values between 1 and 14, and between 741 and 754, the combiner 28 passes the compressed luminance signal Y0 as the signal YN. In response to counter values between 15 and 740, the combiner passes the signal YE as the signal YN. The signals IN and 10 QN are produced by the comhiner ~8 using means identical to that described above, operating on the signals I0 and IE, and Q0 and QE, respectively. Combiner 28 also includes appropriate signal delays ~not shown) for equalizing the transit times of the signals being combined.
A modulator 30, bandpass filter 32, H-V-T
bandstop filter 34 and combiner 36 constitute an improved NTSC signal encoder 31. Chrominance signals IN and QN are quadrature modulated on a su~carrier SC at the NTSC
chrominance subcarrier frequency, nominally 3.58 MHz, by the modulator 30 to produce a modulated signal CN.
FIGURE 9 shows details of mod~lator 30. In FIGURE 9, signals IN and QN appear at a four times chrominance subcarrier rate (4 x fsc) and are applied to signal inputs of latches 910 and 912, respectively.
Latches 910 and 912 also rec~ive a clock signal, 4xfsc, to tran~fer in signals IN and QN, and a switching signal, 2xfsc, which is applied to an inverting switching signal input of latch 910 and to a noninverti~g switchi~g si~nal input of latch 912. The signals 4xfsc and 2xfsc are provided by the studio timing signal generator 2. The signal applied to the switching inputs of the latches 910 and 912 condition the output terminals of the latches to alternately exhibit a high impedance. The signal output terminals of latches 910 and 912 are combined into a single output line at which signals I and Q appear al~ernately and are applied to ~i~nal inpu~ terminal~ ~f a noninv~rting latch 914 and an inverting latch 916. The latches ~14 and 916 are clocked at a 4 x f~c rate and receive a switching ~3~ S~
-21- RCA 85,065 sign 1, at the chrominanc~ subcarrier frequency fsc, at inverting and noninverting inputs respectively.
No~inverting latch 914 produces an alternating sequence of positive polarity samples I and Q, and inverting latch 9~6 produces an altarnating sequence of invert~d polarity I and Q signals, i.e. ~ Q. The outputs of latches 914 and 916 are combined in a single output line on which appears an alternating sequence of I and Q signals of mutually opposite polarity pairs, i.e., I, Q, -I, -Q... etc., constituting signal CN. This signal is filtered by a two dimensional V-T filter 32 before being combined, in unit 36, with a signal YP, provid~d by a horizontal-vertical-temporal (~-V-T) fitler 34. The output signal provided by the unit 36 is an NTSC encoded signal C/SL ~component 1) of the form Y+I, Y+Q, Y-I, Y-Q, Y+I, Y+Q... and so on.
FIGURE 10 illustrates a vertical-temporal (V-T) filter which can exhibit first and second V-T bandpass (A
or B) configurations or a V-T low-pass configuration by adjusting weighting coefficients al-a9. The table of FIGURE lOa illus~rates the weighting coeficients associated wi~h V-T bandpass A and V-T bandpass B filter configurations which are employed in the disclosed system.
An H-V-T bandstop filter ~uch as filter 34 of FIGURE la comprises the combination of a horizontal lowpass filter 1020 and a V-T bandpass B ~ilter 1021 as shown in FIGURE
lOb. The V-T bandpass A filter is a frame comb filter which exhibits a frequency response characteristic having peaks correspo~ding to peak~ in t~le freguency spectrum o the modulated chrominance signal. The V~T bandpass B
filter is also a frame comb filter however its frequency - response charac~eristic has nulls corresponding to peaks in the freguency spectrum of the modula~ed chrominance signal.
In the H-V-T ba~dstop filter of FIGURE lOb, a horizontal lowpass filter 1020 exhibits a given cut-off frequency and provides a filtered low freguency signal componen~. ~his signal is subtractively combined in a combiner 1023 with a delayed version of the input signal ~L3~1S3 -22- RCA 85,065 from a compensating delay unit 1022 to produce a high frequency signal component. This high frequency signal component is applied to the V-T bandpass B filter 1021, the output port of which is coupled to an additive combiner 1025. The low frequency component from filter 1020 is subjected to a one frame delay by means of a network 1024 before being applied to the additive combiner 1025. The output signal of the combiner 1025 is an R-V-T bandstop filtered signal, for example, YP. V T filter 1021 is a finite impul~e response (FIR~ filter such as that shown in FIGURE 10 which utilizes the V-T bandpass B filter coefficients shown in Figure lOaO
H-V-T bandstop filter 34 in FIG~RES la and 9 is a frame co~b filter above 1.5 MHz which removes a portion of the frequency components of luminance signal YM which correspond to upwardly moving diagonals. These frequency : components are similar in appearance to chrominance subcarrier components and are removed from the lu~inance signal to make a hole in the frequency spectrum into which the modulated chrominance signal will be inser~ed. The removal of frequency components representing upward diagonal motion from luminance signal YN does not visibly degrade a displayed picture because it has been determined that the human eye is substantially insensitive to these frequency components. Filter 34 passes all frequencies up to approximately 1.5 MRz so as not to impair lu~inance vertical detail information.
An output center/side lows signal C/SL (component 1) from combiner 36 contains NTSC compatible information to be displayed, as derived from the center panel o~ the .:
widescreen signal, as well as compressed side panel lows (both luminanc~ and chrominance) derived from the side panels of the widescreen signal and situated in the left and xight horizontal overscan regions which are not seen by a viewer of an ~TSC receiver display. The compressed side panel lows in the overscan region represent one constituent part of the side panel information for a widescreen , ~
.`' ~' ' , ~3~4~S~
-23- RCA 85,065 display. The other constituent part, the side panel highs, is developed by processor 18 as discussed above.
Referxing to FIGURE la, signal C/S~ produced by the encoder 31 is processed by an intraframe averager 38 to produce a sisnal N, which is applied to an input port of an adder 40. The intraframe avexaged signal N is essentially identical to signal C/SL because of the high coxrelation of intraframe image information in the signal C/SL. The averager 38 averages signal C~SL only above approximately 1.5 MHz to reduce or eliminate vertical-temporal crosstalk between the main and auxiliary signals. FIGURES lla and llb show details of highs intraframe averager 38.
As shown in FIGURE lla the intraframe averager 38 includes an input horizontal lowpass filter 1110 with a cut-off frequèncy of approximately 1.5 MHz, which receives sig~al C/SL. A low frequency component o input signal C/SL is produced at the output of filter 1110, an~ a high frequency component of input signal C/SL is produced at the output of a subtractive com~iner 1112 arranged as shown.
The low frequency componen~ is subjected to a 262~ (one field~ compensatory delay by a unit 1114 before being applied to an adder 1120. The high frequency component of si~nal C/SL is proressed by a V-T filter 1115 before being applied to ~he adder 1120. The output signal of the adder 1120 is the signal N.
Filter 1116 is shown in detail in ~IGURE llb.
The filter 1116 includes a pair of 262~ delay elements 1122 and 1124. Th~ input signal to the filter is applied to the delay eleme~t 1122 and to a multiplier 11~5. The ~i~nal provided by the delay element 1122 is applied to the delay element 1124 and to a multiplier 1126. The output signal of the delay element 11~4 is applied to a multiplier 1127.
The multipliers 1125, 1126 and 1127 multiply their respective input signals by weighting coe~ficients al, a2 and a3, respectively. The multiplier outputs are applied to an adder 1130 which produces a C/SL highs time averaged signal. Weighting coef~ici~nt a2 remains constant, but coefficients al and a3 alternate ~etween 1/2 and 0 from one ~3~ ;3 -24 RCA 85,065 field to the next. Coefficient al exhibits values of 1/2 and 0 when coefficient a3 exhibits respective values of 0 and 1/2. The switching of values for the coefficients al and a3 is synchronized to the incoming signals so that only corresponding pixel values from two fields in the same frame are averaged.
Referri~g to FIGURE la, si~nals I~, QH, and YH
provided by khe format encoder 18 are placed in NTSC format by means of an NTSC encoder 60 which is the ~ame as the.
encoder 31 described above. The output signal produced by the NTSC encoder 60, the signal NTSCH, is the side panel highs information in NTSC format. This signal is illustrated by Figure 5.
The signal NTSCH produced by the encoder 60 is time expanded by a unit 62 to produce an expanded side highs signal ESH. Specifically, as shown in FIGURE 5, th~
expansion is accomplished by a "mapping" process which maps left side panel pixels 1-84 of signal NTSCH into pixel positions 1-377 of signal ES~, i.e., the left side highs of signal NTSCH are expanded to occupy one half the active line time of signal ESH. The right side panel portion ~pixels 671-754) of signal NTSCH is similarly processed to occupy the other half of the active line time. The time e~pansion process reduces the hori20ntal bandwidth of the information comprising signal ESH ~compared to that of signal NTSCH) by a factor of 377/84. The mapping process by which time e~pansion is accomplished can be realized by apparatus of the type shown in FIGURES 12-12d, described above.
Signal ES~ produced by the time expander 62 is intra-frame averaged by a network 64, of the ~ype shown in FI~URE llb, to produce a signal X as illustrated in FIGURE
5. The intraframe averaged signal X is ess~ntially identical to signal ES~ because of the high correlation of intraframe image information of signal ~5~. Signal X is applied ~o a signal input port of a quadrature modulator ~0 .

~3C;4~53 -25- R~A 85,065 Signal YF', provided by the progressive to interlace scan converter 17c, is filtered by a horizontal bandpass filter 70 with a passband of 5 MHz - 6.2 MHz. The output signal from filter 70, representing horizontal luminance highs, is applied to an amplitude modulator 72 where it is heterodyned with a 5 MHz carrier signal fc.
: The signal fc is generated by the studio timing signal generator 2, described below in reference to FIGURE 25.
Modulator 72 includes an output low pass filter (not shown) with a cut-off frequency of approxima~ely 1.2 M~z to :~ produce a signal with a 0-1.2 M~z passband at the output of modulator 72. Effectively, horizontal luminance highs in the frequency range 5.0 MHz - 6.2 MHz have been shift~d to the range 0-1.2 MHz as a result of the heterodyning process and subsequent low pass filtering. The amplitude of the signal fc used in the heterodyning process should be large enough so that the original signal amplitudes are retained after filtering by the 1.2 M~Iz low pass filter.
The frequency-shifted horiæontal luminance highs signal from unit 72 is encoded by means of a format encoder -. 74 to spatially correlate this signal with the main signal, C/SL. The encoder 74 encodes the frequency shifted horizontal luminance highs into a standard 4:3 format using the techniques described above in reference to FIGURES 6-8.
2~ When the center portion of the input signal to encoder 74 is time expanded, its bandwidth drops to approximately 1.0 MHz from 1.2 MHz, and the output signal from encoder 74 becomes spatially correla-ted with the main signal. The side panel information is lowpass filtered within unit 72 to 170 K~z before being time-compressed by encoder 74.
Alternatively, it is contemplated ~hat ~he signal provided by the modulator 72 may be uniformly compressed by the format encoder 74 such that an entire line of samples 1-754 are encoded to occupy pixel positions 15-740 and the side . 35 panel pixel positions are left at the blanking level value.
: If ~his method of forma~ encoding is used, the ba~dwidth of ~ the low pass ilter contained in the amplitude modulator 72 ~ is desirably reduced from 1.2 M~z to 950 KHz.

~3~ S3 -26-- RCA 85, 065 The signal from encoder 74 is intrafr~me averaged by means of apparatus 76 which is the same as that illustrated in FIGURE llb. The signal produced by the averager 76 is applied to unit 80 as signal Z. Intraframe averaged signal Z is essentially identical to the signal from encoder 74 because of the high corralation of intraframe image information of the signal from encoder 74.
The modulating signals X and Z occupy substantially the same band of fre~uencies, approximately 0-1.1 M~z.
The unit 80 performs nonlinear gamma function amplitude compression on large amplitude excursions of the two auxiliary signals, X and Z, and then quadrature modulates the compressed signals onto quadrature phase related alternata subcarrier signals ~SC and ASC'. A gamma of 0.7 is used for the ampli~ude compression, whereby the absolute value of each sample is raised to the 0.7 power and multiplied by the sign of the original sample value.
Gamma compre~sion reduces the visibility of potentially interfering large amplitude excursions of the modulated signals on exisiting receivexs, and allows predictable recovery at the widescreen r~ceiver since khe inverse of the ga~ma function employed at the encoder can be readily implemented at the receiver decoder.
The amplitude compressed signals are then modulated on a 3.1075 M~z pha~e-controlled alternate subcarrier ~SC, and a quadrature phase rela~ed s.ignal ASC'.
The frequency of signals ASC and ASC' is an odd multiple of one half th~ horizontal line frequency (395 x F~/2). The signals ASC and ASC' are generated by the studio timing signal generator 2, described below in reference to FIGURE
25. The phase of the alterna~e ~ubcarrier is caused to alternate 180~ from one field to the next. The field alternating phase of the alternate subcarrier permits the auxiliary modulating information of signal~ X and Z to overlap chrominancs in~ormation and facilita~es the separation of the auxiliary information using a relatively uncomplicated field storage device at the receiver. The quadrature modulated signal, ~1, is added to signal N in ~3~ S3 -27- RCA 85,065 adder 40. The resulting signal, NTSCF, is a 4.2 MHz NTSC
compatible signal.
FIGURE 24 shows details of unit ~0. Signals X
and Z are applied to address inputs of non-linear amplitude compressors 2410 and 2412, respectively. Compressors 2410 and 2412 are programmable read-only memory (PROM) devices each including a look-up table containing programmed values - corresponding to the desired non-linear gamma compression function. This function is illustrated by the instantaneous input vs. output response curve adjacent to : unit 2412. Compressed signals X and Z from data outputs of units 2410 and 2412 are applied to signal input ports of signal multipliers 2414 and 2416, respec~ively. Reference inputs of multipliers 2414 and 2416 receive respective alt~rnate subcarrier signals ASC and ASC' in mutually quadrature phase relationships from the generator 2.
Output signals from multipliers 2~14 and 2416 are added, in a combiner 2~20, to produce a quadrature modulated si~nal M. Referrin~ to FIGURE la the signals M and N are summed by an adder 40 to form the signal NTSCF.
The fourth component or helper siynal is derived from the signal YT provided by the progxessive to interlace ; scan converter 17c. The luminance detail signal YT
produced by the progressive to interlace 6can converter 17c, exhibits a bandwidth of 7.16 ~Hz and is encoded into :~ the 4:3 format hy means of a format encoder 78 which is thesame as that described in reference to FIGU~E 6 and ~. The signal provided by t~e format encoder 78 is horizontally lowpass filtered to 750 KHz by a filter 79 to produce a signal YTN. The side portions are lowpass filtered to 125 KHz before time compression by means o~ an input lowpass filter of format encoder 7~. This filter corresponds to input filter 610 of the apparatus shown in FIGURE 6 but it has a cut-off frequency of 125 K~z. The side portion highs are discarded. Thus signal YTN is spatially correlated with main signal C/SL.
Signals YTN and NTSCF are converted from digital (binary~ to analog form by means of digital to analog ., . .

~3~ L5;3 -28- RCA 85,065 conversion (DAC) units 53 and 54 respectively. The signal provided by the DAC 54 is applied to one input terminal of an analog switch 8 another input terminal of the switch 8 is coupled to recei~e a signal provided by an analog swi-tch 6. A signal SC2, provided by the studio timing siynal generator 2 condi~ions the analog switch 8 to apply either active video signals from D~C 54 and a composite ~ynchronization signal, OCPS, from the timing signal generator 2 or, an external video signal, EV from source 4 and the signal OCPS to one input terminal o~ the RF
quadrature modulator 57. A switch 4 is controlled by signal SC2 to apply either the helper signal from DAC 53 or a helper signal from the external video source ~ to another terminal of the modulator 57. The quadrature modulator 57 modulates the two signals. applied to its input terminals onto an RF carrier in quadrature. The RF modulated signal is afterwards applied to a transmitter 55 for broadcast via an antenna 56.
As set forth above, the studio timing si~nal generator 2 generates a composite synchronization signal for the widescreen progressive scan camera 10, various clock, carrier and timing signals used by the widescreen EDTV encoder and a composite synchronization and training signal which is added to the EDTV signal to be transmitted.
The generator 2 may develop these signals from an internal free-running oscillator or it may be genlocked to an external video signal, EV, provided by the source 4~ Thus, the externaI video source 4 is optional. If it is absent, the system will synchronize itself. If it is present, it may be used only for s~nchronization purposes or it may provide encoded video signals to the switches ~ and 9 which override the encoded video signals available at the output t~rminals of the DACs 53 and 54. The composi~e synchronization signal, OCPS, provided by the studio ~iming signal generator 2 is insexted into the signals to be transmitted whether they are provided by the D~Cs 53 and 54 or the external video source 4. This configuration allows ~he equipment in a local television studio t~ be ~3~ i3 -29- RCA 85,065 synchronized ~o, for example, programming provided by a ne~work. Synchronization of this type is impoxtant if local programs are to be mixed with programming from other sources without annoying switching artifacts.
The following is an overview of exemplary circuitry, shown in FIGURE 25, which may be u~ed as the studio timiny signal generator 2. Thw signal 8xfsc, generated by a voltage controlled oscillator (VCO~ 2520, is applied to a counter 2524. The count value, a si~nal PC, provided by the counter 2524 represents the position, on a horizontal line, of the pixels being digitized by the ADCs 14. The signal PC is applied to a read-only memory (ROM) 2526 which generates timing sig~als representing various events occurring on each line of the signal, e.g.
horizontal blanking and sync. A signal C910 having one p~lse per horizontal line of the signal provided by th~
camera 10 is provided the ROM 2526 to a counter 2534. The counter 2534 generates a signal LC representing the vertical position of the line of samples being digitized by the ADCs 14. The signal LC is applied to a ROM 2536 which generates signals defining events which occur once per field or once per frame such as vertical bl~nking. The signals PC and LC are applied ~o various ROMs 2530, 2532, 2540, 2542, 2544, and 2546 which generate signals defi~ing the rest o the timing and oscillatory signals provided by the generator 2. The switching signals SWl and SW2 as well as the analog composite synchronization signals CCPS and OC~S are also provided by the studio timing signal generator 2.
To simplify the explanation of the timing circuitry, compensating delays, which may be needed to supply the signals produced by the timing generator 2 to the remai~der of the circuitry shown in FIGVRE la, are omit~ed. One skilled in the art of digi~al signal processing circuit design will know where such delays are needed in a particular system.
FIGURE 25 is a block diagram of circuitry suitable for us~ as the stu~io ~iming sig~al qenerator 2.

~3~
-30- RCA 85,065 In FIGURE 25, the signal EV which includes the in-phase component of an encoded widescreen EDTV signal plus relevant horizontal, ~ertical and color burst synchronization signal components, from the external video source 4, is applied to a conventional synchronizing signal separator circuit 2510. The circuit 2510 produces a burst gate signal, BG, and external horizontal and vertical synchroniæing signals, EHS and EVS, respectively.
The signal EV is further applied to a chrominance bandpass filter 2512 which passes the chrominance band : components of the si~nal. EV to the relative exclusion of any other components. The output terminal of the filter 2512 is coupled to an analog gate 2514 which is conditioned by the burst gate signal, BG, to apply the color burst signal component, BURST, of the signal EV to one input terminal of a phase detector 2516. Another input terminal of the phase detector 2516 is coupled to receive a signal C8 provided by the ROM 2526. As explained helow, the signal C8 has substantially the same frequency, fsc, as the signal BURST.
; The phase detector 2516 produces an output signal which is proportional to the instantaneous difference in phase between the signal BURS~ and the signal C8. This phase difference signal is applied to a loop filter 2518.
The loop fil~er 2518 integrates the phas~ difference signal to produce a signal which is proportional to the difference in frequency b~tween the signals BURST and the initial - frequency of the signal C8 which is related to the free-running freguency of ~he VC0 2520. This frequency differ0nce signal is applied to a control input terminal of the VCO 2520. The VC0 2520 includes a resonant cryst~l 2522 which conditions the VCO to have a free-xunning frequency of approximately eight times fsc. The output signal, 8xfsc, of ~he VCO 2520 is applied to the clock 35 input terminal, CLK, of ~he 11-bit counter 2524. The ll-bit output signal, PC (pixel count), provided by ~he counter 2524 is applied to the address input port of the RO~ 2526. The ROM 2526 ls a 20~8 x 9 ~it device which is -31- RCA 85,065 programmed to produce various output signals in response to the count values applied to its address input port. One of these siynals, C8, is in a logic zero state for four consecutive count values and then in a logic o~e state for the next four consecutive count values. Since the count value is incremented at a rate of 8 x fsc, the signal C8 has a frequency substantially egual to fsc. This sign~l is applied to the phase detector 2516 as set forth above.
The combination of the pha~e detector 2516, loop filter 2518, VCO 2520 counter 2524 and ROM 2526 is a pha~e locked loop which produces a signal 8xfsc that is locked in phase to the color burst signal component of the external video signal, EV. As set forth above, ~he signal EV is an optional signal. If it is not present, the loop will op~rate at the free-running freguency of the VCO 2520.
The phase locked loop is further synchronized to the external horizontal synchronizing signal, EHS. This si~nal is applied to one input terminal of an OR gate 2528.
Another input terminal of the OR gate 2528 is coupled to receive a signal C1820, provided by the ROM 2526. The signal C1820 includes a pulse which occurs once for every 1,820 consecutive pulses of the signal 8xfsc. The output terminal of the OR gate 2528 is coupled to the reset input terminal, R, of the counter 2524. For standard NTSC
signals and wideband EDTV signals, the signal C1820 has substantially the sam~ frequency as the horizontal line synchronizing signal. ~hen the signal EHS is present, the pixel count signal, PC, produced by the counter 2524 i5 synchronized to the external source. When E~S is not present, the phase locked loop synchronize~ itself.
Tha ROM 2526 also produces signals which define a 4 x fsc clock signal (4xfsc~, a 2 x fsc clock signal (2xfsc) the ~iming of the first active pixel po~ition on a horizontal line of the output video signal (H), the timing of horizontal sync (OHS) and horizontal blanking (OHB) for the output video signal, the timing of horizontal sync for the progressive scan camera (CHS~, a timing window into which the burst component of the output signal is inserted ~3~ i;3 -32- RCA 85,065 (BF~, and a signal C910, which includes a pulse that occurs once for every 910 consecutive pulses of the signal CK8.
The si~nal C910 defines the star~ of each horizontal line of vid~o siynal provided by the progressive scan camera 10.
This sig~al is applied to the clock input terminal, CLK, of the counter 2534, which, ~ogether with the RO~ 2536, generates the vertical rate timing signals for the camera 10 and for the OlltpUt video signal produced by the encoder.
Counter 2534 is an ll-bit counter which produces an output si~nal, ~C ~line coun-t), that is applied to the address input port of the ROM 2536. A signal C1050 provided by the ROM 2536 is applied to one input terminal of an OR gate 2538, the other input terminal of which is coupled to receive the external vertical synchronizing signal EVS, provided by the synchronizing signal separating circuitry 2510. The signal C1050 includes a pulse that occurs once for every 1,050 consecutive values of the signal LC, and has substantially the same frequency as the signal EVS. The output terminal of the OR gate 2538 is coupled to the reset input terminal, R, of the counter 2534. The signal produced by the OR gate 2538 conditions the counter to reset its count value once for each field of video signal produced by the progressive scan camera 10.
The field rates of the camera 10, the external video signal, EV, and the output signal produced by the widescreen EDTV encoder are the same.
In response to the line count signal, LC, the ROM
2536 produces a signal, FID, which contains the field identi~ier (i.e. 0, 1, 2 or 3) for the current field. This signal is used as set forth below to generate the alternate subcarrier si~nals, ASC and ASC', the color burst signal, the five ~Hz heterodyne carrier signal, ~c, and to define the vertical syncrhonizing signals CVS and OVS for the camera 10 and for the video output signal, respectively.
In addition, the ROM 2536 produces a signal OV~, which defines the vertical blanking interval ~or the output video signal, a signal, O/E, which indica~es whether a line indicated by the signal LC is an odd or even line within ~3~ lS3 -33- RCA 85,065 its field and a signal, L22, which indicates when the value of LC corresponds to line 22 of each field of the output video signal.
The ROM 2530 is programmed to generate ~he alternate subcarrier signals ASC and ASC' in response to an address input signal which includes the pixel count si~n~l, PC, provided by the counter 2524 and the signals FID and O/E provided by the ROM 2536. The signals ASC and ASC' are quadrature phase related signals having a nominal frequency of 395 x ~h/2, 395 times one-hal the horizonta~ line scanning frequency. The signals FID and O/E are included in the address signal for the ROM 2536 so that the phase of the signals ASC ~nd ASC' may change by 180 degrees from line to line and from field to field, as set forth above.
The signals ASC and ASC' are eight-bit sampled data signals having a sample rate of 4 x fsc. Since the signals ASC and ASC' have a known variation in phase from line to line and from field to field (i.e. 180 degrees), the ROM 2530 may contain samples representing two horizontal line periods of ~he alternate subcarrier signals.
In the present embodiedment of the invention, the five MEz signal fc is generated in the same manner by the ROM 2532. This signal is not tied in frequency or phase to the horizontal line scanning sig~al or to the color subcarrier signal of the outpu~ video signal. Howev~r, it may be desirable to change the phase of this signal from line to line or from field to field to prevent it from distorting ~he reproduced image. Accordingly, the signals FI~ and O~ are included with ~he signal PC in forming the address signal for the ROM 2532. ~he signal fc is also an eight-bit sampled data signal having a sample rate of 4 x fsc. The ~OM 2532 may hold sample values representing betwee~ one and four horizontal line intervals of the signal fc.
The ROM 2540 is responsive to an address signal which includes the signals PC, FID and LC for generating signal OVS which indica~es the timing of ~he various components of the vertical synchronization si~nal for ~he ~3~
-34- RCA 85,065 output video signal. The output signal, OVS, of the ROM
2540 is a one-bit binary signal which switches between logic-on~ and logic-zero sta~es at times when the vextical synchronizing signal, which includes the e~ualizing pulses and serrations, changes between values corresponding to black level (i.e. 0 IRE) and sync tip ~i.e. -40 IRE), r~spectively~
Another ROM, 2560, is responsive to an addres~
signal which includes the componen~ signals PC, LC and FI~
to generate a signal, cvs, which indicates the timing of the various components of the verti~al synchronization signal for the progressive scan camera 10.
A sa~pled data burst signal which is inserted in the burst interval of each horizontal line of the output ~ideo signal is generated by the ROM 2542 in response to an address input signal which includes the signals PC, O/E and FID. The ROM 2542 includes a three state output stage which is responsive to the burst flag signal, BF, to provide the eight-bit sampled data burst signal only during the burst interval, a high impedance is provided at the output port of the ROM 2542 at all other times.
The RO~ 2544 produces a training signal for insertion into the output video signal during the time defined by the 22nd horizontal line interval of each field.
The signals PC and FID are combin~d to form the address input signal for the ROM 2544. The ROM ~544 includes a three-state output stage which is responsive to the signal L22 to present the txaining signal at its outpu~ port only during the 22nd horizontal line interval of each output video field~ A high impedance is presen~ed at the output of the ROM 2544 at all other times. The signal FID is applied to ~he RO~ 2544 becau~e the training signal pxovided by the ROM is inverted once for each four fields of video signal. This inversion is sen~ed a~ the receiver, as described below, to align the four field seguence of th~
receiver to that of the transmitter. The output ports of the ROM's 2542 a~d 254~ are coupled together and to the input port of a digital to analog converter (DAC) 2554.

13~4~S3 -35- RCA 85,065 The DAC 2554 is a part of the circuitry used by the studio timing signal generator 2 to develop the analog composite synchronization signal, OCPS, which is inserted into the output video signal by the analog switches 6 and 8 described above in reference to FIGURE la. To develop the signal OCPs, the signals O~S and OVS are combined in an OR
gate 2546 to generate a control signal f4r an analog switch 2552. The switch 2552 is conditisned by this control signal to pass the analog value (e,g. -40 IRE) provided by a source of sync tip signal 2550, during ~he times that the output signal of the gate 2546 indicates that a synchronization signal is present, and to pass a blanking signal (e.g. 0 IRE) otherwise. The output signal of the analsg switch 2552 is applied to one input terminal o~ a further analog switch 2556. A second input terminal of the switch 2556 is coupled to receive ~ha combined burst and training signals provided by the DAC 2554. The analog switch 255~ is conditioned by a signal provided by an OR
gate 2558 to pass the burst signal during the burst interval of each line and to pass the training si~nal during line 22 of each field. At all other times, the switch 2556 passes the signal provided by the analsg switch 2552. The input signals to the OR gate 25~8 are the burst flag sigr,al, BF, ~rom ROM 25~6, and the line 22 signal, L22.
The composite synchronization signal, CCPS, for ~he progressive scan camera 10 is developed by apparatus similar to that used to develop th~ signal OCPS. The camera vertical synchronizing signal, CVS, is applied to one input terminal of an OR gate ~570, another input terminal of which is coupled to receive the camera horizontal synchroniza~ion signal, C~S, provided by the ROM
2526. The output signal o the OR gate 2570 is coupled to the control input terminal of an ~nalog switc~ 2568. The switch 2568 is conditioned by this signal to pass an analog value (~40 IRE) ~rom a source of sync tip ~5~4 for the synchronizing ~ignals indic ted by the signal provided by the OR gate 2570 and to pass a blanking level (O IRE), from ~3~ 3 -36- RCA 8S,065 a source 2562, otherwi~e. The outpu~ signal of the analog switch 2568 is the camera composite synchronization signal, CCP~ .
As set forth above in reference to FIGURE la, the an~log switches 6 and 8 are responsive to respective control signals SCl and SC2 for conditionally inserting th~e external video signal, EV, and for unconditionally i~serting the composite synchronization signal OCPS into the output signal of widescreen EDTV encoding system as set forth above, the ~ignal OCPS is inserted regardless of the source of video signal to ensure that locally generated EDTV signals are synchronized to external (e.g. network) signals.
The control signals SC1 and SC2 are generated as follows. ~eferrin~ to FIGURE 25, the synchronization signal separation circuitry 2510 produces a signal ESP
which indicates when an axternal video sig~al EV is present. The signal ES~ is applied to one pole of a switch 2573, the other pole of which is coupled to a source of logic-zero, 2572. The wiper of the switch 2573 is manually controlled; when it is coupled to the signal ESP and the external video signal EV is presenk, the encoding system is bypassed and the signal EV is used both to generate the synchronizing signals OCPS and CCPS and to providP the video output signals of the encoder, when the wiper is coupled to the source 2572, the signal EV is only used to develop the s~nchxonizing signals, the actual video signals are generated by the widescreen EDTV encoder from the signals provided by the camera 10. When the si~nal EV ls not pres~nt, the synchroniziny signals are developed by the signal generator 2 without a reference signal.
To generate the signal SC1, the signal provided by the switch 2573 is inverted by an inverter 2574 and then logically ANDed wi~h the signal L22 in an ~ND gate 2576.
The outpu~ signal of the AND gate 2576 is applied ~o one input terminal of an OR gate 2578. The other two input terminals of the OR gate 2578 are coupled to re~eive the output horizontal and verticaL blanking si~nals, OHB and 43l~
-37- RCA 85,065 OVB. The output sig~al of the OR gate 2578 i5 the control signal SC1. The control signal SC2 is the logical OR of the signal provided by the switch 2573 and the signal SC1.
In operation, when the signal provided by the switch 2573 has a value of logic-one, the output signal of the encoder is the external video signal EV with the horizontal and vertical synchronizing signal com~onen~s and the burst signal component of the signal OCPS inserted in blanking regions defined by the signal SC1. The training signal component of the signal OCPS is excluded; the training signal component contained in the signal EV is passed with the signal through the switches 6 and 8. The training signal component of the external video signal EV
is not overwritten to preserve the timing relationship which was established when the signal was generated. Since the training signal is established when a video signal is encoded, it is desir~ble that the signal not be changed until the video signal is decoded.
When the control signal SC2 has a logic-zero value, the horizontal and vertical synchronizing signals, and the burst signal contained in the signal OCPS are inserted into the video signals g~nerated by the encoder in blanking intervals defined by the signals OHB and OVB; the training signal component of the signal OCPS is inserted in line 22 of the generated video signal As set forth above, the training signal is used to synchronize the encoding and decoding systems. The format of the training signal is not fixed. I~ may be any one of a number of different signals, two of which are presen~ed below. In the presen~ embodiment of ~he invention, the training sig~al is used to determine the timing of the first active video sample on each horizontal line interval of the video signal to within five nanoseconds (ns) and to ensure proper phase alignment of the si~nals ASC, ASC' and fc between the studio and the receiver.
FIGURE ~5a illustrates the burs~ flag signal, BF, the output horizontal blanking signal, O~, and the timing ~3~ 3 -38- RCR 85,065 reference signal H that are gener~ted by ~he timing circuitry 2. The signal ~V is included in FIGURE 25a as a reference. As illustrated by the waveforms shown in FIGURE
25a, the value of the signal PC, provided by the counter 2524, is rese~ to zero coincident with a positive going transition of the signal O B . The first active sample time, indicated by the signal H, occurs when PC is egual to 308. The sample time before the start of the horizontal blanking interval is at PC equal to lal9.
Under the NTSC standard, the phase of the chrominance subcarrier signal is predetermined or each line of the video signal. Thus, the phase value of the first sample time for a particular line depends on the phase of the burst signal, on whether the line is an odd line or an even line, and in which field of the four field sequence the line occurs. The sample time of the first pixel on a horizontal line also corresponds to predeterxined phases of the alternate subcarrier signals, ASC and ASC', and to the heterodyning carrier signal, fc, since in the timing signal generator 2, these signals are derived from the pixel count signal, PC.
In the receiver, the training signal is recovered, used to adjust the phase of a 4 x fsc sampling clock signal and to adjust a count-down circuit which develops a horizontal line synchxonizing signal from the sampling clock signal. This count-down circuit is also used to regenerate the alternate subcarrier signals, ASC
and ASC', and the heterodyning carrier signal, fc. The synchronizing circuitry is described below in reference to FIGURE 26.
In ~his e~bodiment of the inven~ion, the training signal is in~er~ed into line 22 of the video signal produced by the encoder. ~his line is in ~he active video portion of the signal r not in ~he vertical blanking interval. The txaining signal is inserted in ~he active video region as opposed to the vertical blanking interval, because, in many television broadcast and cablecast plants, the synchronization signals are stripped ~rom the ~3~
-39- RCA 85,065 video signals during processing and ~hen reinserted before the signal is transmitted. It has been noticed by the inventors thAt the operation of removing and reinsertiny the synchronization signals may produce slight timing errors in the signal provided by the broadcast and cablecast plants. These timing errors appear as a horizontal or vertical shift in the position o~ the displayed image relative to the original image, or as er~ors in colors reproduced in the displayed image. In ~he system described herein, timing errors of this type may produce additional distortion in the reproduced image as set forth above in the background of the in~ention. These errors are avoided in the present embodiment because the traiIling signal, which determines the timi~g of the various component signals in the receiver, is inserted in a vertical overscan region of the active video region of the processed signal and, thus is not removed during processing at the plant. It is contemplated, however, that the training signal may be inserted in the vertical blanking interval.
The training signal used in this embodim~nt of the invention is a repeated psuedo-random noi~e (PN) sequence which has been band-limited to fit within the ~requency spectrum of an NTSC video signal. The use of a PN sequence for a time reference is well known. See, for example, W.
Peterson, "Error Correcting Codes", MIT Press, 1961 pp 147-148. An alternative training signal is al~o presented, this sequence is a raised-cosine ~T pulse which has been non-causally filtered before being stored in the ROM 2544.
The particular PN sequence used in thi~ embodiment of the invention includes 31 bits of information and is repeated si~ times during the 22nd horizon~al line interval of each field. Because the transmitted signal is bandlimited to 4.2 MHz, each ~it of the PN ~equence used in the training signal is represented by four 4 x fsc samples.
The six repetitions of the sequence may be averaged in the receiver to increase the accuracy o~ the ~irst sample time determination when the video signal is receiv~d through a ~3(~41S3 -40_ RCA 85,065 noisy transmission channel~ FIGURE 25b illustrates the timing of the training signal.
The first 12 bits of the PN seguence are illustrated on the top line of FIGURE 25b. The complete PN
sequence includes 31 bi-ts: 0,C,O,O,l,O,O,l,O,l,l,U,0,1, 1,1,1,1,0,0,0,1,1,0,1,1,1,0,1,0,1. As illustrated by the waveform for the training signal, the second waveform shown in FIGURE 25b, the zero and one levels of the PN sequence correspond to digital sample values which represent 0 IRE
and 100 IRE, respectively. The band-limiting of the P~
sequence limits the rise and fall time of the training signal to two sample periods of the siynal 4xfsc, or 140 ns. The training signal illustrated in FIGURE 25b, is provided by the ROM 2544 in response to succes~ive values of the signal PC, which increases in value at a rate of 8 x fsc. The first sample of the first instance of' the training signal is provided when PC e~uals 312, and the last sample value of the sixth instance of the training signal i5 provided when PC equals 1816.
The alternative ~raining signal is a non-causally filtered raised cosine 2T pulse illustrated by FIGURE 25c.
This training signal is developed as follows. Samples, SC, of a raised-cosine 2T pulse are generated using the equation (1).
SC = 0 f~r N = 0 to 3 SC = (1 cosine[2PI(N - 3)/7])/2 for N - 4 to 9 (1?

SC = 0 for N = 10 to 40 where N is a count of sample times having a sampling fre~uency of 4 x fsc.
The samples SC are then applied to an all-pass filter. An exemplary all-pass filter has th~ tran fer function AF~z) set forth in equation (2), where z is the z-transform variable.

~3~ 3 -41- RCA 85,065 AF(z) = 1.291(0.774z2-1.2z~l)/(z2 - 1.2z ~ 0.774~ (2) Circuitry which realizes this filter is shown in FIGURE
~Sd. This filter is known as an all-pass filter because it passes all frequencies with equal gain but with unequal phase response. This filter has a pair of complex poles and a pair of complex zeros in the Z-plane that are at the same xespective angles but have inverse radius.
The signal, F, shown in FIGURE 25c is ~he output signal produced by this all-pass filter in re~ponse to the 10 2T pulse. This signal has substantially the same frequency spectrum as the 2T pulse, since the filter which produced it is an all pass filter, but the signal is spread temporally and, so, is less susceptible to impulse noise distortion than an unfiltered 2T pulse. Before it is used as the training signal, the 40 sample sequence which defines signal F is time-reversed, such that the filtered sample zexo becomes sample 40 and the filtered sample 40 becomes sample zero. This time-reversed seguence is repeated six times during the 22nd horiæontal line interval of each field to generate the training signal.
When, in a receiver, the repetitions of this training signal are accumulated and ~he resultant signal is applied to a filter having the transfer function set ~orth in equation (2), a time reversed 2T pulse may be substantially recovered. Any impulse noise distortion in the recover~d 2T pulse will be temporally spread.
~n FIGURE 13, a broadcast compatible widescreen EDTV interlaced television signal is received by an antenna 1310 and applied to ~n antenna i~put of an NT5C receiver 1312. Receiver 1312 processes the compatible widescreen signal in normal fashion to produce an image display with a 4:3 aspect ratio, with the widescreen side panel information being in-part (i.e., the low freguency componen~s) compressed into the horizontal overscan regions out of sight of the viewer, and being in part (i.e., the high freguency components) con~ained in the modulated ~3~53 -42- RCA 85,065 alternate ~ubcarrier signal which is perceptually hidden in the display produced during standard receiver operation.
In FIGURE 13, the compatible widescreen EDTV
signal received by antenna 1310 is also applied to a widescreen Progressive scan receiver 1320 cap~ble of displaying a video image with a wide aspect ratio of, e.g., 5:3. The received widescreen signal is processed by an inpu~ unit 1322 including radio frequency (RF) tuner and amplifier circuits and a synchronous video demodulator (a quadrature demodulator) which producas a baseband video signal (NTSCFA) representing the in-phase component of the RF video signal and a si~nal (YTNA~ representing the quadrature phase component of the RF video signal and analog-to-digital (ADC) converter circuits which digitiz~
the signals NTSCFA and YTNA to produce digitized signals NTSCF and YTN. The ADC circuits operate at a sampling rate of four times the chrominance subcarrier frequency (4 x fsc).
Both the analog and digital versions of the signal NTSC~ are applied to a receiver timing signal genera~or 1325. The analog signal is u~ed to develop coarse synchronization signals and the training signal component of the digital signal is u~ed to fine-tune the synchronization signals. Optionally, the digitized version of the signal YTN, representing the quadrature compo~ent of the training signal, may also be applied to ~he generator 1325 to improve the fine-tuning of the synchroniæation signals. The receiver timing signal genera~or 1325 is responsive to the horizontal and vertical synchronizing si~nal components, to the color synchroni7.ing burst signal component and to the training signal component of the signal NTSCFA for genexating various timing signals used by the receiver. These timing signal~ include a 4 x fsc clock si~nal, CLK4; a clock signal, ICK, having nega~ive-going txansitions which occur coincident with the I color difference signal phase of the received color subcarrier signal; two signals, ~SC and ASC'I which represent the guadrature alternate subcarrier signals and are ~3(?~ 3 _43-- RCA 85, 065 substantially identical to the signals of the same name produced by the encoder; a si~nal fc which reprPsents the five M~z heterodyning carrier signal used by the encoder in th~ processing of component 3 o~ the EDTV signal; and a signal, H, which indicates which of the samples in a horizontal line interval of the signal NTSCF is the firs~
active video sample. These signals are used by the widescreen progressive scan receiver 1320 as described below.
The following is an overview of the operation of an exemplary receiver timing signal generator 1325 shown in FI~URE 26. The generator includes a phase locked loop system which generates a clock signal, CLK4, having a frequency that is substantially equal to 4 x fsc and that is locked in phase to the color burst sisnal component of the signal NTSCFA. The pulses of this signal are counted to produce a pixel identiying signal, PID, and an internal horizontal sync pulse, IHS. A microprocessor 2640 is responsive to the signal I~S, and to a signal, L22, which indicates the active pixel interval of the ~2nd horizontal line of each field, to collect samples of the training signal and to correlate them to a stored version of the training signal held in a ROM 2650. From this correlation, the microprocessor 2640 adjusts the phases of the siynals CLK4 and I~S so that they are aligned with the training signal to wi~hin five ns. The microprocessor 2640 also generates a signal FID which indicates which field of the NTSC four field sequence is currently being pxocessed. The signals PID and FID are applied as ad~ress signal~ to RO~s internal to the timing signal generator to produce ~he signals AS~, ASC' and fc.
Specifically, in the arrangement shown in FIGURE
26, the analog in-phase signal, NTSCFA is applied to conventional synchronizing signal separation circuitry ~610 which separates the horizontal line synchroniza~ion signal, HS, and the vertical field synchronization sig~al, VS, from the signal NTSCFA. T~e signals VS and ~S are applied to the respective res~t and clock inpu~ terminals of a ten-bit ~3~41~
-44- RCA 85,065 counter 2612. The output signal o~ this counter is the line number, in the current fi~ld, of the samples of the signals NTSCF and YTN that ~re currently being provided by the ADC 1323. This signal is applied to a line 22 detector 261~ which g~nerates a signal L22. The signal L22 is a pulse occurring once per field which spans the 22n~
horizontal line interval of the field.
A burst gate signal BG, is also produce~ by the circuitry 2610. This signal is applied to a conventlonal PLL 2616 which uses ~he burst gate signal to separate the burst signal component from the signal NTSCFA. The PLL
2616, which includes a resonant crystal, 2617, regenerates the chrominance subcarrier signal, Fsc, which is locked in phase to the burst signal component of the signal NTSCFA.
The signal Fsc is applied to one input terminal of a conventional controllable phase shifting circuit 2618. The circuit 2618 is responsive to an analog phase shift control signal, P~, applied to a control input terminal, for shifting the phase o the signal Fsc by an angle between -45 and +45 degrees. The phase shift control si~lal PH is provided by ~he microprocessor 2640 ~ia a DAC 2654. The generation of the si~nal PH is described below in reference to FIGURES 26a through 26f.
The phase shifted signal ~sc, provided by the 25 circuitry 2618, is applied to a further PLL 2620. The PLL
2620, which may be of con~entional design, provides an output oscillatory signal, CLK~, that has a frequency substantially equal to 8 x fsc and that is locked in phase to the signal Fsc. The signal C~K8 is applied to a freguency divid~r 2622 which halves the frequency of the signal CLK8 to produce the signal CLK4.
The signal CLK4 is applied to the clock input terminal of a ten-bit coun~er 26~4. The output signal of the counter 2624 is the signal PID which, when the sy6tem is synchronized, co~tains a sample index, relative to the star~ of the horizon~al blankiny interval, ~or each sample of the signals NTSCF and YTN provided by the ADC's 1323.
This sample index is used to generate the various timing ~Q~53 -45- RCA 85,065 and synchronization signals as described below. The signal PID is applied to the input port of a decoding circuit 2638. The circuit 2638 generates the pulse siynal, IHS, which is in a logic-one state for one period of the signal CLK4 coincident with the signal PID having a value of 909.
The signal IHS is applied to an input terminal of data write control circuitry 2642. The circuitry 2642 is responsive to the signals IHS, CLK4 and L22 and to a write ready signal, WRDY, for generating a write request signal, WREQ, for a first-in-first-out (FIF0) memory 2644.
The FIFO 2644 is responsive to the signal WREQ to store samples of the signal NTSCF that are applied to its input port. When the FIF0 is ready to accept a new sample, it applies a logic-one value as the signal WRDY to the data write control circuitry 2642. The FIFO 2644 is conditioned by the signal WREQ to store all of the samples of the signal NTSCF occurring between the time that the signal L22 indicates that samples from the 22nd horizontal line interval of a field are being provided and the occurrence of the pulse of the signal IHS. When the signal IHS is properly aligned to the training signal, this operation stores the complete training signal component of the siynal NTSCF into the FIFO 2644.
In an alternatiYe embodiment of the invention, the signal WREQ is further coupled to a FIF0 2646 ~shown in phantom) to condition the FIFO 2646 to store samples representing the 22nd line interval of the signal YTN.
These samples are used by the microprocessor 2640 to correlate the received training signal to the stored traini~g signal and so synchronize the ~imi~g signals used in ~he receiver to those u ed in the studio. In this alternative configuration, the signal WR~Y from the FIF0 2646 is logically ANDed ~not shown) with the signal WRDY
pro~ided by the FIFO 2644 for applicatio~ to the da~a write control circuit 2642.
The sample values stored during the 22nd horizontal line interval of a ~i~ld ar read from the FIF0 2644 during the ensuing field interval. The microprocessor :~3~4~53 -46- RCA 85,065 2640 reads data from the FIFO 2644, via the bus6 RDATA, by repeatedly causing a pulse si~lal RREQ to be generated.
The FIFO indicates that it is ready to provide the next sample value by applying a logic-one value, as a siynal RRDY, to the microprocessor 2640. When ~he last data value stored of the FIFO 2644 has been read, the FIFO applies a logic one value as the signal END to the microprocessor 2640. When the microprocessor 2640 receives a one-valued END signal, it causes a pulse sig~al RST to be generated which, in turn, resets the FIFO 2644, enabling it to accept data for the next field. In the alternate embodiment of the invention, the FIFO 2646 provides signals RRDYJ, ENDJ
and JDATA which correspond to the signals RRDY, END and RDATA provided by the FIFO 2644. The signals END and ENDJ
are logically ORed (not shown) so that either one may indicate the end of valid data to the microprocessor 2640.
The data read from the FIFO 2644 and optionally from FIFO 2646 are correlated to samples stored in the ROM
2650 which, for the PN seguence, are substantially identical to one repetition of the samples of the training signal stored in the ROM 2544 of the studio timing signal generator 2. When the filtered and time-reversed 2T pulse is used as a training signal, the stored training signal is substantially a time reversed version of th~ 2T pulse that was used to generate the training signal.
In order ~o obtain as close a correlation between the received and stored training signals as is possible, the microprocessor 2640 adjusts the phase of the siynal IHS
via a signal applied to the preset value (PV) input port of the counter 2624. When a pulse of the signal IHS occurs, the instantaneous value of the signal applied to the PV
input port of the counter is loaded as the initial count value~ The microprocessor 2~40 adjusts the phase of the signal CLK4 by changing the value of the phase 6hif~ signal PH applied to the phase shift circuitry 2618. The correlation operation is repeated on each field of the received signal to maintain the synchronization of the receiver within close tolerances (i.e. within 5ns~ The ~3~ 53 -47- RCA 85,065 signals PV and PU are, in eff~ct, time reference signal~
which align the signals derived from ~he signal PSc and the coun~er 2624 to corresponding signal~ generated by the widescreen EDTV encoder described above with reference ko FIGURE la.
In the present embodiment of the invention, the ROM 2650 includes a stored program which controls the functioning of the microprocessor 2640. In addition to the ROM 2650, the microprocessor 2640 uses a RAM 26~8 as a scratchpad memory during the correlation process.
The correlation process performed by the microprocessor 2640 is illustrated by the flow charts shown in FIGURES 26a through 26f. To simplify the explanation of the correlation process, the description below initially assumes that ~amples of the PN sequence training signal are stored in the FIFO 2644. Modifications to ~he procesæ to use the FIFO 2646 and to use the time reversed 2T pulse as the training slgnal are described separately.
The following is an overview of the processing represented by the flow charts in FIGURES 26a ~hrough 26c.
After initializing the memory locations used by the microprocessor (steps 2662-2664), the program in FIGURE 26a extracts sample values from the FIFO 2644 and accumulates them in 124 memory locations of a data array ACC (steps 2666, 2668 and 2680~. If the program determines ~step 2674) that the samples were not taken at the proper time during line 22, it conditions the microprocessor to change the preset value, PV applied to the counter 2624 ~step 267S) to correct the timing error, and then repeats the sample accumulation steps.
In FIGNRE 26b, the program conditions the microprocessor 2640 to calculate a sequence of sum-of product values. Each sum-of-product value represents the sum of each sample held in the array ACC multiplied by a corresponding value from a reference array REF which hold one instance of the training sign~l. The different sum-of-product value~ indicate different alignments of the samples from the arrays ACC and REF. As it calculates the ~3~1S3 -~8- RCA 85,065 different sum o product values, the microprocessor (at st~p ~698~ determines the maximum sum of product value and the alignment of the arrays ACC and REF which produced it.
The program steps illustrated by FIGURE 26c use the re~ults of the correlation operation illustrated by FIGURE 26b to calculate new values for the phase adjust signal PH and for the signal PV. This adjustment brings the timing and clock signal generated by the circuits illustrated in FIGURE 26 into proper alignment with the 0 corresponding signals used in the widescreen EDTV encoder.
The process begins in FIGURE 26a with a block 2660 labeled START. This block represents, for example, any initialization procedures which are performed by the microprocessor before the correlation process begins. When 5 the system is initialized, the microproc~ssor, at step 2662, waits for a negative-going transition of the signal L22. This transition marks ~he end of ~he 22nd horizontal line interval o a fieldO When this transition is detected, the training signal should be stored in the FIF0 2644~ ~t step 2664, the microprocessor 264~ zeroes each entry in an array of memory location~, ACC, and assigns a value of zero to the variable SCCOUNT and to the output signals PV and DPH. The array ACC is used to accumulate the repetitions of the training signal; the variable 5 SCCOUNT holds a count of the sample values read from the FIF0 2644. At step 2666, the microprocessor 2640 reads a sample value from the FIF0 2644, assigns the sample value to the variable RDATA. At step 2668, the microprocessor increments the sample count variable, SCCOVNT.
As each sample value is read from the FIF0 2644, the microprocessor, at step 2670, ch~cks ~he state of th~
signal END provided by the FIF0 ~644. If the signal END is in a logic-one state, no more samples may be read from the FIF0 2644. In this instance, the microprocessor 2640 resets the FIF0 2644 at step 2~72. ~f, at step 2674, the sample count (SCCOUNT) is ~reater than 898, indicating that a complete training signal was stored into the FIFO 2644, the microprocessor 2640 branches to block 2682 of FIGURE

~3~4tS3 -49- RCA 85,065 26b. Otherwise, at step 2676, a value of 899 minus the sample count (SCCOUNT) is assigned to the signal PV and the correlation process is restarted. The steps 2672 through 2676 enæure that the signal IHS is roughly aligned with the signal L22 before a correlation is attempted.
If, at step 2670, the signal END is in a logic-zero state, the microproceæsor, at stap 2678, checks if the sample count is less than 154~ If so, the samples represent the portion of the 22nd horizontal line interval which includes the horizontal blanking interval. This interval is ignored since it does not include any of the training signal. Consequently, the yes (Y) branch from the decision block 1678 conditions the microprocessor 2640, at step 2666, to read the next sample value from the FIFO
2644.
If the sample count, SCCOUNT, at step 2678 is greater than or equal to 154, the microprocessor accumulates the sample value, RDATA, in the array ACC.
Since each repeated sequence of the training signal includes 124 sa~ple values, samples that are separated by 123 intervening samples are corresponding sample values from successive sequences. The step 2680 determines the index (IXP) in the array ACC for the current sample using modulo (MOD) 124 addition (step 2680) and then adds the sample value to the accumulated sum at that index. The microprocessor 2640 branches to the step 2666 once the step 2680 has been performed.
The step 2682 of FIGURE 26b, which is performed due to a Y branch from the decision block 2674, begins the correlation process. In this process, the accumulated data in the array ACC is correlated to reference data in an array REF which is stored in the ROM 2650. The correlation process treats each of the arrays ACC and REF as being circular in structure, that is, it assumes that the entry at index O follows the entry at index 123. Ideally, the correlation process would proceed as follows. Each value in the array ACC is multiplied by a corresponding value in the array REF and the resultant products are summed to ~3~ i3 -50- RCA 35,065 generate one value. Next, the indicies of the arrays ACC
and REF are oset to change their correspondence a~d another value would be generated. This proce~s is repeated until all possible correspondenc~s hav~ been tried. It is a property of the PN sequence that the largest generated value occurs at the closest correlation between the arrays ACC and REF.
Referring to FIGURE 26b, the step 2682 assigns a value of zero to a variable INIX which holds the index offset value for the arrays ACC and REF. In step 2683, a variable MS~M which holds the maximum sum of pxoducts value is assigned a value of zero and each entry of an array SUM
is set to zero. The array SUM holds the sum-of-product values for each correspondence between ACC and REF as they are calculated. The next step, 2684, assigns the value in INIX to the index, IXP, for the array ACC and assigns a value of zero to the inde~, IXR, for the array REF.
The steps 2686, 2688 and 2690 implement an approximation of a multiplication operation that is used ~o form each product of a sum of products value. The decision block 2686 checks if the currently indexed reference value is negative. If so, the Y branch of the decision block causes step 2688 to be executed ne~t~ Otherwise, step 2690 is executed. Step 2688 subtxacts the currently indexed ~5 value of ACC from the value in the array SUM, while step 2690 adds the indexed value of ACC to the value in the array SUM. This process effectively reduces the array ~EF
to an array containing only values of +1 or -1 to the extent that the entries of the array REF mul~iply entries of the array ACC. Since, i~ the presen~ embodiment of the invention, television signals are guantized in eight-bit twos complement values, where -40 IRE and 100 IRE
correspond to respective quantized values of -128 and ~127, samples of the training signal representing values less than 30 IRE are negativ~ and samples representing values greater than 30 IRE are positive. While this appro~imation i~ less rigorous than a true multiplication op~ration, the inventors have determine~ that it produces satis~actory ~3C~
-51- RCA ~5,065 results and significantly reduces the computation time for the correlation operation.
Step 2692 increments the index variables IXR and IXP. The variable IXP is incremented modulo 124 to implement ~he circular correlation described above. The decision block 2694 causes the sum and product operations to repeat while IXR is less than 124. When IXR e~uals 124, all entries of the reference array have been used and the sum a.nd product operation is complete for the offset value held in the variable INIX.
The decision block 2696 compares the absolute value of the newly computed sum to the absolute value of thP largest sum computed so far, MSUM. If the new sum is greater than MSUM, it is assigned, at step 2698, to MSUM, and the offset, INIX, between the arrays ACC and R~F that was used to develop the new sum is assigned to the variable MIX. After executing step 2698 - or on the no (N) branch of the decision block 2696 - the value of the variable INIX
is increased by one. If, at step 2702, the value of INIX
is less than 123, the computation of the sum of products terms continues, at step 2684, with a larger offset between the arrays ACC and REF.
Wh~n the value of INIX eguals or exceeds 122, the circular correlation of th~ arrays ACC and REF is complete.
The microprocessor 2640 next executes the decision block 2704 shown in FIGURE 26c. The block 2704 compares the sum of product values ~or the index offset values that immediately surround MIX. If the magni~ude of the sum of product value for the index less th~n MIX is greater than that for the index grea~er than MIX, the step 2708 assi~ns SUM [MIX - 2] to a variable PSUM and assigns the valu~
MIX - 1 to a variable PIX. Otherwise the values of SUM
[MIX ~ 2] and MIX + 1 are assigned to the variable~ PSUM
and PIX in the ~tep 2714. These steps establish the optional off~t between the arrays ACC and REF as being between the values held in ~IX and PIX. Decision block~
2710 and 2716 following the respective steps 2708 and 2716 check the magnitude of the respective difference between ~l3~ 5~
-52- ~CA 85,065 ¦SUM[MIX + 1]l and PSUM or ISUM[MIX - 1] and PSUM against a mi~imum threshold value, DELTA. A difference less than this threshold value indicates that the receiver and transmitted signal are aligned to within 5ns . I f the difference exceeds the threshold value, further adjustment in the phases of the signals CLK4 and IHS is desirable.
Thus, at the respective steps 2712 and 2718, the microprocessor 2640 assigns new values to the variables PV
and DP~. The determination of whether a phase adjustment is needed and calculation of the phase adjustment value to be assigned to the variable DPH use product-of~sum values that are displaced by one index in each direction from MIX
and PIX. These product-of sum values lie on portions of a bell-shaped curve that have the greatest slope.
Conse~uently,~these product-of-sum values are the most sensitive to the slight phase changes caused by adjusting the value of the signal PH.
After executing either of the steps 2712 or 2718 or on the Y branches of either of the decision blocks 2710 or 2716, the microprocessor 2640 e~ecutes the decision block 2720. The block 2720 checks if the largest sum of products value is negative. If so, the value of the signal FID, provided by the microprocessor ~40 to a latch 2652, is set to zero at step 2724. Otherwise, the value of FID
is increme~ted at step 2722. As set for~h above, ~he training signal provided by the encoder is inverted (i.e.
100 IRE corresponds to -128 and -40 IRE corresponds to +127) once every four fields to transmit the field identifier (O, 1, 2, or 3) to ~he receiver. After executing either of the steps 2722 or 2724, th~
microproc~ssor 2640 branches to step ~662 ~o ~egin the correlation operation for the next video field. Thus, the correlation operation continues as lo~g as widescreen EDTV
signals are received.
Since the ~TSC video signal is ~ransmitted as a vestigial sideband signal, and since the training signal, whether it is the PN sequence or the filtered and time-reversed ~T pulse, occupies the full bandwidth of the video ~3a~s3 -53- ~CA a5,065 signal, the correlation operation described above may be affected by multipath distortion. A strong secondary (ghost~ signal ma~ cause crosstalk between the in-phase and ~uadrature phase components of the primary video signal by changing the apparent phase o the video carrisr signal.
This apparen~ phase error occurs because the carrier detected by the sy~chronous demodulator 1322 of FIGURE 13 is the vector sum of the carriers of the primary and ghost signals. When this detected carrier is used to demodulate the video signal, portions of in-phase co~ponent of the primary signal appear in ~he demodulated quadrature phase component and vice-versa. This reduces the amplitude of the traininy signal and adds quadra~ure distortion to it.
One method of compensating for potential multipath di~tortion is to use both the in-phase and guadrature phase components of the training signal in the correlation oparation. This is accomplished by treating the in-phase and quadrature components of the video signal, NTSCF and YTN, r~spectively as the real and i~aginary parts of a single complex signal. Modifications of the FI~URES
26a, 26b and 26c to accommodate the signal YTN in addition to the signal NTSCF are shown in FIGUXES 26d, 26~ and 26f, respectively. The al~orithm described by these figures is essentially the same as the algorithm described above.
Consequently, only the differences ~etween the FIGURES 26a, 26b and 26c and the respective FIGURES 26d, 26e, 26f are described~ In FIGURE 26d a variable JDATA and an array ACCJ are added to hold the quadrature phase samples provided by the FIFO 2646~ Sample values are provided to the variable JDATA from the F~FO 2646 at step 2766. At step 2780, samples from the FIFO 2646 are accumulated in the array ACCJ at ~he same time that samples rom the FIFO
2644 are accumulated in an array ~CCR. The array ~CCR i5 the ~ame as the array ACC of FIGURE 26a.
When step 2782 of FI~URE 26e is executed, the arrays ACCR and ACCJ have values representing the respective accumulation of six instances of the in~phase component and six instances of the ~uadrature phase ~3~ 53 54-- RCA 85, ()65 component of the training signal. ~t step 2783, arrays SUMR and SUMJ are initialized in addition to -the array SUM.
At step 2786, the product of samples representing the in-phase component of the ~raining signal held in the a.rray ACCR and samples of a stored in-phase training signal, held in an array REFR, and the product of samples representing the qua~rature phase component of the ~raining signal held in the array ACCJ and samples of a stored yuadrature phase training signal, held in an arry REFJ are summed and stored into an array SUMR. At step 2786, the product of corresponding values in the arrays REFJ and ACCR is subtracted from the product of values in the arrays REFR
and ACCJ. The resulting difference values ar~ accumulated in an entry of the array SUMJ. Corresponding values in the array SUMR and SUMJ are squared and summed in step ~795 to calculate a value for the array SUM. The calculation illustrated in step 2786 is a multiplication of a complex vector (ACCR, ACCJ~ representing the in-phase and quadra~ure phase components of the received training si~lal by the complex conjugate, a complex vector (REFR, REFJ) representing the in phase and quadrature phase components of the stored reference training signal.
When step 2804 of FIGURE 26f is executed, the array SUM holds values representing the sum-of-products of the arrays ACCR, ACCJ and REFR, REFJ for each correspondence of indicies between the two sets of arrays.
The algorithm in FIGURE 26f differs from that o~ FIG~RE 26c in that the absolute value operation is not used in step~
2704, 2710, and 2716, and that ~he value SUMR [MIX3 is used in place of MSUM in step 2720. Since the value SUM~ [MIX~
is the produc~ of the in-phase componen~s of the received and refere~ce training signals at the index corresponding to a maximum sum-of-products value, ik is essentially the same as the value MSUM used in FIGURE 26c. The value MSUM
is not used i~ this alternative algorithm to synchronize the field sequence of the television rec~iver to that of the widescreen EDTV encoder because, due to the sguaring 13~ i3 -55- RCA B5,065 operations in step ~786, the value of MSUM is always positive.
In additio~ to compensating for multipath distortion, the algorithm illustrated by FIGURES 26d-26f may improve the image produced by an EDTV receiver fro~ a weak or nois~ signal. This improvement in performance occurs because the correlation operation uses signal energy in the quadrature component of the r~cieved signal in addition to energy in the in-phase component. The algorithm presented above with reference to FIGURES 26a-26c use~ only energy in the in-phase component of the received signal.
If the time-reversed fil~ered 2T pulse is used as the training signal, the correlation process is modified to include additional calculations (not shown) between the step 267~ of FIGURE 26a and step 2682 of FIGURE 26b which simulate the filter shown in FIGURE 25c, and to replace the steps 2686, 2688 and 2690 with a step (not shown) that actually multiplies the eutries i~ the array ACC by entxies in the array REF. It may also be desirable to shorten the number of samples in the repeated sequence to, for example, 40, since there is negligible energy in the filtered 2T
signal beyond 40 samples. Otherwise, ~he procedure for correlating ~he training signal to ~he reerence signal is the same as that described above. As an alternative to simulating the all-pass filter, shown in Figure 25d, using the microprocessor 2640, the receiver timing signal generator shown in FIGURE 26 may include circuitry (not shown) ~uch as that shown in Figure 26d, at the input port of the F~FO 2644. This circuitry would cause a sequence o six repetitions of a time-reversed 2T pulse to be stored in the FIF0 2644. In this embodiment, the stored training signal would also be a time reversed 2T pulse Referring, once more, to FIGURE 2~, ~he pixel identification signal, PID, generated by the counter 2624 is applied to a decoder 2626 which emi~s a time referenc~
pulse signal, H, having a pulse width of approximately 70 ns when the value of the signal PID is 156. This ~ime ~3n~i3 -56- RCA 85,065 reference pulse is emitted once for each horizontal line of video si~al and correspond~ to the first sample of active video on the line. The signal PID; the field identification signal, FID, generated by the microprocessor 2640 and stored in the latch 2652; and a signal O/E, provided by the counter 2612, which indicates whether the current line of samples is an odd or an even line in its field; are applied to ROMs 2628 and 2630. These ROMs may be programmed similarly to the respective ROMs 2530 and 2532 described above in reference to FIGURE 25. The only difference between the ROMs 262~, 2630 and the ROMs 2530, 2532 is the number of bits in ~he address signal PID. The signal PID in FIGURE 26 is a ten-bit signal which changes at a rate of 4 x fsc while the signal PC used in FIGURE 25 is an eleven-bit signal which changes at a rate of 8 x f~c.
The ROM 2628 generates the alternate subcarrier signals ASC
and ASC'. The ROM 2630 generates the 5 MHz heterodyning signal fc. These signals are used by the decoder circuitry as described below.
The signal O/E and the signal FID are fur~her applied to a ROM 2634. The XOM 2634 is programmed to produce a logic-one output signal for each horizontal line interval in which the first active video sample has a chrominance signal componen~ at the Q phase of the regenerated colox subcarrier signal, Fsc. The signal provided by the ROM 2634 is logically ANDed with the signal H by an AND gate 2636. The pulse signal provided by the AND gate 2636 is applied to the reset input t~,rminal, R, of a frequency divider 2632. ~he signal input terminal of the frequency divider 2632 is roupled to receive the 4 x fsc clock signal, CK4~ The output si.gnal of the frequency divider 2632 is the signal ICK which has a frequency substantially equal ~o ~ x ~sc and which has negative going transitions that occur in substantial coinci~ence with the I phase of the color subcarrier signal, Fsc.
Referring ~o Figure 13, the signal NTSCF is applied to an intraframe averager differencer unit 1324 which averages (additively combines) and differences ~3~4~

-57- RCA 85,065 (subtractively combines) image line~ 262H apart within a frame, at fre~uencies greater than 1.7 MHz, to recover main signal N and guadrature modulated signal M substantially free from V-T crosstalk. A 200 KHz horizontal crosstalk guardband is provided between the 1.7 MHz lower limit operating frequency of ~he intra-frame averager-differencer 1324 and the 1.5 MHz lower limit operating frequency of the intra-frame averager 38, used in the encoder of FIGURE la.
This guard band substantially eliminates crosstalk between the signal ~ and the luminance signal components of the signal N. The recovered signal N contains information which is essentially visually identical to image information of main signal C/SL, due to the high visual intraframe image correlation of original main signal C/SL
as intraframeiaveraged in ~he encoder of Figure la.
Details of averager-differencer unit 1324 are shown in FIGURE 15. Signal NTSCF is low pass filtered by unit 1510 to produce a "LOWS" component which is subtractively combined with signal NTSCF in a unit 1512 to produce the "HIGHS" component of signal NTSC~. This component is delayed by one field period, averaged (additively combined) and differenced tsl~tractively combined) by a unit 1513 to produce an averaged highs component NH at an averaging output ~+), and signal M at a differencing output (-). Exemplary circuitry for use as the averager-diferencer 1513 is shown in Figur~ 16.
Component NH is summed in an adder 1514 with a 262H delayed output signal from filter 1510 to produce signal N.
Referring to Figure 13, the signal M is coupled to a quadra~ure demodulator and amplitude expand~r unit 1326 for demodulating auxiliary signals X and Z in re~ponse to alternate subcarriPr signals ASC a~d ASC' which have the same characteristics as the signals ASC and ~SC' described abo~e in reference to the widescreen EDTV encoder circuitry. Demodulated sisnals X and Z contain information which is essentially visually identical ~o image information of signal ESH and of the output signal from unit 74 in Figure la, respec~ively, due to the high ~3t~5~
-58- RCA as ~ 065 intraframe image correlation of the&e signals as intraframe averaged by the encoder of Figure la. Exemplary circuitry which may be used for the guadrature demodulator and amplitude expander 1326 is shown in FIGURE 27. This circuitry includes two multipliers 2750 and 2752 which multiply the signal M by ASC an~ ASC', respectively. The signals provided by the multipliers 2750 and 275~ ar~
filtered by respective low-pass filters 2753 and 2757, which have a passband from, for example 0 to 1.5 MHz. The filters 2752 and 2757 remove u~wanted high-freque~cy modula~ion components. The signal~ provided by the filters 2753 and 2757 are subject to an in~erse gamma function, via the PROM's 2754 and 2756 respectively, to produce the signals X and 2.
Referring to FIGURE 13, a unit 1328 time compresses the color encoded side panel highs (signal X) so that they occupy their original time slots, thereby recovering signal NTSCH. The si~nal NTSCH is substantially identical to the signal NTSC~ described above in reference to Figure la.
A luminance (Y) highs decoder 1330 decodes the luminance horizontal highs (signal Z) into widescreen format. The sides are time expanded to reverse the time compression performed by the encoder of FIGURE la, and the center is time compressed to reverse the time expansion performed by the encoder of FIGURE la.
~ n FI5URE 17, which shows details o unit 1330 of FIGURE 13, signal Z is applied to a side-center separator (demultiplexer) 1710 which provides separated luminance highs side and center signals, YHO and Y~E respectively.
The demultiplexer 1710 is controlled by a counter 1706 and a decoder 1708. The counter 1706 is reset by ~he signal - at a time corresponding to the first active pixel of the signal Z and is clocked by the 4 x ~sc signal ~K4 to co~mt the pixels of the signal Z. The decoder 1708 is responsive to a count value signal provided by the counter 1706 to produce a control signal which conditions the demultiplexer 1710 to direct side panel pixels (count values 0 13 and ~L3~
-59- RCA 85,0fi5 740-753) to the signal Y~O and to direct the center pan~l pixels (count values 14-739) to the signal YHE.
The signals YHO and Y~E are respectively time expanded and time compre~ed by units 1712 and 1714 using mapping techniques, described above in reference to FIGURES 12 and 12a through 12d to produce signals representing the luminance high frequency components for the sides and center o the image, YHS and YHC, respectively. These signals are spliced by a unit 1716.
FIGURE 14 depicts side panel-center panel splicing apparatus suitable for use as splicer 1716. In FIGURE 14, the splicer is shown as comprising a network 1410 for producing full bandwidth luminance signal YF' from side panel luminance signal component YS and center panel luminance signal component YC, as well as an I signal splicer 1420 and a Q signal splicer 1430 which are identical in structure and operation to network 1410. The center panel and the side panels are purpos~ly overlapped by, for example, ten pixels; the center and side panel signals have shared several redundant pixels throughout the signal encoding and transmission process as illustrated by Figure 3.
In the widescreen receiver, the center and side panels are reconstructed from their respective signals, but because of the time expansion, time compression and filtering performed on the side and center panel signals, several pixels at the side and center panel boundaries are corrupted, or distorted. The overlap regions (Oh3 and corrupted pixels (CP; slightly exaggerated for clarity~ are indicated by the waveforms associated with si~nals YS and YC in FIGURE 14. If the pa~els had no overlap region, ~he corrupted pixels would be abutted against each other, and a sea~ would be visible. An overlap region ten pixels wide has been found to be wide enough to compensate for three to five corrupted boundary pi~els.
In the splicer 1410, a multiplier 1411 multiplies side panel signal YS by a weighting function w in the overlap regions, as illustrated by the associa~ed waveform.

~L3~ ;3 -60- RCA 85,065 The signal produced by the multiplier 1411 is applied to a signal combiner 1415. Similarly, a multiplier 1412 multiplies center panel signal YC by a complementary weighting function (1-W) in the overlap regions, as illustrated by the associated waveform, and applies the resultant signal to the combiner 1415. The w~ighting functions W and l-W exhibit a linear ramp-type characteristic over the overlap regions and contain values between 0 and 1. After weighting, the side and center panel pixels are summed by combiner 1415 so ~hat each reconstructed pixel is a linear combination of side and center panel pi~els.
The weighting functions preferably should approach unity near the innermost boundary of the overlap region, and should approach zero at the outermost boundary.
This will insure that the corrupted pixels have relatively little influence on the reconstruc~ed panel boundary.
Weighting functions W an~ l-W can be readily generated by a network including a look-up table ~not shown) responsive to an input signal representative of pixel positions, and a subtractive combiner (not shown~.
The look-up table is programmed to provide xamp function output values from 0 to 1 in the overlap xegion, in response to the input signal. The inpu~ signal can be developed in a variety of ways, such as by a pixel counter which is reset by the signal H.
Referring to FIGURE 13, an amplitude modulator 1332 amplitude modulates the signal from decoder 1330 on a 5.0 MHz carrier fc. The amplitude modulated signal is 30 afterwards high pass filtered by a filter 1334 with a 5.0 Mhz cut-off freguency to remove the lower side~and. In the output siynal from filter 1334, center panel freguencies of - 5.0 to 6.2 MHz are recovered, and side panel freguencies of 5.0 to 5.2 MHz are recovered. The signal from filter 1334 is applied to an adder 1336.
Signal NTSCH from compressor 1328 is applied to a unit 1340 which separates the luminance highs from the ~3~ 15;3 -61- RCA 85,065 chrominance highs to produce signals ~, IH and QH. This can be accomplished by the arrangement of FIGURE 18.
In FIGURE 18 an H-V-T bandpass filter 1810, which ha~ the configuration of FIGURE lOc and a pass~and of 3.58 ~ O.5 MHz, passes chrominance~band compon~nts of the signal NTSCH to a subtractive combiner 1814, which reseives the signal NTSCH that has been delayed through a transit time equalizing delay 1812. The separated luminance highs signal YH appears at the output of combiner 1814. The filtered signal NTSC~ from filter 1810 is quadrature demodulated by circui~ry which includes latches 1815 and 1816, selective twos complementing circuits 1818 and 1820, an inverter 1822 and a frequency divider 1824. The latches 1815 and 1816 are responsive to the signal ICK and its logical inverse, respectively, to store samples representing the respective I and Q color difference signals. A~ set forth ab~ve, in reference to FIGURE 9, these samples alternate in polarity. To inver~ the polarity of alternate ones of each of the I and Q color difference samples, the demodulator includes the selectiv~
two's complementing circuits 1818 and 1820. These circuiks are responsive to a signal provided by the frequency divider 1824, having a frequency that is half the frequency of the signal ICK to invert only alternate ones of the sample values provided by the latches 1815 and 1816. The output signals of the two's complementing circuits 1818 and 1820 are the respective color difference signals IH and Q~.
Signal N from unit 1324 is separated into its consituent luminance and chrominance components YN, ~N and QN by means of a luminance-chrominance separator 1342 which may be the same as the separator 1340, described above.
Signals YH, IH, Q~ and YN, IN, QN are provided as inputs to a ~-I-Q format decoder 1344 which decode~ th~
luminance and chrominance components in~o widescreen format. Details of decoder 1344 are shown in FI~URE 19.
In FIGURE 19, signals YN, IN and QN are separated into compressed side panel lows Y0, I0, Q0 and into expanded center panel signals YE, IE, Q~ by means of a ~3(~ 3 -62 RCA 85,065 side-c~nter panel signal separator (time de-multiplexer) 1940. Demultiple~er 1940 can employ the principles of demultiplexer 1710 and its peripheral circuits 1706 and 1708 discussed previously in reference to FIGURE 17.
Si~nals Y0, I0 and Q0 are time expanded by a side expansion factor (the inverse of ~he side compression factor in the encoder of FIGURE la) by means of a time expander 1942 ~o restore the original spatial relationship of the side panel lows in ~he widescreen signal, as represented by restored side panel lows signals YL, IL and QL. Similarly, to make room for the side panels, center panel signals YE, IE and QE ar~ time compressed by a center compression factor (the inverse of the center expansion factor in the encoder of FIGURE la) by means of a time compressor 1944 to restore the original spatial relationship of the center panel signal in the widescreen signal. The output signals produced by the compressor 1~44 are the restored center panel signals YC, IC and QC.
Compressor 1944 and expander 1942 can be of the type described above in reference to FIGURE 12.
Spatially restored side panel highs YH, IH and QH
are combined with spatially restored side panel lows YL, IL
a~d QL by a combiner 1946 to produce reconstructed side panel signals YS, IS and QS. The~e signals are spliced to the reconstructed center panel signal YC, IC and QC by means of a splicer 1960 to form a partially reconstructed widescreen luminance signal YFo' and reconstructed widescreen color difference signals IF' and QF'. Splicing of the side and center panel signal components is accomplished in a manner which virtually eliminates a visible seam at the boundary between the center and sid~
panels, apparatus suitable for use as the splicer 1960 is described above in reference to FIGURE 14.
Referring to FIGURE 13, the signal YF~' provided 35 by the decoder 1344 is coupled to the adder 1336 where it is s D ed with the high frequency luminance signal from filter 1334 to generate a reconstructed wide bandwidth luminance signal, YF'.

~3~4~
-63- RCA 85,065 Signals YF', IF' and QF' are converted from interlaced to progressive scan format by means of converters 1350, 1352 and 1354, respectively. Luminance progressive scan converter 1350 also responds to "helper"
luminance signal Y'~ from a format decoder 1360, which decodes encoded "helper" signal YTN. Decoder 1360 decodes signal YTN into widescxeen format, and exhibits a confiyuration of the type shown in FIGURE 17.
The I and Q converters 1352 and 1354 convert interlace scan signals to progressive scan signals by tempor~lly averaging lines one frame apart to produce the missing progressive scan line information. This can be accomplished by apparatus of the type shown in FIGURE 20.
In FI&URE 20, interlace signals IF' (or QF') are delayed 263H by an element 2010 and then applied to the input port of a dual-port memory 2020. This delayed signal is subjected to an additional 262E delay by an element 2012 before being added to the undelayed input signal in adder 2014. The output signal from adder 2014 is coupled to a divide-by-two network 201~. The signal produced by the network 2016 is applied to the input port of a dual-port memory 2018. Memories 2020 and 2018 accep~ data at a 4 x fsc rate and provide data at an ~ x sc ra~e. The output ports of the memories 2018 and 2020 are coupled to a multiplexer 5MUX) 2022 which switches between ~he signals provided by the memories 2018 and 2020 to produce an output progressive scan signal IF(QF). Also shown in FIGURE 20 are wavefonms illus~rative of the interlace input signal (two lines, with pixel s~mples C and X designated) and the proscan output signal comprising pixel samples C and X.
The luminance progressive scan conv~rter unit 1350 i~ similar to that shown in FIGURE 20, except that signal YT is added as shown by the arrangement of FIGURE
21.
Referring to FIGURE 13, widescreen progressive scan signals YF, IF and QF p.~ovided ~y the conver~ers 1350, 1352 and 1354 are co~er~ed to analog form by means of a digital~to~analog converter 1362 which produces signals Y, ~3~S3 64- RCA 85,065 I and Q that are applied to a video signal processor and matrix a~plifier unit 1364. The video si~nal processor component of unit 1364 includes signal ampli~ing, DC level shifting, peaking, brightness control, contrast control and other conventional video signal processing circuits.
Matrix amplifier 1364 combines luminance signal Y with color difference signals I and Q to produce color image representative video signals R, G and B. These color signals are amplified by display driver amplifiers in unit 1364 to a level suitable for directly driving a widescreen color image display device 1370, e.g. a widescre~n kinescope.

Claims (18)

1. Apparatus comprising:
a source of television signal having a main signal component including a luminance signal sub-component and a color information signal sub-component, an encoded augmentation signal component, and a training signal component;
signal separating means, coupled to said source, for separating said main signal component, said encoded auxiliary signal component and said training signal component from said video signal;
main signal processing means, coupled to said signal separating means, for separating the luminance signal sub-component and the color information signal sub-component from said main signal component;
means, coupled to said signal separating means, for processing said training signal component to develop a time-reference signal;
decoding means, coupled to said signal separating means and responsive to said time-reference signal for decoding said encoded augmentation signal component to generate a decoded auxiliary signal;
means for combining said decoded auxiliary signal with one of said luminance signal sub-component and said color information signal sub-component to generate video signals representing an enhanced video image.

-66- RCA 85,065

2. The apparatus set forth in Claim 1, wherein:
said television signal includes first and second synchronizing signal components having a mutual phase relationship which repeats with a period of N field intervals, where N is a positive integer greater than one;
said training signal is reversed in polarity for one out of every N field intervals to indicate the phase relationship; and said means for processing said training signal includes means responsive to the polarity of said training signal for generating said first and second synchronizing signal components having substantially said mutual phase relationship.

3. The apparatus set forth in claim 1 wherein:
said training signal includes plural repetitions of a basic training signal and occurs during a portion of one horizontal line period in each field period of said television signal;
said means for processing said training signal includes:
sample value accumulating means for combining the plural repetitions of the basic training signal occurring during one field period of said television signal to develop an accumulated basic training signal; and means for correlating said accumulated basic training signal to a reference training signal to to generate said time-reference signal.

-67- RCA 85,065

4. The apparatus set forth in Claim 3 wherein:
said training signal includes an in-phase component and a quadrature phase component;
said sample value accumulating means includes means for separately combining the plural repetitions of the in-phase and quadrature phase components of said basic training signal to develop respective in-phase and quadrature phase accumulated basic training signals; and said means for correlating includes means for correlating said in-phase and quadrature phase accumulated training signals with in-phase and quadrature phase reference training signals to generate said time reference signal.

5. The apparatus set forth in Claim 3 wherein said basic training signal and said reference training signal represent a pseudo-random noise sequence.

6. The apparatus set forth in Claim 3 wherein:
said basic training signal is a time-reversed all-pass filtered raised-cosine 2T pulse;
said reference training signal is a time-reversed raised-cosine 2T pulse; and said means for correlating includes:
means for filtering said basic training signal to generate a modified training signal representing a time-reversed raised-cosine 2T pulse; and means for correlating said modified training signal to said reference training signal.

-68- RCA 85,065

7. The apparatus set forth in Claim 1, wherein:
the color information signal sub-component of said main signal component includes first and second color difference signals which modulate a suppressed subcarrier signal in quadrature and a color reference burst signal having substantially the same frequency as said suppressed subcarrier signal;
said means for processing said training signal includes means responsive to said to said color reference burst signal and to said training signal for generating a reference oscillatory signal; and said main signal processing means includes means, responsive to said reference oscillatory signal, for demodulating the color information signal sub-component of said main signal component to obtain said first and second color difference signals.

8. The apparatus set forth in Claim 7 wherein:
the television signal provided by said source represents an image having significantly greater horizontal detail than a conventional television image;
said main signal component includes said luminance signal sub-component and said color information signal sub-component which represent an image having substantially the same level of horizontal detail as said conventional television image;
said auxiliary signal component includes a frequency-shifted, high-pass filtered luminance signal, representing the difference in horizontal detail between the image represented by the signal provided by said source and the image represented by said main signal component, and occupying a band of frequencies within the band of frequencies occupied by said main signal component;
said means for processing said training signal includes means responsive to said time-referance signal and to said reference oscillatory signal for generating an oscillatory carrier signal;

-69- RCA 85,065 Claim 8 continued said decoding means includes means for heterodyning said oscillatory carrier signal with said frequency-shited, high-pass filtered luminance signal to generate a high-pass filtered luminance signal; and said combining means includes means for additively combining said high-pass filtered luminance signal and said main signal component to generate said video signals representing said enhanced video image, having greater horizontal detail than said conventional television image.

9. The apparatus set forth in Claim 8, wherein:
the frequency-shifted, high-pass filtered luminance signal of said auxiliary signal component modulates a suppressed alternate subcarrier signal having a frequency within the band of frequencies occupied by said main signal component;
said means for processing said timing signal includes means responsive to said time-reference signal and to said reference oscillatory signal for regenerating said alternate subcarrier signal; and said decoding means includes means, responsive to said auxiliary signal component and to said regenerated alternate subcarrier signal, for demodulating said frequency-shifted high-pass filtered luminance signal.

-70- RCA 85,065

10. The apparatus set forth in claim 1, wherein:
the television signal provided by said source represents a widescreen image having an aspect ratio greater than a conventional aspect ratio;
said main signal component includes first, second and third portions representing respective center panel and left and right side panel portions of said widescreen image, wherein said center panel portion has an aspect ratio substantially equal to said conventional aspect ratio, and wherein said second and third portions represent relatively low detail information in the side panel portions of said widescreen image;
said auxiliary signal component includes first and second portions representing relatively high detail information in the respective left and right side panel portions of said widescreen image; and said decoding means includes means, responsive to said time-reference signal, for aligning the first and second portions of said encoded auxiliary signal component with the respective second and third portions of said main signal signal component to produce said decoded auxiliary signal component.

11. A system for controlling the relative timing of a plurality of signal components of an augmented video signal, comprising:
a source of augmented video signal including main and auxiliary component signals;
a source of training signal representing a predetermined instant in a horizontal line period of said video signal;
means for combining said augmented video signal and said training signal to generate a transmitted signal;
means, coupled to receive said transmitted signal, for separating the training signal from said transmitted signal;
means for processing said training signal to generate a time-reference signal indicative of said predetermined instant;

-71- RCA 85,065 Claim 11 continued means, coupled to receive said transmitted signal, for separating the main and auxiliary component signals therefrom;
means, responsive to said time-reference signal, for aligning said main and auxiliary signals to produce time-aligned main and auxiliary signals;
means for combining said time-aligned main and auxiliary signals to generate video signals representing an enhanced image.

12. The system set forth in Claim 11, wherein: said source of augmented video signal includes:
a source of enhanced video signal representing a widescreen image having an aspect ratio greater than a conventional aspect ratio;
means for separating said enhanced video signal into said main and auxiliary signal components, said main signal component representing an image having a conventional aspect ratio and said auxiliary signal component representing an enhancement signal for reconstructing with said main signal component, said widescreen image;
said source of said training signal includes timing means for generating a composite synchronizing signal including horizontal and vertical synchronizing signal components and a color reference burst signal component, and said training signal, wherein said predetermined instant is defined relative to a pulse of said horizontal synchronizing signal; and said means for combining includes:
means for combining said main and auxiliary signal components with said composite synchronizing signal to generate a combined signal; and means for inserting said training signal between two consecutive pulses of said horizontal synchronizing signal component of said combined signal to generate said transmitted video signal.

-72- RCA 85,065

13. The system set forth in Claim 12, wherein said timing means includes:
means for generating a basic training signal having a predetermined displacement in time from said pulse of said horizontal synchronizing signal; and means for repeating said basic training signal an integral number of times to generate said training signal.

14. The system set forth in Claim 11 wherein said basic training signal is a pseudo-random noise sequence.

15. The system set forth in Claim 12, wherein said basic training signal is a time-reversed, all-pass filtered, raised-cosine 2T pulse.

16. The system set forth in Claim 12, wherein:
said combined signal includes an active video interval which contains image information and a vertical blanking interval which contains no image information; and said training signal occurs within said active video interval.

17. The system set forth in Claim 13, wherein said means for processing said training signal includes:
sample value accumulating means, coupled to said means for separating said training signal from said transmitted signal, for combining instances of the repeated basic training signal from the training signal to generate an accumulated basic training signal; and means for correlating said accumulated basic training signal with a reference training signal to generate said time-reference signal.

-73- RCA 85,065

18. The system set forth in Claim 16 wherein:
said training signal includes in-phase and quadrature-phase components;
said sample value accumulating means includes means for separately combining the repeated instances of the respective in-phase and quadrature phase components of said training signal to generate respective in-phase and quadrature phase accumulated basic training signals; and said means for correlating includes complex value correlating means for correlating a first complex signal which includes said in-phase and quadrature phase accumulated basic training signals with a second complex signal which include in-phase and quadrature phase reference training signals, to generate said time reference signal.