CA1246254A - System for improving signal-to-noise ratio in a direct sequence spread spectrum signal receiver - Google Patents

Abstract

SYSTEM FOR IMPROVING SIGNAL-TO-NOISE RATIO IN A
DIRECT SEQUENCE SPREAD SPECTRUM SIGNAL RECEIVER

Abstract A plurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different assigned code sequence shift. A receiver, synchronized to the clock, discriminates the signal transmitted by a predetermined transmitter from signals transmitted by the others by generating a first pseudo-random code that is a replica of the common bipolar pseudo-random code and has a code sequence shift corresponding to that of the predetermined transmitter, and a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unassigned code sequence shift. The difference between the first and second bipolar pseudo-random code sequences, which is a trinary code sequence, is cross-correlated with the incoming signal. The cross-correlation despreads only the signal having the predetermined code sequence shift. Each receiver includes a number of correlation detectors offset from each other by a fraction of a code chip, together with decision circuitry to identify cross-correlation peaks for optimum synchronization. The output of each sub-receiver is processed to extract data using weighting factors selected according to the particular distortion present, to improve signal-to-noise ratio.

Description

44 . 349 ~z~z54 . Canada CORRELA~ION DETEC~O~S FOR USE IN DIRECT
SEQUENCE SPREAD SPECTRUM SIGNAL RECEIUER

Technical Field _ me invention relates generally to code division multiplexing using direct sequence spread spectrum signal processing, and more particularly, toward signal processing to increase the number of transmitters multiplexed for a given code len~th.

Background Art In a spread spectrum system, a transmitted signal is spread over a frequency band that is much wider than the minimum bandwidth required to transmit particular information. Whereas in other forms of modulation, such as amplitude modulation or frequency modulation, the transmission bandwidth is comparable to the bandwidth of the information itselfp a spread sFectrum system spreads an information bandwidth of, for exa~ple, only a few ~2~6Z5~

kilohertz over a band that is many megahertz wide, by modulating the information with a wideband encoding signal. Thus, an i~portant characteris~ic distinguishing spread spectrum systems from other types of broadband transmission systems is that in spread spec~rum signal processing, a signal other than the information being s~nt spreads the transmitted signal.
Spreading cf the transmitted signal in typicAl spread sFectrum systems is provided by 11) direct se~uence modulation,

(2) frequency hopping or (3) pulsed-~ or "chirp" modulation. In direct sequence modulation, a carrier is modulated by a digital code sequence whose bit rate is much higher than the inormation signal bandwidth. Frequency hopping involves shifting the carrier frequency in discrete increments in a pattern dictated by a code sequence, and in chirp modulation, the carrier is swept over a wide band during a given pulse interval. Other, less frequently used, carrier spreading techniques include tlme hopping, wherein transmission time, usually of a low duty cycle and short duration, is governed by a code sequence and time-frequency hoyping wherein a code sequen oe determines both the transmitted frequency and the time of transmission.
Applications of spcead sFec~rum systems are various, depending upon characteristics of the codes being employed for band spreading and other facto~s. In direct sequence spread spectrum systems, for exa~ple, wherein the code is a pseudo-random sequence, the composite sign 1 acquires the characteristics of noise, maXing the transmission undiscernable to an eavesdroeFer who is not capable of decoding the transmission. Additional applications include navigation and ranging with a resolution depending upon the particular code rates and sequenoe lengths used. Reference is made to the textbook of R.C. Dixon, Spread Spectrum Systems, 30hn Wiley and Sons, New York, 1976, especially Cha~ter 9, for application details.
Direct sequence mcdulation involves modulation of a carrier by a code sequenc~ of any one of several different formats, such as AM or FM, although biphase phase-shift keying is the most common. In biphase phase shift keying (PSK), a balanced mixer 59~

whose inputs are a code sequence and an RF carrier, controls the carrier to ~e transmitted with a first phas2 shift of X when the code s2quence is a "1" and with a second ~hase shift of (180 + X1 when the code sequence is a "o~ iphase phase-shift keyed modulation is advantageous over other fon~s because the carrier is suFpressed in the transmission making the transmission more di~icult to receive by conventional e~uipment and ~reserving more eower to be applied to information, as opposed to the carrier, in the transmission. Characteristics of bi~hase phase-shift keying are given in Chapter 4 of tne aforementioned Dixon text.
The type of code used for spreading the bandwidth of the transmission is preferably a linear code, particularly if message security is not required, and i5 a maximal code for best cross correlation characteristicsO Maximal codes are, by definition, the longest codes that could be generated by a given shift register or other delay element of a given length. In binary shift register sequence generators, the maximum len~th (ML) sequence that is capable of being generated by a shift register having n stages is 2 - 1 bits. A shift register sequence generator is formed frcm a shift register ~ith certain of t`ne shift register stages fed back to other stages. The output bit stream has a length depending upon the number of stages of the regis~er and feedback employed, before tne sequence re~eats. A
shift register having five st~ges, for example, is capable of generating a 31 bit binary sequence (i.e. 2 - 1), as its max~mal length (ML) sequence. Shift register ML sequence ~enerators having a large num~er of stages generate ML sequences tnat repeat so infrequently that t`ne sequences aFpear to be random, acquirLng the attributes of noise, and are difficult detect. Direct sequen oe syst~ms are tnus sometimes called ~pseudo-noise" systems.
Properties of max~mal sequences are summarized in 9ec~ion 3.1 of Dixon and feedback connections for maximal code generators frcm

3 to 100 stages are listed in Table 3.5 of the Dixon text. For a 1023 bit code, corres~onding to a shift register having 10 stages

- 4 -with maximal length feedback, there are 512 ~l"s and Sll IlOns; the diference is 1. Whereas the relative ~ositions of "l"s and "O"s vary among ML code sequences, the number of "l~s and the num~er of "O"s in each maximal length sequence are constant for identical ML
length sequences.
Because the di~erence between the number of "l"s and the n~mber of "onS in any maximal length se~uence i5 unity, autocorrelation o~ a maximal linear code, which is a bit by bit ccmearison of the sequence with a phase shifted replica of itself, has a va;ue of -1, except at the 0 1 bit ~hase shift area, in which correlation varies linearly from -l to (2n - 1). A 1023 bit maximal code (2n - 1) therefore has a peak-to-average autocorrelation value of 1024, a range of 30~1 db.
It is this characteristic which makes direct sequence spread spectrum transmission useful in code division multiplexing.
Rec~ivers set to diferent shifts of a common ML code are synchronized only to transmitters having that shit of the common code. Thus, more than one signal can be unambiguously transmitted at the same frequency and at the same time. In an autocorrelation type multiplexed system, there is a common clock or timing source to which several transmitters and at least one recei~er are synchronized. The transmitters generate a common maximal length sequence with the code of each transmitter phase shited by at least one bit relative to the other codes. The receiver generate~
a local replica of the common transmitted maximal length sequence having a ccde sequence shift that corresponds to the shift of the particular transmitter to which the receiver is tuned. The locally generated sequence is autocorrelated wi~h th2 incoming signal by a correlation detector adjusted so as to recognize the level associated with only ~ l-bit synchronization to despread and extract infonmation from only the signal generated by the predetermined transmitter.
Because the autocor~elation characteristic of a maxim~l length code sequence has an offset correspondi~g to the inverse of the code length, or ~1/ (2n 1) 25~

where V is the magnitude of voltage correspondin~ to "1" and n is the number of shift register stages, overlap occurs in neighboring channels. Thus, there is imperfect rejection of unwan~ed incoming signals~ Unambiguous signal discrimination thus requires a guard band between channels reducing the number of potential txansmitters for a given code length. A long max~nal length sequence campensates for the guard band to increase the number of potential transmitters, but this slows syncnronization and creates power imbalance of the multiplexing transmitters.
10 / In such systems, synchronization of the receiver to the predetermined transmitter is performed in stages. First, there is static delay of receiver timing to compensate for fixed variations in synchroniæation timing between the receiver and tne predeterminecl transmitter. Static delay can be deternined bas~d upon the distance between the transmitter and receiver a~d the characteristics of the medium, e.g., transmission line, between them, or can be simply measured to synchroni~e the receiver and predetermined transmitter to be within plus or minus one code chip of eacn other (a code chip is defined as a bit Feriod of the pseudo-random code generator within the direct sequence spread spectrum system)~
Second, variable delays, which are ~nknc~n, are compensated within the receiver by a v æ iable, or dynamic, delay that is controlled in two steps, fine tuning and coarse tuning. Fine tuning of the receiver is limited to a range of plus or minus a por~ion of a cx~de chip from a predetermined point which may be at the last correct location of a message receive7~. Fine tuninc, causes the recei~er to lock onto a local peak when the signal is present. There are several di~ferent methods by which fine tuning is accomF,lishe~, such as through serial h~m ting, using a code preamble to reduce l w ~on time. Coarse tuning, operative after the receiver has ~een fine tuned at a local peak determines whether the local peak is the "correct" local peak for best corrPl ation, in c,ther wc,rds, whether the receiver and pr~determined tr~nsmitter are both locke7~ onto the sam~ system of clock signals. If the receiver and trans~itter are synchroniæed to different clock signals, the receiver will lock onto an improper correlation peak. During coarse tuning, the receiver tests correlations of the receiver timing with neighboring correlation peaks and selects the largest, based upon maximum signal-to-noise ratio.
In a communication system of this type, as well as of other types, it is desirable to optimize system perform-ance by maximizing signal-to-noise ratio and receiver-to-transmitter synchronization. Because multiple ~nels, each containing a sub-receiver with a correlation detector, exist in a system of the above described typa, i~formation is available that is not presently used. For example, the correlation properties of the code employed as a function of code chip delay differences between received and re~erence codes has a peak when synchronization is achieved with an absolute value dropping to "zero" as synchronization difference approaches a code chip or greatar. The sign of the pattern is dependent upon the data bit being used to modulate the transmitter. By monitoring the sign of the correlation output when the receiver is properly synchron-ized to the transmitter, it is possible to recover the transmitted data. With each sub-receiver tuned to a different correlation peak, data are present at each and are available to be processed to enhance the signal-to-nvise ratio of the receiver as well as to improve synchronization.
Disclosure of Invention It is accordingly a primary object of the inv~ntion to improve the signal-to-noise ratio in a code division multiplex receiver. Another ob~ect is to improve si~-to-noise and synchronization characteristics in a code divi~
sion multiplex receiver of a type having a plurality of correlation detectors times to successive code shift de-lays of a common pseudo-random code sequence, with outputs processed to determine optimum receiver synchronization.
These and other objects are satisfied by the method and system o~ the present inven-tion which is used to improve the ,~,. ..

~2~

signal-to-noise ratio in a direct sequence spread s~ectru~ system of the type where m a plurality of transmitters and at least one receiver are synchroniæed to a common timing signal source. Each transmitter transmits a data signal spread by a bipolar pseudo-random code which is a different assi~ned shit of a com~on bipolar code sequenc~ The receiver is formed oE a plurality of correlation detectors, each generating two local bipolar pseu~o-random codes that are replicas of the transmitted common bipolar pseudo-random code. One of the locally yenerated codes has the same code sequence shift as ~he code sequence shit assigned bo the predetermined transmitter, whereas the other locally generated code has a code sequence ~hit that is not assigned to any of the transmitters. The two locally generated codes are proces~ed in each correlation detector to obtain a trinary code sequence which i5 cross-correlated with th~ incoming signals to develop correlation signals that are aFplied to adiust receiver timing such that each correlation detector is located at a local correlation peak. In accordance with the invention, in addition to providing receiver synchronization, the outputs o~ the correlation detectors are processed to receive data and to o~timiæe signal-to-noise ratio. Recoqnizing thak the sign of each correlation Feak corresponds to the data si~n bein~ transmitted, when the recei~er is properly synchronized, the correlation outputs are processed using weighting factors selected according to the particular distortion present, to optimize signal-to-noise ratio.
Still other objects and advantages of the present invention will become readily aF~arent to those skilled in this art from ~he follawing detailed description, wherein there is shown and described only the preferred embodiment of the invention, simply by way o illustration of the best mcdes contem~lated of carrying out the invention. As ~ill be realized, the invention is caeabl~
of other and different embcdiments, and its several details are capable of modi~ica~ion in varlous, ob~ious resFects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as res~rictive.

~L2~ 4 Brief Description of the Drawings _ _ _ _ _ _ _ _ . _ _ _ _ _ _ Figure 1 is a simplified block diagram showing a DSSS code division multiplex receiver;
Figure 2 is a representation of a bipolar pseudo-random pulse sequence;
Figure 3 is a diagram showing an autocorrelation pattern for a bipolar pseudo-random pulse sequence of the type shown in Figure 2;
Figure 4 is a superposition of several autocorrela-tion patterns corresponding to neighboring -transmi-tters in a code division mul-tiplex system;
Figure 5 is a diagram corresponding -to Figure ~, with signals of neighboring transmi-tters separated by guard bands;
Figures 6(a)-6(d) are wave forms showing trinary code genera-tion;
Figure 7 is a simplified block diagram showing a receiver opera-ted in accordance with the principles of -the inven-tion;
Figure 8, on the second shee-t of drawings, is a diagram showing an idealized cross-correlation pattern between a locally developed trinary code sequence and an incoming binary code sec~uence in accordance with the i.nvention;
Figures 9(a)-9(c) are diagrams showing correla-tion patterns developed by multiple channel correla-tion detectors in accordance with various embodimen-ts of -the invention;
Figure 10, on the four-th sheet of drawings, illus-trates an actual correlation pattern obtained in the receiver of the present invention when operated in the presence o:E various degrading factors;

;Z54 _9_ 60398-11538 Figure 11 illustrates an analog embodiment of mul-tiple correlation detectors for determining the degree of cor-relation in accordance with the invention;
Figure 12 .is a circuit simpli~ication of the analog embodiment of Figure 11 using binary reference signals;
Figure 13 is a further circuit si.mplification of the analog circui-t of Figure 11, using digital logic to reduce the number of analog multiplexers;
Figures 14(a) and 14(b) illustrate two methods of implementing the circuit of Figure 13;
Figure 15 is a digital implementation of one channel of the circuit shown in Figure 11;
Figure 16 is an N-channel generalization of the cir-cuit implementation in Figure 15;
Figure 17, on the tenth sheet of drawings, shows another digital implementation of a single channel correla-tor of a type shown in Figure 11;
Figure 18 is an N-channel generalization of the circuit shown in Figure 17;
Figure 19 illustrates an in-phase and quadrature-phase correlation pattern, together with the locations of sub-rece~ver channels for correlation detection;
Figures 20(a) and 20(b) are flow charts showing -two alternative methods for performing fine tuning of the receiver;
Figure 21, on the seven-th sheet of drawings, illus-trates a microprocessor based circui-t for performing fine -tuning of the receiver and signal presence detection;
Figures 22(a) and 22tb) are flow charts respectively showing methods for correcting receiver timing and for per~orming signal presence detection and appear on -the fif-teenth and four-teenth sheets of drawings, respectively;

~r .

~2~6~59L
-9a- 60398-11538 Figure 23 is a Elow chart showing one technique for performing coarse tuning of the receiver;
Figures 24(a) - 24(e) are timing diagrams showing the relationship of timing pulses between a transmitter and a receiver;
Figure 25, on the ninth sheet of drawings, illus-tra-tes a circuit for locking a transmitter and receiver ~o the same timing pulse; and Figure 26 illustrates a microprocessor based circuit for performing data recovery in the receiver.
Bes-t Mode for Practicing the Invention General In spread spectrum communications, spreading of signal bandwidth beyond the bandwidth normally required for data being lZ46'~54 lish~d by first phase sh rrier wavefrm by data t sultant signal by a refer t a repetition ~ate whi d ta rate. Forms of mdUla mod late the carrier as ~el lthOu~h ~SR is preferred earlier -th signal transmission~ the m~ltiplied by the same ref used to 5pread the composite transmis5iOn~ and assumin9 tnat the llY generated receiVer C
i rsionS caused by the cod o~ea and the ie~ is reS~red in the re ill StrateS the spread SFeCtrum i er incO~o~atin9 on~ Fec i er lO0 receives a di i al transmitted by a pa f such transmitterS, and pro iminate the signal tranS~
a~ong the signals tra the 8 aring in mind that 1 ted twice~ that is~ the h compoSite is modUlated Y
ad the composite o~er a f ~ne pseudo~random sequ ideS twO sta9eS of dem~dU
the transmission data- Th dy ed or multi~lied by the Sig~al is 'oeing diScrim OtherS. ~huS~ aSSUmin9 t'e codeS generated a i~r are 5ynchronous~ the PSR ~Odulation at the t i~6~:5~

at multiplier 102, and the original base-band modulated caerier is resto~ed. ~he narrow-band restored carrier is a~plied to a band pass filter (not shown) designed t~o pass only the base-band modulated carrier. ~ase-band data are then extracted by heterodyning or multiplying the restored carrier by a locally generated carrier at multiplier 1.04. ~he output of multiplier 104 is aQp~ied to a co~ventional correlation filter 106, such as an integrate and dumQ circuit, follcwed by a sample and hold circuit 1 5ignalS corresponding to the t The receiver 100 is controlled by a standard microprocessor ~08, synchronized to a syste~ clock 110, to which the tran5mitters are also synchronized. secause noise and undesired transmissions are treated in the same process o~ multi~lication in multiplier 102 by the lccally generated reference code that comQresses the ~5 ~ecei~ed direct sequence signal into the ori9inale carrier i oming signa~ not sYnCh~nUS
generated reference code is s~real into a bandwidth equal to tne d idth of ~he inc~ming signal t~ne ~eerence code. Since this unsynchroni~ed input si~nal is maFQed into a bandwidtn that is at least as wide as the reference code, a band pa55 ilter can reject a signi~icant amount of the Fcwer of an undesired signal. This is the signiicance of a DSSS
system, synchronous in~ut signals at t'ne reference code modulated bandwidth are transforme~ to the base-band mod~lated h nous input signals re~ain p code-modulated bandWidth-i ~ion processing makes use of Ul code ~hat is employed at th autocorrelation of a maximal 1 gth (ML) sequence, that multiplication of the sequence by a time shifted replica o k when synchronization is ac that drops to -P /L, where P
d L is the cod~ length, as sy h time difference between th Z~4 replica app~oaches a code chip or greater). The sign of the autocorrelation pattern is dependent upon the data bit being used to modulate the transmitter. It is thus Fossible to reco~er the trans~itted data at the receiver by monitoring the sign of the autocorrelation output when the receiver and transmitter are properly synchronized.
Referring to Figure 2, a pseudo random code sequence of a type to which receiver 100 is tuned is bipolar, that is, it is assumRd to switch polarities of a constant voltage pcwer supQly.
In the invention, bipolar, rather than uniFolar, sequences are u3ed to improve Fcwer transmission efficiency, since ~he carrier is supprecsed in bipolar transmission. Bipolar transmission also a~oids high concentrations of energy in any frequency band to hel~
avoid interference between transmissions by different transmitters in the sys~em. Each bipolar sequence has a magnitude P and a chip duratlon Tc. The length of the ML sequence deeends upon the number of different transmitters whose signals are to be code-division multiplexed within the system. Each transmitte~ is assigned the sa~e transmission code havin~ a dif~erent specified chip o~ the common ML sequence. The ma~imum number of transmitters that are ca~able of bein~ multiplexed within this sy~tem thus corresponds to the length of the ~L sequenceO
~he number of transmitters that may be multiplexed without interference within a code-division multiplex system of this type i~ equ 1, theoretically, to the bit length of the sequence. For an ~L code ha~ing a length of 63 bits, for example, the transmission channel i5 theoretically ca~able of multiplexing 63 different transmitters. This assumes that synchronization is deemed to be achie~ed between the receiver and a ~reselected transmit~er when the autocorrelation between the code received ~rom the transmitter and the locally generated code~ both synchronized to a common t~ming source, is at a Feak~ In ~ractice, howe~er, the num~er of transmitters that can be code ltiplexed in the s~st~m i5 3 ZL~6~254 13 ~
because there is overlap due to the -P /~ term in of the ML sequence. This can be better aFpreciated with ~eference i h shoWS a correlatin curv d Figure 4 which sh~Ws a n curves for neighboring transmissionsl that is~ for ~ransmissions i f~5~t rom each other by a 9 the correlation curve haS
smitted and locallY generate off5et from each other by greater than a code chip Tc, where P
gnit~de of the sequenCe a Wh n the tranSmitted and local Y 9 h izatiOn~ that is, are ~ithi h ther the correlation inCre a peak of p2 at perfect synchronization- Thus, synchroniz~tion i er and a single tran5mitte ~onitoring the correlation output and deemin9 synchronization to the correlation si9nal is po5itive value~
Re~rring now, howe~er, to Figure ~, assume thath ~he~e are d code sequences k, k-l and k i gle code chiP- ~ach crre ~eak value of p2 and a negative peak value of _p /~, as in elation curves of neighbo g t~ regionS shoWn by crosa h I thSe regionS, neighb in9 co~e se~uences have c king it impSsible to a practiCal mattert to av i ionS it is nece55arY to between s~o~n in Fi9Ure 5- ThiS
i ionS to sequence shiftS c hiP delaYgt ra~her than to ~he reSULt is that, at be issions, compared to the

5~

n~ ber- can be mult~ exed- In practice~ even fewer than one~'nalf the theoretical maxim~ tran5mitters are capa~}e of being mu~.tiplex~d in a code di~7ision multiplex syst~ usirlg bips:~l r Seque~ce5 beca~l5p a guard band ~hat is greater than that p~Vided nate code shift delays i synchronization ambi~uities aspect o~ the inv~ntion, ~
trai~ itters tnat are caQable of being ~ltiple:ced is inc~eased to tneoretical limit by cross c lOtrina~y code develo~ed by ob ce assigned to the partic recpiver is tuned ~d a edIn other words, two bipo ceiver one Qf ~e codeS i 15ce transmitted by all the if . ~ ha~ cs~rreSponds to the of the :rarlsmitters. rrh 'Ch common bi.eolar se~uence igned to any of the tranSm 20ed codeS is subtracted frcm tr inarY code geq~enCe ~ i 15 T~e S~quence shift b ght to within one ~ode erate.~ by the preSeleC ~ anSmitte~, using a st hl: nizati~n techniqUe to below. P rfeCt 5ynch~Onization betw~en the recei~ler a~ preseleC~ted tranSmitter dynamic synchronization ~ al btain~d gener ally by succ ~ver by a fraction of a co rr~latOr. ~hen the cr~el and preSe1~cted tranSmitte ch o~her. ~ssuming naw t lso syr,chronized to Co~
itt r is n~t synchronized to hrOniz~d to ano~:he~ ~ Ch P
~cput is monitored to extrac ~ ~6'~S~

~evelcement of the trinary pulse sequen oe to be cross-correlated with the transmitted sequences is bet~er understood with reference to Figures 6(a)-6(d). In Figure 6(a), a transmitted bipolar sequence s(t) having an absolute magnitude P
and chip period ~c is shown. This sequence is a simplification o~ an actual sequence which, ~n practice, would be substantially longer, e.g., 63 bits. Within th~ receiver is develoFed a first reference pulse sequen oe r(t) shown in Figure 6(b). The se~uence r(t) is identical to the sequence s(t) transmitted by the predetermined transmitter shown in Figure 6(a), becaus2 the transmitter and receiver sequences have the same delay and are presumed s~chronized to each otherO
Ihe receiver generates a second referen~e pulse sequence e(t), shown in Figure 6(c), which is the sa~e sequence as the one transmitted by the preselected tran5mitter as well as by all the other transmitb~rs but has a sequence delay that is not assigned to any of ~he transmitters.
The difference Ir(t) - e(t)~ between the two locally generated reference pulse sequences is obtained, to provide the trinary pulse sequence shown in Figure 6(d). The ~rinary sequence has a value {~2, 0, -21, depending upon the relati~e binary ~alues of the two reference pulse seq~ences r(~) and e(t).
It is to be understool that the sequence length in the example shcwn in Figure 6 is 7 bits, ~lthough in practice, much ~5 longer sequences would be aFplied to accommodate a relatively large number of transmitters to be code division mLd.tiplexed.
Referring to Figure 7, development of the trinary reference sequence to be cross-correlated with incom m ~ bi~olar pulse sequences for signal dehultiplexing is ~rovided in a receiver 200. The recei~er 200 receives the transmitted pulse sequences s(t) and a~plies ~he inco~in~ sequences to the inputs of a irst correlation multi~lier 202 and a second correlation multiplier 204. ~he first correlation multiplier 202 multiplies the incoming s2quences s(t~ by the locally generated reference pulse sequence ~z~%~

~ 16 -r (t) having a s ~ ence shift corresponding ~o the sequence shift o~ ~he pre;elected transmi~ter~ ~he multiplier 204 ~ltiplies the incoming sequences s(t) by ~he pulse sequence e(t) having an unassigned pulse sequence shift. The resultant multiplication p~:oducts are applied to a difference circuit 206, and the dif~erence is integrated and sampled in a standard correlation filter 208 to dev~lop an ou~put signal YOut~
It is pointed out tha~ in Figuxe 7, the input sequences s(t) lti~lied respectively by the sequences r (t) and e(t), and then th~ product dif~erenCe 15 obtained in dif~erence circuit 206. This is equivalent to obtaining the difference between the two reference pulse seque~ces r(t) and e(t) and then multiplying the difference by the inComm9 sequences s(t).
~ cross-correlation is shown that each correlation cu n e has a value 0 when the preselected transmission and locally qenerated reerence sequence r(t)-e(t) ed ro~ each other by more th contras~s with the cross-correlation curve of Fi~ure 3, wherei~
ti e residual correlation h 9 P~/L. ~he magnitude of the correlatio~ curve increases ~inearly f p(~ when the presel~ct d re~erence pulse sequences a The advantage of this correlation stsategy is appreciated by 9a shcwing the correlati smlssins in accordance wi articular, Fi9- 9a shcWS ~ode ~er it will be a~reciated ~an be displa~ed from each shift and that there is no overlap bet~een the correlations of i ionS whereas in Figure 4, cross-hatched por~ions~ The in~ention thus enables ~he number of able of being multiplexed to be q than the length of the pulse sequence in bits, a ~esult that i~

- ~7 -no~ possible us mg prior art ~ys~ms. Even if a guard band is plaoe d between transmissions in the strategy shawn in Figure 9a, the number of trans~issions that can be reliably multiplexed is substantially ~reater than the number that can ~e reliably mwltiplexed using the correlation strategy shown in Figure 4.
~ ssume ~ha~ the code-divi~ion multiplexed PSR signal Y(t) incoming at the receiver is expressed as oll~ws:
Y(t) ~ ~ PjdjXj(t)cos(Wct + O) + ~(t) (1) ~--1 where for J incoming transmissions:
O C t ~ T, where T is a code chip period;
P. is the pcwer within each incom m g bipolar pulse sequence;
d~ is the polarity o~ sign of each corres~ondin~ incoming se~uence Xj(t) is the tran ~ tted data;
W is the fre~uency of the carrier in radians;
O is the carrie~ phase; and ~(t) is nois~.
The out~ut ~(T) o~ the conve~tional r~ei~er, using a f ence code sequence, is d~fin V~(~) S ~d~ Pjdj +
j~r where:
Pr is the power of the desired incoming sequence;
dr is the data sign of the desired se~Uenc~;
L is the puls~ sequence length in bits;
P. is the power o~ each of the undesired sequen~es;
~ s~Ondin9 data sign of the un N is noise.
~ ) of tne receiver operating With the principles of the i~ention is defined as follows:
Prdr (1 ~ ) + NB

1;~4~5~

Becaus2 the correlation method of the invention involves a subtr~ction of a code sequence ha~ mg an unassigned code sequence shift, aIl undesired trans~ission components ( identif ied by the subscript "rn) in the output VB(T) are FerfeC~ly ~ejected~
whereas in the prior art receiver, the out~ut ~A(T) involves contributions of the undesired transmissions (ha~ing the subscri~t ) as ~ell as the desired tran5missions (subscript ~rn).
Multiplexer trinary signal correlation induces an additional three decibels of degradation in data signal-to-noise de~cdulation wi~h res~ct to white noise aFpearing at the receiver input, c~mpared to con~entional correlation using only the particular transmission binary pulse sequ~n oe . Thus, =~=
(4) ~ = 2(1~1/L) ~ -ing stsategy discussed above r unwanted access ~ejection caFability using ML codes of any length in a code-division multiplex syste~. In the past, only ML code~
1 long length were potential y number of allowable multiplexers being much less than the code length. Even there, power imbalances of the m~ltip~exing transmitters occurred.
~dditionally, the ide~l cros5 correlation ~attern in Fi9. 9a lends itselC to multiplexing schemes using m~e than ~he theoretical limit of code, each ti~e-offset by less than a code Chip, and assuming a re complex receiver configura,ion. For exam~le, it has been discovered that the number of tran~mitters which could be multiplexed can be increased to 2 x (L-2) ~hannels by adding a code between each of the code sequences sho~n in Fig-4, wi~h onlY a slight trade off in oVerall reCeiver signal-to-noise Ferformance. ~s shown in Fig. 9b an additional code can be inserted between each of the codes shown in Fig- 4-The codes are detected at a plurality of taes pro~ided at the tputs of ~he various receiver p 9b are as follow5:

~ ~6~

q~
. extLa code 2. 1/2 extra code 3~ null 4. 1/2 code 1 code 1 ~ 1/2 code 1

6, 1/2 ccde 1 + code 1' + 1/2 code 2 1. 1/2 code 1' ~ code 2 ~ 1/2 code 2' equatiOnS maY then ~e solved o channel 1 5 2 x ta~ 4 channel 1' = ~ x (tap 5 channel 1) 1 2 ~ 2 x ~taP 7 - channel 1 2 X (ta~ 7 - channel 2 - ~ap 5) ,.
~, "
channel L' = 2 x ta~(2L ~ 3) tice the abo~e arrangemen som~what 1 ent due to both noise an Y
alt rnati~e ~m~lementation would equ 2 occurred at ~he ~oint whe enveloFe is equal to 1/2 t~e max~mum. In such an ar~angement, ~he i s for the out~u~s of the tapS

~
eX~ra cde 2. null 3. null 4. null 5. code 1 60 code 1' , code 2 t allo~s for fUll data r ~e~ i~ maY still be some noise.

~%~

_ 20 -c~ the boYe problems, ~ in which two or more c groupedd sepaI:ated b~ gUard~ban Sel?aratiOn of the grou~S or the pa~:tern~ com?riSin9 the groUPs is inde~der~t of thiS ar~aT~e~ ~is ae~roaCh als alloWs t~e -ouping of trarlsmitters similar charact .mplifies syr~chroniza ion probl dUlation by data b~ar g neceSsary ~ro~ d co~ icatin betW ~ .ctorS arld in ~rated in ~e abVe desC
i i n req!lir~d is that ~y addit ~ Ch necesSary timing o~ the s t ining receiver m~tiplexing se 5ynchronization - G2ner~
~d o~ eselected tranSmit Ch o~cher before data can b ar~d tran5mitter are sync (if ~che co~nercial po~der in i i~ cas~ be obtained frcm i tion is a ma~ter o adapt 9 t ~?ropagation delays of ~h i nal a~ld to dela~!s i~here~t 5~e o these delay5 are ~sta~ delay~ to ~Yn~hr ed transmit:ter to within one a chiÇ? is def ined as code ge}~eratr-eneral., static delaY can sated dur ing initial ~ h recei~er, sirlce n~St sta occu~ 5 ha~e~e~, when th ieh che transmitter and ~o a c~e and wherein co i bLdirec~ional- StatiC d Y

~2~:Z5~ .

- 2~ -fron two refer~nce points/ one ~here the transmitter is at the timing source and the other where the receiver i~ at the timing source.
With the transmitter Located at the timing source ~nd the S receiver lw ated elsewhere, the timing signal and ~ransmitted signal will propagate at aFprox~mately ~he same speed from the transmitter to the receiver~ Other tining variations betwe~n the transmitter and receiver are due to delays induced within the transmitter aNd receiver circuitry, and can be preset to synchronize the transmitter and receiver to within one code chi~
of each otherO All receivers remote frcm the t~ming source can thus have identical static dela~s.
If the receiver is l~cated at the timing source and the transmitter is located elsewhere, however, each receiver may require a static delay that is unique for each re~ote transmitter to account for dif~e~ent signal propagation dist~nces. Thus, to enable a receiver to recei~e signals from a multiplicity of transmitters, the static delay of the receiver must be variable.
In practice, the static delay between each transmitter and the 2G receiver is measured upon installation of the transmitter; that static delay value for aIl future com~unications with a paLticular transmitter is preset within the receiver. ~henever a transmission is received from that transmitter, to obtain united synchronization of the transmitter, receiver timing is 2~ aut~atically adjuste~ to acccmm~date the delay associated with the pasticular transmitter.
In one embodiment of the invention, there are a plurality of~
transmitter/receiver units disposed in a so-called "master/slave'~
arrangement. In this arrangement, one transmitter/receiver unitt called ~he master station, acts as the source of ti~ mg signals for the other stations (slave units). The amount of delay associated with the timi!ng si~nals between the master station and each of the slave stations includes such thin~s as the filter delay for ~he timing signal source at -the master station, the ~Z~ 54 ~ 22 -received filter delay a~ the master station, the signal propagation delay between the master and a particular slave, the coupling delay at the m2ster station and the transmit filter delay at the master s~ation. Rnowledge of these various del3ys will S give an estimate of the amount of static delay associated between the master station and a particular slave station. Hawever, some variation Ln each delay will occur with changes in the transmission line associated with temperature changes, transmission frequency, etc~
Wh;le dynamic delay adjustnents can take care of most of these changes Ln the static delay characteristics between the master and slave units, the m~ltiplexing capabilities of ~he system may be s~mewhat reluced because the receiver at a particular master or slave unit must be capable o tracking delay variations over a range of several code chips~ This r~quires a guard band that is wide enough to allow the si~nals oE two adjacent receivers to vary in time over their associat~d bands with~ut interference.
~cwever, it has been discovered that the amount of reguired guard band may be reduced ~y periodically measuringr at the master station, the static delays associated with signal transmission betwe~n the naster station and each of the slave stations and t'nen peri~dically adjusting the transmitter signal tLming at the slave in order to bring the static delay back into a desired range.
- This allows more slave stations to tr~nsmit at one time since the guard band required for delay variations can ~e greatly reduced thus allowing more usable code delays for multiolexing~
Variations from synchronization established by ~he static delay are comFensated by a dynamic delay mechanism within each receiver. Ihe dynamic delay consists of two stages: fine tuning and coars~ tuning. Whereas static delay timing causes the receiver and predetermined transmitter to be synchronized to each other to within one code chip~ fine tuning uses correlation detection to make fine adjustments in receives timing as a ~%~s~

func~ion of received transmission, rather than as a function of an expected transmission (s~atic delay).
After fine ~uning has est~blished that receiver t~ming is at a loc 1 correlation peak, it becomes necessary to determine if the ; loc~l peak to which the receiver is timed is the "correct" ~ocal peak for best correlation. ~his is necessaxy because, depending upon the correlation properties of the code selected, as well as other factors, there are likely to be multiple correlation peaks, with the primary local peaks havLng the greatest peak magnitude.
These multiple peaks arise fr~m carrler correlation within the ~l~c code correlation peak. Finally, it must be determined which of the system timing pulses present in each data bit is ~he proper one for synchronization. Without such a determination, a condition can exist wherein the transmitter is locked to one timing pulse while the receiver is locked to another timing pulse. This is because these are two timing pulses in a data period and incorrect timing causes a quadrature condition between transmitter and receiver data periods. Thus, the net energy for such quadrature d~ta periods is zero. Even with the receiver and transmitter properly synchronized to each other, data cannot be extracted from the ~eceived sequence because it is not possible to detect and decode the data transmission unless the receiver and transmitter are loc~ed to the same timing pulses. Fine tuning and coarse tuning as well as synchronization to the pro~er timing pulse within each data bit shall now be described in ~ore detail.
Figure 10 illustrates the correlation pattern obtained by cross-correlating an incoming, bi-polar pulse sequen oe together with its carrier and the locally generated trina~y reference sequence. The correlation pattern has a ma~or peak at receiver timing Vl and has minor correlation peaks at recei~er timings V2, V3, ~6 and V1, ref2rred to hereinafter as "channels". The correlation peak a~ priDary channel Vl depends ueon the correlation proeerties of the code selected as a function of code chip time delay difference between the incoming code sequence and ~2~5~

the reference code sequence. The correlation is at a peak when synchronization between the receiver and transmitter is achieved, with the absolute value of the correlation dropping to zero as the synchronization difference aFproaches a code chip or greater. It-s should be noted that, due to imperfect correlation properties of the code and due to the influence on correlation by the sinu~oidal carrier, the correlation shown in Figure 10 is approximately sinusoidal as cam~ared to the piece-wise linear, ideal correlation profile shown in Figure 9a which does not in~lude a carrier. m is is the reason that coarse tunin~ is required; fine ~uning adjusts receiver timing until a correlation peak is determined; coarse tunin~ the~ determines whether the correlation peak is the major correlation peak as~ociated with cha~nel Vl or is a minor correlation peak associated with channels V2, V3, V6 or V7, or others.
In accordan oe with one aspect o~ the invention, synchronization of the receiver is achie~ed by providing a plurality of separate sub-receivexs or correlation detectors that are tuned to each receiver channel. Assu~ing that each of ~he channels Vl, ~2, V3, ~6 and V1 are spaced apart from each othe~ in time by one third of a code chip, fine tuning adjusts thQ receiver timing such that ~he channels are all located at local Feaks.
Furthe~more, as~uming that channel Vl is within a code chip of being syn~hroni~ed, the channel Vl is within one 5ix~h of a code chip of a lccal peak. The outputs of the correlation detectors are aeplie~ ~o a micrc~rocessor 314, described below, to de~elop a receiver timing signal for synchronization to the transmitter and to ex~rac~ ~ransmission data. Various embodiments of the multiple correlation detectors are illustrated in Figures ll-18.
Correlatlon Cetection One em~odiment of the multiple channel correlation detector shown in Figure 11 is generalized for N correlation channels. The multiple channel correlation circuit identified generally by 300 ccmprises for ea~h channel a correlator 302 each ccmprising a first multiplier 304, a second multiplier 306 and a difference circuit 308. The first multiplier 304 has one input ~hat receives the incoming sequences s(t) and a second input that receives the first locally generated reference s~quence r(t) having a sequence shift that corresFonds to the sequence shift of a predeterm m ed transmitter. The multiplier 306 has one input that receives incoming sequ~nces s(t) and a second input that receives the second reference sequen~e e(t) havLng an unassigned sequence shift. The outputs of the two multipliers 304 and 306 re~resenting, respec~ively, the products of the incoming sequences and the t~o locally generated reference sequences are applied to the inputs of difference circuit 308. The difference ou~ut is applied to an integrate and dump type filter 310, matched to the period of a bit at the chip rate, to develop a si~nal V~ for t v~ = S s(t)lr(tN) - e(tN)]dt ~5) wherein ~ and s(t) are analog signals while r~ ~) and e( ~) are binary signalsO The output of the integrate and dump circuit 310 is ap~lied to a sample and hold circuit 312 which monitors and stores the magnitude and polarity of the integrator out~ut V~.
qhis value if aFQli~d to a conventional microprocessor 314 tha~ in 2~ response to outputs from all ~ of the detectors 302 extracts the binary data from t'ne predet~rmined transmission and develops a timing error signal to retain the ~eceiver locked in synchronism with the predetermined tLansmitter, as discussed in more detail belo~.
The analog multiple channel correlation detector shown in Fi.~ure 11 requires a substantial number of calibration adjustments associated with the multipliers 3~4, 306, the difference circuits 308, the integrate and dump circuits 310 and the sample and hold circuits 31~. ~n practice, an 8-channel ~etector of ~his type requires aFproximately 80 calibration adjus~ments.

~.'h'~ 5~

If only ~he polarity of the reference seq~ences r(t) and e(t) is used, considerable simQlification of the system results, with only a slight degradation in perorm~nce. Because the ~wo reference sequences are bina~y (bi-polar) signals, mNltiplication can be achieved in an ~ channel correlator using Z~ two-input analog multiplexers and one in~erter, shown in Figure 12. In this implementation, the binary ~eference signal determines whether the input signal s(t) or an inverted input signal 5 (~) is selected to be aeplied to subtraction circuit 308. Bearing in min~ that the desired output of each of the ~ difference circuits 308 is s(t~)[r(~) - e( ~)1, each channel in the correlation detector 400 shown in Figure 12 comprises a first tWo-i~Qut multiplexer ~02 and a second two- m~ut multiplex~r 404 controlled, respectivel.y, by the instantaneous polarities of the first and second bi-polar reference sequences r(t~) and e(t~ . One input of each of ~he t~o multiplexe~s 40~, 404 is connected to a first line 405 that receives the incoming sequences s(t) a~d a second input connect~d to a line 408. The line 4~8 receives the inconing sequen~es s(t) in~erted in polarity by an in~erter 4l0.
~he multi~lexers 402 and 404 are dri~en by the reference sequences r(~) and e~t~) through dri~ers 412 and 414.
Assuming tnat the polarities of r(t~) and e(~) are identic~1, both o~ the multiple~ers 402 and 404 ase connected to the li~e 406. The input sequence s~t) i5 thus aFQlied to both the positive and negative input terminals of the difference circuit 308 whe~eby a zero signal is a~pLied to integrate and dm~ circuit 310 (Fig. ~l). If r( ~) is positive and e(tN) is negative, multiplexer 402 is connecte~ to line 406 and multiplexer 404 is connect~d to line 408. ~he sequence s(t) is thus aFQlied to the positive input of di~ference circuit 308 and the inverted sequence s (t) is applied to l:he negative input terminal of circuit 308; the se~ ce 2s (t~ is thus aE~plied to ~ntegrate and du~ circuit 310 .
If, on the other hand, the relative pol2ritie5 of the two refOEence sequences are reversed, the ~equence s (t) i5 aeplied to 5~

, the negative input of difference circuit 308 and the inverted input s ~ en oe s(t) is applied to ~he Eositive inFut of difference ci~cuit 308. The signal -2s(t) i5 thus a~plied bo integrate and dump circuit 310, thereby satisfying the equation VN(t) = s(~) k (~) - e(t~)]-The circuit of Figure 12 is adva~tageous over the circuit of Fi~ure 11 because analog multiplier calibration adjus~ments are not required in Figure 12, although the inverter 410 requires two (balanoe and offset) calibration adjustments. The number of adjusbments requi ed for an eight-channel detector is thus reduc~d from aFproximately 80 to 34.
Referring to Figure 13, a further sim~liication of ~he circuit shown in Figure 11 can be achie.ved by r~cognizing th~t the input to each integrate and d~np circuit 310 is che difference between ~wo signals, each of which is t~e input s~quenc~ s(t) multiplied by a +l sr a -1, with the output being zero when the two reference SeqUellCeS a~e equal to each other. In ~ccordance with Figure 13, the 2N multipliers and the ~ subtractors are replaced, in circuit $00~ by N three-input analog multiplexers 502. One i~put of each of the multiplexers Sû2 1s connected to a line 504 which receives the input sequence s(t). A s~cond input of multiplexer 502 is connected to a line 506 ~hich receives an inversion 5 (t) of the input se~uence, inverted by 508. The third input of multiplexer S02 is connected to a Line 51U ~hat in turn is connected to ground.
The first reference sequence r(tn) is connected directly to the control input of multiplexer 502 through an inverter/driver 512. Also connected to th control in~ut of multiplexer 502 is an exclusive-CR circuit 514 having inputs connect~d respectlvely to the two referen oe sequences r(tn) and e(t~).
When the two reference sequences are equal to each other, the output of the exclusi~e-CR circuit 514 drives the multiplexer to line 510, causing the output of multi~lexer 502 to generate a zero signal to integrate/dump circuit 310 (Fig. ll). If the first ~ ~6Z5~

referen oe r(tn) equals 1, the out~ut v(t) of multiplexer 502 equals ~(t)o If r(t) equals 0, on the other hand, the multiplexer out~ut v(t) equals -s(t). The outeut of the difference circuit thus generates the signal s(tn)~r(tn) - e(tn)l and the S integrate and dump output for each channel is S s~t)[r(tn) - e(tn))dt, Y requirffd. (5) Two circuits for ~mplementing the three-in~ut analog multiplexer 502 of Fi9ure 13 are shown respecti~ely in Figures 14a and 14b~ In Figure 14a, each of the two two-input multiplexers 600, 602 have the following characteristics:
Y~ = xO~ when ~ = O;
x = xl, when A = 1.
i5 ~he first re~erence sequence r(t) is oonnected to control terminal A of multiplexer 600 and to one input of an exclusive-OR circuit 604. The se~ond reference sequence e(t) is connected to a second input of exclusive-CR circuit 604. The output of the exclusi~e-OR
604 is connecte~ to .the control terminal A of mul~iplexer 602.
The incoming sequences stt) are connected to one input ter~inal xl of multiplexer 600, and, through an in~erter 606, to the second input x0 or the same multiplexer. The out~ut x of multiplexer 600 is ap~lied to one input xl of multiplexer 602;
the second input x0 of m~ltiplexer 602 is connected to ground.
The output v~t~ of the multiplexer shown in Figure 14a is defined ~y ~he follawing truth table, which corresponds to the required equation v(t) = s(t)lr(tn) - e(tn)I.
~LE III
r(t) e(t) r ~3 e 0 1 1 -s(t) 1 0 1 5(t) O

In the e~bodiment of ~he ~hree-input multiplexer 606 shown in Figure 14b, the output x is connected selectively to any one of the four in~uts xO, xl, x2, x3, deFending upon the binary values of control in~uts A, B. m e input sequences s(t) are connected directly to input x2 and through an inverter ~08 to input xl~ Inputs xO and x3 are connected to ground. The two reference sequences e(t) and r(t) ~re connected resFectively to control inputs A and B of multiplexer 606.
The oFeration of ~ultiplexer 606 is described by the truth table set forth above wi~h resFect to FiguLe 14a and also orovides the desired out~ut v(t).
The correlation detector embodiments of Figures 11-14 are based upon the analog technique of integratin~ a continuous signal~ The number of calibration adjusbments required can ke reduced further by replacin~ an~log integration in the correlation detec~or by discrete signal summation. Referring to Fiyure 15, correlation detector 700, provided in each channel of the receiver, digitizes the incoming se~uences s(t3 and al~e~raically 5ums the digit1zed sign~l in an accumulator over a period o~ t~me equal to a bit period. The difference between the initial and fin~l values in the accum~lator represents the value of s(t) integrated over a bit period. Accumulation is controlled by the ~alues of the reerence se~uences r(t) and e(t3. ~hen the two reference sequences are equal~ the accumulated value is unchanged. When r(t) and e(t~ ase unequal, the accumulation is incremented or decremented by the ~alue of s(t) de~ending upon the value of r(t).
Correlation det~ctor 700 comprises an analog-to-digital converter 702 that receives the analog sequence s~t) and in response generates a corresFonding digital signal at output ter~inal D. The out~ut of analo9^to-di9it~l converter 102 is aFplied to one input A of an adder/subtracter circuit 704 having an out~ut applied to the in~ut of an accumulator register 706.
The output of the accumulator 706 is applied ~o output register 708 and also to the second input B of adder/subtracter 704.

~.æ~ 5~

Opesation of ~he units 702-708 as well as of a sequencer 710 are synchronized to a bit period T. Sequencer 710 in turn controls the conversion times of ~/D converter 702 and the accumulation times of accumulator register 706 at outputs 712 and 714, respectively. The accumulator register 706 is also controlled by the values of the two ~efrence seguences r(t) and e(t) thsough exclusive-CR gate 716 and ~D gate 718.
The adder/subtracter 704 develops an output signal which is the sum of the digitized input sequence s(t) and the contents of ac~umulator re~ister 706 when reference sequence r(t) is 1 and generates the dif~erence between the accumulator reyis~er contents and the digitized ~alue of input sequence s(t) when reference sequence r(t) is zero. Selective addition and subtraction of the t~o s~gnals aFplied at adder/subtracter inputs A, B are controlled by the signal aFplied at input F, de~eloped by reEeren oe sequence r(t) through ~n inYerter 7200 If r(t) equals e(t), the exclusive-OR gate 716 develops a logic O signal that is aFplied to one input of ~D gate 718. To the output input of WND gate 718 is a write-accumulation signal de~eloped by se~uencer 710. Sequencer 710 alternately de~elo~s a "convert input" signal aFQlied to A/D converte~ 702 to provide an analog-todigital conversion o input sequence s(t) and a "write acc~mulat~r~ signal which ad~s or subtracts the instan~aneous value o s~t) to the current accumulated value, to be applied to output register 108 and then to micro~rocessor 314 (Figure 11) which develops binary output and timing error signals.
Thus, the content of the accumulator register 706 remains unchanged when r(t) equals e(t) under control of an exclusive-OR
gate 716. When r(t) equals a logic 1, the content of accumulator register 706 is incremented by the ~alue of the incoming se~uence s(t); when r(t) equals a logic O, on the other hand, the content of the accumulator register is decremented by ~he value of the in~ut sequence s(t). This has the eLfect of ~ultielying s(t) by ~1 or -1 and integrating.

~L6;2S4 , - 31 ~

The cQrrelation detector 700 of Figure 15 is generalized into an N-channel ~orrelation det~c~or 800 in Figure 16. The reference sequen oe s r(tn) and e(tn) are applied to an input latch 802 havLng r(tn) and e(tn) outputs that are applied respectively to a pair of N to 1 mNltiplexers 804, 806. The GUtpUt5 of the two multiplexers 804, 806 in turn are aFplied to the inputs of exclusive-CR gate 808 that controls accumulator memDry 810 throu~h ~ND gate 812.
Accumulator memo~y 810 in Figure 16 corresponds to accumulator register 706 in Figure 15. ~lemory 810, however, contains a plurali~y of mYmory regions corresFonding to each channel and addressed by a channel sequencer 814 controlled by ~he output of sequencer 816. Similarly, the ou~put o accumulator memcry 810 is applied to an output memory 818 that corresponds to output register 7~8 in Figure 15. Memory 818, however, contains a plurality of memory regions corresponding to the correlation channels and addressed by the out~ut of sequencer 816.
The inc~ming sequence s~t) is sampled by a sample and hold circuit 820 and applied to analog-to-digital con~erter 822 wherein the incoming analog s~quence s(t) is digitized and applied to adder/subtracter 824 in a manner described with resFect to Figure 15.
In ope~ation, sample and hold circuit 820 sam~les the incoming analog sequence s(t) and converts the samples to corresFonding digital ~alues in synchronism with the bit period T
de~eloped by micrcerccessor 314 (Figure 11) and a~pli~d to sequencer 816. The content of the accumulator memory 810, within each mem~ry region addressed by sequencer 816 is increm~nted or decremented by the curr~nt ~alue of s(t), depending upon the value of the reference se~uence r(t) at the corresponding channel~ The circuit 800 thus succe~sively samples the input seq~ence, multiplies the sequence by ~1 or -1 and integrates for each channel N, under control of channel sequencer al4 and sequencer 816, as well as of the microprocessor 314. The accumulator memory 1~625~ , _ 32 -810 and output m2mory ~18 thus monitor N accumulation channels, with time synchronism of signals during channel sequencing being preserved by the samQle and hold circuit a20 and the i~put latch 8~
Referring now t~ Figure 17, another digital implemen~ation of a single channel correlation detector 900 ccm~rises a conYentional voltase-to-frequency conYerter 902 that receives the absolute vallle of input sequence s(t) through an absolube value circuit 904. Absolute value circuit 904 is required beca~se the volta~e-to-~re~uency converter 902 responds, as is conventional, to a uni~olar input signal. Voltage-to frequency con~erter 902 converts the instantaneous ma~nitude of the inccming sequen~ s(t) bo a single corresFonding frequency signal to be aFplled to an up/down counter 906 through one in~ut of an ~D gate 908.
The input sequence s(t) is also aFQlied to an analog ccmparator 908 which kee~s track of the Folarity of the input sequence s(t). In other words, the output of the analog ccmearator 908 is representative of the sign of the input sequence slt). The reference sequences r(t) and e(t) are a~plied to the r~maining input of gate 908 through e~clusive-CR gate 910.
~he up/down counter 906 is controlled by a second exclusi~e~CR gate 912 that receives the output of the analog compara~or 90~ and the Eirs~ reference seguence r(t). Thus, the up/do~n c~unter is c.on ~olled to increment when the signs of the input ~equence s(t) and reerence sequence r (t) are the same;
otherwise the counter i5 caused to decrement. ~he outpu~ of counter 9û6 is apQlied to a latch 914 synchronized to bit period T.
qhe clock Cl~ of up/down col~nter 906 is disabled by exclusive CR gate 910 when the two reference sequences r(t) and ~(t) are equal to ea~h othe~. Otherwise, th~ co~nter clock is enabl2d and the counter 906 track~ ~he incom m g sequence s(t)O In other wvrds, when r(t) is ~, the counter counts up for a ~ositi~e polarity sequence bit s~t) and counts down fot a nega~ive polarity sequence bit s(t). When the reerence sequence r(t) is a logic 1%~Z54 zero, on the other hand, accumulation is subtracted and the count direction is reversed.
The circuit 900 cf Figur 17 is generalized to ~ channels of correlation detection by circuit 1000 in Figure 18. In circuit 1000, voltage to-frequency converter 1002, absolute value circuit 1004 a~d analog comearator 1006 correspond to corresponding components in Figure 17 and are ccmmon to all channels. Up/down counter 1008 as well a~s ~ND gate 1010 and exclusive-CR gates 1012 and 1014, however, are duplicated for each channel. The output of each binary up/down counter 1008 is aF~lied to a latch 1016~
commonly synchronized to a bi~ Feriod To The ou~uts of the N
latches are applied to microprocessor 314 (such as shown in Fig~
11) which processes the indl~idual channel correlation signals and in response develops binary data recovered frcm the predetermined transmitter and timing ~ignals to shift receiver timin~ into synchronism with the predetermined transnitter.

Dynamic Synchronization ~s discussed abo~e, static synchronization in~olves establishLng predetermined delays in the receiver that correspond to different pro~a~ation times asscciated with different transmitt~rs. Static delays, preset in the receiver dur mg initial set-u~, synchronize the transmitter and receiver to within one code chip of each other. Per~ect correlation is then established by microprocessor 314 in response to the correlation signals de~eloped by the correlation detectors described a~ove.
~icroprocessor 314 more specifically pr x esses the channel correlation signals to control recei~er timing to synchronize to the predetermined transmitter in two stages; namely, fine and coarse tuning, followed b~ synchroni~ation correction, if necessary, to the proper pulses o~ the system clock.
Referring again ~a Figure 10, it is recalled that code correlation is a function of code chip time delay differences between a recei~ed code and a ref rence code and, depending upon 1~6,'~5'~ , the particular correlation properties of the code employed, has a peak when synchsonization is achieved and has an absolute value that drops to æero as the synchronization difference approaches a code chip or greater. Data are recovered from the correlation pattern, based uQon the re~ognition that the sign of the ~attern deFends upon the data bit used to ~cdulate the transmitter. Thus, when the receiver and a predetermined transmitter are pro~erly syn~hronized bo each other, trans~i~ted data are recovered by monitoring the sign of ~he voltage Yl at the primary correlation channel.

Fin~ Tuning ~Qferr~ng to Figure 19, a correlation pattern corresFonding to the correlation pattern shown in Figure 10 is identified by 1100. This is an n in-phase" correlation pattern, with coarse corre~tion channels Vl, V~, V3, V6 and V7 that are used to determine which of the correlati4n peaks corresponds to the primary channe~, with ~ax~mwm correlation at synchronlzation~ An ~dditional pair of channels V4, VS are fine, or vernier, correction channels, which maintain receiver synchronization by maximizing the corr elation output of the primary channel Vl. In the foregoing discussion, it shOUla be recognized that all referen oe s to fraction of a code chip are related to the ratio be~ween the carrier frequency and code generation frequencies. ~s one example, the carrier ~re~uency is 5670 ~z, and the code generation frequency is at 3870 bits/second, so that references to fractions of a code chip are related by a ratio of 3/2, allowing three peaks per code chip. The additional correlation curve 1200 in Figure 19 i5 a quadrature-~hase correlation curve ~hat is dis~laced frcm ~he in-phase correlation curve by 90 degrees~ The significan oe of the quadrature phase correlation cur~e is that ~he value of the quadrature~phase curve is at zero when the value of the in-phase quadrature curve is at a maxlmum. ~s shall be discussed belGw, signal processing, and particularly correlation p ak detection, is simplified using quadrature-phase correlation.

g~ S4 - 3~ -Because there are three correlation peaks per code chip, assuming that the primary correlation channel Vl is within a code chip of keing properly synchronized~ the primary channel Vl is within one-sixth of a code chip of a "local" peak. Fine tuning S causes the receiver to adjust its tining, under control of microprocessor 314, such that the correlation channels Vl, V2, V3, V6 and V7, spaced a~art from each other by one-third of a code chip, are all located at local peaks. One method of adjusting receiver timing to locate the five correlation channels to local peaks is by serial hunting shown in the ~low chart given m Figure 20(a). ~lis involves use of a preamble of a length 2~p~ s), where s is the number of smoothings on each bit and p is equal to on~-sixth (in this example) of a code chip period divided b~ the receiver correlation resolution, or ~he number of correlations of minimum resalution required to adjust the receiver from a synchronization null to a peak.
For each data bit in the preamble, the recei~er primary correlation channel Vl timing is adjusted by a minimum ~raction V 6(p) of a code chip (step 1320) and the magnitude of the correlation voltage Vl is stored ~1330). This process is repeated un~il the receiver has chanqed its timing over a maximum o a full one-third of a cod~ chip (1340). ThereaftQr, th~ point at which the magnitude of the primary correlation Vl is at a maximum is selected as being the local peak (13S0), and the timing of the recei~er is adjusted to position channel Vl at that poi~t (1350)~
An alternative fine tuning method controlled by microprocessor 314 is the use of fine tuning channels V4 and V5 shown in Figure 19. The fine tuning channels V4 and V~, provided by an additional pair of correlation detectors (not shcwn), are offset in time from the primary correlation channel ~1 by an equal fraction of a code chip that is less than one-six~h of a code chip. Optionalltl, a pre~mble may be included in the method, having a worst case length of p o 5 with a minimum receiver correction (resolution) being l/6(p) of a code chip. Referring to ~ z~.G~5 Figure 20 (b), the correlation voltages V4 and V5 are applied to micr~processor 314 (step 1950) along with the correlation voltage of the primary channel Vl. ~y comparLng the relative ~agnitudes of V4 and V5 (steps 1960, 197n), th~ microprccessor determanes the direction toward which receiver ~iming is to be shifted (steps 1980, 1990) to position the primary channel Vl at the major local correlation peak. A syst~ o~ this type is shc~n schematically in Figure 21. Programming of microproces~or 314 is omitted for brevity, but is considered routine to impl~ment 'oased upon the s~mplified flow chart of Figure 20~b) and ~he discussion herein.
Another aLternative fine tuning method involves the use of a channel whose timing is generated with a quadrature-phase carrier. Recognizing fr~m Figure 19 that the nulls of ~he quadrature-phase correlation pattern 1200 occur at the peaks of in-phase correlation patt~rn 1100, an error volta~e may be developed by microproces~or 314 based u~on the sign of the product of the in-phase and quadLature-phase patterns. The sign of the error voltage thus indicates a direction to which receiver timing must ~e shifted to cause the receiver correlation channels to 2U synchronize to local correlatio~ peaks. It is also possible to apply the magnitud~s of the i~-phase and quadrature-phase correlation voltages lmo and 1200 to determin~ not only the direction of shift of receiver timi~g to achieve synchronization but also the amount of shift required to obtain a local peak.
Thus, in accordance wi~h another aspect of the invention and as summarized in the flow chart of Figure 22 (a), ~he in-phase Vl and quadrature~phase Vlq correlation voltages are measured (step 2050). The ratio of the in-phase Vl and quadrature-phase Vlq correlation voltages is calculate (2060), and if the ratio is positive (2080), the two ~orrelations are presu~ed to have the same polarity and receiver ~imin~ delay is increased (2095);
otherwise, the two correlations are presu~ed to have opposite polarities and receiver tim mg delay is decreased (2090). To prevent receiver ~ming from being changed if ~he receiver is ~'~4~2S~

perfectly synchronized to the predetermined transmitter, and to avoid complications caused ~ delay in the receiver whereby a correction decision is made using information that is m~re than one data bi~ old, the absolute value of the ratio Vl/Vlq, which-is essentia11y a cotangent function, is m~nito ed. A table stored in a memory associated with microprocessor 312 relates th~ ratio Vl/Vlq to the num~er of fin~ tunLng corrections, e.g., l/4~th o~ a code chip or each correeticn, to reach optimal synchronization.
The table is set forth below.

Number of Correction (Equal fra~tions of a C~de Chi~_ ~o 1 5.02 2 2.41 3 1.49 4 1.00 0.668 6 0.4149

7 0.1999

8 0 Thus, the number o corrections applied to receiver tLming i5 determined dire ~ y frcm Vl~Vlq, and ~here is a correc~ion dead band when the ratio is greater than S.02, el ~inating receiver hunting about optLmum synchronization. Furthermore, the number of data bits needed to move ~he receiver from a correction null to a correlation peak is reduced from 8 ~in this example) to as low as 1, minimi2ing the length of any required preamble and providing accelerated serial hunting. Finally, i~ is possible to i~hibit tracking corrections on consecutive data bits without decreasing the tracking rate of the receiver, thereby eliminating overshoot.

.X~25 Signal Presence Detection The provision of quadrature-phase ~lq as well as in phase Vl correlation voltages fur~hermore m~kes it possible ~o determ me a - signal present within a background of noise. As summarized in the program flow chart of Figure 22(b), when only noise is present at the receiver input, both the in-phase Vl and quadrature-phase Vlq voltages will haYe a~proximatel~ the same value K, such that the ratio Vl/Vlq will be olose to unity. With bath signal and noise preSent~ how~ver, fine tuning maximizes Vl and minimizes Vlq to obtain a ratia mu~h greater than unity. The ratio Vl/Vl~ is thus used as an indication of signal present. In practice, the ratio may be monitored over a number of d ta bits, with smoothing techniques or majority voting being aFplied to ensure ~ccuracy.
Circuitry for detecting presence of a signal in a bac~ground ~5 of noise is shown in Figure 21, with microprocessor 314 developing signals Vl and Vlq in response to the outputs of the correlation detectors discussed above. The signals Yl, Vlq are processed with the microprocessor 314 to develop the ratio Vl/Vlq and the ab~olute 0 value ~l~Vlq of the resultant is magnitude com~ared with a predetermined threshold magnitude to determine whether an incoming signal represents a data transmission or wnether it is merely noise.
Following determination that the receiver is tuned to a local peak using Eine ~uning as described above, it beccmes necessary ~o determine through coarse tuning, whe~her the current local ~eak is the "correct" local peak such that the receiver has best correlation.

Coarse Tuning In accordance with one embodiment, coarse ~uning of th~
receiver to a predetenmin0d transmitter to ensure that the receiver is tuned to the maxinum, and other ~han a secondary, correlation peak involves serial hunting wherein, having once Eixed a point as a local peak, the receiver is adjusted in ~6~

multiples of one~third of a c~de chip to measure the magnitude of the receive si~nal a~ each adjacent local Feak~ Once ~he magnitudes of the peaks are determined, a decision as to the proper peak is made. Because the magnitudes of ~djacent peaks near the center of the orrel~.tion pat~ern are difficult to distinguish fron one another due ~o channel filter distortion, a convention~l "center-of~mass" approach may be used to identify the maximum local peak by basing ~he decision on the relative values of all channels rather than on only a selection of ~he channel having tha greatest correlation magnitude.
The micro~roce~sor 314 is programmed in a coarse tuning, serial hunt mode to cause the receiver, foLlowing identification of a lacal peak, to shift in timing by multiples of one-third of a code chip, measure and store correlation magnitude~ and make ccmFarisons using the cente~ of mass approach or other approach to identi~y the corre~t correlation peak. Serial hunting requires a transmission preamble of length W ~ s where W is the width of the peak search range (in thirds of a code chip) and s is the number of bits of smcothing in the voltage readings.
In Figure 23, a simplified flow chart of programming of microprocessor 314 ~o provide coarse ~uning by serial hunting includes a test at step 1200 to determine, using ine tuning as discussed a~ove, whether the receiver is at a local peak. If the receiver is not at a local peak, the receiver is fine tuned until ~he receiver is determin2d to be at a local peak~ The receiver, once at a local peak, is incremented (step 1202) until its timing is at R + N, wherein R is the timing of the local peak obtained during fine tuning and N is a predetermlned number of thirds of a code chip. Ihe correlation value of K ~ N is measured and stored (st~p 12~4), and the receiver timing is decremented by one-third of a code chip (step 1206). The correlation of the receiver and predetermined transmitter is ncw measured and stored ~step 1208), and receiver timing is tested to deter~ine whether it is at (~ - N), that is, at the opposi~ side of the initially detected lZ~S~

local peak R (step 1210). If not, the receiver timing is again decremented and the correlation is measured and stored.
Otherwise, all the stored correlations are tested (step 1212) to identify a peak correlation.
In acGordance with another embodiment, to reduce the preamble length, m~ltiple secondary re~eiv~r channels, offset frcm each other by multiples of one-third of a code chip on both sides of the primary channel Vl develcp prim~ry and secondary correlation signals to be applied to microprocessor 314. The mLicroproc~ssor 314 is programmed, uslng center of mass an~lysis or other an lysis, bo identify the primary channel Vl which has the greatest maxim~m correlation and the secondary channels. ~y usin~
a multiple number of recelver channels or correlation detectors, ra~her than serial hun~ing circuitry or programming, the length of the preamble ceguired for coarse corrections may be reduced to ~he number of bits of sm~o~hing, s. This assumes of course that for the desired wid~h of search, a channel exists with common offsets of multiples of one-third of a code chip on both sides of the pri~sry correlation channel Vlo With multi~le receivers it is not necessary to program the microprocessor to seriall~ hunt. The microprocessor 314 is instead progr2mmed to simply compare the out2uts of the correlation detectors, all tuned to a local peak, to identify the pe~k havin~ the greatest magnitude.
Timing sign 1 Correction If the data bit rate of the tran~mission is less than one-half the pulse repetition rate of the timing source, the transmitter and recei~er may beccme lock~d to different timing pulses even though they appear to be perfectly synchroniz~d to each other. ~or ex~mple, for a data bit rate of 30 bits per second, a timiny pulse source of 60 HZ and a carrier fr~quency located between 60 Hz harmonics, the transmitter may become locked to a first 60 Hz timing pulse with the receiver locked to the next ~LZ4G254 successive 60 ~z timing pulse. An alternating data transmission will not be detected due to ~mproper receiver data timin~ re overy with otherwise perfect $ynchxonization between the receiver and transmitter.
To illustrate this condition more clearly, Figure 24(a) is a diagram representing the timin~ pulses to which the receiver and a predetermined transmitter are synchroni~.ed. The tran~itter carrier is shown in Figure 24(b~ and transmitted data representing alternate ones and zeros are shown in Figure 24(b). Assuming that the receiver and transmitter are synchronized to the same t~mLng pulsesl the integrate and dump circuits 310 o~ the receiver will be synchronized to the transmitted data inversions so as to dump at the trailing edge of each datum, as shown in Figure 24~d), where "dots" designate integration dump points. The sampled integrator output is thus a replica o~ the da~a embedded within the transmission.
If the transmitter and receiver are not synchronized to the same ~iming pulses, however, the integrate and dump circuits 310 will not be properly synchronized to the data being transmitted.
This condition is shown is Figure 24 (5), where ~he integration dump points occur between transmission data inversions, and the sampled output of the integrator 310 is at ze~o.
In other words, wlth the receiver and transmitter respectively synchronized to successive~ rather than the sa~e, timing pulses, it i5 impo~sibLe to recover any of the transmission data. It is therefore necessary to test the receiver and transmitter to ensure that the two units are synchronized to the S~l~t rather than successive, timing pulses.
In accordance with one asFect of th~ invention, asscciated with the primary receive~ channel Vl is a secondary receiver channel Vl' having a built-in additional delay of one-half a data bit. One of the two channels Vl and Vl' will always therefore detect the transmitted signal~ A determination is made by aF~lying an alternating data preamble associated with the ~ ~ ~gj~5 tsansmission to the primary and secondary receiver channels~ By comparing the magnitudes of the correlation outputs of ~he two reGeiver channels, the correct channel (having the larger correlation magnitude) is the one synchronized to the same timi-ng pulse as ~he transmitter is. Data are monitored at the ncorrect"
channel only~
A simplified circuit for synchronizing receiver timing to cause the receiver and transmitter to be locked to the same timing pulses as shcwn in Figure 25. Microprocessor 314 develops a secondary channel Vl' offset from channel Vl by one-half of a data bi~. In response to an incaming sequence hav mg an alternating preamble, the microprocessor ccmpares the magnitudes of the data outputs frcm the channel Vl and its half bit dela~ed channel Vl', and identifies the one channel having the larger magnitude. mis channel is thus presumed to be the one which is locked to the same timing pulses as the transmitter is, and is reaFplied to the microprocessor for data recovery.
In an alternative e~bodiment of the invention, the need for the secondary receiver channel Vl' may be eliminated. The transmitter and receiver can be synchronized when ~he timing referen oe frequency is less than or equal to the data sampling rate and the ra-tio of the da~a sampling rate to the tim m~
reference frequency is an integer by combining more than one of the consecutive data samples together to yield one data point or bit. By combininy these data samples, an optimum data sample point may be determined whi1e recei~ing an alternating sign oreamble by ccmparing the magnitudes of all possible su~mations and selecting the sa~ple which give a maximun output. If each sample is assigned to its own synchroni2ation point, then synchronization may be acco~plished by locking to the time that gives the max1mum output~
For example, if the timing signal has a frequency of 60 ~ertz and a data sampling rate of 30 samples per second, for a data rate of 30 bits per second each data sample is used to yield one data ~%~6~4 point or bit. For data rates of lS, 7.5 or 3.75 bits per second two~ four and eight consecutive data samples are used to yield one data bit. In addition to eliminating the need for a redundant data channel, the a~ove technique eliminates the need for the data samplLng rate to be the same as the data rate. In fact, sampling may occur at a rate higher than the data rate~ This allows the data samples to be c~nbined digitally, for example m a microprocessor, and allows the data rate to be independent of the actual hardware timing.
Data Recovery Data recovery in s~read spectrum systems is well known. As background, reference is made to section 5.3 of the Dixon text mentioned earlier, and particularly to the discussion of Costas loop demodula~ors beginning on page 155.
Because the spread spectrum system as provided herein includes multiple corrPiation channels, data recovery is improved in accordance with one aspect of the mvention by extractin~ data at each channel rather than at only a single correlation channel.
It is thereby possible to lcwer system message error rate and possibly to also reduce the length of or eliminate any re~uired preambles for receiver synchronizationl With reference again to Figure 19, it is noted that the correlation pattern 1000 is centered a~out the primary correlation channel Vl. ~he sign of the primary correlation channel Vl is dependent upon the siyn of the da~a being transmitted. A positive value of Vl thus corresponds to a logic 1 being transmitted whereas a negative value of the correlation Vl corresponds to a logic 0 being transmitted.
The correlations at V2, V3, V6 and V7 also have values tha~
correspond to the sign of the data being transmitted, Specifically, the relationship of the voltage outputs at channels Vl, V2, V3, V6 and V7, in ~he absence of noise and distortion, are descri~ed as follcws:

5~

V2 = V~ - Rl~ Vl V6 - V7 - R2 ~ Vl where (7) Rl - -2/3 ` R2 = l/3 In accordance with the inVentiQn, the data sign at the output of each correlation detector, following proper receiver synchronization, is monitored. Depending upon the characteristics of noise and distortion, data may be extracted using only the outputs at channels Vl, V2 and V3, with an efective signal-to-noise ratio gain of (l+l/L)-( ~ u;~Kj)2 (8) (l+l/L)~ ~ uj 2 + 2~(Rl+l/L) uL~(u2+u3) + 2~(R21-l/L)~u2~u3 j-l where Rj = relative noise free amplitude of Vj with respect to Vl, j a 2, 3 (Kj = Rl in the distortion free case), L - the length of the pseudo-random code and u; - ~eighting façtor for Vj, j = 1, 2, 3. m e weighting factors are s~lected according to the particular distortion present.
Figure 26 is a simplified circuit dla~ram showing microprocessor 314 responsive to channels Vl, V2 and V3 and programmed to combine all ~hree correlation channel outpu~s to extract tran$mission data, with weightin~ factors select~d according to particular distortion known to ~e present on the transmission medium. Table V illustrates the signaL-to-noise enhancements under a few possible distortion and weighting factor scenarios~

~2~6~54 V

~ 5~ .
SWEIGHTI~G F~CTORS FoR V~ DISIOR$ICN F~CTORS FQR Vj IMPRS~$3NT
Ul U2 u3 kl k~ k3 F~CTOR
_ ~ , 1 -1 -1 1 -1 -1 1.44 ____ __~
1 -1 -1 1 -0.9 -0.9 1.254 . _ _ _ . _ ~
1 -1 -1 1 -0.8 ~8 1.082 _ _ _ __ _ __ 1 -1 -1 1 -0.7 -0.7 0.922 . , . _ _ . .... ._ _ _ _~
1 -9.3~ 0.34 1 -0.67 -0067 0.971 _ . . _ . _ 1 -0~67 -0~67 1 -0~67 -3~67 ~o91~3 _ . . _ . ~ _~
1 -0.9 -0~6 1 -O.g -0.6 1~055 . _ . _ , _ - , _ ~
1 -0.~ -0.8 1 -0.~ -0.8 1.09 _ _. _ . _ . , . __~
1 -O.g -0.9 1 -0.9 -0~9 1.252 . _ _ _ _ _ _ _ .
An ~ditional advantage of providing a recovery on all channels of the r~ceiver is ~hat random and burst errors, which tend to affect all channels, can be identified and ignored. This is similar to signal presence detection using in-phase and guadrature-phase correiation outputs, as discussed ~bvve, but employs all channels rather than orthogonal outputs associated with a single channel.
Furthermore, as an additional advan~age of obtaining data re~ove~y at all correlation channels or at least several correlation channels, it is possible to monitor synchronization durin~ message reception. Although synchronization adj?l~tments are not feasible during message reception, the message content may be r~covered, without repeats, using the additional receiver channels.
In this disclosure~ ~here is shown and described only the preferred embodiments of the invention, however, it is to be ~Z~6~54 -- ~6 -~dersl:ood that the irlvention is ca~able of use in var ious other combinat:ions and environments and is capable of changes or modif icatior~s with~n the scope of the inventive concept as expressed herein.

Claims (3)

WHAT IS CLAIMED IS:

1. A direct sequence spread spectrum code division multiplex system, including a plurality of transmitters synchronized to a common timing signal and each transmitting a data signal spread by a bipolar psuedo-random code which is a different assigned shift of a common bipolar sequence, characterized by:
a receiver synchronized to said timing signal for receiving said transmitted signal spread by a bipolar pseudo-random code having a predetermined assigned code sequence shift, said receiver including a plurality of correlation detectors and means for applying to each of the correlation detectors (1) a first reference bipolar pseudo-random sequence that is a replica of the common bipolar psuedo-random sequence and has a code shift that is within one code chip of the assigned shift of a predetermined transmitter and is displaced from the common bipolar pseudo-random code sequence applied to the other correlation detectors by a fraction of a code chip less than unity, and (2) a second reference bipolar psuedo-random sequence that is a replica of the transmitted common bipolar pseudo-random sequence and has an unassigned code sequence shift, each of said correlation detectors including first means for obtaining the product of the transmitted sequence and the first reference bipolar pseudo random sequence;
second means for obtaining the product of the transmitted sequences and the second reference bipolar pseudo-random sequence and third means for obtaining a difference between the products obtained by the first and second means; synchronous integrator means for integrating the difference; means for synchronously sampling an output of the integrator means and signal processor means responsive to outputs of said correlation detectors to synchronize said receiver to said predetermined transmitter;
means responsive to the output of each of the correlation detectors for recovering data transmitted by said preselected transmitter.

2. The receiver of Claim 1 characterized in that said data recovering means includes means for restoring weighting factors depending upon a particular form of distortion present and means for applying said weighting factors to amplify the respective outputs of said sub-receivers, to optimize signal-to-noise ratio.

3. In a direct sequence spread spectrum code division multiplex system, including a plurality of transmitters synchronized to a common timing signal and each transmitting a data signal spread by a bipolar psuedo-random code which is a different assigned shift of a common bipolar sequence and a receiver synchronized to said timing signal for receiving said transmitted signal spread by a bipolar pseudo-random code having a predetermined assigned code sequence shift, said receiver including a plurality of correlation detectors and means for applying to each of the correlation detectors (1) a first reference bipolar pseudo-random sequence that is a replica of the common bipolar pseudo-random sequence and has a code shift that is within one code chip of the assigned shift of a predetermined transmitter and is displaced from the common bipolar pseudo random code sequence applied to the other correlation detectors by a fraction of a code chip less than unity, and (2) a second reference bipolar pseudo-random sequence that is a replica of the transmitted common bipolar pseudo-random sequence and has an unassigned code sequence shift, each of said correlation detectors including first means for obtaining the product of the transmitted sequences and the first reference bipolar pseudo-random sequence; second means for obtaining the product of the transmitted sequences and the second reference bipolar pseudo-random sequence and third means for obtaining a difference between the products obtained by the first and second means;
synchronous integrator means for integrating the difference; means for synchronously sampling an output of the integrator means and signal processor means responsive to outputs of said correlation detectors to synchronize said receiver to said predetermined transmitter;
the improvement comprising:
a method of improving signal-to-noise ratio comprising the steps of storing weighting factors corresponding to the output of each of said correlation detectors and selected depending upon the particular form of distortion present; amplifying the outputs from said correlation detectors as functions of said weighting factors; and combining said amplified outputs.