CA1246199A - Method for controlling a multistage space switching network - Google Patents
Method for controlling a multistage space switching networkInfo
- Publication number
- CA1246199A CA1246199A CA000492537A CA492537A CA1246199A CA 1246199 A CA1246199 A CA 1246199A CA 000492537 A CA000492537 A CA 000492537A CA 492537 A CA492537 A CA 492537A CA 1246199 A CA1246199 A CA 1246199A
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- Canada
- Prior art keywords
- controlling
- network
- switching
- matrix
- signal
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/52—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements
- H04Q3/521—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements using semiconductors in the switching stages
Abstract
A METHOD FOR CONTROLLING A MULTISTAGE SPACE SWITCHING NETWORK
ABSTRACT OF THE INVENTION
This invention is a cost efficient method for controlling a multistage space switching network for high voltage applications. This method minimizes the number of control signal leads required to operate a multistage space switching network.
If a switching network has N space switching stages, then the present invention provides for performing the space switching function with N+1 control signal leads. The present space switching method may also be employed for conventional non-high voltage space switching applications.
ABSTRACT OF THE INVENTION
This invention is a cost efficient method for controlling a multistage space switching network for high voltage applications. This method minimizes the number of control signal leads required to operate a multistage space switching network.
If a switching network has N space switching stages, then the present invention provides for performing the space switching function with N+1 control signal leads. The present space switching method may also be employed for conventional non-high voltage space switching applications.
Description
~2~
A METHOD FOR CCWTROLLING A MWLTISTAGE SPA OE SWITCHING NETWORK
BA~KGROUND OF q~E INVENTICN
me present invention pertains to an electrcmechanical space switching network and more particularly to an arrangement for mu m mizing the number of control leads required to operate a multistage network.
Mcdern switching syste~ls typically incorporate ful]y electronic time and space s~itching networks in their design and imple~entation. Examples of such switching systems include the GTD-5 ~X manufactured by GTE Communication Systems Corporation and No. 5 ESS manu~actured by Western Electric.
All switching systems require a network, which is capable of switching relatively high voltages for such functions as subscriber line ringing and coin control functions. mese networks are auxiliary networks and not part of the voice or data switching path. These auxiliary networks are line or service circuit concentrator networks. With currently existing technology, use of fully electronic networks to switch high voltages is costly and, therefore, of little use in mDdern s~itching systems.
Conventional electromechanical switch mg net~ork ccmp~nents and techm ques are not always compatible with these modRrn ~switching systems designs. Furthermore, these conventional electromechanical ~witching networks require a number of control leads in order to operate the network. Any reduction in the number of control Ieads results in more efficien-t packaging of printed circuit boards. Also, network control is ~ade simpler by the reduction of control signals.
SUMM~RY OF q~E INVENTION
In a space switching network, a method for controlling a multistage netw~rk first selects an idle path from a number of pa~hs through the switching matrices of the space switching netw~rk. Next, a number of netw~rk parameters are formulated.
These parameters correspond to the idle path which has been select0d for transmission through each switching matrix.
~6~
Then, these switehing parameters are group0d into two sets. These tw~ sets correspond to the selected idle path. These sets of parameters are stored in registers and transmitted to the switehing matrices at the appropriate time.
~lorizontal and vertieal control sic;nals are generated from these sets of parameters. Certain of these horizontal and vertical controls are shared between switching matriees, sueh that, a vertical control signal of one matrix is also a horizontal ; eontrol signal in the n~xt switehing matrix. Lastly, latching means in each switching matrix, which are eonnected to the corresponding vertical and horizontal control signals via corresponding leads, are sinultaneously operated to establish a physical signal path from an inlet of the first switehing matrix ko an outlet of the last switching matrix. This path is the idle path which was previously selected.
A BRIEF DESCRI CN OF THE DRAWINGS
Figure 1 is a schematic diagram of a crosspoint ; configuration utilized in the switching network embodying the present inventionO
Figure 2 is a schematie diagram showing the implementatic~n of a multiple stage switching network of the present invention.
Figure 3 is a block diagram of the control portion for the switching network embodying the present invention.
DESCæIPTICN OF THE PREFERRED EMBCDIMEMT
Referring to Figure 1, a crosspoint eonnection for a space switching network is shcwn~ As diagrammatieally pietured, two elements are provided at the interseetion of eaeh horizontal line and eaeh vertieal lille of a space switching network. The first element is a crosspoint switehin~ element Xr which when aetivated establishes a signal path between a particular horizontal signal lead and a particular vertical signal lead. The erosspoint switehing ele~ent X may comprise ferreed, rela~ device or other metallie contact device. These eleetromeehanical ~2~
crosspoints are used to switch high voltage signals such as, subscxiber line ringing or coin control ~unctions. ~nis network configuration may also be applied to voice or data net~rks. For a voice or data network application, the signal switching element or electr~nechanical crosspoint would be replaced with an electronic crosspoint. This electronic crosspoint would sufficiently ha-ndle the relatively low voltages associated with voice and data txansmission.
The second element req~lired to complete a signal switching path is the control memory M. me control m~mory el~nent M operates in response to two control signals, a horizontal control lead and a vertical control lead. In response to the simultaneous occurrence of both the vextical anc~ horizontal control lead signalsr the control memory elernent M produces the switching element control signal, which is transmitted to the signal switching element X. merefore, in order to complete a connection through a stage of space ~switchirlg matrix, a vertical and a horiz~ntal control lead signal is supplied to the appropriate control m~rnory element M in order to activate its corresponding signal switching ele~ent X to establish a path between a corresponding horizontal signal lead and a vertical signal lead.
The signal switching element X may co~prise a an electromechanical crosspoint, such as, a mlniature single winding DIP (dual in-line packagel relay or a ~erreed type.
Referring to Figure 2, a four stage space switching network is shown. The switching matrices ~ through D are represented by the intersection of horizontal and vertical lines.
A four stage space swithing network is shown, although, the present invention would be applicable to a space switching network with any number of switching stages.
Each space switching rnatrix requires two signals in order to select a path thxough the n~trix. Ihese two signals are a horiæontal control signal and a vertical control signal. In a conventional space switching network, control signals are usually independently generated for each matrix stage. Therefore, a four ~stage network as shown in Figure 2 would require eight control sign~ls, a vertical control signal and a horizontal control signal for each of the four stages. In the present invention, N
switching matrices may be opera~ced with N plus 1 control signals.
Eor example, the four stage switching network, shown in Figure 2, may be o~erated with five control signals.
For drawing simplicity only one matrix of each matrix stage is shown. In an actual network configuration, each stage would include several switching matrices. For example, the A
matrix shcwn would be connected to several other B matrices (not shown~; in addition to the connection to the particular B matrix shown in Figure 2. '~his is true for each matrix stage. These interconnections between the matrix stages are called links and the interconnection pattern is called the fabric of the netw~rk.
Each intersection of the network matrix horizontals and verticals ccmprises a network switching element as shown in Figure 1. The signal switching element for this configwration is a crosspoint. 'me control memory element in the con-figuration in Figure 1 is a D-type latch, as shown in Figure 2.
To establish a connection through the space switching network shown in Figure 2, a path must be established frcm an A
Horizontal through the A, B, C and D matrices to a D ver'cical lead. In order to establish the sample network connection shown in Figure 2 in dark solid and dashed lines, an active data signal is provided to the hB and CD leads; ~hile, a clock signal is applied to the A horizontal, BC and D vertical leads. The A
horizontal signal, which is a clock signal, is connected to the A
matrix as a horiz~ntal control signal. The AB signal, which is a data signal, is connected to the A matrix as a vertical control signal and is c~nnected to the B matrix as a horizontal control signal (shown in the heavy dashed lines of Figure 2).
The switching element at the intersection of the A
hori20ntal signal (shown in the heavy solid line) of matrix A with the AB lead wi]l be operated and a signal path will be established ~z~
from the horizontal input to the A matrix (shc~n in heavy solid line) through the AB vertical signaling lead to the B matrix (shcwn in heavy dashed lines). The configuration of the D-type latch for the A matrix and C matrix is shown in lower left portion of the sketches of these matrices. me connection of the D~t~pe latches ~or the B and D matrices is shown in the lower right portion of Figure 2.
In the A matrix, the veltical data control signal, shown in dashed lines, is connected to the D input of the latch;
and, the horizontal clock control signal is connected to the clock input of the latch. When these two control signals are active, the crosspoint associated with the latch is closed and connects a signal path through the A matrix.
Coincident with the operation of the A matrix, the AB
(data) signal, which is also the horizontal control signal of the B matrix, operates along with the BC (clock) signal, which is a vertical control signal of the B matrix, to switch a patll through the B matrix. As a result, the D-type latch at the intersection of these two control signals is enabled and operates its corresponding B matrix crosspoint. The crosspoint establishes the connection from the A matrix through the B matrix via the dashed heavs7 line and the heavy solid line shown as the BC signal to the C matrLx. The hea~7y solid and dashed lines in~icate both the control signals and the signal leads, as previously shcwn in Figure 1.
Simultaneously with the connection of the A matrix and B matrix, a connection is made from the B matrix to the C matrix.
The ~C signal, which was used as a vertical control signal for the B matrix, is applied to the C matrix as a horizontal control signal ~shown in heavy solid line)~ The CD signal (shown in heavy dotted line) is the vertical control signal for selection in the C
matrix. The D-type latch at the intersection of the BC and CD
signals is as shown in the lcwer left portion of Figure 2. The CD
signal is connected to the D input of the latch. When this latch is activated, the corresponding crosspo~nt to which it is ~2~
connected is operated to establish the path shown through the C
matrix.
Simultaneously with the estciblishment of paths through the A, B and C matrices, the final path through the D matrix is established. The CD signal which was applied as a vertlcal control signal to the C matrix, is applied as a horizontal control signal to the D matri~ (shown in heavy dotted line~. The vertical control signal for the D matrix is the D vertical signal shown in solid dark line The latch at the intersection of these two signals in the D matrix ls as shown in the lcwer right portion of Figure 2. The D vertical signal is connected to the clock input of the associated latch; and, the CD sigrkal is connected as the data input of the latch. When an active signal is present on the CD and D vertical leads, the latch is operated and its associated crosspoint produces a path fr~n the C matrix along the CD
horizontal to the D vertical and out of the D matrix. As a result, a path is established through the A, B, C and D matrices.
When an activ~ signal or logic 1 is present on the data lead of the D-type latch, together wnth the application of the clock signal, the latch is operated to store the active signal.
As a result, the crosspoint is operated and remains operated ~or as long as the latch remains set. Each of latches may all simultaneously be reset hy applying inactive or logic 0 signal in the presence of the appropriate clock pulses.
me AB signal is a vertical control signal in the A
matrix and a horizontal control signal in the B matrix. The AB
signal is the data signal appIied to the data input of each D-t~pe latch along a particular vertical of the A matrix. Each successive space switching ~atrix will alternate the use of a clock signal to fulfill the roll of a vertical control signal in one matrix and a horizontal control signal in the next adjacent matrix. For example, the BC signal performs these functions for the B and C matrices respectively. The shared signal for C and D
matrices will be a data signal, the CD signal. Addition of subsequent matrices to this configuration w wld be accomplished by alternately sharing data and clock signals as shcwn in Figure 2.
Referring to Figure 3, the control logic which produces the required data and clock control signals is shown. Processor 10, ~hich may be implemented with the microprocessor, is connected to network terminal and link map 20. Network terminal c~nd link map 20 indicates whether particular network links are busy or idle. mis indication is accomplished by setting a particular bit or resetting a particular bit corresponding to each network link.
In addition, processor 10 also includes other local memory for storing the processor's operating program.
The processor scans the network terminal c~nd link map 20 for a combination of idle network links with which to connect a path through the network matrices. When a particular network path has been selected by the processor 10, each bit which indicates the busy/idle status of a particular link is marked busy, set to logic 1.
Processor 10 i5 ~urther connected to I/O port 40, which transmits control data. The I/O poxts 30 ~ld 40 are connected to ; the parameter registers 50. Each of the parameter registers 51 through 56 is connected to both I/O p~rt 30 and I/O port 40. One parameter register is required for each category of network fabric parame~ers.
Each parameter register i5 a multiple bit register.
The size of each parameter register is determined by the number of variables wi~hin a given parameter type. The width or size of the A horizontal parameter register 51 is Nl. This corresponds to the number of inlets per A matrix. Each of the A matrices in the switching network has the same number of inlets. A ~atrix parameter register 52 is wide enough to contain the number of A
matrices in the switching network, N2. Similarly, B matrix 53, C
matr~x 54 and D matrix 55 parameter registers are of sufficient size to indicate the numker of , C and D matrices, N3, N4 and N5 respectively. In addition, D vertical parameter register 56 is of sufficient to contain the nu~ber of outlets per D matrix, N6.
In order to establish a particular path through the network, processor 10 selects an idle path by scanning network terminal and link map 20. ~hen an idle Fath is ~ound, processor 10 transmits the identity of each inlet ~nd outlet via I/O port 30 to the respective parameter registers 51 thro~gh 56. A bit is set in each parameter register 51 through 56 corresponding to the particular path which is selected.
In order to derive the horizontal and vertical control signals shown in Figure 2, the outputs of the parameter registers 50 are gated through clock signal gates 60 and data signk~l gates 80. Paraneter registers 51 and 52 are connected to a number of AND gates represented by AND gate 61. In order to derive control signals for each A horizontal, one AND gate, 61, must be encibled.
e number of A horizontal PND gates 61 is c.alculated by multiplying the size of the A horizontal parameter register 51 times the size of the A matrix parameter register 52 or Nl times N2. For example, if there are four inlets per A matr.Lx equal to N1, and sixteen A matrices equal to N2, then, it is required that 64 A horizontal AND gates 61 be connected to the parametex registers 51 and 52. The connection of the parc~meter registers 51 a~d 52 to the A~D gates 61 is in a matrix fashion so that one AND
gate 61 will respond when a particular inlet represented by parameter register 51 and a particular matrix represented by parameter register 52 is selected.
Similarly the number of AND gates 62, which are connected to parameter register 53 and 54, is found by multiplying N3 times N4. I'he number of AND gates 63 is found by multiplying N
5 times N 6, which corresponds to the number of D matrices multiplied by number of outlets.
~hen the proper clock signal gates 61, 62 and 63 are selected which represent the particular A horizontalr BC l.~nk and D outlet respectively, these gates are enabled at the appropriate ti~e. This is accomplished by AND gate 70, which gates the network clock with a signal transmitted via I/O port 40 by processor 10. As a result of processor 10 transmitting the enabling signal and the coincidence of this enabling signal with the network clock, the appropriate ones of ~ND gate 61, 62 and 63 are enabled to operate the corresponding D-type latches of the network.
A similar operation exlsts for deriving the data control signals by data signal gates 80, as did for deriving the clock control signals by clock signal gates 60. The number of AND
gates represented by 2ND gate 81 is equal to N 2, the number A
matrices, multiplied by N 3, the number B matrices. This is the number of AB links. For example, if the number of A matrices is 16 and the number of B matrices is 4, there w~uld be 64 AND gates 81 which is the number of AB links. Parameter registers 51 and 52 are connected to data signal gates 81 in a matrix fashion so that one gate i8 selected f~r the concurrence of the parameter registers 52 and 53. Similarly, A~D gates 82 are connected to parameter r~gisters 54 and 55. The number of AND gates 82 is equal to the number of C matrices, N 4, multiplied by the number of D matrices, N 5.
Simultaneously with enabling the clock si~nal gates 60, processor 10 via I/O port 4~ operates the data signal qates 81 and 82, to generate the AB and CD data signals. me AB and CD data signals serve to operate the D-type latches at the intersectio~ of ; the various verticals and horizontals of the netw~rk matrices, as indicated above.
When the path through the space swltching matrix is required to be disconnected, processor 10 a~ain operates all parameter registers 50, but indicates a logic 0 for each of the data signal gates 80. The clock signal gates 60 are operated the same as for establishing the connection. As a result, on the next clock cycle, each of the D-type latches which was set, now has a logic 0 clocked in at data and becomes resetO In addition, the corresponding crosspoint is released and the connecting path opened.
Although the preferred embodiment of the invention has been illustxated, and that form described in detc~ilr it will be readily apparent to those skilled in the art that various m~difications may be made therein without departing ~rom the spirit of the invention or from the scope of the appended claims.
A METHOD FOR CCWTROLLING A MWLTISTAGE SPA OE SWITCHING NETWORK
BA~KGROUND OF q~E INVENTICN
me present invention pertains to an electrcmechanical space switching network and more particularly to an arrangement for mu m mizing the number of control leads required to operate a multistage network.
Mcdern switching syste~ls typically incorporate ful]y electronic time and space s~itching networks in their design and imple~entation. Examples of such switching systems include the GTD-5 ~X manufactured by GTE Communication Systems Corporation and No. 5 ESS manu~actured by Western Electric.
All switching systems require a network, which is capable of switching relatively high voltages for such functions as subscriber line ringing and coin control functions. mese networks are auxiliary networks and not part of the voice or data switching path. These auxiliary networks are line or service circuit concentrator networks. With currently existing technology, use of fully electronic networks to switch high voltages is costly and, therefore, of little use in mDdern s~itching systems.
Conventional electromechanical switch mg net~ork ccmp~nents and techm ques are not always compatible with these modRrn ~switching systems designs. Furthermore, these conventional electromechanical ~witching networks require a number of control leads in order to operate the network. Any reduction in the number of control Ieads results in more efficien-t packaging of printed circuit boards. Also, network control is ~ade simpler by the reduction of control signals.
SUMM~RY OF q~E INVENTION
In a space switching network, a method for controlling a multistage netw~rk first selects an idle path from a number of pa~hs through the switching matrices of the space switching netw~rk. Next, a number of netw~rk parameters are formulated.
These parameters correspond to the idle path which has been select0d for transmission through each switching matrix.
~6~
Then, these switehing parameters are group0d into two sets. These tw~ sets correspond to the selected idle path. These sets of parameters are stored in registers and transmitted to the switehing matrices at the appropriate time.
~lorizontal and vertieal control sic;nals are generated from these sets of parameters. Certain of these horizontal and vertical controls are shared between switching matriees, sueh that, a vertical control signal of one matrix is also a horizontal ; eontrol signal in the n~xt switehing matrix. Lastly, latching means in each switching matrix, which are eonnected to the corresponding vertical and horizontal control signals via corresponding leads, are sinultaneously operated to establish a physical signal path from an inlet of the first switehing matrix ko an outlet of the last switching matrix. This path is the idle path which was previously selected.
A BRIEF DESCRI CN OF THE DRAWINGS
Figure 1 is a schematic diagram of a crosspoint ; configuration utilized in the switching network embodying the present inventionO
Figure 2 is a schematie diagram showing the implementatic~n of a multiple stage switching network of the present invention.
Figure 3 is a block diagram of the control portion for the switching network embodying the present invention.
DESCæIPTICN OF THE PREFERRED EMBCDIMEMT
Referring to Figure 1, a crosspoint eonnection for a space switching network is shcwn~ As diagrammatieally pietured, two elements are provided at the interseetion of eaeh horizontal line and eaeh vertieal lille of a space switching network. The first element is a crosspoint switehin~ element Xr which when aetivated establishes a signal path between a particular horizontal signal lead and a particular vertical signal lead. The erosspoint switehing ele~ent X may comprise ferreed, rela~ device or other metallie contact device. These eleetromeehanical ~2~
crosspoints are used to switch high voltage signals such as, subscxiber line ringing or coin control ~unctions. ~nis network configuration may also be applied to voice or data net~rks. For a voice or data network application, the signal switching element or electr~nechanical crosspoint would be replaced with an electronic crosspoint. This electronic crosspoint would sufficiently ha-ndle the relatively low voltages associated with voice and data txansmission.
The second element req~lired to complete a signal switching path is the control memory M. me control m~mory el~nent M operates in response to two control signals, a horizontal control lead and a vertical control lead. In response to the simultaneous occurrence of both the vextical anc~ horizontal control lead signalsr the control memory elernent M produces the switching element control signal, which is transmitted to the signal switching element X. merefore, in order to complete a connection through a stage of space ~switchirlg matrix, a vertical and a horiz~ntal control lead signal is supplied to the appropriate control m~rnory element M in order to activate its corresponding signal switching ele~ent X to establish a path between a corresponding horizontal signal lead and a vertical signal lead.
The signal switching element X may co~prise a an electromechanical crosspoint, such as, a mlniature single winding DIP (dual in-line packagel relay or a ~erreed type.
Referring to Figure 2, a four stage space switching network is shown. The switching matrices ~ through D are represented by the intersection of horizontal and vertical lines.
A four stage space swithing network is shown, although, the present invention would be applicable to a space switching network with any number of switching stages.
Each space switching rnatrix requires two signals in order to select a path thxough the n~trix. Ihese two signals are a horiæontal control signal and a vertical control signal. In a conventional space switching network, control signals are usually independently generated for each matrix stage. Therefore, a four ~stage network as shown in Figure 2 would require eight control sign~ls, a vertical control signal and a horizontal control signal for each of the four stages. In the present invention, N
switching matrices may be opera~ced with N plus 1 control signals.
Eor example, the four stage switching network, shown in Figure 2, may be o~erated with five control signals.
For drawing simplicity only one matrix of each matrix stage is shown. In an actual network configuration, each stage would include several switching matrices. For example, the A
matrix shcwn would be connected to several other B matrices (not shown~; in addition to the connection to the particular B matrix shown in Figure 2. '~his is true for each matrix stage. These interconnections between the matrix stages are called links and the interconnection pattern is called the fabric of the netw~rk.
Each intersection of the network matrix horizontals and verticals ccmprises a network switching element as shown in Figure 1. The signal switching element for this configwration is a crosspoint. 'me control memory element in the con-figuration in Figure 1 is a D-type latch, as shown in Figure 2.
To establish a connection through the space switching network shown in Figure 2, a path must be established frcm an A
Horizontal through the A, B, C and D matrices to a D ver'cical lead. In order to establish the sample network connection shown in Figure 2 in dark solid and dashed lines, an active data signal is provided to the hB and CD leads; ~hile, a clock signal is applied to the A horizontal, BC and D vertical leads. The A
horizontal signal, which is a clock signal, is connected to the A
matrix as a horiz~ntal control signal. The AB signal, which is a data signal, is connected to the A matrix as a vertical control signal and is c~nnected to the B matrix as a horizontal control signal (shown in the heavy dashed lines of Figure 2).
The switching element at the intersection of the A
hori20ntal signal (shown in the heavy solid line) of matrix A with the AB lead wi]l be operated and a signal path will be established ~z~
from the horizontal input to the A matrix (shc~n in heavy solid line) through the AB vertical signaling lead to the B matrix (shcwn in heavy dashed lines). The configuration of the D-type latch for the A matrix and C matrix is shown in lower left portion of the sketches of these matrices. me connection of the D~t~pe latches ~or the B and D matrices is shown in the lower right portion of Figure 2.
In the A matrix, the veltical data control signal, shown in dashed lines, is connected to the D input of the latch;
and, the horizontal clock control signal is connected to the clock input of the latch. When these two control signals are active, the crosspoint associated with the latch is closed and connects a signal path through the A matrix.
Coincident with the operation of the A matrix, the AB
(data) signal, which is also the horizontal control signal of the B matrix, operates along with the BC (clock) signal, which is a vertical control signal of the B matrix, to switch a patll through the B matrix. As a result, the D-type latch at the intersection of these two control signals is enabled and operates its corresponding B matrix crosspoint. The crosspoint establishes the connection from the A matrix through the B matrix via the dashed heavs7 line and the heavy solid line shown as the BC signal to the C matrLx. The hea~7y solid and dashed lines in~icate both the control signals and the signal leads, as previously shcwn in Figure 1.
Simultaneously with the connection of the A matrix and B matrix, a connection is made from the B matrix to the C matrix.
The ~C signal, which was used as a vertical control signal for the B matrix, is applied to the C matrix as a horizontal control signal ~shown in heavy solid line)~ The CD signal (shown in heavy dotted line) is the vertical control signal for selection in the C
matrix. The D-type latch at the intersection of the BC and CD
signals is as shown in the lcwer left portion of Figure 2. The CD
signal is connected to the D input of the latch. When this latch is activated, the corresponding crosspo~nt to which it is ~2~
connected is operated to establish the path shown through the C
matrix.
Simultaneously with the estciblishment of paths through the A, B and C matrices, the final path through the D matrix is established. The CD signal which was applied as a vertlcal control signal to the C matrix, is applied as a horizontal control signal to the D matri~ (shown in heavy dotted line~. The vertical control signal for the D matrix is the D vertical signal shown in solid dark line The latch at the intersection of these two signals in the D matrix ls as shown in the lcwer right portion of Figure 2. The D vertical signal is connected to the clock input of the associated latch; and, the CD sigrkal is connected as the data input of the latch. When an active signal is present on the CD and D vertical leads, the latch is operated and its associated crosspoint produces a path fr~n the C matrix along the CD
horizontal to the D vertical and out of the D matrix. As a result, a path is established through the A, B, C and D matrices.
When an activ~ signal or logic 1 is present on the data lead of the D-type latch, together wnth the application of the clock signal, the latch is operated to store the active signal.
As a result, the crosspoint is operated and remains operated ~or as long as the latch remains set. Each of latches may all simultaneously be reset hy applying inactive or logic 0 signal in the presence of the appropriate clock pulses.
me AB signal is a vertical control signal in the A
matrix and a horizontal control signal in the B matrix. The AB
signal is the data signal appIied to the data input of each D-t~pe latch along a particular vertical of the A matrix. Each successive space switching ~atrix will alternate the use of a clock signal to fulfill the roll of a vertical control signal in one matrix and a horizontal control signal in the next adjacent matrix. For example, the BC signal performs these functions for the B and C matrices respectively. The shared signal for C and D
matrices will be a data signal, the CD signal. Addition of subsequent matrices to this configuration w wld be accomplished by alternately sharing data and clock signals as shcwn in Figure 2.
Referring to Figure 3, the control logic which produces the required data and clock control signals is shown. Processor 10, ~hich may be implemented with the microprocessor, is connected to network terminal and link map 20. Network terminal c~nd link map 20 indicates whether particular network links are busy or idle. mis indication is accomplished by setting a particular bit or resetting a particular bit corresponding to each network link.
In addition, processor 10 also includes other local memory for storing the processor's operating program.
The processor scans the network terminal c~nd link map 20 for a combination of idle network links with which to connect a path through the network matrices. When a particular network path has been selected by the processor 10, each bit which indicates the busy/idle status of a particular link is marked busy, set to logic 1.
Processor 10 i5 ~urther connected to I/O port 40, which transmits control data. The I/O poxts 30 ~ld 40 are connected to ; the parameter registers 50. Each of the parameter registers 51 through 56 is connected to both I/O p~rt 30 and I/O port 40. One parameter register is required for each category of network fabric parame~ers.
Each parameter register i5 a multiple bit register.
The size of each parameter register is determined by the number of variables wi~hin a given parameter type. The width or size of the A horizontal parameter register 51 is Nl. This corresponds to the number of inlets per A matrix. Each of the A matrices in the switching network has the same number of inlets. A ~atrix parameter register 52 is wide enough to contain the number of A
matrices in the switching network, N2. Similarly, B matrix 53, C
matr~x 54 and D matrix 55 parameter registers are of sufficient size to indicate the numker of , C and D matrices, N3, N4 and N5 respectively. In addition, D vertical parameter register 56 is of sufficient to contain the nu~ber of outlets per D matrix, N6.
In order to establish a particular path through the network, processor 10 selects an idle path by scanning network terminal and link map 20. ~hen an idle Fath is ~ound, processor 10 transmits the identity of each inlet ~nd outlet via I/O port 30 to the respective parameter registers 51 thro~gh 56. A bit is set in each parameter register 51 through 56 corresponding to the particular path which is selected.
In order to derive the horizontal and vertical control signals shown in Figure 2, the outputs of the parameter registers 50 are gated through clock signal gates 60 and data signk~l gates 80. Paraneter registers 51 and 52 are connected to a number of AND gates represented by AND gate 61. In order to derive control signals for each A horizontal, one AND gate, 61, must be encibled.
e number of A horizontal PND gates 61 is c.alculated by multiplying the size of the A horizontal parameter register 51 times the size of the A matrix parameter register 52 or Nl times N2. For example, if there are four inlets per A matr.Lx equal to N1, and sixteen A matrices equal to N2, then, it is required that 64 A horizontal AND gates 61 be connected to the parametex registers 51 and 52. The connection of the parc~meter registers 51 a~d 52 to the A~D gates 61 is in a matrix fashion so that one AND
gate 61 will respond when a particular inlet represented by parameter register 51 and a particular matrix represented by parameter register 52 is selected.
Similarly the number of AND gates 62, which are connected to parameter register 53 and 54, is found by multiplying N3 times N4. I'he number of AND gates 63 is found by multiplying N
5 times N 6, which corresponds to the number of D matrices multiplied by number of outlets.
~hen the proper clock signal gates 61, 62 and 63 are selected which represent the particular A horizontalr BC l.~nk and D outlet respectively, these gates are enabled at the appropriate ti~e. This is accomplished by AND gate 70, which gates the network clock with a signal transmitted via I/O port 40 by processor 10. As a result of processor 10 transmitting the enabling signal and the coincidence of this enabling signal with the network clock, the appropriate ones of ~ND gate 61, 62 and 63 are enabled to operate the corresponding D-type latches of the network.
A similar operation exlsts for deriving the data control signals by data signal gates 80, as did for deriving the clock control signals by clock signal gates 60. The number of AND
gates represented by 2ND gate 81 is equal to N 2, the number A
matrices, multiplied by N 3, the number B matrices. This is the number of AB links. For example, if the number of A matrices is 16 and the number of B matrices is 4, there w~uld be 64 AND gates 81 which is the number of AB links. Parameter registers 51 and 52 are connected to data signal gates 81 in a matrix fashion so that one gate i8 selected f~r the concurrence of the parameter registers 52 and 53. Similarly, A~D gates 82 are connected to parameter r~gisters 54 and 55. The number of AND gates 82 is equal to the number of C matrices, N 4, multiplied by the number of D matrices, N 5.
Simultaneously with enabling the clock si~nal gates 60, processor 10 via I/O port 4~ operates the data signal qates 81 and 82, to generate the AB and CD data signals. me AB and CD data signals serve to operate the D-type latches at the intersectio~ of ; the various verticals and horizontals of the netw~rk matrices, as indicated above.
When the path through the space swltching matrix is required to be disconnected, processor 10 a~ain operates all parameter registers 50, but indicates a logic 0 for each of the data signal gates 80. The clock signal gates 60 are operated the same as for establishing the connection. As a result, on the next clock cycle, each of the D-type latches which was set, now has a logic 0 clocked in at data and becomes resetO In addition, the corresponding crosspoint is released and the connecting path opened.
Although the preferred embodiment of the invention has been illustxated, and that form described in detc~ilr it will be readily apparent to those skilled in the art that various m~difications may be made therein without departing ~rom the spirit of the invention or from the scope of the appended claims.
Claims (16)
1. In a space switching network, a method for controlling a multistage network comprising the steps of:
selecting an idle path from a plurality of paths through a plurality of switching matrices of said space switching network;
formulating a plurality of parameters corresponding to said selected idle path through each said switching matrix;
transmitting a first set and a second set of said formulated parameters from a plurality of register means, said first and second sets of said parameters corresponding to said selected idle path;
generating a plurality of horizontal and vertical control signals from said first and second sets of transmitted parameters;
simultaneously operating at least one D-type latching means of each switching matrix in response to said generated horizontal and vertical control signals to establish a physical signal connection from an inlet of a first switching matrix to an outlet of a last switching matrix.
selecting an idle path from a plurality of paths through a plurality of switching matrices of said space switching network;
formulating a plurality of parameters corresponding to said selected idle path through each said switching matrix;
transmitting a first set and a second set of said formulated parameters from a plurality of register means, said first and second sets of said parameters corresponding to said selected idle path;
generating a plurality of horizontal and vertical control signals from said first and second sets of transmitted parameters;
simultaneously operating at least one D-type latching means of each switching matrix in response to said generated horizontal and vertical control signals to establish a physical signal connection from an inlet of a first switching matrix to an outlet of a last switching matrix.
2. A method for controlling a multistage network as claimed in claim 1, said step of selecting comprising the steps of:
selecting a path through said plurality of switching matrices; and testing map indicators, associated with each switching matrix, to determine whether said selected path through said switching matrix is idle.
selecting a path through said plurality of switching matrices; and testing map indicators, associated with each switching matrix, to determine whether said selected path through said switching matrix is idle.
3. A method for controlling a multistage network as claimed in claim 2, wherein there is further included the step of iterating the steps of claim 2 until an idle path through each of said plurality of switching matrices has been determined.
4. A method for controlling a multistage network as claimed in claim 3, wherein there is further included the step of marking said map indicators of said determined idle path to indicate said idle path as being presently busy.
5. A method for controlling a multistage network as claimed in claim 4, said step of formulating comprising the steps of:
setting logic one in bit positions of a plurality of parameter words corresponding to said selected idle path through each of said switching matrices; and writing said plurality of parameter words into a corresponding plurality of parameter registers.
setting logic one in bit positions of a plurality of parameter words corresponding to said selected idle path through each of said switching matrices; and writing said plurality of parameter words into a corresponding plurality of parameter registers.
6. A method for controlling a multistage network as claimed in claim 5, said step of generating comprising the steps of:
first gating certain ones of said parameter registers to produce said first set of formulated parameters; and second gating certain ones of said parameter registers to produce said second set of formulated parameters.
first gating certain ones of said parameter registers to produce said first set of formulated parameters; and second gating certain ones of said parameter registers to produce said second set of formulated parameters.
7. A method for controlling a multistage network as claimed in claim 6, said step of generating further comprising the step of first enabling said first set of formulated parameters to be transmitted to said plurality of switching matrices in response to a network clock signal and a processor control signal.
8. A method for controlling a multistage network as claimed in claim 7, said step of generating further including the step of second enabling said second set of formulated parameters to be transmitted to said switching matrices in response to said processor control signal.
9. A method for controlling a multistage network as claimed in claim 6, said step of first gating including the step of AND-gating.
10. A method for controlling a multistage network as claimed in claim 6, said step of second gating including the step of AND-gating.
11. A method for controlling a multistage network as claimed in claim 7, said step of first enabling including the step of AND-gating said processor control signal with said network clock signal to produce a first enabling signal to enable transmission of said first set of formulated parameters.
12. A method for controlling a multistage network as claimed in claim 8, said step of simultaneously operating including the step of first connecting said first set of formulated parameters, said first parameter of said first set being connected as a horizontal control signal of said first switching matrix and said second parameter of said first set being connected as a vertical control signal of said second switching matrix and being connected as a horizontal control signal of said third switching matrix.
13. A method for controlling a multistage network as claimed in claim 12, wherein there is further included the step of repeating the step of claim 12 for each of said formulated parameters of said first set.
14. A method for controlling a multistage network as claimed in claim 12, said step of simultaneously operating further including the step of second connecting said second set of formulated parameters, said first parameter of said second set being connected to said first switching matrix as a vertical control signal and being connected to said second matrix as a horizontal control signal.
15. A method for controlling a multistage network as claimed in claim 14, wherein there is further included the step of repeating the step of claim 14 for each of said formulated parameters of said second set.
16. A method for controlling a multistage network as claimed in claim 14, said step of simultaneously operating further including the step of simultaneous latching said one latching means in each switching matrix, which is operated in response to a particular horizontal and vertical control signal to produce said physical signal connection.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/668,342 US4613969A (en) | 1984-11-05 | 1984-11-05 | Method for controlling a multistage space switching network |
| US668,342 | 1984-11-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1246199A true CA1246199A (en) | 1988-12-06 |
Family
ID=24681959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000492537A Expired CA1246199A (en) | 1984-11-05 | 1985-10-09 | Method for controlling a multistage space switching network |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4613969A (en) |
| JP (1) | JPS61114694A (en) |
| BE (1) | BE903572A (en) |
| CA (1) | CA1246199A (en) |
| IT (1) | IT1186039B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4897641A (en) * | 1986-12-04 | 1990-01-30 | Pascom Pty. Ltd. | Space switch |
| CA1306496C (en) * | 1987-04-13 | 1992-08-18 | Joseph L. Ardini, Jr. | Method and apparatus for high accuracy measurement of vlsi components |
| US4845722A (en) * | 1987-10-16 | 1989-07-04 | Digital Equipment Corporation | Computer interconnect coupler employing crossbar switching |
| US4967405A (en) * | 1988-12-09 | 1990-10-30 | Transwitch Corporation | System for cross-connecting high speed digital SONET signals |
| US5033064A (en) * | 1988-12-09 | 1991-07-16 | Transwitch Corporation | Clock dejitter circuit for regenerating DS1 signal |
| US4914429A (en) * | 1988-12-09 | 1990-04-03 | Transwitch Corp. | Switch components and multiple data rate non-blocking switch network utilizing the same |
| US5040170A (en) * | 1988-12-09 | 1991-08-13 | Transwitch Corporation | System for cross-connecting high speed digital signals |
| US5040173A (en) * | 1989-05-08 | 1991-08-13 | At&T Bell Laboratories | Network control arrangement based on topological equivalence |
| US5153757A (en) * | 1991-02-27 | 1992-10-06 | At&T Bell Laboratories | Network control arrangement |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3573384A (en) * | 1968-09-13 | 1971-04-06 | Itt | Electronic crosspoint switching array |
| US3729591A (en) * | 1970-11-25 | 1973-04-24 | Stromberg Carlson Corp | Path finding system for a multi-stage switching network |
| US3843849A (en) * | 1972-06-20 | 1974-10-22 | Itt | Multiple stage telecommunications switching network |
| US3832500A (en) * | 1972-11-22 | 1974-08-27 | Dynalec Corp | Automatic telephone system with improved line selecting apparatus |
| US3916124A (en) * | 1973-08-31 | 1975-10-28 | Bell Telephone Labor Inc | Nodal switching network arrangement and control |
| AR205127A1 (en) * | 1974-06-10 | 1976-04-05 | Ericsson Telefon Ab L M | AN IMPROVED MATRIX OF RELAYS |
| US4004103A (en) * | 1975-10-15 | 1977-01-18 | Bell Telephone Laboratories, Incorporated | Path-finding scheme for a multistage switching network |
-
1984
- 1984-11-05 US US06/668,342 patent/US4613969A/en not_active Expired - Fee Related
-
1985
- 1985-10-09 CA CA000492537A patent/CA1246199A/en not_active Expired
- 1985-10-31 IT IT22689/85A patent/IT1186039B/en active
- 1985-11-04 BE BE2/60832A patent/BE903572A/en not_active IP Right Cessation
- 1985-11-05 JP JP60246470A patent/JPS61114694A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| IT1186039B (en) | 1987-11-18 |
| IT8522689A0 (en) | 1985-10-31 |
| JPS61114694A (en) | 1986-06-02 |
| BE903572A (en) | 1986-03-03 |
| US4613969A (en) | 1986-09-23 |
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