|Publication number||CA1242804 A|
|Application number||CA 494379|
|Publication date||4 Oct 1988|
|Filing date||31 Oct 1985|
|Priority date||31 Oct 1984|
|Also published as||CA1242804A1, CN1008317B, CN85109170A, DE3587336D1, DE3587336T2, EP0183080A2, EP0183080A3, EP0183080B1, US4766590|
|Publication number||CA 1242804 A, CA 1242804A, CA 494379, CA-A-1242804, CA1242804 A, CA1242804A|
|Inventors||Takuji Hamada, Masahiro Takahashi, Kotaro Hirasawa, Jushi Ide, Hitoshi Fushimi, Seiichi Yasumoto|
|Applicant||Takuji Hamada, Masahiro Takahashi, Kotaro Hirasawa, Jushi Ide, Hitoshi Fushimi, Seiichi Yasumoto, Hitachi, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Classifications (2), Legal Events (1)|
|External Links: CIPO, Espacenet|
Loop transmission system having variable station order The present invention relates to a loop transmission system having transmission stations connected by loop transmission lines and, more particularly, to a loop trans-mission system suitable for employing a digital integrated ring network in which data terminals and non-data terminals can coexist as data processors connected with the transmission stations.
A typical prior art technique for a digital integrated ring network is described in papers such as C & C - NET
LOOP 6830 Universal Link System: NEC Technical Report Vol.
36, No. 7/1983: Ito et al., pp. 32 to 38. In the trans-mission system disclosed in this report, the circuit exchange function is realized by a plurality of time sharing, time slots. This requires a number of such time slots, when a large volume of traffic, such as digitized video data, is to be processed as the transfer data, and the amount of network simultaneous storage is severely limited. For ring network topology, there exists a system employing a star network in which the respective relay lines are concentrated at one place, as is disclosed in "A Local Communications network Based on Inter-connected Token-Access Rings: A Tutorial: IBM J. RES. DEVELOP Vol.
27, No. 5, 1983: C. Strole: pp. 481 to 496. However, this I, system aims at improving its reliability, and the circuit switching means, called a "wiring concentrator", has its construction and operation directed only towards bypassing a malfunctioning station; it does not improve the transmission performance of the system in the least.
An object of the present invention is to provide a loop transmission system having a variable station order, that can multiplex and store the traffic necessary for high speed transfer of a large volume of data, such as digital video data in a loop network.
According to the present invention there is provlded a loop transmission system for conducting data transmission among a plurality of transmission stations, and in which a plurality of said transmission stations have data proces-sors connected thereto compeising: a plurality of trans-mission stations, each transmission station having a receiver for receiving data and a transmitter for transmit-ting data, said receiver and said transmitter in each station being connected to a respective transmission line to provide a data input line and a data output line for said transmission station, respectively, and outputting means for transmitting a switching request signal on the data output line of the transmission station and a concentrator connected to said plurality of transmission stations via said respective transmission lines in such a manner as to selectively form a series transmission loop through said concentrator in which said transmission stations are connected in series in a selected order, said concentrator including switching means for changing the connection relationship between a number of data input lines and the same number of data output lines of the transmission stations connected thereto to any arbitrary order, and switching control means responsive to said switching request signal for outputting switching commands of "t '~`'~,.,.~
- 2a -to said switching means to control the connection relationship of said transmission stations in said series transmission loop to connect said station in an order indicated by said switching request signal.
In a preferred embodiment, the relay lines of a loop network are concentrated in one place, where the order of connection of transmission stations is changed in accordance with a transfer requirment, by noting that the ~2~
circuit switching is suitable for data that are to be stored for a long time, but must be instantly retrievable, whereas packet switching by the loop network is suitable for the other data, so that the combination of the two makes it possible to integrate data transfer having differ-ent traffic characteristics on one transmission line. The loop network makes simultaneous transmissions of plural stations for the same time period if the receiving station is positioned downstream of and adjacent to the sending station.
In the Drawings:
Figs. 1, 2 and 3 are each diagrams showing the con-struction of a loop transmission system having a variable connection order and expressing the characteristics of the present invention;
Fig. 4 is a transmission time chart and a format diagram Fig. 5 is a diagram showing the structure of connection order change-over means;
Fig. 6 is a diagram showing the structure of the change-over control means;
Fig. 7 is a diagram showing the structure of a transmission station;
Figs. 8, 9, 10 and 11 are each flow charts showing the operations of respective portions of a time slot multiplex control unit;
Fig. 12 is a diagram of data transfer flow between adaptors Fig. 13 is a diagram showing one embodiment of an adaptor;
Fig. 14 is a schematic diagram for explaining the operations; and Fig. 15 is a schematic diagram of the station order change-over.
The present invention will first be explained in connection with one embodiment thereof with reference to Fig. 1 which shows an example of overall structure of a loop network to which the present invention is applied.
A variety of data processors 11 to 18, such as computers or terminals, which are widely distributed in factories, offices, buildings and universities, interface on a loop transmission system through transmission stations 21 to 24, respectively, in order to transfer data among themselves.
Each transfer station is constructed of a transmitter (T) 2127, 2227, 2327 or 2427, a receiver (R) 2111, 2211, 2311 or 2411, a time slot multiplex control unit 211, 221, 231 or 241, and an equipment adaptor 131 to 134, 141 to 144, or 151. The transmission stations are connected in a loop by bit-serial transmission lines 3, and these lines are concentrated at a concentrator 4 called a "stream changer" to for a star-ring network. The stream changer is constructed of transmitters 451 to 454, receivers 411 to 414, switching means 41 and switching control means 42. As shown, a decision how to make the connection order is determined by an equipment adaptor (ADP) 151 of the transmission station 21, and its instruction is delivered to the switching means (CTL) 42. The connection order shown is the transmission stations 21, 22, 23 and 24, as indicated by the broken lines in the switching control means 41. Figure 1 shows an example in which four transmission stations are respectively connected with two data processors. However, the present invention is not limited to the number of stations or processors. These respective components will be described sequentially below.
The data processors to be connected with the trans-mission stations are classified into the following two kinds from their traffic transferring characteristics:
(1) Type 1: in which data must be instantly transferred after having been held for a long time; and ~,~
- s -
(2) Type 2: in which immediate retrieval is not so strictly required for data transfer and a short holding time is typical.
In the structural example of Fig. 1, the equipment of Type 1 is exemplified by the ITV camera 12, the image processor 15, the color still image file 14 and the image reference terminal 17, whereas the equipment of Type 2 is exemplified by computers 11 and 13 and their data processing terminals 16 and 18. In the system shown, 10 moreover, those data having different traffic character-istics can coexist on the same transmission line.
Generally speaking, it is well known in the art that circuit exchange is suitable for the former data, whereas packet exchange is suitable for the latter data. In order 15 to realize this, according to the present arrangement, the connection order in the stream changer 4 is controlled such that the transmission station 23 connected with the image processor l is located just downstream of the transmission station 21 accommodating the ITV camera 12, 20 and such that the transmission station 24 connected with the image locating terminal 17 is located downstream of the transmission station 22 accommodating the image file 14 acting as the sender.
The description referring to Fig. 1 is directed to a 25 case in which the stream changer has a star-ring network shape in the system, but the transmission system according to the present invention is not limited thereto. More specifically, Fig. 2 shows an example of a distributed star-ring network configuration that is composed of a plur-30 ality of stream changers. For simplicity of illustration, components other than the transmission stations, the stream changers and the transmission lines are now shown. The present shape is advantageous in that it is possible to shorten the transmission line length and to limit the 35 number of transmission stations connected with the stream changers, when the scale of the system applied is so large that the system has more transmission stations and a longer distance between the transmission stations than those of the system of Fig. 1. Fig. 3 shows an example in which the ring network is constructed in a mesh configuration. This case can better withstand obstruction to transmission, because a portion of the line joining the stream changers, i.e., the line portion between SCl and SC4 in this example can be constructed so as Jo be a redundant preparatory line.
In order to explain the operations of the respective portions according to this transmission system, an example of the transmission time chart is shown in Fig. 4.
Moreover, the present example corresponds to the case in which the following traffic occurs simultaneously in the system structure of Fig. 1:
(i) A video signal is sent out from the ITV camera of the transmission station 21 (STl) to the image processor 15 of the transmission station 23.
(ii) A still image is sent out from the image file 14 of the transmission station 22 (ST2) to the image reference terminal 17 of the transmission station 24.
(iii) Data on the state of the plant is sent out from the data terminal 18 of the transmission station 24 (ST4) to the computer 11 of the transmission station 21.
(iv) Data on the control of the plant is sent out from the computer 13 of the transmission station 22 (STl) to the data terminal of the transmission station 23.
The data format of multiplexed signals transmitted through the transmission line of a repetition of a plur-ality of (e.g., five in this example), time slots is called a "frame". The frame synchronisation for recognizing the order of the time slot is achieved by detecting a frame synchronisation character SYN. The synchronisation character can be realized by various methods such as unique bit pattern or violation of code pattern, but details are omitted here. The respective time slots have the common structure of a fixed length and are composed of three characters: a time slot control character C as header data; a destination address character DA for designating a receiving transmission station or equipment; and a data length character LNG indicating the effective data length in the time slot. The portion of the time slot other than the header data is stored with the data DATA resulting from the free format for each device.
The time slot control C contains, as shown, an F/s bit expressing the occupation state of the time slot, and a P/C
bit for discriminating whether the time slot is used for data transfer of the aforementioned Type l or 2.
In the present figure: the aforementioned traffic tiii) is processed by using the time slot TSl; traffic (iv) by the time slot TS2; traffic (i) by the time slots TS4 and TS5; and traffic (ii) by the time slot TS4. It should be noted that time slots are used exclusively by some stations for the transfer of data of traffic Type l; whereas other time slots are used commonly by a plurality of stations for the transfer of data of Type 2. This indicates that the present system can simultaneously transfer data of Type 1 in the same time slot.
Specific embodiments of the respective components for realizing a transmission system according to the present invention will now be described. Firstly, the hardware structure of the stream changer 4 will be described with reference to Fig. 5. The present changer 4 is constructed basically of switching means 41 and switching means 42 for controlling the former, as has been described above. The present embodiment requires signal transmitting and receiving units, because it is an active transmission line.
The receivers 411 to 414 have their inputs permanently connected to the transmission stations, respectively, to I'm ';
have the functions of signal amplification, waveform equalization and so on. Bit synchronizers (PLL) ~31 to 434 extract timing RTIM from the signal received. Timing converters (TC) 421 to 424 are composed mainly of FIFO
(i.e., First in First Out) registers to absorb the phase differences and fluctuations between the sending and receiving timing. A sending clock STIM is supplied from an oscillator (OSC) 44. The switching means 41 is composed of multiplexers (MPX) 541 to 544, because the data flow may be unidirectional. All the input signals to said multi-plexers are identical to the outputs of the timing converters (TC) 421 to 424. The respective selection signals MSELl to MSEL4 are supplied from the switching controller (CTL). ye transmitters (SCT) 4~1 to 4~4 are used to re-transmit the outputs of the multiplexers (MPX) 541 to 544 to the lines, and are permanently connected to the respective transmission stations like the receivers.
Fig. 6 shows the detailed structure of the switching control means (CTL) 42. This means is constructed such that it can change the connection order of the transmission stations by the following:
(1) manual switch; or (2) external setting means.
Which of these is to be selected is determined by a mode selecting switch 4216. A change of the order of connection of the transmission stations can be conducted by sequent-ially changing the values of the multiplexer selection signals MSELl to MSEL4 in the change-over means 41 and requires registers 4226 to 4229 which hold those values.
All the inputs to said registers are supplied from a multiplexer (SEL) 4219, and the selection data to the respective registers are stored on a time sharing basis.
The storing timing is generated by a circuit composed of a one-shot multivibrator (OSM) 4220, a decoder 4221 and NAND
gates 4222 to 4225. More specifically, only the register that is selected in accordance with the register selection data input to the decoder 4221 is fed as a resister write timing with a pulse signal having a certain width, which is prepared by the one-shot multivibrator 4220. The output of either a set switch (SET SW) 4213 or a set timing flip-flop 4210 is selected by a multiplexer (SEL) 4217 and fed to the input of the one-shot multivibrator 4220. Likewise, the output of either a register selecting switch (RES SW) 4214 or a register selecting data storage buffer (BUF) 4211 is selected by a multiplexer (SEL) 4218 and is fed to the input to the decoder 4221. Moreover, the multiplexer (SEL) 4219 selects the output of either a selection data switch ~SEISW) 4215 or a selection data storage buffer (BUF) 4212.
The hardware structure of a transmission station is shown in Fig. 7 which shows an example o the transmission station 21, since all the transmission stations have the same structure. In the system, only one station con-currently operates as the transmission control station.
This transmission control station performs those functions necessary to generate and monitor the frame signals and to compensate for the loop round trip delay. A receiver (STR) 2111, a timing converter (TC) 2113 and a transmitter (STT) 2127 are made to have the same functions as those used in the stream changer shown in Fig. 5, and their repeated explanations are unnecessary. A frame controller (FC) 2114 adjusts the loop round trip delay to an integral number of frame periods and is composed of components such as a two-port memory and an input/output timing controller. A time slot header controller (THC) 211~ executes the monitor and write ox the F/B bit and the P/C of the time slot header unit, as has been described in Fig. 4. A multiplexer (MPX) 2116 executes change-over between the repeat data and the data sent from a self-station, as the data sent from the sending station. A demodulator (DEM) 2118 converts the Manchester-coded signal on the transmission line to an NRZ
(i.e., No Return Jo Zero) data. The frame synchronisation character SY~ shown in Fig. 4 can be detected by the present circuit if it is composed of a code violation.
A modulator (MOD) 2126 executes the inverse conversion.
A serial/parallel converter (S/P) 2119 and a parallel/
serial converter (P/S) 2125 are respectively constructed of shift registers. suffer registers (BUF) 2120 and 2124 are connected between a connector interface data bus and a 10 transmission control. A time slot controller ~TSC) 2122 counts and generates the timing for the time slot recognition and is composed mainly of a counter. The initialization of the counter is effected by detecting the frame synchronisation character at the demodulator (3EM) 15 2118.
received data transfer controller (RTC) 2121 supplies timing for transferring the data oE the time slot addressed to the self-station to connecting equipment.
A sent-data transfer controller (STC) 2123 executes 20 various kinds of controls for capturing the corresponding time slot and transferring the data sent out from the connection equipment.
The sent-data is taken from the transmission line 3 into the receiver (STR) 2111 and is sent out again to the 25 transmission line 3 via the timing converter (TC) 2113, the frame controller (FC) 2114, the time slot header controller (THC) 2115, the multiplexer (MPX) 2116, and a sender (STY) 2127. Simultaneously with this, the output of the frame controller (FC) 2114 is also fed to the 30 demodulator (DEM) 2118 and is therefore transferred via thè series/parallel converter (S/P) 2119 and, in the case of the data aassigned to the self-station, further via the buffer register (BUF) 2120, a connection equipment inter-face data bus INBUS and the adaptors 131, 141 and 151 to 35 the connection devices 11, 12 and 4. Conversely, data sent from the connecting devices 11 and 12 are sent out ,~
via the adaptors 131 and 141, a connection equipment interface data bus ~TBUSI the buffer register (BUF) 2124, the parallel/series converter (P/S) 2125, the modulator (MOD0 2126, the multiplexer (MPS) 2126 and the sender (STT) 2127 to the transmission line 3.
The operations of the present transmission station will be described in more detail with reference to the processing flow charts shown in Figs. to 11. Fig. 8 shows the initialization processing flow, up to the establishment of the frame synchronisation, in case the present transmission station operates as the transmission control station. Moreover, this will explain the operations of the frame controller 2124 and the timing converter 2113. First of all, the multiplexer 2116 is set at side B to start the sending operation of dummy data and to confirm that it circulates around the loop. In the next step, the establishment of the timing conversion is realized by using the received clock pulse as the input timing of the FIFO register and by using the sent clock pulse as the output timing of the FIFO register after the storage of predetermined bit data has been completed. In accordance with this stored bit data, the phase difference and fluctuations of the clock pulse which was sent and the one which was received are absorbed. When round trip delay compensation of the loop is accomplished, the modulator (MOD) 2126 is instructed to send out the frame synchronisation character SYN. After this, simultaneously with sending out, the frame controller (FC) 2114 is instructed to start its operation. In response to this instruction, the frame controller (FC) 2114 starts storage of the data received subsequently, when the return of the frame synchronisation character SYN is detected, and then starts to take out the stored data in the order of receipt, when the end of the frame is detected. As a result, the aforementioned delay can be compensated. After this the multiplexer (MPX) 2116 i8 switched to side A to start relay of the data that are read out from the frame controller 2114. At this time, the header of each time slot in the frame is initialized so that each transmission station can perform its sending operation. When the present transmission station operates as an ordinary transmission station, the initialization may simply await the establishment of bit and frame synchronisation, while the multiplexer 2116 is left at side A without any data storage in the frame controller (FC) 2114.
Fig. 9 not only shows the processing flow of the receiving operation at each transmission station, but also explains the operation of a received data transfer controller (RTC) 2121. The data received after establish-ment of the frame synchronisation are introduced via the demodulator (DEM) 2118 and the series/parallel converter (P/S) 2119 into the received data transfer controller (RTC) 2121. This received data transfer controller (RTC) 2121 checks and stores the designated address character DA
and the data length character LNG in response to the signal coming from the time slot controller (TSC) 2122, indicating that the time slot header data are present. When the address is designated to the self-station, the correspond-ing adaptor is instructed to take in the content of the buffer register (BUF) 2120. How many bytes are to be transferred depends on the data length character stored in advance.
Fig. 10 shows a data sending processing flow of the packet switching type. With reference to Fig. 10 and subsequently Fi9. 11, the detailed description will be based mainly upon the operations of the sent data transfer controller (STC) 2123 and the time slot header controller (THC) 2115. For example, a request RQl output from the connection equipment 11 for packet switching is sent via ,;
the adaptor (ADP) 131 to the send data transfer circuit (STC) 2123. Here, whatever equipment the request comes from is determined and this information is passed to the time slot header controller (THC) 2115. I'he time slot header controller (THC) 2115 checks the F/B bit of said time slot in response to the time slot header detection signal from the time slot controller 2122. If F (free), this is changed to B (busy) and communicated to the sent-data transfer circuit (STC) 2123. This sent-data transfer circuit (SCT) 2123 instructs an adaptor (ADP) 131 to transfer the data and the multiplexer (MPX) 2116 to select the B side whereby to perform the sending operation.
The time slot number used at this time is read in and stored by the time slot controller (TSC) 2122. When a sending operation involving one or more time slots is desired, it is necessary to await one cycle for the same time slot of the next frame. When sending is complete, the busy bit of said time slot is rewritten to the free one.
Fig. 11 shows a data sending processing flow of the circuit exchange type. For example, a data sending request RQ2 of the circuit switching type sent out from the connection equipment is sent via the adaptor (ADP) 141 to the sent-data transfer circuit (STC) 2123. Here, whatever equipment made the request is determined and that information is given to the time slot header controller (THC) 2115. In the present embodiment, when the time slot used is of the circuit switching type, as shown in Fig. 4, its applicable range is determined in advance. On the basis of the time slot number supplied by the time slot controller (TSC) 2122, the time slot header controller (THC) 2115 checks the P/C bit of the corresponding time slot to examine whether it has already been used for the circuit switching type transfer. If that bit is used for the packet switching, the system waits for that time slot a until it is free. When the time slot is free, it is changed to the busy state. Simultaneously with this, the use of the circuit switching type is written in the P/C
bit. This busy state is repeated by the number of the time slots required by the equipment 12. When the occupation of all slots is accomplished, moreover, data transfer is executed such that the sent-data transfer controller (STC) 2123 sends the adaptor (ADP) 141 a read strobe signal WSTB and such that the multiplexer (MPX) 2116 is set at the B side. Once data transfer of the circuit switching type is started, the same time slot cannot be used for the packet switching type transfer, because the F/B bit of the time slot header remains busy.
When the end of the transmission is desired, the P/C bit of the time slot header is rewritten from circuit switching use to packet switching use. If a check of the same bit after one loop cycle reveals that it is unchanged, the F/B
bit is changed to be free, because no other transmission stations use that time slot. If the bit is rewritten to the circuit switching use after one loop circulation, the transmission is terminated without any operation, because the other transmission stations still use the same. When no request for data transfer of the circuit switching type is made, the time slot can be used for data transfer of the packet switching type by the control thus far described, so that the transmission lines can be used more effectively.
The changing of the connection order at the stream changer 4 will now be described. This change-over method can be first divided roughly into the following two types:
(1) The relationship of the circuit switching equipment is fixed, and the connection order is set by the manual switch shown in Fig. 6 when the system is constructed.
(2) The relationship of the circuit switching equipment can be freely changed, and the connection order is .,,~.~
dynamically changed in accordance with the demand prom each device.
Since a further description of method (1) is unnecessary, method (2) will be described hereinafter realization of the method (2) is further classified, as follows:
(2-1) The stream changer directly receives and executes the demand from each device.
(2-2) A predetermined transmission station receives and sends the demand to the stream changer.
The latter is further divided into the following two methods in accordance with how to send the instruction.
(2-2-a) The instruction passes through the transmission lines (2-2-b) The instruction passes through the equipment interface bus of the transmission station, as shown in Fig. 1.
The quantity of hardware required of the stream changer is the most or system (2-1) and can be minimized for system (2-2-b). No matter which method is adopted, the procedures of control are basically identical, and system (2-2-b) will be described in connection with the following embodiment.
First of all, the summary of the operations will be explained with reference to the time chart of Fig. 12. In this figure, all three adaptors are shown: the respective adaptors 141 and 133 for connecting the sending and receiving equipment with the time slot multiplex controlling unit; and the SC adaptor 151 for connecting the stream changer. The time lapse is shown downwardly in the drawing. The transmitting procedures are:
(1) A data sending demand of the circuit switching type is generated by some connection equipment and is transmitted to the adaptor 141.
(2) In response to this, the adaptor 141 prepares the connection demand data to generate the request RQl to the time slot multiplex controlling unit.
(3) This time slot multiplex controlling unit captures the free time slot to send out said data.
(4) In response to this, the time slot multiplex controlling unit transfers it to the corresponding equip-ment adaptor 133, which informs the connection equipment of it.
(5) The connection equipment at the reception side returns an answer depending upon whether it is busy.
~6) The adaptor 133 sends the answer data in accordance with a procedure like (2) and (3) above.
(7) In response to the answer data, the adaptor 141 sends it again after a predetermined time, if the data is a negative answer (NAK). If the data is an affirmative answer (ACK), the adaptor 141 sends a change-over demand to the SC adaptor 151.
(8) In response to this instruction, the SC adaptor 141 first returns an answer indicating reception of that instruction to the adaptor 141 and then instructs all the adaptors to interrupt sending. Next, the stream changer is instru_ted to change the order of connection. After this, all the adaptors are also instructed to restart sending operations. The adaptors having interrupted the sending operations restart them, whereas the adaptor 141 sends a circuit switching type of sending request (RQ2) to the time slot multiplex controlling unit.
(9) The adaptor 141 instructs the connection equipment to send out the data thereby to conduct the data transfer.
In response to this, the adaptor 133 transfers it to the connection equipment.
(10) In response to the send-ending instruction, the adaptor 141 again feeds the request ~Q2 to the time slot multiplex controlling unit to interrupt the data sending operation and to inform the adaptor 133 of the end.
(11) In response to this, the adaptor 133 returns an answer indicating reception and reports the end to the connection equipment.
Fig. 13 shows the hardware structure of the aforementioned SC adaptor 151. This is a device for setting the transmission station connection order externally for the stream changer 4 and is constructed of the following components:
(1) an instruction interface circuit SCIC 1513 for trans-ferring an instruction to the stream changer;
(2) a memory (RAM) 1514 for storing the instant trans-mission station connection order;
(3) a display (DISP) 1510 for displaying the instant transmission station connection order;
(4) a transmission interface circuit 1511 for controlling data transfer with a time slot multiplex controlling unit (TMP) 211;
(5) a processor 1512 for outputting an instruction to the stream changer 4 from the change-over demand received and the instant transmission station connection order, and transfers the various sent data to the time slot multiplex control unit (TMP) 211.
(6) an internal bus 1515 for mutually connecting the respective circuits described above.
The processor 1512 is composed primarily of a micro-processor (SCADP) 1521, an interruption controller (PIC) 1522, a high-speed memory transfer controller (DMAC) 1523, a timer controller (PTM) 1524, a program memory (ROM) 1520.
The change-over demand to be transferred from the time slot multiplex control unit (TMP) 211 is introduced into the FI~O memory 1531 in the transmission interface circuit (SBIC) 1511 and is then written in the memory (RAM) 1514 by the high-speed memory transfer controller (DMAC) 1523 until it is judged by the microprocessor (MPU) 1521. The answer to the change-over demand and the instructions to interrupt and restart sending are stored in memory from the microprocessor (MPU) 1521 and are then stored in the FIFO register 1530 in the transmission interface circuit (SBIC) 1511 by the high-speed memory transfer controller (DMAC) 1523 until they are sent out to the time slot multiplex control unit. On the other hand, the same are written directly in the switching control means 42 in the stream changer 4 from the microprocessor (~PU) 1521 via the instruction interface circuit (SCIC) 1513.
The procedures in which the SC adaptor 151 chanqes the stream changer 4 will be described in more detail with reference to the schematic diagram of Fig. 14. In this example, it is assumed that there are four transmission stations and that the immediate connection order is 1, 2, 3, 4, 1, --- and so on, as shown in a memory (RAM) 1525 in the SC adaptor 151. Here, the leading address of the present table is indicated at SOTTA, and the number of steps from that address indicates the connection order.
It is assumed that the transmission station 1 receives a change-over instruc'~ion to the transmission line 3. At this time, the processor prepares the instruction to set the two buffer registers 4211 and 4212 in the switching control means 42 of the stream changer 4 by the instant transmission station connection order tables SOTTA+3 in the following manner. The instruction to be stored in the register 4211 is composed of the following three words having a memory address RESTA as a header:
(a) RESTA --- Receiving Station Address (3);
(b) RESTA+l - - - Receiving Just IJpstream Station Address (2); and (c) RF.STA~2 - - - Receiving Just Downstream Station Address (4).
The instruction to be stored in the register 4212 is composed of the following three words having a memory address SEITA as a header:
(d) SEITA - - - Sending Station Address (1), (e) SEITA+l - - - Rece;ving Station Address (3); and (f) SEITA+2 - - - Sending Just Downstream Station Address (2).
After this, the instant transmission station connection order table is renewed. The procedures are followed by temporarily storing the receiving station address (3) in a 10 memory address TEMPA and by pushing all the memory contents down by one word from the memory address (SOTTA+l) stored with the sending just downstream station address (2) to the memory address (SOTTA+2) stored with the receiving station address (3). Then, the address SOTTA+l has its content lost, and the 15 address SOTTA+2 is entered by 2. After this, the content (3) temporarily stored in the TEMPA is transferred to the memory address (SOTTA~l) in which the sending just downstream station address has been present before. As a result, the order of connection of the transmission stations is 1, 3, 2, 4 and 1.
20 This order is sent to the display (DISP) 150. For the switching control means 42, the content from the memory address ~ESTA may be transferred to the buffer register 4211, and the content from the memory address SEITA may be transferred to the buffer register 4212. Fig. 15 shows how 25 the order of connection of the transmission stations is caused to change by the aforementioned transfers. Fig. 15(a) shows the mode before the change. The content of the memory address RESTA is transferred to the buffer register 4211, and the content of the SEITA is transfered to the buffer register 4212 30 for writing as shown in Fig. 15(b). Like the above, Fig. 15(c) is obtained if the content of the address RESTA-~l is trans-ferred to the registers 4211 and 4212. Moreover, the final mode of Fig. 15(d) is obtained if the content of the address RESTA+2 is transferred to the registers 4211 and 4212.
Even when a large amount of traffic requiring a high speed and large capacity transmission channel, such as a digital video signal occurs in the system, it can be accommodated by the circuit exchange using the same time slot. As a result, the transmission performance of this loop transmission system can be significantly improved.