CA1239696A - Aircraft flight data recorder data acquisition system - Google Patents
Aircraft flight data recorder data acquisition systemInfo
- Publication number
- CA1239696A CA1239696A CA000469948A CA469948A CA1239696A CA 1239696 A CA1239696 A CA 1239696A CA 000469948 A CA000469948 A CA 000469948A CA 469948 A CA469948 A CA 469948A CA 1239696 A CA1239696 A CA 1239696A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- signals
- analog
- input
- acquisition system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D9/00—Recording measured values
- G01D9/005—Solid-state data loggers
-
- G—PHYSICS
- G07—CHECKING-DEVICES
- G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
- G07C5/00—Registering or indicating the working of vehicles
- G07C5/08—Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle or waiting time
- G07C5/0841—Registering performance data
- G07C5/085—Registering performance data using electronic data carriers
Abstract
AIRCRAFT FLIGHT DATA RECORDER
DATA ACQUISITION SYSTEM
Abstract of the Disclosure A data acquisition system for use in an aircraft flight data recorder receives multiple analog and discrete signals representative of variousaircraft parameters. A single address command from the night data recorder central processing unit (CPU) causes a first multiplexer to select a set of analog signals. Each selected analog signal is amplified by a gain factor under CPU
control and passed to track-and-hold circuitry which holds a level of the amplified analog signal upon receipt of a suitable command. The held analog signal levels are passed to a second multiplexer which also receives a set of discrete signals selected by a third multiplexer in response to a CPU address command. A control sequencer sequentially passes each signal at the input of the second multiplexer through an analog-to-digital converter, with the resultant digital signal being loaded into memory. After either all the selected and processed analog signals or the selected discrete signals have been analog-to-digital converted and stored in memory, the control sequencer issues an interrupt signal to the CPU.
DATA ACQUISITION SYSTEM
Abstract of the Disclosure A data acquisition system for use in an aircraft flight data recorder receives multiple analog and discrete signals representative of variousaircraft parameters. A single address command from the night data recorder central processing unit (CPU) causes a first multiplexer to select a set of analog signals. Each selected analog signal is amplified by a gain factor under CPU
control and passed to track-and-hold circuitry which holds a level of the amplified analog signal upon receipt of a suitable command. The held analog signal levels are passed to a second multiplexer which also receives a set of discrete signals selected by a third multiplexer in response to a CPU address command. A control sequencer sequentially passes each signal at the input of the second multiplexer through an analog-to-digital converter, with the resultant digital signal being loaded into memory. After either all the selected and processed analog signals or the selected discrete signals have been analog-to-digital converted and stored in memory, the control sequencer issues an interrupt signal to the CPU.
Description
~2~ 6 ~IRCR~FT PLIGHT DATA RECORDER
DATA ACQIJBITION SYSTEM
Technical ~ield This invention rel~tes to d~tfl ~cquisition systen)s for use with S flight data recorders and, more particul~rly, to flight dAta acquisition systems ~or receiYing night dat6 signsls in a Yariety of signal forms.
Background of the lnvention Flight data recorders are monitoring and recording instruments, carried aboard an aircraft, which systematicslly monitor and store the instan-10 taneous values of various aircraft parameters. Early recorders were analogelectromechanical de~rices which periodically marked, in snalog ~orm, the value of a given airplane parameter on a moving wire or other permanent storage medium. The time of occurrence of the parameter was also suitably scribed into the medium opposite the mark for the sensed parameter.
Subsequently, digital flight data recorders have been developed which operate by converting each 8nalog aircraft parameter into a corresponding digital signal, and storing the digitfll signals on B permanent storage medium such as magnetic tape.
The numerous mechanical parts employed in the nnalog and digital 20 type electromechanical flight data recorders have rendered such units expensive to construct and buL~y in design, requiring periodic maintenarlce of the mechanical parts. In addition, extract}on of the stored dats rom these dats recorders re~uires physical removal of the storage medium.
The development of solid state memory devices~ such as electri-
DATA ACQIJBITION SYSTEM
Technical ~ield This invention rel~tes to d~tfl ~cquisition systen)s for use with S flight data recorders and, more particul~rly, to flight dAta acquisition systems ~or receiYing night dat6 signsls in a Yariety of signal forms.
Background of the lnvention Flight data recorders are monitoring and recording instruments, carried aboard an aircraft, which systematicslly monitor and store the instan-10 taneous values of various aircraft parameters. Early recorders were analogelectromechanical de~rices which periodically marked, in snalog ~orm, the value of a given airplane parameter on a moving wire or other permanent storage medium. The time of occurrence of the parameter was also suitably scribed into the medium opposite the mark for the sensed parameter.
Subsequently, digital flight data recorders have been developed which operate by converting each 8nalog aircraft parameter into a corresponding digital signal, and storing the digitfll signals on B permanent storage medium such as magnetic tape.
The numerous mechanical parts employed in the nnalog and digital 20 type electromechanical flight data recorders have rendered such units expensive to construct and buL~y in design, requiring periodic maintenarlce of the mechanical parts. In addition, extract}on of the stored dats rom these dats recorders re~uires physical removal of the storage medium.
The development of solid state memory devices~ such as electri-
2~ cally erasable re~d-only memory, has led to the design of all solid state night dats recorders. The solid state 1ight data recorders commonly employ a dnta acguisition system (DAS) which receives and processes the various aitcrsft ;nputs;gnals to be monitored and stored under the control of a centrsl processing unit (CPU). The analog aircraft signals are converted to digiW signals by the DAS
30 and, under CPU control, are passed over a data bus to the solid stste memory devices. Progrsmming within the CPU controls the processing of input airplane ~23965~;
~Ignsls to corresponding digital s~gnals through the DAS ~nd the subsequent transference of these digital signals to controlled locations in the solid statememory.
The signRls representstive of monitored aircra~t parameters are 5 typically either discrete level signals or analog signals. Discrete signals are typically switch posltions and produce either a high or a low level output depending upon the status of the particular switch. A typical exumple ~n an aircraft is a squat switch, which indicates whcther or not a load is being borne by the lsnding gear. The analog signals may be either straight DC signals, DC
lD ratiometric signals, synchro signals or AC ratiometric signals. The DC signPls are static in nature, and generally range between a minimum and maximum vslue for the parameter belng monitored. DC ratiometric signals are DC signals hsving a rAtio representative of the value of the parame~er being sensed. A
typical DC r~tiometric signal Is th~t produced by a potentiometer having a DC
15 voltage applied across its tesistive element, with the wiper position indicative of the level o~ the sensed parameter. Thus, the ratio o~ the wiper voltage to She voltage across the potentiometer's resistive eiement represents the level of theparameter being monitored.
Synchros are commonly employed to indicate the angle of ~
20 parameter. A synchro sensor is normally excited by two reference AC signals and outputs three active AC signals. The relative phasing and amplitude between the active AC signals and the reference signals indicate the angle of the synchro and, thus, the angle of the sensed parameter.
A typicsl AC ratiometric aircraft signal is that produced by a 25 linear variable differential tranformer tLVDT). LVDTs are commonly employed to indicate the relative position of aircraft control surfaces. Here, the ratio of the LVDT output sense AC signal to ~ reference AC signal is indicative of both total deflection and direction of deflection of the ~ontrol surface.
To ~ccurately collect d~ta from synchro snd ratiometri~type 30 sensors, therefore, the DAS should simultaneously colleet and hold each signal associated with the multisignal-type sensor.
~ urther, it is desirable to minimize the overhead on the CPU in itsaccessing of data as collected by the DAS. In prior art flight dat~ recorder designs, the CPU sends a request to the DAS asking for the value of a given 35 aircraft parameter and this parameter is then selected, processed, and analog-to-digital converted by the DAS which then signals the CPU th~t the requested information is available. Since ~ Isrge number of -airplane parameters may be ~23~g6 monitored by the night data recorder, constant requests by the CPU on the D~S
significsntly Increases CPU overhe~d.
Purther, ~t is desirable to conform the night data recorder such that it ~s ~apabl2 of being conveniently modified to operate ~n ~ny one Or several different types of aircraft. To this end, the DAS is preferably configured such that its inputs may be assigned by the CPU to handle any analog or discrete input sign61. Further, he levels of the various signals at the inputs of the DAS mustoften be scaled for proper processing within the DAS. For example, in~smuch as all input signals are analog-to-digital (A/D) converted, the DAS typically includes a convention~l A/D converter. The accuracy of an A/D converter is n function of the signal level applied at the input to the converter. To minimize A/D c~nverter errors, herefore, ~t is essentiQI that eAch ~ircraft parameter sensor signal be scaled before being applied to the A/D converter. In order to assure 8 universal 1ight data recorder design, the scaling factors applied to each ~5 input signal should be under CPU eontrol.
Summary of the Inveneion The present invention, therefore, is directed to R da-a acquisition systern for use in a flight data recorder. An aspect of the present invention isthe ability of the data acquisition system to process R set of parameter sense signals 5n response to a single CPU request. In this way, integrity of multiple signal sensor data is sssured and overhead on CPU operation is r educed.
A further aspect of the invention is the universal applicstion of the present data acquisition system. Analog or discrete aircraft parameter signals m~y be assigned to ~ny of the multiple data acquisition system inputs under CPU
control. Further, the DAS is responsive to CPV control to vsry the scaling applied to each input signal.
Briefly, according to the invention, a data acquisition system for an aircraft flight data recorder is responsive to n central processor unit (CPU)for selectively processing a plurality of input signAls. The data acquisition system comprises a multiplexer which outputs selected sets of the input signals, with each selected input signal set being output responsive to a corresponding address command signal. Logic is responsive to a single command from the CPU
for producing each address command signal. Each sign~l in a selected signsl set is processed by provided processing means.
Preferably, the processing means includes gain controlled amplifiers which respond to gain control ~ommand signals from the CPU for amplifying eAch signal in a selected sign~l set by a predelermincd g~in fActor.
~239~i9f~
Track-an~hold clrcuitry tracks the v~lue of each umplified signal 3n e selected ~ignal set and, ~n response to a hold cornmand signal, holds the Jnstantaneous value ~f each amplified signal. An ~malog-to-digital converter converts esch signsl st ~ts input to a corresponding digital signal at its output. A controller predeterminedly couples the Instantaneous value of each signal in the selected signal set to the input of the analog-to-digital converter.
In addition, Jnput scaling circuits may be provided for attenuating selected input signals by a predetermined scaling factor. The gain factors for the gain controlled smplifiers ~re selected such that each signal, after being attenusted in the Jnput scaling circuit snd amplified by the gain controlled amplifier has ~ leYel in a range selected to minimize analog-to digital comerter error.
Prefer~bly, the data ncquisition system includes digital memory for ~toring each analog-to-digital converted instantaneous value of a signal in a selected signal set. The controller produces an interrupt signal to the CPU uponall of the snslog-to~igital converted instantaneous values of the signals in a selected sign~l set belng stored In the digital memory.
Preferably, the logic circuit responds to a single CPU command siKnal to:
a) produce a predetermined ~ddress command signal such that the multiplexer outputs the set of selected input signals, b) produce predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and c) activate the controller such that the analog-to-digital con-verted instantaneous value of each signsl in a selected signal set is loaded into the digit~l memory.
For ~pplications wherein at least three of the input signals to the data acguisition system are the output signals from a synchro sensor, the logic 30 circuit produces an address command signal causing the multiplexer to output the three synchro signals as a selected signal set.
In applications wherein at least one of the input signals is sn AC
ratiometric signal and at least one of the input signals is the reference AC signal for the AC ratiometric signal, the logic circuit produces an ~ddress command 35 signal causing the multiplexer to output the AC ratiometric and rererence AC
signal as a selected signal set.
Brief Description of the Drawin~s ~ IGURE I ~s a block diagram Illustrating the principal components of ~ solid state tlight data recording system employing A data acguisition system;
FIGURE 2 ~s a block diagram ~llustrating the principal components 5 of the preferred dqta acquisition system;
FIGl~RE 3 is a logic flow diagram illustrating the sequential steps performed by the control sequencer of the preferred dat6 acquisition system;
FIGURES 4A-4F are detailed schematic diagrams showing the preferred construction of the dsts acquisition system; and FIGURE 5 is a detailed schematic diagrsm sf the data acquisition signal prGcessors used in the data scquisltion system.
Detailed Description FIGU~E I a block diagrAm illustsating the principsl c~>mponents of a solid state flight data recording system, shown enclosed within dotted line 10. A night data recorder JS ~arried aboard an ~ircraft and systematically monitors and stores information related to aircraft parametric data. Such recorded data may be analyzed at a subsequent time to yield information related to the source of an ~ircraft mishap, or simply to provide a diagnostic and information tool as to the air~raft's performance.
The flight data recorder must be capable of receiving and proces-sing three distinct types of parametric data. The first dats grouping is analog data, indicated by block la. The analog data may be any one of four distinct types. Information related to an angle, such as engine nozzle position, is commonly provided by a synchro sensor. Each synchro sensor typically provides 25 three active signals Sl, S2 and S3 which are phase and amplitude related to areference signal (commonly 400 Hz in aircraft). By processing the three active signals in the known manner, the angle of the parhmeter being monitored is derived.
A second type of analog dats is AC ratiometric data. AC
30 ratiometric data is commonly provided in aircraft by a sensor known as a linear variable differential tranformer (LVDT). An LVDT is typically employPd to monitor the position of an aircraft control surfAce. It is stimulated by an AC
reference signal, and produces an AC output signal. She ratio of these two signals is related to relative movement between component parts of the LVDT
35 nnd, thus, deflection of the control surface being monitored.
Finally, analog data signals may be either DC or ratiometric DC
signals. The standard DC signals are voltsge levels which vary within a defined range, the magnitude of which is indicative of the status of the parameter being ~23969~i -monitored. Ratlometric DC ~ignals are slgnal pairs, the ratio of which is indicative of the parameter being monitored. An example of a ratiometric DC
~ignal is the output from a potentiometer. Typically, a voltage Is ~pplied across the resistive element of the potentiometer, this voltage constituting the first S ratiometric signal. The wiper of the potentiometer is linked to the parameter being monitore~ such that ~t moves in response to parameter changes. As such, the ratio of the wiper voltage to the total resistive element ~oltage is indicative of the value of the parameter being sensed. Examples Or ratiometric DC signals produced in aircraft are rate signals such as pitch, yaw and roll.
Discrete data, indicated by block 14, are signals which assume either a low or a high state ~n response to the status of the parameter being monitored. Such signals are, commonly, produced by switches, an example being the aircraft squat switch which produces H discrete output indicating whether ornot the aircraft landing gear is under load.
FinRlly, the flight data recorder receives digital data, as indicated by block 16. The digital dsta originates from other systems within the Rircrsft.For example, digital inlormation indicative of navigation information, as produced by aircraft onboard navigation computers, may be provided to the night data recorder.
Both the analog data 12 and the discrete data 14 are processed within the night data recorder through a data acquisition system 18. The function of the data acquisition system 18 is to receive each analog and discrete input signal and, under external control, sequentially convert each input signal to a corresponding digital signal. The digital signals are then output on a system bus 20. The data acguisition system 18 is described in detail hereafter.
A controller 22 receives the input digital da-a from the aircraft systems 16. The controller 22 provides any signal conditioning required and is responsive to external control to output the digital data on system bus 20.
Overall control for the flight data recorder is provided by a central processing unit (CPU) 24. Associated with the CPU 24 is a read-only memory (ROM) 26 which contains the programming used by the CPU 24. Also associated with CPU 24 is random access memory (RAM) 28 which is used by CPU 24 ss required for temporary storage.
Also attached to the system bus 20 are three controllers 31-33.
The first controller 31 connects to the crash survivable memory unit 34. The crash survivable memory unit 34 is a solid state memory storage which is housed within a container designed to survive an aircralt crash.
~23~i96 Connected to the output of controller 32 is an ~uxiliary memsry unit 36. As with the crash survivable memory unit 34, the auxiliary memory unit 36 Includes solid state, electronle memory. Electrically erasable program mable re~d-only memory (EaPROM) may be used as the storage devlces in either 5 the crash survivable memory unit 34 or the auxiliary memory unit 36.
The output from controller 33 is adapted for connection to ground read out equipment 38. Once the aircraft has landed, intormation stored within the crash survivable memory unit 34 or the auxiliary memory unit 36 may be accessed by the ground read out equipment 38 and stored on magnetic tape or 10 other perm~nent storage medium.
Operation of the flight data recorder, shown in FIGURE 1, is understood QS follows. The CPI~ 24, in response to its prc>gr~mming stored in ROM 26, sends commands to the data acquisition system 18 instructir~ that certain sets Or analog deta 12 or discrete data 14 be converted to corresponding15 digital signals. In addition, as will be discussed in more detail with respect to PIGllRE 2, commands from the CPU 24 cause the data ~cquisition system 18 to level adjust each of the processed analog signals. Once the set of ~nalog or discrete data signals has been processed, the data acquisition system 18 notifies CPV 24 by an appropriate interrupt signal over ~n interrupt line Qssocisted with20 the system bus 20.
Similarly, the CPV 24 msy ~ccess any di~ital data from the ~ircraft systems 16 via commands to the controller 22.
In response to the digitsl parametric signals from the data a~quisi-tion system 18 ~nd the aircraft systems 16 through controller 22, the CPU
25 performs any further signal processing required, such as conYerting synchro or LVDT signals to corresponding angle or position signals, respectively, therearter loading the digital signals into either the crash survivable memory unit 34 or the suxili~ry memory unit 36 via commands to the appropriate controllers 31, 32, respectively. Typically~ parametric data relevant to system ~ailures on the 30 sircraft is loaded into the crash sur-/ivable memory unit 34, whereas data which is informational in nature is routed to the auxiliary memory unit 36.
Upon landing, the ground read out eguipment 38 is sttached to the system .ria controller 33 ~nd, by appropriate commands to the CPU 24, da~a stored within the crash ss~rvivsble memory unit 34 ~nd the ~uxiliary memory 35 unit 36 msy be read out and loaded into permanent storage.
FIGURE 2 is a detailed block diagram of the dat~ ~cquisition system 18 ~s shown in FIGURE 1. Input to tl~e data acquisition sys~em are a series of ~nalog input s~gnals, indicated generally at 50, and ~ series of discrete input si~nals, indicated generally at 52.
Each anal~g ~ignal is fed over 8 line to an Input of an isolation and scaling network 54. The input Isolation and scaling networks ~re comprised of 5 passive ~omponents, namely precision resistors and capscitors which scale ea~h~nput signal to ensure feedback fault isolation and, further, to optimize the sîgns~ ~loltage range prior to analog-t~digital processing, QS Will be describedhereafter.
Also applied es an input to the isolation nnd scaling networks 54 is 10 a built-in test (BIT) signsL This signal is 8 predetermined, known voltage level signal which is ~pplied to the system input and monitored st the output to identify any syst~m processing errors.
Each scaled (attenuated) input analog signal is passed over a line to an input o~ a multiplexer network 56 comprised of three multiplexers. The 15 multiplexer network 56 responds to a digital signsl applied to its address bus 58 to selectively output a set of three input analog signals. The selected ana~og signals appear on multiplexer network output lines 56B-56C.
A feature of the data acquisition system is that in respon~e to one ~ommand input from the CPU (FIGURE 1), a predetermined set (here a set of 20 three) of snalog signals is selected for processing. In this way, overhead on the CPU is reduced (by reducing commands and interrupts between the CPl~ and the data ~cquisition system) and the phase integrity of synchro and AC ratiometric signals is preserved. Thnt is, for analog input signals corresponding to the S1, S2 and S3 active synchro output signals, these three signals are selected as a se 25 and, as such, are simultaneously processed by the data acquisition system, thereby eliminating errors due to monitoring the synchro lines at slightly different times. For LVDT signals, both the return signal and the reference signals are processed simultaneously, thereby elso avoiding phase related errors.
Also, for two LVDTs sharing a common reference signal, a set can include each 30 LVDT signal and the single reference signal, thereby avoiding the need to access the re~erence signal twice.
Each output line 56a-56c from the multiplcxer network 56 con-nects to the input of a gain controlled amplifier 61-63, respectively. Each gaincontrolled amplifier 61-63 has a gain control input 61a-63a, respe~tively, ~nd, in 35 response to a command over its gain control input, cach gain controlled smplifier 61-63 amplifies a signal at its input by 8 predetermincd gain factor.
The amplified signaLs at the outputs o~ gnin controlled ampli-fiers 61-63 are applied st the inputs to three track-and-hold circuits 71-73, ~23~6~6 respectl~ely. EOEch tr~ck-and-hold circuit 71-73 7-as a hold command input line 71a-73a, respectively. The track-an~hold circuits 71-73 operate to tra~k the levels of the signals out of gain controlled ~rnplifiers 61-63 until a hold commGnd signal is received. Once a hold command signal is received, each track-and-hold circllit 71-73 produces at its output the held level of the signal Rt its input st the time of receipt of U~e hold command. The three held signal le~rels are applied via output lines from the track-~nd-hold circuits 71-73 to three inputs of a multiplexer 80.
Each 9f the discrete input signals 52 is carried over e line to an input vf the isol~tion ~qnd Uas networks 82. As with the isolation and scaling networks 54, the Isol~tion and bias networks 82 ensure feedb~ck fault isol~tion and, if reguired, input s~ale or input biHs each discrete signal to make it compatible with subsequent data ~cquisition system processing circuitry.
Also applied as an input to the isolation and biss networks 82 is ~
built-in test (BIT) signal which is a predetermined leve] sign~l used to check the accur~cy of system processing.
Eech discrete input signal and the BIT signal ~re processed through the isolation and bias networks 82 and applied as ~n input to a multiplexer 84.
Multiplexer 84 has an address bus input 86 and, in response to digital addresseson address bus 86, selects a set of three dlscrete input signals which appear onthe multiplexer 84 output lines 84a-84c. The selected discrete signal set is ~pplied to the remaining three inputs of the multiplexer 80.
The multiplexer 80, in response to an address command provided at its address input 80a, sequentially p~sses a selected signal at its input to themultiplexer output 80b. The output 80b of multiplexer 80 connects to the input of an an010g-t~digital SA/D) converter 90. In the known manner, A/D cor~
verter 90 converts each signal applied at its input to a corresponding digitsl signal at its output.
Each digital sig~al ~ppearing at the output of A/D converter 90 is ~pplied to the input of a random access memory (RAM) 92. The RAM 92 responds to control signals at its control input 92~ to loHd each digitHI signal at its input into ~n appropriate storage location. Further, upon receiving an ~ppropriate command at its command input 92a, RAM 92 outputs its stored digital values on the system information bus 94 which connects to the CPU.
Control signals to the multiplexer 80 and tl-e RAM 92 are provided by a control sequencer 96. Control sequencer 9fi receives ~ control input sign~lat its input 96a and a clock signal, from e clock 98, at its clock input 96b. Also, control sequencer 96 is capable of producing an interrupt signal at its output 96c ~239~6 which leads to the CPV. In ~dditlon, the control sequencer 96 provides a hold control output ~6d wh~ch is ed to the hold control 3nputs 71a-73Q of the track-and-hold circuits 71-73, respectively.
Both the control bus and the information bus from the CPU are fed to the input/output (I/O) control circuitry 100 nssociated with the dat~ ~guisi-tion system. Also, ~he CPU Information bus is applied to the input o~ a set sf input ports 102. The input ports 102 produce a set of gain control sign~ls, on lines 102a, which are applied to the gain control inputs 61a-63~ of the gain controlled amplifiers 61-63, respectively. Also appearing as an output o~ the lD input ports 102 on output lines 102b are the multiplexer address signals which are coupled to the multipl~xers 56 ~nd 84. A control line 102c from input ports 102 connects to input 96a of control sequencer 96. Finally, a control line 102d out of the input ports 102 is fed to the control input ~6a of the control sequencer 96.Operation of the data acquisition system shown in FIGURE a is understood as follows.
The CPU accesses the data acquisition system by applying an appropriste address signal over the control bus which is recognized, and responded to by the l/O control 100. A CPU produced signal on the Wormation bus is processed by the input ports 102 which produce an appropriate multiplexeraddress output on outpùt lines 102b. In response to this address, the multiplexer networlcs 56, 84, select a set of three analog signals and three discrete signals, respectively. The selected set of three discrete signals are applied directly asinputs to multiplexer 80. The selected set of three analog signsls, appearing onoutput lines 56a-56c o- multiplexer network 56, are coupled as inputs to the gain controlled amplifiers 61-63. Esch gain controlled amplifier 61~63 receives at its gain control input 61a-63a, respectively, a gain control signal as coupled from the information bus through input ports 102 and applied on output lines 102a.
The accuracy of A/D converter 90 is dependent upon the level of the input signal. Thus, to minimize A/D errors, the CPU selects a gain for the gain controlled amplifiers 61-63 which, in association with the attenustion to each input signal provided by the isolation and scaling networks 54, level adjusts each analog signal for minimum A/D converter error.
A hold control signal ~t output line 96d rrom the control sequencer 96 causes the track-an~hold circuits 71-73 to output a held level of the gain factored anslog signals. These held values appear at the input to multiplexer B0.
The control sequencer 96 receives a control signal at its control input 96a from the control output 102c of the input port 102 indicating that the ~3~696 CPU ~s requesting processed psrametric data. ln response, the control ~equencer 96; at a r~te determined by the clock 9B, sequentially passes, ViQ
Appropriste ~ddresses to control input 80a, each signal at the input o multi-plexer 80 to the multiplexer output line 80b where it is then A/D converted by converter ~0. The corresponding digitel signal out of converter 90 is then loaded into an address in RAM 92 determined by the control sequencer 96 produced signal at the control input ~2a. Once the control sequencer 96 has determined that either ~ full set of selected analog signsls, or 8 full set of discrete signals, has been fully processed and stored as digital signals in the RAM 92, the contrsl sequencer 96 generates an ~nterrupt signal at its output 96c indicating to the CPU that the data stored in the RAM 92 is available on the information bus 94.
F]GURE 3 is B logic llow diagram il]ustrsting the sequcnti~l steps performed by the control sequencer 96. Initially, ~t block 120, ~U tr~ck-~nd-hold circuits are set in their trsck mode. Also, a control sign~l is applied to the eddress input 80Q of the multiplexer 80 such that the first one of the various input signals to be processed is selected. Further, ~ signal is sent to the control input 92a of the ~AM 92 such that the first signal out of the AtD converter 90 is loaded into the initial address in the RAM 92. Finally, ~ny interrupt at output 96c is cleared.
At decision block 122, the control sequencer tests for the presence of a CPU command. If no command has been received, the control sequencer simply maintains all initial conditions.
Once 8 CPU comm~nd has been received by the control sequencer 96, a finite delay period is instituted at block 124. This finite delay period is to allow sufficient time for the track-and-hold circuits 71-73 to Acguire the signals.
At block 126, upon completion of the finite delay period 124, all of the track-~nd-holds 71-73 are set to their "hold" mode. The A/D converter 90 is then activated to convert the first output from multiplexer 80 to a corresponding digital signal.
At decision block 128, the control sequencer tests for whether or not it has received an "end Or convert" signal from the A/D converter 90. The A/D converter produces the "end of convert" signal to signify that its output digital word is valid. Absent the appropriate "end of convert" si~nQl, the system merely waits. However, once the AID "end of convert" signal is received, the control sequencer 96 responds et block 130 by writing the A/D digital output signal to the RAM 92.
~2~
At block 132, the address to RAM 92 at ~ontrol input 92a Is ~ncremented, dS ~S the address at ~nput 80~, to the multiplexer 80. Then, at decision block 134, a determinstion is made ~s to whether or not ~ total Or three signals has been ~tored in the RAM ga. If ~ total of three signals has not been 5 stored, the system returns to block 126 to process the next selected signal. If, however, either all three analog or ~11 three discrete signals have been processed and stored, an interrupt request is set at block 136 on line 96~ to the CPU
indicating that the RAM 92 is ready to output aU three of its stored digital signals on the information bus 94.
The control sequencer 96 then returns to initialize block 120 awaiting a ~urther CPU command.
Various features of the data acquisition system shown in FIGVRE 2 are of note. First, inasmuch as the system is csp~ble of processing a set o~ three signals in response to each CPU eommand, and produces ~n interrupt signal to the CPU only upon the ~ull digital ~onversion of the three selected sign~ls, commsnds and responses between the CPU and data ~cquisition system are reduced, thereby reducing overhead on the CPU. In addition, by processing signals in sets, errors, such as phasing errors which may be otherwise encoun-tered in monitoring synchro Qnd LVDT signals, may be eliminsted simply by ~electing as signal sets each synchro produced signal and each LYDT related signal. Further, inasmuch as the signal set to be processed by the data acquisition system is under full control of the CPU, as are the gain levels to be applied to each analog signal, the present data acquisition system is sery flexiblc in application, and by sirr.ple software changes to the C~U may be adapted to different applications.
FIGURES 4A-4F are detailed schematic dingrams o~ the prererred embodiment of the data acquisition system. The various analog input signals to the system are divided into five groups, A-E. Each of the analog signsl groups A-E is eonnected to the inputs of one of fi~e input isolation and scaling networks 201-205, respectively. It should be understood thst an input line pair is used to carry each di~ferential analog signal. Each input isolation and scaling network 201-2û5 contains resistor networks which are designed to provide fault feedback current isolation to the input anQlog signals. In addition, each analogsignal may be sca~ed in a voltage divider to ensure signsl level compatibility with the remainder of the data acquisition system circuitry. In addition, built-in test (BIT) signals are applied at the inputs of input isolntion nnd scaling networks 202, 203, 204 and 205. The BIT signals are predetermined DC reference levels which ~23~;9~ -are processed through the system as parametric signals and used by the CPU to determine ~ystem f~ult conditions.
The discrete input ssgnals are divided into three groups A-C. Eech discrete sign~l group A-C Is passed to the inputs of three Input ~solation and bias networks 211-213, respectively. The input ~solation and bias networks 211-213 ensure full fe~dback isolation, bias level setting ~nd filtering, so that the resulting processed discrete signals are compatible with the data acquisition system circuitry.
The output lines from each input isolation and bias network 211-213 ~re passed to the inputs of three discrete sign~l multiplexers 221-223, respectively. Also p~ssed to ~n ~nput of each discrete multiplexer 211-213 is a CPU produ-ed BIT signal on line 214. In the illustrated emb~diment of the invention, esch input isol~tion and bias network 211-213 is cap~ble of h~ndling up to 16 input signsls. Thus, the discrete signal multiplexers 221-223 are 16 channel-type discrete multiplexers. A commerci~lly ~vailable multiplexer ~ircuit suitable for use as each multiplexer 221-223 is the Harris Semiconductortype HI-506A-8.
E~ch of the discrete signal multiplexers 221-223 has four ~ddress inputs labelled "AD". The address inputs AD for each of the discrete signal multiplexers 221-223 are tied to a bus 230. As described hereafter, eddress command signals from the CPU sre routed over the bus 230 to tlle address inputs AD of the discrete signal multiplexers 221-223 causing each discrete sign~l multiplexer 221-223 to output a selected one Or its 16 inputs on its corresponding output terminal, labelled "OUT". The selected output signals from the discrete signal multiplexers 221-223 are passed to the number 3, 4 snd 5 inputs, respectively, of ~n A/D multiplexer 232.
The outputs from the first two input isolation and scaling net-works 201, 202 are passed to the inputs of a pair of dual, eight-channel multiplexers 241, 242, respectively. The ducl, eight-channel multiplexers 241, 242, preferQbly comprised of commercially available type Hl-507A-8 integrated circuits, each include three address input lines, labelled "ADDR" which connect to the bus 230. In response to address signals from the CPU on the bus 230, eachmultiplexer 241, 242 outputs o selected one of its input sn~og signsls at its output lines labelled "OUT A" ~nd "OUT B".
The selected sign~l output from the first dual, eigh~-chnnnel multiplexer 241 is applied ~s an input to a first data acguisition system processor 251. Also Rpplied as inputs to the first dats scyuisition processor 251 are the outputs from the third input isolation and scaling network 203.
~23~
The selected signal output Itrom the second dual, eight-channel multiplexer 242 is fed to the input of a second digital acquisition processor 252.
Also fed 8s lnputs to the second data acqusition system processor 252 are the outputs ~rom the fifth input isolation and scaling network 205. .
The outputs from the fourth input isolation and scaling network 204 are fed to the inputs of a third data acquisition system processor 253.
The use of the dual, eight-channel multiplexers 241, 242 illustrates the convenient manner by which inputs to the dats ecquisition system mey be expanded. By simply including additional multiplexers such as multiplexers 2~1, 242 ~nd input isolstion and scaling networks, such ss networks 201, 202, a user may substantially increase the number of input signals which may be handled by the system.
ERch one of the three dQt~ ~cquisition proce~sors 251-253 includes a multiplexer for the input signals, under the control of an address signal on bus 230 applied to the "ADDR" inputs of each processor 251-253. In this ~ay, each processor 251-253 selects one of its input signals for further processing.
The input signsl selected by the multiplexer in each processor 251-253 is amplified in 8 gain controlled Amplifier by a predetermined gain factor set by the CPU via a digital signal on the bus 230. This 2-bit gain control signal is applied to the inputs labelled "GAIN" in each of the three proces-sors 251-253.
Each processor 251-~53 also includes track-and-hold circuitry which tracks the values of the signals out of the E~in controlled amplifiers andholds the instantaneous value of each amplified signal upon receipt o2 an eppropriate signal at its track/hold control input, labelled "T/H CTRL". This control signsl is provided over Q control line 260 to each of the three proces-sors251-253. The held values out of the three processors 251-253 are provided at the outputs labelled '~/H OUT" and are applied, respectlvely, as the first three inputs to the A/D multiplexer 232.
FIGURE S is d detHiled functional diagr6m illustrating the design of each o the processors 251-253. Each processor is capable of receiving up to eight input signals. These signals are spplied to the inputs o2 a multiplexer 300.
The multiplexer 300 responds to a 3-bit address signal at its "AVDR" input line to select one of the eight input signsls. Each lead sf the selected signal is passed to the noninverting input of one of a pair of buffer amplifiers 302~ 303.The buffer amplifiers are connected in a unity gain con2iguration. As such, eachinput line is isolated from source resistances external to the processor, thereby 9~;
preservlng Q high common mode re~ection ratio. Also, the buffers provide ~ high ~nput imped~nce for esch of the signals.
The outputs rom the buffer amplifiers 302, 303 Qre fed to the input of a gain ~ontrollable ~mplifier, indicated generally st 310. The gain controllable ~mplifier 310 is comprised of first snd second sets 312, 314 of series input g~in control resistors, the common connection of which connect to the outputs of buffer amplifiers 302, 303, respectively. A multiplexer 316, under the control of the 2-bit !'GAlNr ~ommand from the CPU, connects a selected resistor in esch series resistor bsnk 312, 314 to a corresponding ~nput of an operational amplifier 320. A pair of parallel resistor banks 322, 324 connect inparallel from output to input of the operational smplifier 320 through the multip~exer 316. The low side of the signsl is passed through a buffer ~mplifier 330, designed for unity g~in, to maintain n high common mode rejection ratio.
In response to the 2-bit signal on the "GAIN" ~ontrol input lines, the multiplexer 316 connects a selected one of the series input resistors 31a, 314, and a corresponding one of the parallel resistors 322, 32~ as a g~in control circuit for oper~tionsl smplifier 320. The resulting gain f~ctor produced by theover~ll amplifier 310 is, thus, a function of the ~lalues of the resistors 312, 314, 322, and 324. In the preferred embodiment of the invention, the resistor values sre selected such that gains of 1, 2, 4 or 8 are reali~ed.
The output from the gsin controllable nmplifier 310 drives the buffer amplifier 340 of the track-~nd-hold circuit, indicated within the dotted line 342. Upon receipt of R "HOLD" signal at the "T/H CONTROL" input, the tr~ck-and-hold circuit 342 eloses un internsl switch 344 connecting the input signal to the input of a second amplifier 346 and to a holding capacitor 348. The output rom amplifier 346 in the hold mode is the held level, on cspacitor 348, of the input signsl at the time 8 "hold" control signsl W85 received. This signal is provided at the output of the tr~ck-and-hold circuit 342. With switch 344 open (as shown), the track and-hold circuit 342 produces the buffered, g~in controlled signal at its output labelled 'rr/H OUT".
In the preferred embodiment of the invention, the process-ors 251-253 are comprised of commercially available type Hl-5900 devices.
Returning to FIGURES 4A-4F, the A/D multiplexer 232 selects one of its six input signals in response to a 3-bit signal ~t its ~ddress inputs, labelled "A0-A2." The A0, Al lines are provided out of the control sequencer circuitry, on lines 400, 401, and select one of the three anslog input signals snd one of the 9~;
-~6-thsee input discrete sign01s. The A2 input, t~ken of of bus 230, selects either qn analog or ~ discrete sign~l.
The A/D multiplexer may be comprised of a commercially avail-able type Hl-508A8 device.
The selected output signal from the A/D multiplexer 232 is buf-fered through a unity gain amplifier 404 and psssed to the input, labelled "EINn, of an A/D converter 406. The A/D converter 406 responds to s "st~rt convert"
signal on input line 408 to ~nalog-t~digital convert signals applied ~t the input of the converter 406. The conversion process takes place at the rste of a clock signal, provided ~n line 410. Upon completion of sn analog-t~digital conversion,the con~lerter 406 produces U~ "end of conversionr signal which Qppears on the output line 412. The AJD converter 406 is, in the preferred embodiment of the invention, a 12-bit converter, producing a 12-bit digital output Q0-Q11. The A/D converter 4D6 may be comprised o~ 8 commercially available type AD5215 device.
The 12-bit digit~l signal output from the A/D converter 406 is csrried on 8 twelve line bus 414 to the inputs of three 4-bit by 4-bit random access memories (RAMS) 421-423 configured to ~orm ~ 12-bit by 4-bit arrQy capable of storing up to lour 12-bit signals out of the A/D converter 406. Data is ~ddressed into the RANIS 421-~23 vis write address lines 400, 401, provided out of the control sequencer. The control sequencer ~lso provides a write ensblesign61 on a line 424.
In turn, data is read out of the RAMS 421-423 under control of the CPU via read ~ddress lines 431, 432 and a resd enable line 433. Output date from the RAMS 421-423 is buffered through bus drivers 441, 442.
The RAMS 421-423 may be comprised of commercially available type 52LS670 integrated circuits, whereas the bus drivers 441, 442 mQy be comprised of commercially avsilable type 54LS373 integr~ted circuits.
The control sequencer, indicsted generslly at 450, is comprised of a programmable srrsy logic device 452 ~nd a 5-bit binary counter 454. The control sequencer 450 responds to an input/output signal on lines 455, 456 to produce the hold comm~nd applied to the processors 251-253 on line 260. Afler Q finite time period, determined by the 5-bit binary counter 454 counting clock pulses from s clock 460, the control sequencer 450 ectiv~tes its output line 408to institute the analog-to~igit~l conversion process. Once the conversion process h~s been completed or the selected three signal set, the controi seguencer 450 responds to an end-of conversion signal on line 41a to produce an interrupt request on output line 470.
The programmable arrsy logic device 452 mQy be comprised of a commerei~lly avail~ble type MM116R8-4 device, whereas the 5-bit binary counter 454 may be comprised of B 4024B device.
The CPU supplies information to, Qnd extr~cts data from the dstQ
5 acquisition system via a 16 line information bus 500. Connected to the data bus 500 are the outputs from the bus drivers 441, ~42. In this way, parametric dats stored within the RAMS 421-423 may be output to the CPU.
Input commands from the CPU on the information bus 5ûO are passed to four input ports 601-604. Upon receipt of a clock pulse st its CP
input, each input port 601-6û~ passes the signals ~t its inputs D0-D7 to its output lines Q0-Q7. Most ôf the d~t~ on the output lines Q0-Q7 of ~he input ports 601-604 is directed to the individual processors 251-253 and provides eachprocessor with ~ddress in~ormation for selecting a desired input signal and gsininformation for multiplying the selected signal by 8 selected gain factsr. In addition, cert~in output lines from the input ports 601-6M sre fed to the discrete multiplexers 221-223 to select the desired set of three discrete signals.
Also, special function lines are pro~ided. For example, line 230 indicates to the A/D multiplexer 232 whether the ~nalog signal set or the discrete signal set is to be selected. ln addition, line 214 carries the CPI~ produced BIT sign~l to the discrete multiplexers 211-213 The input ports 601-60~ m~y be comprised of commercially avail-able type 54LS374 integrated circuits.
The CPU accesses the data acquisition system by mesns of e control bus 700. The control bus 70û connects to input/output logic comprised offirst ~nd second address latches 701, 702, an address compare circuit 703 and anaddress decode circuit 704. The eight most significant bits of the information bus 500 ~re fed to the eight data inputs D0-D7 of the first address latch 701.
The two least significant bits of the information bus are fed to the D2, D3 inputs, respectively, of the second address latch 702. Applied to the D0 input of Qddress latch 702 is a CPU produced signal indicating whether R memory instruction ~ddress or an input/output command is being applied on the informa-tion bus. The Dl input of the second ~ddress latch 702 receives a CPU produced signal indicating whether the CPU is to read information off the informstion bus, or write information for the data ~c~uisition system on the information bus. Thefirst and second address lstches 701, 702 Are enabled by a CPU signal strobe A.
The ~ddress decoder 704 is enabled by a strobe D sign~l from the CPU.
The Q0-Q7 outputs from the first sddress latch 701 feed to the address inputs of the ~ddress compare eircuit 703. The E~O-B7 addresses of
30 and, under CPU control, are passed over a data bus to the solid stste memory devices. Progrsmming within the CPU controls the processing of input airplane ~23965~;
~Ignsls to corresponding digital s~gnals through the DAS ~nd the subsequent transference of these digital signals to controlled locations in the solid statememory.
The signRls representstive of monitored aircra~t parameters are 5 typically either discrete level signals or analog signals. Discrete signals are typically switch posltions and produce either a high or a low level output depending upon the status of the particular switch. A typical exumple ~n an aircraft is a squat switch, which indicates whcther or not a load is being borne by the lsnding gear. The analog signals may be either straight DC signals, DC
lD ratiometric signals, synchro signals or AC ratiometric signals. The DC signPls are static in nature, and generally range between a minimum and maximum vslue for the parameter belng monitored. DC ratiometric signals are DC signals hsving a rAtio representative of the value of the parame~er being sensed. A
typical DC r~tiometric signal Is th~t produced by a potentiometer having a DC
15 voltage applied across its tesistive element, with the wiper position indicative of the level o~ the sensed parameter. Thus, the ratio o~ the wiper voltage to She voltage across the potentiometer's resistive eiement represents the level of theparameter being monitored.
Synchros are commonly employed to indicate the angle of ~
20 parameter. A synchro sensor is normally excited by two reference AC signals and outputs three active AC signals. The relative phasing and amplitude between the active AC signals and the reference signals indicate the angle of the synchro and, thus, the angle of the sensed parameter.
A typicsl AC ratiometric aircraft signal is that produced by a 25 linear variable differential tranformer tLVDT). LVDTs are commonly employed to indicate the relative position of aircraft control surfaces. Here, the ratio of the LVDT output sense AC signal to ~ reference AC signal is indicative of both total deflection and direction of deflection of the ~ontrol surface.
To ~ccurately collect d~ta from synchro snd ratiometri~type 30 sensors, therefore, the DAS should simultaneously colleet and hold each signal associated with the multisignal-type sensor.
~ urther, it is desirable to minimize the overhead on the CPU in itsaccessing of data as collected by the DAS. In prior art flight dat~ recorder designs, the CPU sends a request to the DAS asking for the value of a given 35 aircraft parameter and this parameter is then selected, processed, and analog-to-digital converted by the DAS which then signals the CPU th~t the requested information is available. Since ~ Isrge number of -airplane parameters may be ~23~g6 monitored by the night data recorder, constant requests by the CPU on the D~S
significsntly Increases CPU overhe~d.
Purther, ~t is desirable to conform the night data recorder such that it ~s ~apabl2 of being conveniently modified to operate ~n ~ny one Or several different types of aircraft. To this end, the DAS is preferably configured such that its inputs may be assigned by the CPU to handle any analog or discrete input sign61. Further, he levels of the various signals at the inputs of the DAS mustoften be scaled for proper processing within the DAS. For example, in~smuch as all input signals are analog-to-digital (A/D) converted, the DAS typically includes a convention~l A/D converter. The accuracy of an A/D converter is n function of the signal level applied at the input to the converter. To minimize A/D c~nverter errors, herefore, ~t is essentiQI that eAch ~ircraft parameter sensor signal be scaled before being applied to the A/D converter. In order to assure 8 universal 1ight data recorder design, the scaling factors applied to each ~5 input signal should be under CPU eontrol.
Summary of the Inveneion The present invention, therefore, is directed to R da-a acquisition systern for use in a flight data recorder. An aspect of the present invention isthe ability of the data acquisition system to process R set of parameter sense signals 5n response to a single CPU request. In this way, integrity of multiple signal sensor data is sssured and overhead on CPU operation is r educed.
A further aspect of the invention is the universal applicstion of the present data acquisition system. Analog or discrete aircraft parameter signals m~y be assigned to ~ny of the multiple data acquisition system inputs under CPU
control. Further, the DAS is responsive to CPV control to vsry the scaling applied to each input signal.
Briefly, according to the invention, a data acquisition system for an aircraft flight data recorder is responsive to n central processor unit (CPU)for selectively processing a plurality of input signAls. The data acquisition system comprises a multiplexer which outputs selected sets of the input signals, with each selected input signal set being output responsive to a corresponding address command signal. Logic is responsive to a single command from the CPU
for producing each address command signal. Each sign~l in a selected signsl set is processed by provided processing means.
Preferably, the processing means includes gain controlled amplifiers which respond to gain control ~ommand signals from the CPU for amplifying eAch signal in a selected sign~l set by a predelermincd g~in fActor.
~239~i9f~
Track-an~hold clrcuitry tracks the v~lue of each umplified signal 3n e selected ~ignal set and, ~n response to a hold cornmand signal, holds the Jnstantaneous value ~f each amplified signal. An ~malog-to-digital converter converts esch signsl st ~ts input to a corresponding digital signal at its output. A controller predeterminedly couples the Instantaneous value of each signal in the selected signal set to the input of the analog-to-digital converter.
In addition, Jnput scaling circuits may be provided for attenuating selected input signals by a predetermined scaling factor. The gain factors for the gain controlled smplifiers ~re selected such that each signal, after being attenusted in the Jnput scaling circuit snd amplified by the gain controlled amplifier has ~ leYel in a range selected to minimize analog-to digital comerter error.
Prefer~bly, the data ncquisition system includes digital memory for ~toring each analog-to-digital converted instantaneous value of a signal in a selected signal set. The controller produces an interrupt signal to the CPU uponall of the snslog-to~igital converted instantaneous values of the signals in a selected sign~l set belng stored In the digital memory.
Preferably, the logic circuit responds to a single CPU command siKnal to:
a) produce a predetermined ~ddress command signal such that the multiplexer outputs the set of selected input signals, b) produce predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and c) activate the controller such that the analog-to-digital con-verted instantaneous value of each signsl in a selected signal set is loaded into the digit~l memory.
For ~pplications wherein at least three of the input signals to the data acguisition system are the output signals from a synchro sensor, the logic 30 circuit produces an address command signal causing the multiplexer to output the three synchro signals as a selected signal set.
In applications wherein at least one of the input signals is sn AC
ratiometric signal and at least one of the input signals is the reference AC signal for the AC ratiometric signal, the logic circuit produces an ~ddress command 35 signal causing the multiplexer to output the AC ratiometric and rererence AC
signal as a selected signal set.
Brief Description of the Drawin~s ~ IGURE I ~s a block diagram Illustrating the principal components of ~ solid state tlight data recording system employing A data acguisition system;
FIGURE 2 ~s a block diagram ~llustrating the principal components 5 of the preferred dqta acquisition system;
FIGl~RE 3 is a logic flow diagram illustrating the sequential steps performed by the control sequencer of the preferred dat6 acquisition system;
FIGURES 4A-4F are detailed schematic diagrams showing the preferred construction of the dsts acquisition system; and FIGURE 5 is a detailed schematic diagrsm sf the data acquisition signal prGcessors used in the data scquisltion system.
Detailed Description FIGU~E I a block diagrAm illustsating the principsl c~>mponents of a solid state flight data recording system, shown enclosed within dotted line 10. A night data recorder JS ~arried aboard an ~ircraft and systematically monitors and stores information related to aircraft parametric data. Such recorded data may be analyzed at a subsequent time to yield information related to the source of an ~ircraft mishap, or simply to provide a diagnostic and information tool as to the air~raft's performance.
The flight data recorder must be capable of receiving and proces-sing three distinct types of parametric data. The first dats grouping is analog data, indicated by block la. The analog data may be any one of four distinct types. Information related to an angle, such as engine nozzle position, is commonly provided by a synchro sensor. Each synchro sensor typically provides 25 three active signals Sl, S2 and S3 which are phase and amplitude related to areference signal (commonly 400 Hz in aircraft). By processing the three active signals in the known manner, the angle of the parhmeter being monitored is derived.
A second type of analog dats is AC ratiometric data. AC
30 ratiometric data is commonly provided in aircraft by a sensor known as a linear variable differential tranformer (LVDT). An LVDT is typically employPd to monitor the position of an aircraft control surfAce. It is stimulated by an AC
reference signal, and produces an AC output signal. She ratio of these two signals is related to relative movement between component parts of the LVDT
35 nnd, thus, deflection of the control surface being monitored.
Finally, analog data signals may be either DC or ratiometric DC
signals. The standard DC signals are voltsge levels which vary within a defined range, the magnitude of which is indicative of the status of the parameter being ~23969~i -monitored. Ratlometric DC ~ignals are slgnal pairs, the ratio of which is indicative of the parameter being monitored. An example of a ratiometric DC
~ignal is the output from a potentiometer. Typically, a voltage Is ~pplied across the resistive element of the potentiometer, this voltage constituting the first S ratiometric signal. The wiper of the potentiometer is linked to the parameter being monitore~ such that ~t moves in response to parameter changes. As such, the ratio of the wiper voltage to the total resistive element ~oltage is indicative of the value of the parameter being sensed. Examples Or ratiometric DC signals produced in aircraft are rate signals such as pitch, yaw and roll.
Discrete data, indicated by block 14, are signals which assume either a low or a high state ~n response to the status of the parameter being monitored. Such signals are, commonly, produced by switches, an example being the aircraft squat switch which produces H discrete output indicating whether ornot the aircraft landing gear is under load.
FinRlly, the flight data recorder receives digital data, as indicated by block 16. The digital dsta originates from other systems within the Rircrsft.For example, digital inlormation indicative of navigation information, as produced by aircraft onboard navigation computers, may be provided to the night data recorder.
Both the analog data 12 and the discrete data 14 are processed within the night data recorder through a data acquisition system 18. The function of the data acquisition system 18 is to receive each analog and discrete input signal and, under external control, sequentially convert each input signal to a corresponding digital signal. The digital signals are then output on a system bus 20. The data acguisition system 18 is described in detail hereafter.
A controller 22 receives the input digital da-a from the aircraft systems 16. The controller 22 provides any signal conditioning required and is responsive to external control to output the digital data on system bus 20.
Overall control for the flight data recorder is provided by a central processing unit (CPU) 24. Associated with the CPU 24 is a read-only memory (ROM) 26 which contains the programming used by the CPU 24. Also associated with CPU 24 is random access memory (RAM) 28 which is used by CPU 24 ss required for temporary storage.
Also attached to the system bus 20 are three controllers 31-33.
The first controller 31 connects to the crash survivable memory unit 34. The crash survivable memory unit 34 is a solid state memory storage which is housed within a container designed to survive an aircralt crash.
~23~i96 Connected to the output of controller 32 is an ~uxiliary memsry unit 36. As with the crash survivable memory unit 34, the auxiliary memory unit 36 Includes solid state, electronle memory. Electrically erasable program mable re~d-only memory (EaPROM) may be used as the storage devlces in either 5 the crash survivable memory unit 34 or the auxiliary memory unit 36.
The output from controller 33 is adapted for connection to ground read out equipment 38. Once the aircraft has landed, intormation stored within the crash survivable memory unit 34 or the auxiliary memory unit 36 may be accessed by the ground read out equipment 38 and stored on magnetic tape or 10 other perm~nent storage medium.
Operation of the flight data recorder, shown in FIGURE 1, is understood QS follows. The CPI~ 24, in response to its prc>gr~mming stored in ROM 26, sends commands to the data acquisition system 18 instructir~ that certain sets Or analog deta 12 or discrete data 14 be converted to corresponding15 digital signals. In addition, as will be discussed in more detail with respect to PIGllRE 2, commands from the CPU 24 cause the data ~cquisition system 18 to level adjust each of the processed analog signals. Once the set of ~nalog or discrete data signals has been processed, the data acquisition system 18 notifies CPV 24 by an appropriate interrupt signal over ~n interrupt line Qssocisted with20 the system bus 20.
Similarly, the CPV 24 msy ~ccess any di~ital data from the ~ircraft systems 16 via commands to the controller 22.
In response to the digitsl parametric signals from the data a~quisi-tion system 18 ~nd the aircraft systems 16 through controller 22, the CPU
25 performs any further signal processing required, such as conYerting synchro or LVDT signals to corresponding angle or position signals, respectively, therearter loading the digital signals into either the crash survivable memory unit 34 or the suxili~ry memory unit 36 via commands to the appropriate controllers 31, 32, respectively. Typically~ parametric data relevant to system ~ailures on the 30 sircraft is loaded into the crash sur-/ivable memory unit 34, whereas data which is informational in nature is routed to the auxiliary memory unit 36.
Upon landing, the ground read out eguipment 38 is sttached to the system .ria controller 33 ~nd, by appropriate commands to the CPU 24, da~a stored within the crash ss~rvivsble memory unit 34 ~nd the ~uxiliary memory 35 unit 36 msy be read out and loaded into permanent storage.
FIGURE 2 is a detailed block diagram of the dat~ ~cquisition system 18 ~s shown in FIGURE 1. Input to tl~e data acquisition sys~em are a series of ~nalog input s~gnals, indicated generally at 50, and ~ series of discrete input si~nals, indicated generally at 52.
Each anal~g ~ignal is fed over 8 line to an Input of an isolation and scaling network 54. The input Isolation and scaling networks ~re comprised of 5 passive ~omponents, namely precision resistors and capscitors which scale ea~h~nput signal to ensure feedback fault isolation and, further, to optimize the sîgns~ ~loltage range prior to analog-t~digital processing, QS Will be describedhereafter.
Also applied es an input to the isolation nnd scaling networks 54 is 10 a built-in test (BIT) signsL This signal is 8 predetermined, known voltage level signal which is ~pplied to the system input and monitored st the output to identify any syst~m processing errors.
Each scaled (attenuated) input analog signal is passed over a line to an input o~ a multiplexer network 56 comprised of three multiplexers. The 15 multiplexer network 56 responds to a digital signsl applied to its address bus 58 to selectively output a set of three input analog signals. The selected ana~og signals appear on multiplexer network output lines 56B-56C.
A feature of the data acquisition system is that in respon~e to one ~ommand input from the CPU (FIGURE 1), a predetermined set (here a set of 20 three) of snalog signals is selected for processing. In this way, overhead on the CPU is reduced (by reducing commands and interrupts between the CPl~ and the data ~cquisition system) and the phase integrity of synchro and AC ratiometric signals is preserved. Thnt is, for analog input signals corresponding to the S1, S2 and S3 active synchro output signals, these three signals are selected as a se 25 and, as such, are simultaneously processed by the data acquisition system, thereby eliminating errors due to monitoring the synchro lines at slightly different times. For LVDT signals, both the return signal and the reference signals are processed simultaneously, thereby elso avoiding phase related errors.
Also, for two LVDTs sharing a common reference signal, a set can include each 30 LVDT signal and the single reference signal, thereby avoiding the need to access the re~erence signal twice.
Each output line 56a-56c from the multiplcxer network 56 con-nects to the input of a gain controlled amplifier 61-63, respectively. Each gaincontrolled amplifier 61-63 has a gain control input 61a-63a, respe~tively, ~nd, in 35 response to a command over its gain control input, cach gain controlled smplifier 61-63 amplifies a signal at its input by 8 predetermincd gain factor.
The amplified signaLs at the outputs o~ gnin controlled ampli-fiers 61-63 are applied st the inputs to three track-and-hold circuits 71-73, ~23~6~6 respectl~ely. EOEch tr~ck-and-hold circuit 71-73 7-as a hold command input line 71a-73a, respectively. The track-an~hold circuits 71-73 operate to tra~k the levels of the signals out of gain controlled ~rnplifiers 61-63 until a hold commGnd signal is received. Once a hold command signal is received, each track-and-hold circllit 71-73 produces at its output the held level of the signal Rt its input st the time of receipt of U~e hold command. The three held signal le~rels are applied via output lines from the track-~nd-hold circuits 71-73 to three inputs of a multiplexer 80.
Each 9f the discrete input signals 52 is carried over e line to an input vf the isol~tion ~qnd Uas networks 82. As with the isolation and scaling networks 54, the Isol~tion and bias networks 82 ensure feedb~ck fault isol~tion and, if reguired, input s~ale or input biHs each discrete signal to make it compatible with subsequent data ~cquisition system processing circuitry.
Also applied as an input to the isolation and biss networks 82 is ~
built-in test (BIT) signal which is a predetermined leve] sign~l used to check the accur~cy of system processing.
Eech discrete input signal and the BIT signal ~re processed through the isolation and bias networks 82 and applied as ~n input to a multiplexer 84.
Multiplexer 84 has an address bus input 86 and, in response to digital addresseson address bus 86, selects a set of three dlscrete input signals which appear onthe multiplexer 84 output lines 84a-84c. The selected discrete signal set is ~pplied to the remaining three inputs of the multiplexer 80.
The multiplexer 80, in response to an address command provided at its address input 80a, sequentially p~sses a selected signal at its input to themultiplexer output 80b. The output 80b of multiplexer 80 connects to the input of an an010g-t~digital SA/D) converter 90. In the known manner, A/D cor~
verter 90 converts each signal applied at its input to a corresponding digitsl signal at its output.
Each digital sig~al ~ppearing at the output of A/D converter 90 is ~pplied to the input of a random access memory (RAM) 92. The RAM 92 responds to control signals at its control input 92~ to loHd each digitHI signal at its input into ~n appropriate storage location. Further, upon receiving an ~ppropriate command at its command input 92a, RAM 92 outputs its stored digital values on the system information bus 94 which connects to the CPU.
Control signals to the multiplexer 80 and tl-e RAM 92 are provided by a control sequencer 96. Control sequencer 9fi receives ~ control input sign~lat its input 96a and a clock signal, from e clock 98, at its clock input 96b. Also, control sequencer 96 is capable of producing an interrupt signal at its output 96c ~239~6 which leads to the CPV. In ~dditlon, the control sequencer 96 provides a hold control output ~6d wh~ch is ed to the hold control 3nputs 71a-73Q of the track-and-hold circuits 71-73, respectively.
Both the control bus and the information bus from the CPU are fed to the input/output (I/O) control circuitry 100 nssociated with the dat~ ~guisi-tion system. Also, ~he CPU Information bus is applied to the input o~ a set sf input ports 102. The input ports 102 produce a set of gain control sign~ls, on lines 102a, which are applied to the gain control inputs 61a-63~ of the gain controlled amplifiers 61-63, respectively. Also appearing as an output o~ the lD input ports 102 on output lines 102b are the multiplexer address signals which are coupled to the multipl~xers 56 ~nd 84. A control line 102c from input ports 102 connects to input 96a of control sequencer 96. Finally, a control line 102d out of the input ports 102 is fed to the control input ~6a of the control sequencer 96.Operation of the data acquisition system shown in FIGURE a is understood as follows.
The CPU accesses the data acquisition system by applying an appropriste address signal over the control bus which is recognized, and responded to by the l/O control 100. A CPU produced signal on the Wormation bus is processed by the input ports 102 which produce an appropriate multiplexeraddress output on outpùt lines 102b. In response to this address, the multiplexer networlcs 56, 84, select a set of three analog signals and three discrete signals, respectively. The selected set of three discrete signals are applied directly asinputs to multiplexer 80. The selected set of three analog signsls, appearing onoutput lines 56a-56c o- multiplexer network 56, are coupled as inputs to the gain controlled amplifiers 61-63. Esch gain controlled amplifier 61~63 receives at its gain control input 61a-63a, respectively, a gain control signal as coupled from the information bus through input ports 102 and applied on output lines 102a.
The accuracy of A/D converter 90 is dependent upon the level of the input signal. Thus, to minimize A/D errors, the CPU selects a gain for the gain controlled amplifiers 61-63 which, in association with the attenustion to each input signal provided by the isolation and scaling networks 54, level adjusts each analog signal for minimum A/D converter error.
A hold control signal ~t output line 96d rrom the control sequencer 96 causes the track-an~hold circuits 71-73 to output a held level of the gain factored anslog signals. These held values appear at the input to multiplexer B0.
The control sequencer 96 receives a control signal at its control input 96a from the control output 102c of the input port 102 indicating that the ~3~696 CPU ~s requesting processed psrametric data. ln response, the control ~equencer 96; at a r~te determined by the clock 9B, sequentially passes, ViQ
Appropriste ~ddresses to control input 80a, each signal at the input o multi-plexer 80 to the multiplexer output line 80b where it is then A/D converted by converter ~0. The corresponding digitel signal out of converter 90 is then loaded into an address in RAM 92 determined by the control sequencer 96 produced signal at the control input ~2a. Once the control sequencer 96 has determined that either ~ full set of selected analog signsls, or 8 full set of discrete signals, has been fully processed and stored as digital signals in the RAM 92, the contrsl sequencer 96 generates an ~nterrupt signal at its output 96c indicating to the CPU that the data stored in the RAM 92 is available on the information bus 94.
F]GURE 3 is B logic llow diagram il]ustrsting the sequcnti~l steps performed by the control sequencer 96. Initially, ~t block 120, ~U tr~ck-~nd-hold circuits are set in their trsck mode. Also, a control sign~l is applied to the eddress input 80Q of the multiplexer 80 such that the first one of the various input signals to be processed is selected. Further, ~ signal is sent to the control input 92a of the ~AM 92 such that the first signal out of the AtD converter 90 is loaded into the initial address in the RAM 92. Finally, ~ny interrupt at output 96c is cleared.
At decision block 122, the control sequencer tests for the presence of a CPU command. If no command has been received, the control sequencer simply maintains all initial conditions.
Once 8 CPU comm~nd has been received by the control sequencer 96, a finite delay period is instituted at block 124. This finite delay period is to allow sufficient time for the track-and-hold circuits 71-73 to Acguire the signals.
At block 126, upon completion of the finite delay period 124, all of the track-~nd-holds 71-73 are set to their "hold" mode. The A/D converter 90 is then activated to convert the first output from multiplexer 80 to a corresponding digital signal.
At decision block 128, the control sequencer tests for whether or not it has received an "end Or convert" signal from the A/D converter 90. The A/D converter produces the "end of convert" signal to signify that its output digital word is valid. Absent the appropriate "end of convert" si~nQl, the system merely waits. However, once the AID "end of convert" signal is received, the control sequencer 96 responds et block 130 by writing the A/D digital output signal to the RAM 92.
~2~
At block 132, the address to RAM 92 at ~ontrol input 92a Is ~ncremented, dS ~S the address at ~nput 80~, to the multiplexer 80. Then, at decision block 134, a determinstion is made ~s to whether or not ~ total Or three signals has been ~tored in the RAM ga. If ~ total of three signals has not been 5 stored, the system returns to block 126 to process the next selected signal. If, however, either all three analog or ~11 three discrete signals have been processed and stored, an interrupt request is set at block 136 on line 96~ to the CPU
indicating that the RAM 92 is ready to output aU three of its stored digital signals on the information bus 94.
The control sequencer 96 then returns to initialize block 120 awaiting a ~urther CPU command.
Various features of the data acquisition system shown in FIGVRE 2 are of note. First, inasmuch as the system is csp~ble of processing a set o~ three signals in response to each CPU eommand, and produces ~n interrupt signal to the CPU only upon the ~ull digital ~onversion of the three selected sign~ls, commsnds and responses between the CPU and data ~cquisition system are reduced, thereby reducing overhead on the CPU. In addition, by processing signals in sets, errors, such as phasing errors which may be otherwise encoun-tered in monitoring synchro Qnd LVDT signals, may be eliminsted simply by ~electing as signal sets each synchro produced signal and each LYDT related signal. Further, inasmuch as the signal set to be processed by the data acquisition system is under full control of the CPU, as are the gain levels to be applied to each analog signal, the present data acquisition system is sery flexiblc in application, and by sirr.ple software changes to the C~U may be adapted to different applications.
FIGURES 4A-4F are detailed schematic dingrams o~ the prererred embodiment of the data acquisition system. The various analog input signals to the system are divided into five groups, A-E. Each of the analog signsl groups A-E is eonnected to the inputs of one of fi~e input isolation and scaling networks 201-205, respectively. It should be understood thst an input line pair is used to carry each di~ferential analog signal. Each input isolation and scaling network 201-2û5 contains resistor networks which are designed to provide fault feedback current isolation to the input anQlog signals. In addition, each analogsignal may be sca~ed in a voltage divider to ensure signsl level compatibility with the remainder of the data acquisition system circuitry. In addition, built-in test (BIT) signals are applied at the inputs of input isolntion nnd scaling networks 202, 203, 204 and 205. The BIT signals are predetermined DC reference levels which ~23~;9~ -are processed through the system as parametric signals and used by the CPU to determine ~ystem f~ult conditions.
The discrete input ssgnals are divided into three groups A-C. Eech discrete sign~l group A-C Is passed to the inputs of three Input ~solation and bias networks 211-213, respectively. The input ~solation and bias networks 211-213 ensure full fe~dback isolation, bias level setting ~nd filtering, so that the resulting processed discrete signals are compatible with the data acquisition system circuitry.
The output lines from each input isolation and bias network 211-213 ~re passed to the inputs of three discrete sign~l multiplexers 221-223, respectively. Also p~ssed to ~n ~nput of each discrete multiplexer 211-213 is a CPU produ-ed BIT signal on line 214. In the illustrated emb~diment of the invention, esch input isol~tion and bias network 211-213 is cap~ble of h~ndling up to 16 input signsls. Thus, the discrete signal multiplexers 221-223 are 16 channel-type discrete multiplexers. A commerci~lly ~vailable multiplexer ~ircuit suitable for use as each multiplexer 221-223 is the Harris Semiconductortype HI-506A-8.
E~ch of the discrete signal multiplexers 221-223 has four ~ddress inputs labelled "AD". The address inputs AD for each of the discrete signal multiplexers 221-223 are tied to a bus 230. As described hereafter, eddress command signals from the CPU sre routed over the bus 230 to tlle address inputs AD of the discrete signal multiplexers 221-223 causing each discrete sign~l multiplexer 221-223 to output a selected one Or its 16 inputs on its corresponding output terminal, labelled "OUT". The selected output signals from the discrete signal multiplexers 221-223 are passed to the number 3, 4 snd 5 inputs, respectively, of ~n A/D multiplexer 232.
The outputs from the first two input isolation and scaling net-works 201, 202 are passed to the inputs of a pair of dual, eight-channel multiplexers 241, 242, respectively. The ducl, eight-channel multiplexers 241, 242, preferQbly comprised of commercially available type Hl-507A-8 integrated circuits, each include three address input lines, labelled "ADDR" which connect to the bus 230. In response to address signals from the CPU on the bus 230, eachmultiplexer 241, 242 outputs o selected one of its input sn~og signsls at its output lines labelled "OUT A" ~nd "OUT B".
The selected sign~l output from the first dual, eigh~-chnnnel multiplexer 241 is applied ~s an input to a first data acguisition system processor 251. Also Rpplied as inputs to the first dats scyuisition processor 251 are the outputs from the third input isolation and scaling network 203.
~23~
The selected signal output Itrom the second dual, eight-channel multiplexer 242 is fed to the input of a second digital acquisition processor 252.
Also fed 8s lnputs to the second data acqusition system processor 252 are the outputs ~rom the fifth input isolation and scaling network 205. .
The outputs from the fourth input isolation and scaling network 204 are fed to the inputs of a third data acquisition system processor 253.
The use of the dual, eight-channel multiplexers 241, 242 illustrates the convenient manner by which inputs to the dats ecquisition system mey be expanded. By simply including additional multiplexers such as multiplexers 2~1, 242 ~nd input isolstion and scaling networks, such ss networks 201, 202, a user may substantially increase the number of input signals which may be handled by the system.
ERch one of the three dQt~ ~cquisition proce~sors 251-253 includes a multiplexer for the input signals, under the control of an address signal on bus 230 applied to the "ADDR" inputs of each processor 251-253. In this ~ay, each processor 251-253 selects one of its input signals for further processing.
The input signsl selected by the multiplexer in each processor 251-253 is amplified in 8 gain controlled Amplifier by a predetermined gain factor set by the CPU via a digital signal on the bus 230. This 2-bit gain control signal is applied to the inputs labelled "GAIN" in each of the three proces-sors 251-253.
Each processor 251-~53 also includes track-and-hold circuitry which tracks the values of the signals out of the E~in controlled amplifiers andholds the instantaneous value of each amplified signal upon receipt o2 an eppropriate signal at its track/hold control input, labelled "T/H CTRL". This control signsl is provided over Q control line 260 to each of the three proces-sors251-253. The held values out of the three processors 251-253 are provided at the outputs labelled '~/H OUT" and are applied, respectlvely, as the first three inputs to the A/D multiplexer 232.
FIGURE S is d detHiled functional diagr6m illustrating the design of each o the processors 251-253. Each processor is capable of receiving up to eight input signals. These signals are spplied to the inputs o2 a multiplexer 300.
The multiplexer 300 responds to a 3-bit address signal at its "AVDR" input line to select one of the eight input signsls. Each lead sf the selected signal is passed to the noninverting input of one of a pair of buffer amplifiers 302~ 303.The buffer amplifiers are connected in a unity gain con2iguration. As such, eachinput line is isolated from source resistances external to the processor, thereby 9~;
preservlng Q high common mode re~ection ratio. Also, the buffers provide ~ high ~nput imped~nce for esch of the signals.
The outputs rom the buffer amplifiers 302, 303 Qre fed to the input of a gain ~ontrollable ~mplifier, indicated generally st 310. The gain controllable ~mplifier 310 is comprised of first snd second sets 312, 314 of series input g~in control resistors, the common connection of which connect to the outputs of buffer amplifiers 302, 303, respectively. A multiplexer 316, under the control of the 2-bit !'GAlNr ~ommand from the CPU, connects a selected resistor in esch series resistor bsnk 312, 314 to a corresponding ~nput of an operational amplifier 320. A pair of parallel resistor banks 322, 324 connect inparallel from output to input of the operational smplifier 320 through the multip~exer 316. The low side of the signsl is passed through a buffer ~mplifier 330, designed for unity g~in, to maintain n high common mode rejection ratio.
In response to the 2-bit signal on the "GAIN" ~ontrol input lines, the multiplexer 316 connects a selected one of the series input resistors 31a, 314, and a corresponding one of the parallel resistors 322, 32~ as a g~in control circuit for oper~tionsl smplifier 320. The resulting gain f~ctor produced by theover~ll amplifier 310 is, thus, a function of the ~lalues of the resistors 312, 314, 322, and 324. In the preferred embodiment of the invention, the resistor values sre selected such that gains of 1, 2, 4 or 8 are reali~ed.
The output from the gsin controllable nmplifier 310 drives the buffer amplifier 340 of the track-~nd-hold circuit, indicated within the dotted line 342. Upon receipt of R "HOLD" signal at the "T/H CONTROL" input, the tr~ck-and-hold circuit 342 eloses un internsl switch 344 connecting the input signal to the input of a second amplifier 346 and to a holding capacitor 348. The output rom amplifier 346 in the hold mode is the held level, on cspacitor 348, of the input signsl at the time 8 "hold" control signsl W85 received. This signal is provided at the output of the tr~ck-and-hold circuit 342. With switch 344 open (as shown), the track and-hold circuit 342 produces the buffered, g~in controlled signal at its output labelled 'rr/H OUT".
In the preferred embodiment of the invention, the process-ors 251-253 are comprised of commercially available type Hl-5900 devices.
Returning to FIGURES 4A-4F, the A/D multiplexer 232 selects one of its six input signals in response to a 3-bit signal ~t its ~ddress inputs, labelled "A0-A2." The A0, Al lines are provided out of the control sequencer circuitry, on lines 400, 401, and select one of the three anslog input signals snd one of the 9~;
-~6-thsee input discrete sign01s. The A2 input, t~ken of of bus 230, selects either qn analog or ~ discrete sign~l.
The A/D multiplexer may be comprised of a commercially avail-able type Hl-508A8 device.
The selected output signal from the A/D multiplexer 232 is buf-fered through a unity gain amplifier 404 and psssed to the input, labelled "EINn, of an A/D converter 406. The A/D converter 406 responds to s "st~rt convert"
signal on input line 408 to ~nalog-t~digital convert signals applied ~t the input of the converter 406. The conversion process takes place at the rste of a clock signal, provided ~n line 410. Upon completion of sn analog-t~digital conversion,the con~lerter 406 produces U~ "end of conversionr signal which Qppears on the output line 412. The AJD converter 406 is, in the preferred embodiment of the invention, a 12-bit converter, producing a 12-bit digital output Q0-Q11. The A/D converter 4D6 may be comprised o~ 8 commercially available type AD5215 device.
The 12-bit digit~l signal output from the A/D converter 406 is csrried on 8 twelve line bus 414 to the inputs of three 4-bit by 4-bit random access memories (RAMS) 421-423 configured to ~orm ~ 12-bit by 4-bit arrQy capable of storing up to lour 12-bit signals out of the A/D converter 406. Data is ~ddressed into the RANIS 421-~23 vis write address lines 400, 401, provided out of the control sequencer. The control sequencer ~lso provides a write ensblesign61 on a line 424.
In turn, data is read out of the RAMS 421-423 under control of the CPU via read ~ddress lines 431, 432 and a resd enable line 433. Output date from the RAMS 421-423 is buffered through bus drivers 441, 442.
The RAMS 421-423 may be comprised of commercially available type 52LS670 integrated circuits, whereas the bus drivers 441, 442 mQy be comprised of commercially avsilable type 54LS373 integr~ted circuits.
The control sequencer, indicsted generslly at 450, is comprised of a programmable srrsy logic device 452 ~nd a 5-bit binary counter 454. The control sequencer 450 responds to an input/output signal on lines 455, 456 to produce the hold comm~nd applied to the processors 251-253 on line 260. Afler Q finite time period, determined by the 5-bit binary counter 454 counting clock pulses from s clock 460, the control sequencer 450 ectiv~tes its output line 408to institute the analog-to~igit~l conversion process. Once the conversion process h~s been completed or the selected three signal set, the controi seguencer 450 responds to an end-of conversion signal on line 41a to produce an interrupt request on output line 470.
The programmable arrsy logic device 452 mQy be comprised of a commerei~lly avail~ble type MM116R8-4 device, whereas the 5-bit binary counter 454 may be comprised of B 4024B device.
The CPU supplies information to, Qnd extr~cts data from the dstQ
5 acquisition system via a 16 line information bus 500. Connected to the data bus 500 are the outputs from the bus drivers 441, ~42. In this way, parametric dats stored within the RAMS 421-423 may be output to the CPU.
Input commands from the CPU on the information bus 5ûO are passed to four input ports 601-604. Upon receipt of a clock pulse st its CP
input, each input port 601-6û~ passes the signals ~t its inputs D0-D7 to its output lines Q0-Q7. Most ôf the d~t~ on the output lines Q0-Q7 of ~he input ports 601-604 is directed to the individual processors 251-253 and provides eachprocessor with ~ddress in~ormation for selecting a desired input signal and gsininformation for multiplying the selected signal by 8 selected gain factsr. In addition, cert~in output lines from the input ports 601-6M sre fed to the discrete multiplexers 221-223 to select the desired set of three discrete signals.
Also, special function lines are pro~ided. For example, line 230 indicates to the A/D multiplexer 232 whether the ~nalog signal set or the discrete signal set is to be selected. ln addition, line 214 carries the CPI~ produced BIT sign~l to the discrete multiplexers 211-213 The input ports 601-60~ m~y be comprised of commercially avail-able type 54LS374 integrated circuits.
The CPU accesses the data acquisition system by mesns of e control bus 700. The control bus 70û connects to input/output logic comprised offirst ~nd second address latches 701, 702, an address compare circuit 703 and anaddress decode circuit 704. The eight most significant bits of the information bus 500 ~re fed to the eight data inputs D0-D7 of the first address latch 701.
The two least significant bits of the information bus are fed to the D2, D3 inputs, respectively, of the second address latch 702. Applied to the D0 input of Qddress latch 702 is a CPU produced signal indicating whether R memory instruction ~ddress or an input/output command is being applied on the informa-tion bus. The Dl input of the second ~ddress latch 702 receives a CPU produced signal indicating whether the CPU is to read information off the informstion bus, or write information for the data ~c~uisition system on the information bus. Thefirst and second address lstches 701, 702 Are enabled by a CPU signal strobe A.
The ~ddress decoder 704 is enabled by a strobe D sign~l from the CPU.
The Q0-Q7 outputs from the first sddress latch 701 feed to the address inputs of the ~ddress compare eircuit 703. The E~O-B7 addresses of
3 ;23~ 6 address compare clrcu}t 703 are ~11 tied to a low level. The Input "E~n" to the ~ddress comp~re circuit 703 Is from the Q0 output of the second cddress latch 702. The output '~out" from the address compare circuit 703 ~eeds to the first input A1 of the ~ddress decoder 704. The Ql output from the second address latch 702 feeds to the first input A0 of the address decoder 704, with the Q2 and Q3 outputs from the second eddress lstch 702 feeding to the second A1 and first A0 inputs to address decoder 704.
The address latches 701, 702 may be comprised of commercially ~vailable type 54LS374 integrated circuits. The address comparator 703 may be comprised Or a commercially svailable type 25LS2521 integrated circuit, with the ~ddress decoder being comprised of ~ type 54LS1~8;ntegr~ted circuit.
The basic function of the input/output logic is to comp~re the ~ddress latched through the first latch ~ddress 701 to a reference address in the nddress comparator ~03. If the address comparator recognizes the address from the CPU as being the eddress of the dsta scquisition system, Rn output to the address decoder 70g results In the production of control signals to the data ~cquisition system. These control signals include a clock pulse which sllows data to be input via input ports 601-604 snd "read" signals, allowing data to be output from the RAMS 421-423 over the information bus 500. In addition, the input/-output logie produces control signals on lines 455, 456, causing the oontrol sequencer to institute the conversion and storing process.
In summary, a data acquisition system or an aircraft night data recorder has been described which is capsble of processing and converting a set of input signals in response to a single CPU request, thereby reducing overhead on the CPU. The disclosed dats acquisition system is universal in design in thatit sllows full CPU control of the input signals to be processed and, in addition, CPU control of the gain fsctors spplied to the input signals.
While a preferred embodiment of the invention has been described in detail, it should be apparent thst many modifications and variations thereto ~Ire possible, all of which fall within the true spirit and scope of the invention.
The address latches 701, 702 may be comprised of commercially ~vailable type 54LS374 integrated circuits. The address comparator 703 may be comprised Or a commercially svailable type 25LS2521 integrated circuit, with the ~ddress decoder being comprised of ~ type 54LS1~8;ntegr~ted circuit.
The basic function of the input/output logic is to comp~re the ~ddress latched through the first latch ~ddress 701 to a reference address in the nddress comparator ~03. If the address comparator recognizes the address from the CPU as being the eddress of the dsta scquisition system, Rn output to the address decoder 70g results In the production of control signals to the data ~cquisition system. These control signals include a clock pulse which sllows data to be input via input ports 601-604 snd "read" signals, allowing data to be output from the RAMS 421-423 over the information bus 500. In addition, the input/-output logie produces control signals on lines 455, 456, causing the oontrol sequencer to institute the conversion and storing process.
In summary, a data acquisition system or an aircraft night data recorder has been described which is capsble of processing and converting a set of input signals in response to a single CPU request, thereby reducing overhead on the CPU. The disclosed dats acquisition system is universal in design in thatit sllows full CPU control of the input signals to be processed and, in addition, CPU control of the gain fsctors spplied to the input signals.
While a preferred embodiment of the invention has been described in detail, it should be apparent thst many modifications and variations thereto ~Ire possible, all of which fall within the true spirit and scope of the invention.
Claims (25)
1. A data acquisition system for an aircraft flight data recorder responsive to a central processor unit (CPU) for selectively processing a plurality of input signals comprising:
multiplexing means for outputting selected sets of said input signals, each selected input signal set being output responsive to a corresponding address command signal;
logic means responsive to a single command from said CPU for producing each address command signal; and processing means for predeterminedly processing each signal in a selected signal set.
multiplexing means for outputting selected sets of said input signals, each selected input signal set being output responsive to a corresponding address command signal;
logic means responsive to a single command from said CPU for producing each address command signal; and processing means for predeterminedly processing each signal in a selected signal set.
2. The data acquisition system of Claim 1, wherein said processing means comprises:
gain controlled amplifier means responsive to gain control com-mand signals from said CPU for amplifying each signal in a selected signal set by a predetermined gain factor;
track-and-hold circuit means for tracking the values of each amplified signal in a selected signal set and, responsive to a hold command signal, holding the instantaneous value of each amplified signal;
analog-to-digital converter means for converting each signal at its input to a corresponding digital signal at its output; and controller means for predeterminedly coupling the instantaneous value of each signal in the selected signal set to the input of said analog-to-digital converter means.
gain controlled amplifier means responsive to gain control com-mand signals from said CPU for amplifying each signal in a selected signal set by a predetermined gain factor;
track-and-hold circuit means for tracking the values of each amplified signal in a selected signal set and, responsive to a hold command signal, holding the instantaneous value of each amplified signal;
analog-to-digital converter means for converting each signal at its input to a corresponding digital signal at its output; and controller means for predeterminedly coupling the instantaneous value of each signal in the selected signal set to the input of said analog-to-digital converter means.
3. The data acquisition system of Claim 2, wherein each predetermined gain factor is selected such that the resulting amplified signal coupled to the input of said analog-to-digital converter is in a range selected to minimize analog-to-digital converter means error.
4. The data acquisition system of Claim 2, further comprising:
input scaling circuit means for attenuating selected input signals by a predetermined scaling factor; and wherein said gain factors for said gain controlled amplifiers are selected such that each signal, after being attenuated in said input scaling circuit means and amplified by said gain controlled amplifier, is in a range selected to minimize analog-to-digital converter means error.
input scaling circuit means for attenuating selected input signals by a predetermined scaling factor; and wherein said gain factors for said gain controlled amplifiers are selected such that each signal, after being attenuated in said input scaling circuit means and amplified by said gain controlled amplifier, is in a range selected to minimize analog-to-digital converter means error.
5. The data acquisition system of Claim 2, further comprising:
digital memory means for storing each analog-to-digital converted instantaneous value of a signal in a selected signal set; and wherein said controller means produces an interrupt signal to said CPU upon all of the analog-to-digital converted signals in a selected signal setbeing stored in said digital memory means.
digital memory means for storing each analog-to-digital converted instantaneous value of a signal in a selected signal set; and wherein said controller means produces an interrupt signal to said CPU upon all of the analog-to-digital converted signals in a selected signal setbeing stored in said digital memory means.
6. The data acquisition system of Claim 5, wherein said logic means responds to a single CPU command signal to:
a) produce a predetermined address command signal such that said multiplexing means outputs said set of selected input signals, b) produce predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and c) activate said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set isloaded into said digital memory means.
a) produce a predetermined address command signal such that said multiplexing means outputs said set of selected input signals, b) produce predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and c) activate said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set isloaded into said digital memory means.
7. The data Acquisition system of Claim 1, wherein at least three of said input signals are the output signals from a synchro sensor and wherein said logic means produces an address command signal causing said multiplexing means to output said three synchro signals as a selected signal set.
8. The data acquisition system of Claim 1, wherein at least one of said input signals is an AC ratiometric signal and at least one of said inputsignals is the reference AC signal for said AC ratiometric signals and wherein said logic means produces an address command signal causing said multiplexing means to output said AC ratiometric and reference AC signals as a selected signal set.
9. A data acquisition system for an aircraft flight data recorder responsive to a central processor unit (CPU) for selectively processingmultiple input signals comprising:
multiplexing means responsive to address command signals for outputting selected sets of said input signals;
signal level control means for predeterminedly controlling the level of each signal in a selected signal set, said signal level control means including gain controlled amplifier means responsive to gain control command signals from said CPU for amplifying each signal in a signal set by a predetermined gain factor;
means responsive to a hold command signal to hold the instan-taneous level of each amplified signal in a signal set;
analog-to-digital converter means for converting each signal at its input to a digital signal at its output; and controller means for predeterminedly coupling each held signal level to the input of said analog-to-digital converter means.
multiplexing means responsive to address command signals for outputting selected sets of said input signals;
signal level control means for predeterminedly controlling the level of each signal in a selected signal set, said signal level control means including gain controlled amplifier means responsive to gain control command signals from said CPU for amplifying each signal in a signal set by a predetermined gain factor;
means responsive to a hold command signal to hold the instan-taneous level of each amplified signal in a signal set;
analog-to-digital converter means for converting each signal at its input to a digital signal at its output; and controller means for predeterminedly coupling each held signal level to the input of said analog-to-digital converter means.
10. The data acquisition system of Claim 9, wherein said signal level control means includes input attenuator means for attenuating each of saidinput signals by a predetermined factor.
11. The data acquisition system of Claim 9, wherein said signal level control means controls the level of each signal to a range selected to reduce analog-to-digital converter means error.
12. The data acquisition system of Claim 10, wherein said signal level control means controls the level of each signal to a range selected to reduce analog-to-digital converter means error.
13. The data acquisition system of Claim 9, further comprising:
digital memory means for storing each analog-to-digital converted instantaneous value of a signal in a selected signal set; and wherein said controller means produces an interrupt signal to said CPU upon all of the analog-to-digital converted signals in a selected signal setbeing stored in said digital memory means.
digital memory means for storing each analog-to-digital converted instantaneous value of a signal in a selected signal set; and wherein said controller means produces an interrupt signal to said CPU upon all of the analog-to-digital converted signals in a selected signal setbeing stored in said digital memory means.
14. The data acquisition system of Claim 13, further compris-ing:
logic means responsive to a single CPU command signal for:
a) producing a predetermined address command signal such that said multiplexing means outputs a set of selected input signals, b) producing predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and c) activating said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set isloaded into said digital storage means.
logic means responsive to a single CPU command signal for:
a) producing a predetermined address command signal such that said multiplexing means outputs a set of selected input signals, b) producing predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and c) activating said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set isloaded into said digital storage means.
15. The data acquisition system of Claim 14, wherein at least three of said input signals are the output signals from a synchro sensor and wherein said logic means produces an address command signal causing said multiplexing means to output said three synchro signals as a selected signal set.
16. The data acquisition system of Claim 14, wherein at least one of said input signals is an AC ratiometric signal and at least one of said input signals is the reference AC signal for said AC ratiometric signals and wherein said logic means produces an address command signal causing said multiplexing means to output said AC ratiometric and reference AC signals as a selected signal set.
17. A data acquisition system for an aircraft night data recorder having a plurality of analog input signals and a plurality of discrete input signals and being responsive to a central processor unit (CPU) for selectively processing said analog and discrete input signals into digital signals for transmission to said CPU, the data acquisition system comprising:
first multiplexing means responsive to an address command signal for outputting a selected set of said analog signals;
processing means for predeterminedly processing each signal in a selected signal set;
second multiplexing means responsive to an address command signal for outputting a selected set of said discrete signals;
third multiplexing means responsive to a control sequence signal for selectively outputting one of said first multiplexing means processed signalset and said second multiplexing means output signal set;
analog-to-digital converter means for converting each signal out of said third multiplexing means to a digital signal;
digital memory means for storing each analog-to-digital converter means produced signal; and control sequencer means for producing control sequence signals to sequentially analog-to-digital convert the output signals from said third multi-plexing means, said control sequencer means further providing an inhibit signal to said CPU responsive to said digital memory means having stored each analog-to-digital converted output from said third multiplexer means.
first multiplexing means responsive to an address command signal for outputting a selected set of said analog signals;
processing means for predeterminedly processing each signal in a selected signal set;
second multiplexing means responsive to an address command signal for outputting a selected set of said discrete signals;
third multiplexing means responsive to a control sequence signal for selectively outputting one of said first multiplexing means processed signalset and said second multiplexing means output signal set;
analog-to-digital converter means for converting each signal out of said third multiplexing means to a digital signal;
digital memory means for storing each analog-to-digital converter means produced signal; and control sequencer means for producing control sequence signals to sequentially analog-to-digital convert the output signals from said third multi-plexing means, said control sequencer means further providing an inhibit signal to said CPU responsive to said digital memory means having stored each analog-to-digital converted output from said third multiplexer means.
18. The data acquisition system of Claim 17, wherein said processing means comprises:
gain controlled amplifier means responsive to gain control com-mand signals from said CPU for amplifying each signal in a selected signal set by a predetermined gain factor;
track-and-hold circuit means for tracking the values of each amplified signal in a selected signal set and, responsive to a hold command signal, holding the instantaneous value of each amplified signal.
gain controlled amplifier means responsive to gain control com-mand signals from said CPU for amplifying each signal in a selected signal set by a predetermined gain factor;
track-and-hold circuit means for tracking the values of each amplified signal in a selected signal set and, responsive to a hold command signal, holding the instantaneous value of each amplified signal.
19. The data acquisition system of Claim 18, wherein each predetermined gain factor is selected such that the resulting amplified signal coupled to the input of said analog-to-digital converter is in a range selected to minimize analog-to-digital converter means error.
20. The data acquisition system of Claim 18, further compris-ing:
input scaling circuit means for attenuating selected input signals by a predetermined scaling factor; and wherein said gain factors for said gain controlled amplifiers are selected such that each signal, after being attenuated in said input scaling circuit means and amplified by said gain controlled amplifier, is in a range selected to minimize analog-to-digital converter means error.
input scaling circuit means for attenuating selected input signals by a predetermined scaling factor; and wherein said gain factors for said gain controlled amplifiers are selected such that each signal, after being attenuated in said input scaling circuit means and amplified by said gain controlled amplifier, is in a range selected to minimize analog-to-digital converter means error.
21. The data acquisition system of Claim 17, further comprising logic means, said logic means responsive to a single CPU command signal for:
a) producing a predetermined address command signal such that said first multiplexing means outputs said selected set of analog signals, b) producing predetermined gain control command signals such that each analog signal in said selected signal set is amplified by a predeter-mined gain factor, and c) activating said control sequencer means such that the analog-to-digital converted signals out of the third multiplexing means are loaded into said digital memory means.
a) producing a predetermined address command signal such that said first multiplexing means outputs said selected set of analog signals, b) producing predetermined gain control command signals such that each analog signal in said selected signal set is amplified by a predeter-mined gain factor, and c) activating said control sequencer means such that the analog-to-digital converted signals out of the third multiplexing means are loaded into said digital memory means.
22. The data acquisition system of Claim 18, further comprising logic means, said logic means responsive to a single multibit CPU command signal for:
a) producing a predetermined address command signal such that said first multiplexing means outputs said selected set of analog signals, b) producing predetermined gain control command signals such that each analog signal in said selected signal set is amplified by a predeter-mined gain factor, and c) activating said control sequencer means such that the analog-to-digital converted signals out of the third multiplexing means are loaded into said digital memory means.
a) producing a predetermined address command signal such that said first multiplexing means outputs said selected set of analog signals, b) producing predetermined gain control command signals such that each analog signal in said selected signal set is amplified by a predeter-mined gain factor, and c) activating said control sequencer means such that the analog-to-digital converted signals out of the third multiplexing means are loaded into said digital memory means.
23. The data acquisition system of Claim 21, wherein at least three of said analog input signals are the output signals from a synchro and wherein said logic means produces an address command signal causing said first multiplexing means to output said three synchro signals as a selected set.
24. The data acquisition system of Claim 21, wherein at least one of said analog input signals is an AC ratiometric signal and at least one o said analog input signals is the reference AC signal for said AC ratiometric signals and wherein said logic means produces an address command signal causing said first multiplexing means to output said AC ratiometric and reference AC
signals as a selected set.
signals as a selected set.
25. The data acquisition system of Claim 17, further com-prising:
test circuitry means including means for applying a predetermined analog signal and a predetermined discrete signal as inputs to the data acquisition system, means for causing said predetermined level analog and discrete systems to be processed through said data acquisition system such that digital signals corresponding to said predetermined analog and discrete signals are stored in said digital memory means, and means for reading said digital signals corresponding to said predetermined analog and discrete signals out of said digital memory means, comparing said digital signals to the predetermined value and indicating a fault condition in response to a predetermined discrepancy therebetween.
test circuitry means including means for applying a predetermined analog signal and a predetermined discrete signal as inputs to the data acquisition system, means for causing said predetermined level analog and discrete systems to be processed through said data acquisition system such that digital signals corresponding to said predetermined analog and discrete signals are stored in said digital memory means, and means for reading said digital signals corresponding to said predetermined analog and discrete signals out of said digital memory means, comparing said digital signals to the predetermined value and indicating a fault condition in response to a predetermined discrepancy therebetween.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US576,538 | 1984-02-03 | ||
| US06/576,538 US4656585A (en) | 1984-02-03 | 1984-02-03 | Aircraft flight data recorder data acquisition system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1239696A true CA1239696A (en) | 1988-07-26 |
Family
ID=24304847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000469948A Expired CA1239696A (en) | 1984-02-03 | 1984-12-12 | Aircraft flight data recorder data acquisition system |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4656585A (en) |
| EP (1) | EP0171424B1 (en) |
| JP (1) | JPS61501112A (en) |
| AU (1) | AU568194B2 (en) |
| CA (1) | CA1239696A (en) |
| DE (1) | DE3578016D1 (en) |
| IL (1) | IL74058A (en) |
| WO (1) | WO1985003586A1 (en) |
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-
1984
- 1984-02-03 US US06/576,538 patent/US4656585A/en not_active Expired - Fee Related
- 1984-12-12 CA CA000469948A patent/CA1239696A/en not_active Expired
-
1985
- 1985-01-15 IL IL7405885A patent/IL74058A/en unknown
- 1985-01-22 JP JP60500817A patent/JPS61501112A/en active Pending
- 1985-01-22 AU AU39903/85A patent/AU568194B2/en not_active Expired - Fee Related
- 1985-01-22 EP EP19850901149 patent/EP0171424B1/en not_active Expired - Lifetime
- 1985-01-22 DE DE8585901149T patent/DE3578016D1/en not_active Expired - Fee Related
- 1985-01-22 WO PCT/US1985/000098 patent/WO1985003586A1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| EP0171424A4 (en) | 1986-09-04 |
| AU3990385A (en) | 1985-08-27 |
| IL74058A0 (en) | 1985-04-30 |
| JPS61501112A (en) | 1986-05-29 |
| IL74058A (en) | 1989-01-31 |
| EP0171424B1 (en) | 1990-05-30 |
| AU568194B2 (en) | 1987-12-17 |
| EP0171424A1 (en) | 1986-02-19 |
| DE3578016D1 (en) | 1990-07-05 |
| WO1985003586A1 (en) | 1985-08-15 |
| US4656585A (en) | 1987-04-07 |
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