CA1236589A - Apparatus for masking the contents of a first storage means from a system until the contents of a second storage means is executed by said system - Google Patents
Apparatus for masking the contents of a first storage means from a system until the contents of a second storage means is executed by said systemInfo
- Publication number
- CA1236589A CA1236589A CA000482000A CA482000A CA1236589A CA 1236589 A CA1236589 A CA 1236589A CA 000482000 A CA000482000 A CA 000482000A CA 482000 A CA482000 A CA 482000A CA 1236589 A CA1236589 A CA 1236589A
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- Prior art keywords
- processor
- circuit
- clock
- command
- cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
Abstract
ABSTRACT OF THE DISCLOSURE
A masking circuit for a multiprocessor system is disclosed. In the multiprocessor system, a first command status register contains information associated with a first processor of the multiprocessor system and a second command status register contains information associated with a second processor of the multiprocessor system.
Normally, the command status registers contain command information related to the processing of commands for their respective processors. However, during a flush operation, wherein data stored in the cache of a second processor is flushed to a main memory in order to allow access to the data by a first processor, the command being executed by the first processor must be blocked in order to allow the flush operation to be completed. When the flush operation is complete, the execution of the command by the first processor commences. The first command status register contains the command being executed by the first processor, and the second command status register contains information related to the need for a flush operation. The masking circuit of the present invention senses the existence of the command in the first command status register and the information, related to the flush operation, in the second command status register and masks the command in the first command status register from the multiprocessor system until the flush operation (as indicated by the contents of the second command status register) is complete. When the command is masked, the execution of the command is postponed until the flush operation is completed. When the flush operation is complete, the second command status register is reset. When reset, the multiprocessor system is permitted to commence execution of the command.
A masking circuit for a multiprocessor system is disclosed. In the multiprocessor system, a first command status register contains information associated with a first processor of the multiprocessor system and a second command status register contains information associated with a second processor of the multiprocessor system.
Normally, the command status registers contain command information related to the processing of commands for their respective processors. However, during a flush operation, wherein data stored in the cache of a second processor is flushed to a main memory in order to allow access to the data by a first processor, the command being executed by the first processor must be blocked in order to allow the flush operation to be completed. When the flush operation is complete, the execution of the command by the first processor commences. The first command status register contains the command being executed by the first processor, and the second command status register contains information related to the need for a flush operation. The masking circuit of the present invention senses the existence of the command in the first command status register and the information, related to the flush operation, in the second command status register and masks the command in the first command status register from the multiprocessor system until the flush operation (as indicated by the contents of the second command status register) is complete. When the command is masked, the execution of the command is postponed until the flush operation is completed. When the flush operation is complete, the second command status register is reset. When reset, the multiprocessor system is permitted to commence execution of the command.
Description
~23~ 9 APPARATUS FOR MASKING THE CONTENTS OF
A FIRST STORAGE MEANS FROM A SY~TEM 2 The present invention relates to multiprocessor 10 computer technology, and more particularly, to a 11 masking circuit within a multiprocessor computer 12 system for masking the contents of a first command 13 status register, associated with a first processor, 14 from the multiprocessor system until the contents of 15 a second command status register, associated with a 16 second processor, is executed. 17 In a multiprocessor computer system, when one 19 processor attempts to locate desired data in its own 20 cache, and fails to locate such data, it is 21 necessary to attempt to locate the data in the cache 22 of the other processor. If the data is not found in 23 the cache of the other processor, it is necessary to 24 retrieve the data from a main store. Occasionally, 25 the data is found in the cache of the other 26 processor. The one processor must utilize the 27 desired data in the execution of an instruction. 28 For some instructions, the one processor may 30 retrieve the data directly from the cache of the 31 other processor, store the data in its own cache, 32 and utilize the data in the execution of the 33 instruction. 34 However, for other instructions, the one processor 36 cannot retrieve the data directly from the cache of 37 the other processor. It is therefore necessary to 38 perform a flush operation. During the flush 39 ~k ~3 Ei5t~3~
operation, the desired data is flushed from the cache of the other processor to the main store. The 2 data is then utilized by the one processor in the 3 execution of its instruction. 4 However, during the flush operation, the one 6 processor may be attempting to execute a command. 7 If the command may be classified as one of said 8 other instructions, in view of the need to flush the 9 desired data from the cache of the other processor 10 to the main store prior to the execution of the 11 command, it is necessary to mask the presence of the 12 command, in the one processor, from the remainder of 13 the multiprocessor system until the flush operation 14 is complete. When the flush operation is complete, 15 the mask, associated with the command, is released 16 and the command is executed. However, if the 17 command may not be classified as one of said other 18 instructions, the presence of the command should not 19 be masked from the remainder of the multiprocessor 20 system and execution of the command should commence 21 uninhibited. 22 It is a primary object of the present invention to 26 provide an apparatus for masking the contents of a 27 first storage means from a system until the contents 28 of a second storage means is executed, and for 29 releasing the mask associated with the first storage 30 means when the contents of the second storage means 31 is executed. 32 It is another object of the present invention to 34 provide an apparatus for masking the contents of a 35 first command status register in a multiprocessing 36 system from said system thereby preventing the 37 ~36~9 execution of the contents of said first command status register until the contents of a second 2 command status in said multiprocessing system has 3 been executed and for releasing the mask associated 4 with the first command status register when the 5 contents of the second command status register is 6 executed. 7 These and other objects of the present invention are 9 accomplished by providing a circuit in a system 10 which senses the storage of information in one 11 storage means and senses the storage of information 12 in another storage means and which masks the 13 information in the one storage means from the system 14 in order to permit the system to access the 15 information stored in the second storage means. 16 Specifically, the system is a multiprocessor system, 17 the one storage means being a first command status 18 register for storing command information therein 19 associated with a firs' processor of the 20 multiprocessor system, the second storage means 21 being a second command status register for storing 22 command inform~tion therein associated with a second 23 processor of the multiprocessor system. The circuit 24 in the multiprocessor system is a stacked op 25 discriminator circuit which senses the existence of 26 command information stored in the first command 27 status register and senses the existence of 28 information (not necessarily command information) 29 stored in the second command status register and 30 masks the command information in the first command 31 status register from the multiprocessor system in 32 order to permit the information stored in the second 33 command status register to be executed by the 34 multiprocessor systemO When the information stored 35 in the second command status register has been 36 executed by the multiprocessor system, the mask, 37 associated with the first command status register, 38 3~
is released and the command information stored therein is executed by the multiprocessor system. 2 Further scope of applicability of the present 4 invention will become apparent from the detailed 5 description presented hereinafter. It should be 6 understood, however, that the detailed description 7 and the specific examples, while representing a 8 preferred embodiment of the invention, are given by 9 way of illustration only, since various changes and 10 modifications within the spirit and scope of the ll invention will become obvious to one skilled in the 12 art from a reading of the following detailed 13 description. 14 A full understanding of the present invention will 18 be obtained from the detailed description of the 19 preferred embodiment presented hereinbelow, and the 20 accompanying drawings, which are given by way of 21 illustration only and are not intended to be 22 limitative of the present invention, and wherein: 23 figure 1 illustrates a block diagram of a 25 multiprocessor system in accordance with the present 26 invention; 27 figure 2 illustrates a more detailed block diagram 29 of the multiprocessor system of figure 1; 30 figure 3 illustrates a block diagram of a BS~ 32 control circuit, a portion of the multiprocessor 33 system of figure 2; 34 figure 4 illustrates a block diagram of the stacked 36 op discriminator circuit of figure 3; 37 EN984023 - 4 _ . ~365~9 figure 5 illustrates a block diagram of a pair of alternate cache signal generation circuits, a 2 portion of the multiprocessor system of figure 2; 3 figure 6 illustrates a block diagram of the ICT 5 Control(l), a portion of the alternate cache signal 6 generation circuits of figure 5; 7 figure 7 illustrates a block diagram of a block 9 circuit, a portion of the multiprocessor system of 10 figure 2; 11 ..
figure 8 illustrates a block diagram of a sync 13 circuit, a portion of the multiprocessor system of 14 figure 2; 15 figure 9 illustrates a block diagram of the IPU W~IT 17 TRAP SRL, a portion of the sync circuit of figure 8; 18 figures lOa and lOb illustrate block diagrams of the 20 nand-invert (NI) circuits of figure 9 and the SRL21 latch circuits (SRL) of figures 6, 7, 8, and 9, 22 respectively; 23 figure 11 illustrates a block diagram of the clock 25 circuits of figure 2; 26 figure 12 illustxates the clock se~uences associated 28 with the instruction processing unit (IPU) circuits, 29 IPU 0 and IPU 1, and the BSM control circuit shown 30 in figure 2; 31 figure 13a illustrates an out-of-sync situation 33 wherein a processor's clocks are out-of-sync with a 34 main store (BSM) control clock; and 35 figure 13b illustrates an in-sync situation wherein 37 a processor's clocks are in-sync with a main store 38 (BSM) control clock. 39 - ~2~65i~
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Re~erring to figure 1, a multiprocessor system iS 3 illustrated. In figure 1, a first processor 10, of 4 the multiprocessor system, is connected to a main 5 memory 15 by way of a system bus (the main memory 6 being alternatively termed a Basic Storage Module 7 BSM or a main store). A second processor 20, of the 8 multiprocessor system, is also connected to the main 9 store 15 by way of the system bus. 10 Referring to figure 2, a more detailed block diagram 12 of the multiprocessor system of figure 1 is13 illustrated. In figure 2, the first processor 10, 14 alternatively termed processor 0, includes an 15 instruction processing unit 10a (IPU 0), a cache 10b 16 (cache 0) connected to the IPU 10a, a clock17 generator 10c connected to the IPU 10a, and an X 18 module 10d connected to the clock generator 10c. 19 The X module 10d includes a novel sync circuit 10dl 20 connected to the clock generator 10c and an21 alternate cache search signal generation circuit 22 (ACS GEN) 10d2 connected to the sync circuit 10dl. 23 The first processor 10 further includes a trap 24 priority circuit 10f connected between the sync 25 circuit 10dl of the X module 10d and the clock 26 generator 10c, and a cache directory ~(Z) 10e 27 connected to cache 10b, to the sync circuit 10dl, to 28 the ACS GEN 10d2 of X module 10d, and to IPU 10a. 29 The second processor 20, alternatively termed 31 processor 1, includes an instruction processing unit 32 (IPU) 20a (IPU 1), a cache 20b (cache 1) connected 33 to the IPU 20a, a clock generator 20c connected to 34 the IPU 20a, and an X module 20d connected to the 35 clock generator 20c. The X module 20d includes a 36 novel sync circuit 20dl connected to the clock 37 generator 20c and an alternate cache search signal 38 generation circuit (ACS GEN) 20d2 connected -to the 39 ~236~
sync circuit 20dl. The second processor 20 further includes a trap priority circuit 20f connected 2 between the sync circuit 20dl of the X module 20d 3 and the clock generator 20c, and a cache directory 4 (Z) 20e connected to cache 20b, to the sync circuit 5 20dl and the ACS GEN 20d2 of X module 20d, and to 6 IPU 20a. 7 The multiprocessor system of figure 2 further 9 includes a main store control circuit 30, otherwise lO
termed a Basic Storage Module (BSM) control circuit 11 30 or "BSM Controls 30'l, connected to processor lO, 12 and in particular, to the X module lOd, the cache 13 lOb, and the cache directory lOe of processor 10, 14 and to processor 20, and in particular, to the X 15 module 20d, the cache 20b, and the cache directory 16 20e of processor 20. The BSM control 30 is further 17 connected to a main store 15 or Basic Storage Module 18 (BSM) 15. The BSM control 30 is responsible for 19 controlling the functioning of the multiprocessor 20 system of figure 2, the details of its functioning 21 being described in the paragraphs below which are 22 dedicated to a description of the functional 23 operation of the present invention. 24 Referring to figure 3, a block diagram of the BSM 26 controls 30 of figure 2 is illustrated. In figure 27 3, the BSM controls 30 comprise a command status 28 register (CS REG) 30a connected to the cache - 29 directory (Z) lOe and a command status register (CS 30 REG) 30b connected to the cache directory (Z) 20e. 31 The cache directories (Z) supply 32 hit/miss/flush/modified information to the command 33 status registers 30a and 30b. The command status 34 registers 30a and 30b are each connected to a 35 stacked op discriminator circuit 30d. The stacked 36 op discriminator circuit 30d receives the contents 37 of the command status registers 30a and 30b and 38 develops an oukput signal when the command status 39 3~5~39 registers 30a and 30b contain predetermined information. For example, when command status 2 register 30a contains a WHEREVER word, and command 3 status register 30b contains a flush indication from 4 cache directory (Z) 20e, the stacked op 5 discriminator circuit 30d develops an output signal. 6 The stacked op discriminator circuit 30d would also 7 generate an output signal if command status register 8 30b contained a WHEREVER word and command status 9 register 30a contained a flush indication from cache 10 director~ (z) 10e. The output signal (60j from the 11 stacked op discriminator circuit 30d performs a 12 "masking" function in that it masks the contents of 13 the command status register (CS REG) containing the 14 ~HEREVER word information from the remainder of the 15 BSM controls 30 and prevents the normal start signal 16 61 from being sent to the BSM ops control circuit 17 30g. The output signal 60 of the stacked op 18 discriminator circuit 30d also enables the contents 19 of the command status register containing the flush 20 indication to be seen b~ the BSM ops control circuit 21 30g. The stacked op discriminator circuit 30d is 22 connected to a block circuit 30c and to an AND gate 23 30e. A signal termed "allow reset BSM controls" 24 energizes the other input terminal of the AND gate 25 30e. The block circuit 30c is connected to clock 26 10c, to ACS GEN 10d2. The AND gate 30e is 27 connected, at its output terminal, to an input (set) 28 terminal of a stacked op latch 30fO The output 29 terminal of the stacked op latch 30f is connected to 30 the CS REG 30b and to a BSM OPS CONTROL CIRCUIT 30g. 31 The BSM ops control circuit 30g is connected, at its 32 output, to cache 10b, cache 20b, and to BSM 15, the 33 BSM ops control circuit 30g controlling the transfer 34 of data from the cache memories 10b and 20b to the 35 BSM 15 and vice-versa. 36 Referring to figure 4, a block diagram of the 38 stacked op discriminator circuit 30d of figure 3 is 39 illustrated. In figure 4, the stacked op discriminator circuit 30d comprises an AND gate 30dl 2 connected to CS REG 30a and an AND gate 30d2 3 connected to CS REG 30b. AND gate 30dl is connected 4 to AND gate 30d2~ and vice-versa. Further, AND gate 5 30dl is connected to a "BSM CTLS BUSY FO~ PU0" line, 6 and AND gate 30d2 is connected to a "BSM CTLS BUSY 7 FOR PU1" line. The outputs of AND gates 30dl and 8 30d2 are connected to an OR gate 30d3. The output 9 of OR gate 30d3 represents line 60 as shown in 10 figure 3. 11 Referring to figure 5, a block diagram of the 13 alternate cache search signal generation circuits 14 (ACS GEN) 10d2 and 20d2 of figure 2 is illustrated. 15 In figure 5, the ACS GEN 20d2 comprises portions of 16 an ICT Control (2) 20d2(a). The ICT Control (2) 17 20d2(a) receives signals from cache directory 20e 18 and sync circuit 20dl and generates output signals 19 "-Y busy gate XBRD" and "-Y flush XBRD" in response 20 thereto. The ACS GEN 10d2 comprises portions of an 21 ICT Control (2) 10d2(a) connected to sync circuit 22 10dl and cache directory (Z) 10e, the Control (2) 23 10d2(a) generating output signals "+Y REQ accepted" 24 and "+ flush reset" in response to output signals 25 from the cache directory (Z) 10e and sync circuit 26 10dl. The ACS GEN 10d2 also comprises portions of 27 an ICT Control(1) 10d2(b) connected to the ICT 28 Control (2) 10d2(a) and receiving the output signals 29 therefrom for developing the alternate cache search 30 signals in response thereto, the alternate cache 31 search signals being received by the block circui~ 32 30c. 33 Referring to figure 6, a block diagram of portions 35 of the ICT Control~l) 10d2(b) of figure 5 is 36 illustrated. In figure 6, the ICT Control(l) 37 10d2(b) portion comprises an SRL latch circuit (b~1 38 which receives the "+Y request accepted" signal from 39 ~L~3Çi5;~9 the ICT Control ~2) 10d2(a) and output signals from a clock driver circuit (b)2. The clock driver 2 circuit lb)2 receives an +SO clock signal. The 3 output of the SRL latch (b)l is connected to an 4 input terminal of an OR gate (b)3. The "-Y flush XBRD" signal energizes another input terminal of OR 6 gate (b)3 via receiver circuit (b)4 and inverter 7 (b)5. The "+flush reset" signal energizes another 8 input terminal of OR gate (b)3 via inverter ~b)6. 9 The output of OR gate tb)3 is connected to a second 10 input terminal of OR driver (b)7. The ICT 11 Control(l) 10d2tb) portion also comprises an SRL 12 scan only latch (b)8 connected, at output terminal 13 21, to the OR driver circuit (b)7 via inverter (b)9. 14 The latch (b)8 is connected, at output terminal 10, 15 to a clock driver circuit (b)10. A +Cl/C3 clock 16 also energizes the clock driver (b)10. The clock 17 driver circuit (b)10 is connected, at its output, to 18 the -C and +C input terminals of an SRL latch 19circuit (b)ll. The "-Y busy gate XBRD" signal 20energizes another input texminal of the SRL latch 21 circuit (b)11 via a driver/receiver circuit tb)12. 22 Output terminal 21 of of the SRL latch circuit tb)ll 23 is connected to the first input terminal of OR 24 driver (b)7 via inverters (b)12 and (b)13. A 25 -SO/-S2 clock energizes the second input of OR 26 driver (b)7 via inverter (b)14. The OR driver 27 circuit tb)7 generates the alternate cache search 28 signals which energize the block circuit 30c. 29 Referring to figure 7, a block diagram of the block 31 circuit 30c disposed within the BSM controls 30, is 32 illustrated. The block circuit 30c includes an AND 33 gate 30cl having one input terminal connected to a 34 "BSM busy controls" line and another input terminal 35 connected to the ACS GEN 10d2. The output of AND 36 gate 30cl is connected to OR gate 30c2, the other 37 input of which is connected to a "Reset BSM 38 controls" signal. The output of OR gate 30c2 is 39 connected to the input of a clock driver 30c3, the output of clock driver 30c3 including a +C output 2 terminal and a -C output terminal. The +C and -C 3 output terminals are input to an SRL latch circuit 4 30c4 (L1). The L1 (master) portion of the SRL latch 5 circuit 30c4 is connected internally to an L2 6 (slave) portion which is controlled by OR circuit 7 30c10. See figure 10b for a detailed construction 8 of this SRL latch circuit. An output of the SRL 9 latch circuit 30c4 (L2) is connected to an input of 10 invert gate 30c5. The output of invert gate 30c5 is 11 fed back to another input terminal of the SRL latch 12 circuit 30c4 (L1). An output terminal (~2) of SRL 13 latch circuit 30c4 is connected to one input of NAND 14 gate 30c6 (NAND gate 30c6 comprising an AND gate 15 with an inverter connected to its output terminal). 16 The other input of NAND gate 30c6 is connected to 17 the command status registers 30a and 30b via stacked 18 op discriminator circuit 30d (it should be noted, at 19 this point, that the command status registers 30a 20 and 30b shown in figures 3, 4, and 7 receive 21 hit/miss/modified data information from the cache 22 directories 10e and 20e, data information, and 23 information related to the initiation of exeeution 24 of a special instruetion called a "wherever", 25 abbreviated W.E., instruction). The output of NAND 26 gate 30c6 is conneeted to a clock driver circuit 27 30c7. The elock driver circuit 30e7 develops two 28 outputs: a +C output and a -C output. The +C and 29 the -C outputs of eloek driver 30e7 are eonneeted to 30 input terminals of an SRL lateh eircuit 30c8. The 31 output terminal of the SRL lateh eircuit 30c8 is 32 connected to the BSM ops control eircuit 30g. The 33 BSM ops control circuit 30g functions to initiate 34 the flush of data ~rom a processor's cache 10b or 35 20b to the BSM 15 and then execute the subsequent 36 WHEREVER word which has been masked during the flush 37 operation. 38 ~ ~:3658~
Referring to figure 8, a block diagram of sync circuits lOdl and 20dl is illustrated. In figure 8, 2 sync circuits lOdl and 20dl each comprise an AND 3 gate lOdl(10) connected to cache directories lOe and 4 20e for receiving hit/modified data information from 5 cache directories lOe and 20e, for receiving a clock 6 signal, and for receiving the special "wherever" 7 instruction indicating that the "wherever" 8 instruction is about to be executed. The output of 9 AND gate lOdl(10) is connected to an input of a 10 FLUSH REQ SRL latch circuit lOdl(12). This latch 11 circuit is the same latch circuit, in construction, 12 as the latch circuits 30c4 and 30c8. The SRL latch 13 circuit lOdl(12) is connected to an IPU WAIT TRAP 14 SRL latch circuit lOdl(14). Latch circuit lOdl(14) 15 develops an IP~ ~AIT TRAP REQUEST signal which 16 energizes clock generators lOc and 20c. When the 17 clock signal energizing the IPU's lOa and 20a are in 18 sync with the clock signal energizing the block 19 circuit 30c of the BSM controls 30, the clock 20 generators lOc and 20c generate a DIR MISS/IPU WAIT 21 TRAP signal which resets latch circuit lOdl(14) and 22 which energizes one input terminal of AND gate 23 lOdl(16). The other input of AND gate lOdl (16) 24 originates from the output terminal of latch circuit 25 lOdl(12). The output of AND gate lOdl (16) is 26 connected to an input of clock driver circuit 27 lOdl(18). A clock signal energizes the clock driver 28 circuit. The output of clock driver circuit 29 lOdl(18) is connected to an input of a FLUSH GO SRL 30 latch circuit lOdl(20). The output of the FLUS~ GO 31 latch circuit lOdl (20) iS connected to a reset 32 terminal of the FLUSH REQ latch circuit lOdl(12), 33 and to either the ACS GEN 1 Od2 or to the ACS GEN 34 lOd2 via the ACS GEN 20d2 (depending upon the sync 35 circuit). The ACS GEN lOd2 develops the alternate 36 cache search signal which energizes the block 37 circuitO 38 ii589 Referri~c ~o fi~.-e 9, a detailel construction of the IPU
WAIT TRAP SRT~ lO~l (14~ shown in figure 8 is illustrated.
Referring to figure lOa, a diayram o~ the construction of the nand~invert -ircuit (NI) shown in figure 9 is illus~rated.
Referring to figure lOb, a diagram of the construction of the SRL latch circuit shown in figure 9 is illustrated. In addition~ figure lOb illustrates the construction of the SRL
latch circuits shown in figures 6, 7 (latches 30c4 and 30c8), and 8 (the FLUSH REQ latch lOdl(12) and the FLUSI GO
latch lOdl(20)).
Referring to figure 11, a block diagram of the clock generator lOc and 20c, shown in figure 2, is illustrated. In figure 11, clock generator lOc includes a processor clock module lOcl connected to the sync circuit lOdl. A T clock lOc2 is connected to the processor clock module lOcl. An S clock lOc3 is connected to the processor clock module lOcl. A C
clock lOc4 is connected to an oscillator 70, the oscillator 70 also being connected to the S clock lOc3 and the T clock lOc2. The C clock is connected, at its output, to the block circuit 30c via line 52. Clock generator 20c also includes a processor clock module 20cl connected to the sync EN98~023 - 13 -~:36~i~9 circuit 20dl. The module 20cl is further connected to a T clock 20c2, and to an S clock 20c3, the T 2 clock and the S clocks being connected to oscillator 3 70. The oscillator 70 is further connected to a C 4 clock 20c4 and an R clock 20c5. An output of the R 5 clock 20c5 is connected to an input of the S clock 6 20c3. An output of the S clock 20c3 is connected to 7 IPU 20a. The trap priority circuits lOF and 20F 8 each receive the IPU WAIT TRAP REQUEST signals from 9 the sync circuits lOdl and 20dl, respectively, and, 10 when appropriate, issue the DIR MISStIPU WAIT TR~P 11 signal to the processor clock modules lOcl and 20cl 12 causing them to undertake a clock synchronization 13 action. 14 Referring to figure 12, clock sequences associated 16 with the clocks for IPU lOa, IPU 20a, and the BSM 17 controls 30 are illustrated. Note that, at various 18 points along the sequence, the clock associated with 19 the BSM controls 30 is out-of-sync with respect to 20 the clock associated with IPU 20a and with respect 21 to the clock associated with IPU lOa. For example, 22 at one point along the sequence, the clock 23 associated with the BSM controls 30 generates the 24 following pulse sequence: O, 1, 2, 3, 0; the clock 25 associated with the IPU lOa generates the following 26 pulse sequence: O, 1, 2, 3, 0; however, the clock 27 associated with the IPU 20a generates the following 28 pulse sequence: O, l, 2, 3, 4, 5, O. When pulse 4 29 of IPU 20~ is generated, the clock associated with 30 the BSM controls 30 is out-of-sync with the clock 31 associated with the IPU 20a. As will be 32 demonstrated in the functional description presented 33 in the following paragraphs, the clock associated 34 with the IPU 20a must be synchronized with the clock 35 associated with the ~lock circuit 30c of the BSM 36 controls 30 prior to flushing a desired page of data 37 from the IPU 20a to the BSM 15. 38 ~2365~9 Referring to figure 13a, an out-of-sync situation is illustrated wherein the clock associated with one 2 processor ~e.g.-processor 10) is out-of-sync with 3 the clock associated with the BSM controls 30. Note 4 that pulse zero associated with the Proc 0 clock is 5 out of sync with pulse zero associated with the BSM 6 controls clock. 7 Referring to figure 13b, an in-sync situation is 9illustrated wherein the clock associated with the 10 one processor is in-sync with the clock associated llwith the BSM controls 30. Pulse zero associated 12 with the Proc 0 clock is in sync with the pulse zero 13 associated with the BSM controls clock. The figure 14 13b situation represents an in-sync condition 15because, when pulse 0 of the processor 10 clock 16 energizes IPU lOa, releasing data from cache lOb for 17 storage in BSM 15, pulse 2 of the BSM controls 30 18 clock will energize the BSM 15 at the precise point l9 in time ~two pulse periods from initiation of pulse 20 0) in order to accept the released data. 21 The functional operation of the present invention 23 will be described in the following paragraphs with 24 reference to figures 1 through 13b of the drawings. 25 Referring to figure l, a multiprocessor system is 27 illustrated. In figure l, when processor lO 28 searches for data in its cache and fails to locate 29 the data, it searches for the data in the cache of 30 processor 20. If it locates the data in the cache 31 of processor 20, the data is either directly 32 transferred to the cache of processor lO or it is 33 transferred to BSM 15 for use by processor 10, 34 depending upon the type of instruction being 35 executed by processor 10. If the type of 36 instruction being executed by processor lO requires 37 that the data in the cache of processor 20 be 38 transferred to the BSM 15, prior to the transfer (or 39 ~23~ 9 flush), the clocks of the processor 20 must be synchronized with the clocks energizing the BSM 15. 2 When the clocks of processor 20 are synchronized 3 with the clocks energizing the BSM 15, the data is 4 flushed from processor 20 to the BSM 15. Processor 5 10 may then utilize the data in the execution of its 6 instruction. In the above sequence of functional 7 events, the transfer or flush of the data from 8 processor 20 to BSM 15 is blocked temporarily until 9 the clocks of processor 20 are synchronized with the 10 clocks energizing the BSM 15. When the above 11 referenced clocks are synchronized, the blocking 12 function is terminated. When the blocking function 13 is terminated, the transfer of the data from 14 processor 20 to BSM 15 begins. 15 However, if a further instruction is being executed 17 by processor 10 which does not require a flush of 18 the data from processor 20 to BSM 15, rather, it 19 requires a direct transfer of the data from the 20 cache of processor 20 to the cache of processor 10, 21 the above referenced blocking function is precluded 22 or prevented from occurring; the data is directly 23 transferred from the cache of processor 20 to the 24 eache of processor 10 and execution of the further 25 instruction begins. 26 In the multiprocessor system of figure 1, when the 28 original instruction is being exeeuted by processor 29 10, requiring a flush operation, the blocking 30 function occurs thereby blocking the flush operation 31 until the clock synchronization operation is 32 complete. When the synchronization is complete, the 33 flush operation begins. When the flush operation is 34 complete, the "mask" is removed and the original 35 ins~ruction is executed. However, when the further 36 instruction is being executed by processor 10, not 37 requiring the flush operation, there is no need for 38 a synchronization operation. Therefore, there is no 39 ~2~5~39 need for a blocking functionr since the flush operation is normally blocked in order to permit the 2 clock synchronization to be completed. As a result, 3 when the execution of the further instruction is 4 sensed, the blocking function is precluded from 5 occurring. 6 Referring to figure 2, a more detailed construction 8 of the multiprocessor system of figure 1 is 9 illustrated. In figure 2, when IPU 20a executes an 10 instruction, it may need data stored in BSM 15. 11 Consequently, the data is retrieved from BSM 15 and 12 stored in cache 20b via line 40 marked "data". The 13 data is stored in cache 20b because the length of 14 time required to subsequently withdraw data from 15 cache 20b is much smaller than the length of time 16 required to subsequently withdraw data from BSM 15. 17 When the instruction is executed, the data may be 18 modified. The modified data is re-stored in cache 19 20b. The original, un-modified data still resides 20 in the BSM 15. 21 Assume that processor 10 must execute an instruction 23 which requires the utilization of the modified data 24 stored in cache 20b of processor 20. Further assume 25 that the instruction to be executed by processor 10 26 is a special type of instruction wherein data must 27 be retrieved from the main store (BSM) 15 and cannot 28 be retrieved directly from the other processor 29 [processor 20). This special type of instruction 30 may, for example, be a so-called "wherever" type of 31 instruction. 32 Prior to execution of the instruction, the cache 34 directory lOe of processor 10 evaluates cache lOb to 35 determine if the modified data is stored therein. 36 When it determines that the modified data is not 37 stored in cache lOb, processor 10 instructs cache 38 directory 20e of processor 20, via lines 42 and 43, 39 ~;~36S~9 to search the cache 20b of processor 20 for the modified data. The cache directory 20e searches 2 cache 20b for the modified data, via line 44. 3 Simultaneously with the search of cache 20b for the 5 modified data, cache directory 20e energi~es the ACS 6 GEN circuit 20d2, via line 46. When the cache 7 directory 20e determines that the modified data is 8 stored in cache 20b, the sync circuit 20dl begins a 9 synchronization operation, to be discussed below. 10 However, with respect to the ACS GEN circuit 20d2, 11 referring to figure 5, the ICT Control (2) 20d2(a) 12 of the ACS GEN 20d2 generates the ll_y busy gate 13 XBRD" signal indicating that a search of the cache 14 20b is currently being implemented in an effort to 15 locate the modified data. The "-Y busy gate XBRD" 16signal energizes the ICT Con-trol(l) lOd2(b) of the 17ACS GEN lOd2 via line 48 in figure 2. 18 When the cache directory 20e determines that the 20 modified data is stored in cache 20b, the cache 21 directory 20e of processor 20 transmits hit/modified 22 information to the command status register 30b via 23 line 49 storing a "flush" indication therein. The 24 hit/modified "flush" indication, stored within the 25 command status register 30b, indicates that the 26 desired, modified data is stored in cache 20b and 27 that a flush of the data to the BSM is needed. 28 Command status register 30b, normally associated 29 with processor 20, is being borrowed by processor 10 30 for use during the execution of its instruction. 31 Referring to figure 6, the "-Y busy gate XBRD" 33signal is received by the receiver circuit (b)12 of 34 the ~CT Control(l) lOd2(b) disposed within the ACS 35 GEN lOd2. As a result, the SRL latch ~b)ll is set 36 and an output is generated in response to this 37 signal and in response to outputs from clock driver 38 (b)10 (clock driver generates a signal in response 39 ~N984023 - 18 -~36~
to clocks C1/C3 and the on-board output signal from SRL scan only latch (b)8. The output signal from 2 SRL latch (b)11 eventually energizes the first input 3 terminal of OR driver (b)7 via a pair of inverters 4 (b)12 and (b)13. The OR driver (b)7 of the ICT 5 Control(1) lOd2(b) of ACS GEN lOd2 generates an ALT 6 CACHE SEARC~#l signal, this signal energizing the 7 block circuit 30c of the BSM controls 30 via line 8 50. 9 At this point, the desired, modified data, stored in 11 cache 20b, should be "flushed" from cache 20b of 12 processor 20 to the main store (BSM) 15. However, 13 since the instruction being executed by processor 10 14 is a type which requires that the modified data in 15 cache 2Ob be flushed to the BSM, and since the 16 modified data was located in cache 20b, prior to the 17 flushing of the desired, modified data from cache 18 20b to BSM 15, the clocks of processor 20 must be 19 synchroniz~d with the clocks of the BSM controls 30. 20 Therefore, the "flush" operation must be delayed 21 until the clocks of the processor 20 are 22 synchronized with the clocks of the BSM controls 30. 23 The following discussion will describe the pre-flush 24synchronization operation wherein, in view of the 25 type of instruction being executed by processor 10 26 and in view the flush indication stored in CS REG 27 30b, the flush operation is temporarily blocked 28 (that is, prevented) from occurring while the clocks 29 of processor 20 are synchronized with the clocks of 30 the BSM controls 30. 31 -When the hit/modified information fxom the cache33 directory 20e energizes the command status register 34 30b, a "flush" indication is stored in CS REG 30b. 35 In addition, IPU lOa is executing a special 36 instruction which requires that modified data, 37 located in the other processor's cache ~cache 20b), 38 be flushed to the BSM 15 prior to accessing the data 39 in the BSM 15, rather than directly transferring the modified data from cache to cache. One example of 2 this special instruction is a "wherever" type of 3 instruction. Assuming that the instruction being 4 executed by processor 10 is a "wherever" type of 5 instruction, a special instruction type indication 6 "wherever" is stored in CS REG 30a. In this 7 instance, since the special instruction type 8 indication "wherever" is stored in CS REG 30a and 9 the "flush" indication is stored in CS REG 30b, ~he 10 stacked op discriminator circuit 30d develops an11 output signal therefrom which energizes the block 12 circuit 30c. Furthermore, the ALT CACHE SEARCH#l13 signal from the ACS GEN 10d2 via line 50 also 14 energizes the block circuit 30c. 15 It should be noted that the output signal from the 17 stacked op discriminator circuit 30d was developed 18 in response to the special instruction type 19 indication "wherever" stored in CS REG 30a and the 20 "flush" indication stored in CS REG 30b. If any 21 other combination of said indications was stored in 22 CS REGs 30a and 30b, an output signal from the 23 stacked op discriminator circuit 30d would not have 24 been developed. This output signal is ultimately25 responsible for blocking the flush operation until 26 the clock synchronization operation is complete.27 When the clock synchronization operation is 28 complete, the flush operation begins. When the 29 flush operation is complete, the execution of the 30 special instruction "wherever" begins. The absence 31 of said output signal would prevent the blocking32 function from occurring and would allow execution of 33 the special instruction "wherever" to begin. 34 Therefore, the stacked op discriminator circuit 30d 35 senses the presence of the special type of 36 instruction indication "wherever" stored in CS REG 37 30a and the presence of the flush indication in CS 38 REG 30b and "masks" the "wherever" command or 39 EN98~023 - 20 -indication from the multiprocessing system of figure
A FIRST STORAGE MEANS FROM A SY~TEM 2 The present invention relates to multiprocessor 10 computer technology, and more particularly, to a 11 masking circuit within a multiprocessor computer 12 system for masking the contents of a first command 13 status register, associated with a first processor, 14 from the multiprocessor system until the contents of 15 a second command status register, associated with a 16 second processor, is executed. 17 In a multiprocessor computer system, when one 19 processor attempts to locate desired data in its own 20 cache, and fails to locate such data, it is 21 necessary to attempt to locate the data in the cache 22 of the other processor. If the data is not found in 23 the cache of the other processor, it is necessary to 24 retrieve the data from a main store. Occasionally, 25 the data is found in the cache of the other 26 processor. The one processor must utilize the 27 desired data in the execution of an instruction. 28 For some instructions, the one processor may 30 retrieve the data directly from the cache of the 31 other processor, store the data in its own cache, 32 and utilize the data in the execution of the 33 instruction. 34 However, for other instructions, the one processor 36 cannot retrieve the data directly from the cache of 37 the other processor. It is therefore necessary to 38 perform a flush operation. During the flush 39 ~k ~3 Ei5t~3~
operation, the desired data is flushed from the cache of the other processor to the main store. The 2 data is then utilized by the one processor in the 3 execution of its instruction. 4 However, during the flush operation, the one 6 processor may be attempting to execute a command. 7 If the command may be classified as one of said 8 other instructions, in view of the need to flush the 9 desired data from the cache of the other processor 10 to the main store prior to the execution of the 11 command, it is necessary to mask the presence of the 12 command, in the one processor, from the remainder of 13 the multiprocessor system until the flush operation 14 is complete. When the flush operation is complete, 15 the mask, associated with the command, is released 16 and the command is executed. However, if the 17 command may not be classified as one of said other 18 instructions, the presence of the command should not 19 be masked from the remainder of the multiprocessor 20 system and execution of the command should commence 21 uninhibited. 22 It is a primary object of the present invention to 26 provide an apparatus for masking the contents of a 27 first storage means from a system until the contents 28 of a second storage means is executed, and for 29 releasing the mask associated with the first storage 30 means when the contents of the second storage means 31 is executed. 32 It is another object of the present invention to 34 provide an apparatus for masking the contents of a 35 first command status register in a multiprocessing 36 system from said system thereby preventing the 37 ~36~9 execution of the contents of said first command status register until the contents of a second 2 command status in said multiprocessing system has 3 been executed and for releasing the mask associated 4 with the first command status register when the 5 contents of the second command status register is 6 executed. 7 These and other objects of the present invention are 9 accomplished by providing a circuit in a system 10 which senses the storage of information in one 11 storage means and senses the storage of information 12 in another storage means and which masks the 13 information in the one storage means from the system 14 in order to permit the system to access the 15 information stored in the second storage means. 16 Specifically, the system is a multiprocessor system, 17 the one storage means being a first command status 18 register for storing command information therein 19 associated with a firs' processor of the 20 multiprocessor system, the second storage means 21 being a second command status register for storing 22 command inform~tion therein associated with a second 23 processor of the multiprocessor system. The circuit 24 in the multiprocessor system is a stacked op 25 discriminator circuit which senses the existence of 26 command information stored in the first command 27 status register and senses the existence of 28 information (not necessarily command information) 29 stored in the second command status register and 30 masks the command information in the first command 31 status register from the multiprocessor system in 32 order to permit the information stored in the second 33 command status register to be executed by the 34 multiprocessor systemO When the information stored 35 in the second command status register has been 36 executed by the multiprocessor system, the mask, 37 associated with the first command status register, 38 3~
is released and the command information stored therein is executed by the multiprocessor system. 2 Further scope of applicability of the present 4 invention will become apparent from the detailed 5 description presented hereinafter. It should be 6 understood, however, that the detailed description 7 and the specific examples, while representing a 8 preferred embodiment of the invention, are given by 9 way of illustration only, since various changes and 10 modifications within the spirit and scope of the ll invention will become obvious to one skilled in the 12 art from a reading of the following detailed 13 description. 14 A full understanding of the present invention will 18 be obtained from the detailed description of the 19 preferred embodiment presented hereinbelow, and the 20 accompanying drawings, which are given by way of 21 illustration only and are not intended to be 22 limitative of the present invention, and wherein: 23 figure 1 illustrates a block diagram of a 25 multiprocessor system in accordance with the present 26 invention; 27 figure 2 illustrates a more detailed block diagram 29 of the multiprocessor system of figure 1; 30 figure 3 illustrates a block diagram of a BS~ 32 control circuit, a portion of the multiprocessor 33 system of figure 2; 34 figure 4 illustrates a block diagram of the stacked 36 op discriminator circuit of figure 3; 37 EN984023 - 4 _ . ~365~9 figure 5 illustrates a block diagram of a pair of alternate cache signal generation circuits, a 2 portion of the multiprocessor system of figure 2; 3 figure 6 illustrates a block diagram of the ICT 5 Control(l), a portion of the alternate cache signal 6 generation circuits of figure 5; 7 figure 7 illustrates a block diagram of a block 9 circuit, a portion of the multiprocessor system of 10 figure 2; 11 ..
figure 8 illustrates a block diagram of a sync 13 circuit, a portion of the multiprocessor system of 14 figure 2; 15 figure 9 illustrates a block diagram of the IPU W~IT 17 TRAP SRL, a portion of the sync circuit of figure 8; 18 figures lOa and lOb illustrate block diagrams of the 20 nand-invert (NI) circuits of figure 9 and the SRL21 latch circuits (SRL) of figures 6, 7, 8, and 9, 22 respectively; 23 figure 11 illustrates a block diagram of the clock 25 circuits of figure 2; 26 figure 12 illustxates the clock se~uences associated 28 with the instruction processing unit (IPU) circuits, 29 IPU 0 and IPU 1, and the BSM control circuit shown 30 in figure 2; 31 figure 13a illustrates an out-of-sync situation 33 wherein a processor's clocks are out-of-sync with a 34 main store (BSM) control clock; and 35 figure 13b illustrates an in-sync situation wherein 37 a processor's clocks are in-sync with a main store 38 (BSM) control clock. 39 - ~2~65i~
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Re~erring to figure 1, a multiprocessor system iS 3 illustrated. In figure 1, a first processor 10, of 4 the multiprocessor system, is connected to a main 5 memory 15 by way of a system bus (the main memory 6 being alternatively termed a Basic Storage Module 7 BSM or a main store). A second processor 20, of the 8 multiprocessor system, is also connected to the main 9 store 15 by way of the system bus. 10 Referring to figure 2, a more detailed block diagram 12 of the multiprocessor system of figure 1 is13 illustrated. In figure 2, the first processor 10, 14 alternatively termed processor 0, includes an 15 instruction processing unit 10a (IPU 0), a cache 10b 16 (cache 0) connected to the IPU 10a, a clock17 generator 10c connected to the IPU 10a, and an X 18 module 10d connected to the clock generator 10c. 19 The X module 10d includes a novel sync circuit 10dl 20 connected to the clock generator 10c and an21 alternate cache search signal generation circuit 22 (ACS GEN) 10d2 connected to the sync circuit 10dl. 23 The first processor 10 further includes a trap 24 priority circuit 10f connected between the sync 25 circuit 10dl of the X module 10d and the clock 26 generator 10c, and a cache directory ~(Z) 10e 27 connected to cache 10b, to the sync circuit 10dl, to 28 the ACS GEN 10d2 of X module 10d, and to IPU 10a. 29 The second processor 20, alternatively termed 31 processor 1, includes an instruction processing unit 32 (IPU) 20a (IPU 1), a cache 20b (cache 1) connected 33 to the IPU 20a, a clock generator 20c connected to 34 the IPU 20a, and an X module 20d connected to the 35 clock generator 20c. The X module 20d includes a 36 novel sync circuit 20dl connected to the clock 37 generator 20c and an alternate cache search signal 38 generation circuit (ACS GEN) 20d2 connected -to the 39 ~236~
sync circuit 20dl. The second processor 20 further includes a trap priority circuit 20f connected 2 between the sync circuit 20dl of the X module 20d 3 and the clock generator 20c, and a cache directory 4 (Z) 20e connected to cache 20b, to the sync circuit 5 20dl and the ACS GEN 20d2 of X module 20d, and to 6 IPU 20a. 7 The multiprocessor system of figure 2 further 9 includes a main store control circuit 30, otherwise lO
termed a Basic Storage Module (BSM) control circuit 11 30 or "BSM Controls 30'l, connected to processor lO, 12 and in particular, to the X module lOd, the cache 13 lOb, and the cache directory lOe of processor 10, 14 and to processor 20, and in particular, to the X 15 module 20d, the cache 20b, and the cache directory 16 20e of processor 20. The BSM control 30 is further 17 connected to a main store 15 or Basic Storage Module 18 (BSM) 15. The BSM control 30 is responsible for 19 controlling the functioning of the multiprocessor 20 system of figure 2, the details of its functioning 21 being described in the paragraphs below which are 22 dedicated to a description of the functional 23 operation of the present invention. 24 Referring to figure 3, a block diagram of the BSM 26 controls 30 of figure 2 is illustrated. In figure 27 3, the BSM controls 30 comprise a command status 28 register (CS REG) 30a connected to the cache - 29 directory (Z) lOe and a command status register (CS 30 REG) 30b connected to the cache directory (Z) 20e. 31 The cache directories (Z) supply 32 hit/miss/flush/modified information to the command 33 status registers 30a and 30b. The command status 34 registers 30a and 30b are each connected to a 35 stacked op discriminator circuit 30d. The stacked 36 op discriminator circuit 30d receives the contents 37 of the command status registers 30a and 30b and 38 develops an oukput signal when the command status 39 3~5~39 registers 30a and 30b contain predetermined information. For example, when command status 2 register 30a contains a WHEREVER word, and command 3 status register 30b contains a flush indication from 4 cache directory (Z) 20e, the stacked op 5 discriminator circuit 30d develops an output signal. 6 The stacked op discriminator circuit 30d would also 7 generate an output signal if command status register 8 30b contained a WHEREVER word and command status 9 register 30a contained a flush indication from cache 10 director~ (z) 10e. The output signal (60j from the 11 stacked op discriminator circuit 30d performs a 12 "masking" function in that it masks the contents of 13 the command status register (CS REG) containing the 14 ~HEREVER word information from the remainder of the 15 BSM controls 30 and prevents the normal start signal 16 61 from being sent to the BSM ops control circuit 17 30g. The output signal 60 of the stacked op 18 discriminator circuit 30d also enables the contents 19 of the command status register containing the flush 20 indication to be seen b~ the BSM ops control circuit 21 30g. The stacked op discriminator circuit 30d is 22 connected to a block circuit 30c and to an AND gate 23 30e. A signal termed "allow reset BSM controls" 24 energizes the other input terminal of the AND gate 25 30e. The block circuit 30c is connected to clock 26 10c, to ACS GEN 10d2. The AND gate 30e is 27 connected, at its output terminal, to an input (set) 28 terminal of a stacked op latch 30fO The output 29 terminal of the stacked op latch 30f is connected to 30 the CS REG 30b and to a BSM OPS CONTROL CIRCUIT 30g. 31 The BSM ops control circuit 30g is connected, at its 32 output, to cache 10b, cache 20b, and to BSM 15, the 33 BSM ops control circuit 30g controlling the transfer 34 of data from the cache memories 10b and 20b to the 35 BSM 15 and vice-versa. 36 Referring to figure 4, a block diagram of the 38 stacked op discriminator circuit 30d of figure 3 is 39 illustrated. In figure 4, the stacked op discriminator circuit 30d comprises an AND gate 30dl 2 connected to CS REG 30a and an AND gate 30d2 3 connected to CS REG 30b. AND gate 30dl is connected 4 to AND gate 30d2~ and vice-versa. Further, AND gate 5 30dl is connected to a "BSM CTLS BUSY FO~ PU0" line, 6 and AND gate 30d2 is connected to a "BSM CTLS BUSY 7 FOR PU1" line. The outputs of AND gates 30dl and 8 30d2 are connected to an OR gate 30d3. The output 9 of OR gate 30d3 represents line 60 as shown in 10 figure 3. 11 Referring to figure 5, a block diagram of the 13 alternate cache search signal generation circuits 14 (ACS GEN) 10d2 and 20d2 of figure 2 is illustrated. 15 In figure 5, the ACS GEN 20d2 comprises portions of 16 an ICT Control (2) 20d2(a). The ICT Control (2) 17 20d2(a) receives signals from cache directory 20e 18 and sync circuit 20dl and generates output signals 19 "-Y busy gate XBRD" and "-Y flush XBRD" in response 20 thereto. The ACS GEN 10d2 comprises portions of an 21 ICT Control (2) 10d2(a) connected to sync circuit 22 10dl and cache directory (Z) 10e, the Control (2) 23 10d2(a) generating output signals "+Y REQ accepted" 24 and "+ flush reset" in response to output signals 25 from the cache directory (Z) 10e and sync circuit 26 10dl. The ACS GEN 10d2 also comprises portions of 27 an ICT Control(1) 10d2(b) connected to the ICT 28 Control (2) 10d2(a) and receiving the output signals 29 therefrom for developing the alternate cache search 30 signals in response thereto, the alternate cache 31 search signals being received by the block circui~ 32 30c. 33 Referring to figure 6, a block diagram of portions 35 of the ICT Control~l) 10d2(b) of figure 5 is 36 illustrated. In figure 6, the ICT Control(l) 37 10d2(b) portion comprises an SRL latch circuit (b~1 38 which receives the "+Y request accepted" signal from 39 ~L~3Çi5;~9 the ICT Control ~2) 10d2(a) and output signals from a clock driver circuit (b)2. The clock driver 2 circuit lb)2 receives an +SO clock signal. The 3 output of the SRL latch (b)l is connected to an 4 input terminal of an OR gate (b)3. The "-Y flush XBRD" signal energizes another input terminal of OR 6 gate (b)3 via receiver circuit (b)4 and inverter 7 (b)5. The "+flush reset" signal energizes another 8 input terminal of OR gate (b)3 via inverter ~b)6. 9 The output of OR gate tb)3 is connected to a second 10 input terminal of OR driver (b)7. The ICT 11 Control(l) 10d2tb) portion also comprises an SRL 12 scan only latch (b)8 connected, at output terminal 13 21, to the OR driver circuit (b)7 via inverter (b)9. 14 The latch (b)8 is connected, at output terminal 10, 15 to a clock driver circuit (b)10. A +Cl/C3 clock 16 also energizes the clock driver (b)10. The clock 17 driver circuit (b)10 is connected, at its output, to 18 the -C and +C input terminals of an SRL latch 19circuit (b)ll. The "-Y busy gate XBRD" signal 20energizes another input texminal of the SRL latch 21 circuit (b)11 via a driver/receiver circuit tb)12. 22 Output terminal 21 of of the SRL latch circuit tb)ll 23 is connected to the first input terminal of OR 24 driver (b)7 via inverters (b)12 and (b)13. A 25 -SO/-S2 clock energizes the second input of OR 26 driver (b)7 via inverter (b)14. The OR driver 27 circuit tb)7 generates the alternate cache search 28 signals which energize the block circuit 30c. 29 Referring to figure 7, a block diagram of the block 31 circuit 30c disposed within the BSM controls 30, is 32 illustrated. The block circuit 30c includes an AND 33 gate 30cl having one input terminal connected to a 34 "BSM busy controls" line and another input terminal 35 connected to the ACS GEN 10d2. The output of AND 36 gate 30cl is connected to OR gate 30c2, the other 37 input of which is connected to a "Reset BSM 38 controls" signal. The output of OR gate 30c2 is 39 connected to the input of a clock driver 30c3, the output of clock driver 30c3 including a +C output 2 terminal and a -C output terminal. The +C and -C 3 output terminals are input to an SRL latch circuit 4 30c4 (L1). The L1 (master) portion of the SRL latch 5 circuit 30c4 is connected internally to an L2 6 (slave) portion which is controlled by OR circuit 7 30c10. See figure 10b for a detailed construction 8 of this SRL latch circuit. An output of the SRL 9 latch circuit 30c4 (L2) is connected to an input of 10 invert gate 30c5. The output of invert gate 30c5 is 11 fed back to another input terminal of the SRL latch 12 circuit 30c4 (L1). An output terminal (~2) of SRL 13 latch circuit 30c4 is connected to one input of NAND 14 gate 30c6 (NAND gate 30c6 comprising an AND gate 15 with an inverter connected to its output terminal). 16 The other input of NAND gate 30c6 is connected to 17 the command status registers 30a and 30b via stacked 18 op discriminator circuit 30d (it should be noted, at 19 this point, that the command status registers 30a 20 and 30b shown in figures 3, 4, and 7 receive 21 hit/miss/modified data information from the cache 22 directories 10e and 20e, data information, and 23 information related to the initiation of exeeution 24 of a special instruetion called a "wherever", 25 abbreviated W.E., instruction). The output of NAND 26 gate 30c6 is conneeted to a clock driver circuit 27 30c7. The elock driver circuit 30e7 develops two 28 outputs: a +C output and a -C output. The +C and 29 the -C outputs of eloek driver 30e7 are eonneeted to 30 input terminals of an SRL lateh eircuit 30c8. The 31 output terminal of the SRL lateh eircuit 30c8 is 32 connected to the BSM ops control eircuit 30g. The 33 BSM ops control circuit 30g functions to initiate 34 the flush of data ~rom a processor's cache 10b or 35 20b to the BSM 15 and then execute the subsequent 36 WHEREVER word which has been masked during the flush 37 operation. 38 ~ ~:3658~
Referring to figure 8, a block diagram of sync circuits lOdl and 20dl is illustrated. In figure 8, 2 sync circuits lOdl and 20dl each comprise an AND 3 gate lOdl(10) connected to cache directories lOe and 4 20e for receiving hit/modified data information from 5 cache directories lOe and 20e, for receiving a clock 6 signal, and for receiving the special "wherever" 7 instruction indicating that the "wherever" 8 instruction is about to be executed. The output of 9 AND gate lOdl(10) is connected to an input of a 10 FLUSH REQ SRL latch circuit lOdl(12). This latch 11 circuit is the same latch circuit, in construction, 12 as the latch circuits 30c4 and 30c8. The SRL latch 13 circuit lOdl(12) is connected to an IPU WAIT TRAP 14 SRL latch circuit lOdl(14). Latch circuit lOdl(14) 15 develops an IP~ ~AIT TRAP REQUEST signal which 16 energizes clock generators lOc and 20c. When the 17 clock signal energizing the IPU's lOa and 20a are in 18 sync with the clock signal energizing the block 19 circuit 30c of the BSM controls 30, the clock 20 generators lOc and 20c generate a DIR MISS/IPU WAIT 21 TRAP signal which resets latch circuit lOdl(14) and 22 which energizes one input terminal of AND gate 23 lOdl(16). The other input of AND gate lOdl (16) 24 originates from the output terminal of latch circuit 25 lOdl(12). The output of AND gate lOdl (16) is 26 connected to an input of clock driver circuit 27 lOdl(18). A clock signal energizes the clock driver 28 circuit. The output of clock driver circuit 29 lOdl(18) is connected to an input of a FLUSH GO SRL 30 latch circuit lOdl(20). The output of the FLUS~ GO 31 latch circuit lOdl (20) iS connected to a reset 32 terminal of the FLUSH REQ latch circuit lOdl(12), 33 and to either the ACS GEN 1 Od2 or to the ACS GEN 34 lOd2 via the ACS GEN 20d2 (depending upon the sync 35 circuit). The ACS GEN lOd2 develops the alternate 36 cache search signal which energizes the block 37 circuitO 38 ii589 Referri~c ~o fi~.-e 9, a detailel construction of the IPU
WAIT TRAP SRT~ lO~l (14~ shown in figure 8 is illustrated.
Referring to figure lOa, a diayram o~ the construction of the nand~invert -ircuit (NI) shown in figure 9 is illus~rated.
Referring to figure lOb, a diagram of the construction of the SRL latch circuit shown in figure 9 is illustrated. In addition~ figure lOb illustrates the construction of the SRL
latch circuits shown in figures 6, 7 (latches 30c4 and 30c8), and 8 (the FLUSH REQ latch lOdl(12) and the FLUSI GO
latch lOdl(20)).
Referring to figure 11, a block diagram of the clock generator lOc and 20c, shown in figure 2, is illustrated. In figure 11, clock generator lOc includes a processor clock module lOcl connected to the sync circuit lOdl. A T clock lOc2 is connected to the processor clock module lOcl. An S clock lOc3 is connected to the processor clock module lOcl. A C
clock lOc4 is connected to an oscillator 70, the oscillator 70 also being connected to the S clock lOc3 and the T clock lOc2. The C clock is connected, at its output, to the block circuit 30c via line 52. Clock generator 20c also includes a processor clock module 20cl connected to the sync EN98~023 - 13 -~:36~i~9 circuit 20dl. The module 20cl is further connected to a T clock 20c2, and to an S clock 20c3, the T 2 clock and the S clocks being connected to oscillator 3 70. The oscillator 70 is further connected to a C 4 clock 20c4 and an R clock 20c5. An output of the R 5 clock 20c5 is connected to an input of the S clock 6 20c3. An output of the S clock 20c3 is connected to 7 IPU 20a. The trap priority circuits lOF and 20F 8 each receive the IPU WAIT TRAP REQUEST signals from 9 the sync circuits lOdl and 20dl, respectively, and, 10 when appropriate, issue the DIR MISStIPU WAIT TR~P 11 signal to the processor clock modules lOcl and 20cl 12 causing them to undertake a clock synchronization 13 action. 14 Referring to figure 12, clock sequences associated 16 with the clocks for IPU lOa, IPU 20a, and the BSM 17 controls 30 are illustrated. Note that, at various 18 points along the sequence, the clock associated with 19 the BSM controls 30 is out-of-sync with respect to 20 the clock associated with IPU 20a and with respect 21 to the clock associated with IPU lOa. For example, 22 at one point along the sequence, the clock 23 associated with the BSM controls 30 generates the 24 following pulse sequence: O, 1, 2, 3, 0; the clock 25 associated with the IPU lOa generates the following 26 pulse sequence: O, 1, 2, 3, 0; however, the clock 27 associated with the IPU 20a generates the following 28 pulse sequence: O, l, 2, 3, 4, 5, O. When pulse 4 29 of IPU 20~ is generated, the clock associated with 30 the BSM controls 30 is out-of-sync with the clock 31 associated with the IPU 20a. As will be 32 demonstrated in the functional description presented 33 in the following paragraphs, the clock associated 34 with the IPU 20a must be synchronized with the clock 35 associated with the ~lock circuit 30c of the BSM 36 controls 30 prior to flushing a desired page of data 37 from the IPU 20a to the BSM 15. 38 ~2365~9 Referring to figure 13a, an out-of-sync situation is illustrated wherein the clock associated with one 2 processor ~e.g.-processor 10) is out-of-sync with 3 the clock associated with the BSM controls 30. Note 4 that pulse zero associated with the Proc 0 clock is 5 out of sync with pulse zero associated with the BSM 6 controls clock. 7 Referring to figure 13b, an in-sync situation is 9illustrated wherein the clock associated with the 10 one processor is in-sync with the clock associated llwith the BSM controls 30. Pulse zero associated 12 with the Proc 0 clock is in sync with the pulse zero 13 associated with the BSM controls clock. The figure 14 13b situation represents an in-sync condition 15because, when pulse 0 of the processor 10 clock 16 energizes IPU lOa, releasing data from cache lOb for 17 storage in BSM 15, pulse 2 of the BSM controls 30 18 clock will energize the BSM 15 at the precise point l9 in time ~two pulse periods from initiation of pulse 20 0) in order to accept the released data. 21 The functional operation of the present invention 23 will be described in the following paragraphs with 24 reference to figures 1 through 13b of the drawings. 25 Referring to figure l, a multiprocessor system is 27 illustrated. In figure l, when processor lO 28 searches for data in its cache and fails to locate 29 the data, it searches for the data in the cache of 30 processor 20. If it locates the data in the cache 31 of processor 20, the data is either directly 32 transferred to the cache of processor lO or it is 33 transferred to BSM 15 for use by processor 10, 34 depending upon the type of instruction being 35 executed by processor 10. If the type of 36 instruction being executed by processor lO requires 37 that the data in the cache of processor 20 be 38 transferred to the BSM 15, prior to the transfer (or 39 ~23~ 9 flush), the clocks of the processor 20 must be synchronized with the clocks energizing the BSM 15. 2 When the clocks of processor 20 are synchronized 3 with the clocks energizing the BSM 15, the data is 4 flushed from processor 20 to the BSM 15. Processor 5 10 may then utilize the data in the execution of its 6 instruction. In the above sequence of functional 7 events, the transfer or flush of the data from 8 processor 20 to BSM 15 is blocked temporarily until 9 the clocks of processor 20 are synchronized with the 10 clocks energizing the BSM 15. When the above 11 referenced clocks are synchronized, the blocking 12 function is terminated. When the blocking function 13 is terminated, the transfer of the data from 14 processor 20 to BSM 15 begins. 15 However, if a further instruction is being executed 17 by processor 10 which does not require a flush of 18 the data from processor 20 to BSM 15, rather, it 19 requires a direct transfer of the data from the 20 cache of processor 20 to the cache of processor 10, 21 the above referenced blocking function is precluded 22 or prevented from occurring; the data is directly 23 transferred from the cache of processor 20 to the 24 eache of processor 10 and execution of the further 25 instruction begins. 26 In the multiprocessor system of figure 1, when the 28 original instruction is being exeeuted by processor 29 10, requiring a flush operation, the blocking 30 function occurs thereby blocking the flush operation 31 until the clock synchronization operation is 32 complete. When the synchronization is complete, the 33 flush operation begins. When the flush operation is 34 complete, the "mask" is removed and the original 35 ins~ruction is executed. However, when the further 36 instruction is being executed by processor 10, not 37 requiring the flush operation, there is no need for 38 a synchronization operation. Therefore, there is no 39 ~2~5~39 need for a blocking functionr since the flush operation is normally blocked in order to permit the 2 clock synchronization to be completed. As a result, 3 when the execution of the further instruction is 4 sensed, the blocking function is precluded from 5 occurring. 6 Referring to figure 2, a more detailed construction 8 of the multiprocessor system of figure 1 is 9 illustrated. In figure 2, when IPU 20a executes an 10 instruction, it may need data stored in BSM 15. 11 Consequently, the data is retrieved from BSM 15 and 12 stored in cache 20b via line 40 marked "data". The 13 data is stored in cache 20b because the length of 14 time required to subsequently withdraw data from 15 cache 20b is much smaller than the length of time 16 required to subsequently withdraw data from BSM 15. 17 When the instruction is executed, the data may be 18 modified. The modified data is re-stored in cache 19 20b. The original, un-modified data still resides 20 in the BSM 15. 21 Assume that processor 10 must execute an instruction 23 which requires the utilization of the modified data 24 stored in cache 20b of processor 20. Further assume 25 that the instruction to be executed by processor 10 26 is a special type of instruction wherein data must 27 be retrieved from the main store (BSM) 15 and cannot 28 be retrieved directly from the other processor 29 [processor 20). This special type of instruction 30 may, for example, be a so-called "wherever" type of 31 instruction. 32 Prior to execution of the instruction, the cache 34 directory lOe of processor 10 evaluates cache lOb to 35 determine if the modified data is stored therein. 36 When it determines that the modified data is not 37 stored in cache lOb, processor 10 instructs cache 38 directory 20e of processor 20, via lines 42 and 43, 39 ~;~36S~9 to search the cache 20b of processor 20 for the modified data. The cache directory 20e searches 2 cache 20b for the modified data, via line 44. 3 Simultaneously with the search of cache 20b for the 5 modified data, cache directory 20e energi~es the ACS 6 GEN circuit 20d2, via line 46. When the cache 7 directory 20e determines that the modified data is 8 stored in cache 20b, the sync circuit 20dl begins a 9 synchronization operation, to be discussed below. 10 However, with respect to the ACS GEN circuit 20d2, 11 referring to figure 5, the ICT Control (2) 20d2(a) 12 of the ACS GEN 20d2 generates the ll_y busy gate 13 XBRD" signal indicating that a search of the cache 14 20b is currently being implemented in an effort to 15 locate the modified data. The "-Y busy gate XBRD" 16signal energizes the ICT Con-trol(l) lOd2(b) of the 17ACS GEN lOd2 via line 48 in figure 2. 18 When the cache directory 20e determines that the 20 modified data is stored in cache 20b, the cache 21 directory 20e of processor 20 transmits hit/modified 22 information to the command status register 30b via 23 line 49 storing a "flush" indication therein. The 24 hit/modified "flush" indication, stored within the 25 command status register 30b, indicates that the 26 desired, modified data is stored in cache 20b and 27 that a flush of the data to the BSM is needed. 28 Command status register 30b, normally associated 29 with processor 20, is being borrowed by processor 10 30 for use during the execution of its instruction. 31 Referring to figure 6, the "-Y busy gate XBRD" 33signal is received by the receiver circuit (b)12 of 34 the ~CT Control(l) lOd2(b) disposed within the ACS 35 GEN lOd2. As a result, the SRL latch ~b)ll is set 36 and an output is generated in response to this 37 signal and in response to outputs from clock driver 38 (b)10 (clock driver generates a signal in response 39 ~N984023 - 18 -~36~
to clocks C1/C3 and the on-board output signal from SRL scan only latch (b)8. The output signal from 2 SRL latch (b)11 eventually energizes the first input 3 terminal of OR driver (b)7 via a pair of inverters 4 (b)12 and (b)13. The OR driver (b)7 of the ICT 5 Control(1) lOd2(b) of ACS GEN lOd2 generates an ALT 6 CACHE SEARC~#l signal, this signal energizing the 7 block circuit 30c of the BSM controls 30 via line 8 50. 9 At this point, the desired, modified data, stored in 11 cache 20b, should be "flushed" from cache 20b of 12 processor 20 to the main store (BSM) 15. However, 13 since the instruction being executed by processor 10 14 is a type which requires that the modified data in 15 cache 2Ob be flushed to the BSM, and since the 16 modified data was located in cache 20b, prior to the 17 flushing of the desired, modified data from cache 18 20b to BSM 15, the clocks of processor 20 must be 19 synchroniz~d with the clocks of the BSM controls 30. 20 Therefore, the "flush" operation must be delayed 21 until the clocks of the processor 20 are 22 synchronized with the clocks of the BSM controls 30. 23 The following discussion will describe the pre-flush 24synchronization operation wherein, in view of the 25 type of instruction being executed by processor 10 26 and in view the flush indication stored in CS REG 27 30b, the flush operation is temporarily blocked 28 (that is, prevented) from occurring while the clocks 29 of processor 20 are synchronized with the clocks of 30 the BSM controls 30. 31 -When the hit/modified information fxom the cache33 directory 20e energizes the command status register 34 30b, a "flush" indication is stored in CS REG 30b. 35 In addition, IPU lOa is executing a special 36 instruction which requires that modified data, 37 located in the other processor's cache ~cache 20b), 38 be flushed to the BSM 15 prior to accessing the data 39 in the BSM 15, rather than directly transferring the modified data from cache to cache. One example of 2 this special instruction is a "wherever" type of 3 instruction. Assuming that the instruction being 4 executed by processor 10 is a "wherever" type of 5 instruction, a special instruction type indication 6 "wherever" is stored in CS REG 30a. In this 7 instance, since the special instruction type 8 indication "wherever" is stored in CS REG 30a and 9 the "flush" indication is stored in CS REG 30b, ~he 10 stacked op discriminator circuit 30d develops an11 output signal therefrom which energizes the block 12 circuit 30c. Furthermore, the ALT CACHE SEARCH#l13 signal from the ACS GEN 10d2 via line 50 also 14 energizes the block circuit 30c. 15 It should be noted that the output signal from the 17 stacked op discriminator circuit 30d was developed 18 in response to the special instruction type 19 indication "wherever" stored in CS REG 30a and the 20 "flush" indication stored in CS REG 30b. If any 21 other combination of said indications was stored in 22 CS REGs 30a and 30b, an output signal from the 23 stacked op discriminator circuit 30d would not have 24 been developed. This output signal is ultimately25 responsible for blocking the flush operation until 26 the clock synchronization operation is complete.27 When the clock synchronization operation is 28 complete, the flush operation begins. When the 29 flush operation is complete, the execution of the 30 special instruction "wherever" begins. The absence 31 of said output signal would prevent the blocking32 function from occurring and would allow execution of 33 the special instruction "wherever" to begin. 34 Therefore, the stacked op discriminator circuit 30d 35 senses the presence of the special type of 36 instruction indication "wherever" stored in CS REG 37 30a and the presence of the flush indication in CS 38 REG 30b and "masks" the "wherever" command or 39 EN98~023 - 20 -indication from the multiprocessing system of figure
2. When the mask is established, the blocking 2 function is permitted to occur. When the blocking 3 function is established, the clock synchronization 4 operation is completed. When the clock 5 synchronization operation is completed, the blocking 6 function is terminated. When the blocking function 7 is terminated, the flush operation commences. When 8 the flush operation is completed, the "mask" is 9 removed and the execution of the "wherever" special 10 instruction is permitted to begin. 11 Referring to figure 4, a description of the13 functional operation of the stacked op discriminator 14 30d of figure 3 will be set forth. In figure 4, a 15 WHEREVER instruction indication, stored in CS REG 16 30a, energizes one input of AND gate 30dl. A FLUSH 17 indication, stored in CS REG 30b, energizes another 18 input of AND gate 30dl. Since a third input of AND 19 gate 30dl is active with the BSM CTLS BUSY FOR PU0 20 signal, AND gate 30dl develops an output signal 21 which energizes one input terminal of OR gate 30d3. 22 Therefore, the OR gate 30d3 develops an output 23 signal, representing the output signal of the 24 stacked op discriminator circuit 30d. Note that, in 25 this case, the stacked op discriminator 30d sensed 26 the existence of a WHEREVER instruction indication 27 in CS REG 30a and a FLUSH indication in CS REG 30b, 28 and developed an output signal in response thereto. 29 If the WHEREVER instruction indication were stored 30 in CS REG 30b, one input of AND gate 30d2 would be 31 energized. If the FLUSH indication were stored in 32 CS REG 30a, another input of AND gate 30d2 would be 33 energized. A third input of AND gate 30d2 would be 34 energized via the BSM CTLS BUSY FOR PUl signal. As 35 a result, AND gate 30d2 would develop an output 36 signal, and therefore, OR gate 30d3 would also 37 develop an output signal. With this output signal, 38 the stacked op discriminator circuit 30d will have 39 58~
sensed the existence of the WHEREVER instruction in CS REG 30b and the existence of the FLUSH indication 2 in CS REG 30a. 3 Referring to figure 7, a functional description of 5 the operation of the block circuit 30c will be set 6 forth. In figure 7, the ALT CACHE SEARCH #1 signal 7 from ACS GEN 10d2 energizes the AND gate 30cl while 8 the "BSM busy controls" signal also energizes the 9 AND gate 30cl. The output signal from the AND gate 10 30cl passes through OR gate 30c2 and energizes the 11 clock driver 30c3. In response to the clock signal 12 "CLK", the clock driver 30c3 develops a +C and a -C 13output signal which energizes the +C and the -C 14input terminals of the SRL latch circuit 30c4. The 15 Ll portion of the SRL latch circuit 30c4 is 16 connected internally to an L2 slave portion which is 17 controlled by OR circuit 30c10. See figure 10b for 18 a detailed construction of this SRL latch circuit. 19 The SRL latch circuit 30c4 develops an output signal 21 which energizes invert gate 30c5. As a result, 22 invert gate 30c5 develops an output signal which is 23 fed back to an input terminal of the SRL latch 24 circuit 30c4. An output terminal (L2) of SRL latch 25 circuit 30c4 is connected to one input of AND-invert 26or NAND gate 30c6. The output signal fr~m the 27 stacked op discriminator circuit 30d energizes the 28 other input of NAND gate 30c6. In response, the 29 output of NAND gate 30c6 goes to a "block" state 30 thereby preventing clock driver 30c7 from developing 31 a +C and -C to energize the SRL latch circuit 30c8. 32A detailed construction of the latch circuit 30c8 33 may be found in figure 10b of the drawings. This 34 prevents the latch circuit 30c8 from developing an 35 output signal to energize the BSM ops control 36 circuit 30g. Since the BSM ops control circuit 30g 37 does not become energized, the pending "flush" 38 operation will not start at this time. 39 ~.~3~iS139 Re~?rrirlg o figure 2, it was stated in the above paragraphs that the cache c_ ectG i 20e energizes the sync circuit 20dl via line ~6 simultaneously with the initiation of its search of cache 20b for the modified data. Referring to figure 8, a description of the functional operation of the sync circuit 20dl will be provided.
In figure 8, when the sync circuit 20dl receives the signal from the cache directory 20e via line 46, AND gate lOdl(1) generates an output signal which energizes a FLUSH REQ SRL
latch circuit lOdl(12). The latch circuit is set and an output signal is generated in response thereto. A detailed construction of the latch circuit lOdl(12) is illustrated in figure lOb of the drawings. The output signal from the FLUSH REQ latch circuit energizes the "-flush op" input terminal of the IPU WAIT TRAP SRL latch circuit lOdl(14). A
detailed construction of this latch circuit is illustrated in figure 9 of the drawings. The SRL lOdl~14) develops the "IPU WAIT TRAP REQUEST" output signal which energizes the trap priority circuit 20f. This trap priority circuit determines when a requested trap can be issued and at that time causes the trap to be taken. In this case, ~7hen the IPU wait trap is received by the trap priority circllit 20f, the DIR ~ISS/IPU WAIT TRAP signal is generated therefrom which energizes the clock generator 20c.
Referring to figure 11, a functional description of the clock generator lOc and 20c will be provided. In figure 11, R (lOc5 and 20c5), C (lOc4 and 20c4), S (lOc3 and 20c3) and T (l~c2 and 20c2) are clock ., .
~;~3~i~il39 pulse generation circuits that convert the raw oscillator outputs (O,E,O,E, etc) to various 2 numbered clock pulse sequences (e.g.: 3 R=0,1,2,3,0,1,2,3,etc). In figure 11, when the 4 processor clock module 20cl receives the DIR 5 MISS/IPU WAIT TRAP signal fxom the trap priority 6 circuit 20f, it resets a "run latch" within the S 7 (20c3) and T (20c2) clock pulse generation circuits 8 via line C3(a). This permits these clock pulse 9 generation circuits to cease generating clock pulses 10 when they reach the last numbered clock pulse in the 11 sequence currently in progress. For example, 12 0,1,2,3,4,5 is the S and T clock sequence for the 13 trap microword instruction. When clock pulse 5 is 14 reached, the S (20c3) and T (20c2) clock pulse 15 generation circuits will stop generating clock 16 pulses. The R (20c5) and C (20c4) clock pulse 17 generation circuits are not controlled by line C3 (2) 18 and thus they are free to keep running and producing 19 their 0,1,2,3,0,1,2,3 etc clock pulse sequences. 20 The clock pulse sequences of said R (20c5) and C 21 (20c4) clock pulse generation circuits are always in 22 sync and, furthermore, are always in sync! with the R 23 (lOc5) and C (lOc4) clock pulse generation circuits 24 in clock lOc of processor 0. When pulse 3 is 25 generated from the output of the R (20c5) clock 26 pulse generation circuit, it energizes the S (20c3) 27 clock pulse generation circuit such that its run 28 latch is restored or set to a run state. This 29 allows the S (20c3) clock pulse generatlon circuit 30 to begin generating clock pulse sequences at the 31 next 0 pulse time which will now be coincident with 32 the 0 pulse time being generated by both the R 33 (20c5) and C (20c4) clock pulse generation circuits. 34 In addition, line C3(a) energizes the S (20c3) clock 35 pulse generation circuit such that it will con~inue 36 to produce 0,1,2,3,0,1,2,3 etc clock pulse sequences 37 once it has started. Thus, the output o~ the 38 S(20c3) clock pulse generation circuit is 39 EN9g4023 - 24 -~Z;~5~3~
synchronized with the output of the R(20c5) clock pulse generation circuit. Glven that the outputs of 2 the R (lOc5/20c5) and C (lOc4/20c4) clock pulse 3 generation circuits are always synchronized, the 4 output of the S(20c3) clock pulse generation circuit 5 is now synchronized with the output of the C (lOc4) 6 c:Lock pulse generation circuit which energizes the 7 block circuit 30c. 8 Referring to figure 8, when the trap priority 10 circuit 20f receives the IPU wait trap, it generates 11 the DIR MISS/IPU ~AIT TRAP signal (54) which causes 12 the clock generator 20c energizing IPU 20, to 13 synchronize its clock with the clock energizing the 14 block circuit via line 52. In figure 8, the DIR 15 MISS/IPU WAIT TRAP signal is also received by AND 16 gate lOdl(16) along with an output signal from the 17 FLUSH REQ SRL lOdl(12). AND gate lOdl(16) develops 18 an output signal, energizing clock driver lOdl(18). 19 When energized by the clock signal CLK, the clock 20 driver lOdl(18) develops an output signal which sets 21 the FLUSH GO SRL latch circuit lOdl(20). An output 22 from the the FLUSH GO SRL lOdl(20) energizes the ACS 23 GEN 20d2. The ACS GEN 20d2 energizes the ACS GEN 24 lOd2 and the ACS GEN lOd2 develops the ALT CACHE 25 SEARCH#2 output signal which energizes the block 26 circuit 30c via line 48. The manner in which the 27 ACS GEN 20d2 develops its output signal energizing 28 the ACS GEN lOd2 and the manner in which the ACS GEN 29 lOd2 develops the ALT CACHE SEARCH#2 signal wlll be 30 discussed in the following paragraph with reference 31 to figures 5 and 6 of the drawings. 32 In figure 5, the ICT Control (2) 20d2(a) within the 34 ACS GEN 20d2 develops the "-Y flush XBRD" signal in 35response to the output signal from the FLUSH GO SRL 36 lOdl(20), the "-Y flush XBRD" signal being received 37by the ICT Control(l) lOd2(b) disposed within the 38 ACS GEN lOd2. In figure 6, the receiver (b)4 39 EN98~023 - 25 -~36Si~19 receives the "-~ flush XBRD" signal and generates its output signal which ultimately energizes the OR 2 gate (b)3 via inverter (b)5. The OR gate (b)3 3 generates its output in response thereto which 4 energizes the OR driver (b)7. As a result, the OR 5 driver develops the ALT CACHE SEARCH#2 signal. 6 Referring to figure 7, the ALT CACHE SEARCH#2 signal 8 is generated from the ACS GEN 10d2 and is received 9 by the AND gate 30cl of the block circuit 30c. The 10 other input terminal "BSM busy controls" is still 11 active. The AND gate 30cl develops an output signal 12 which energizes the clock driver 30c3 via OR gate 13 30c2. When the clock signal "CLK" is received by 14 the clock driver 30c3, a +C and a -C output signal 15is generated therefrom. The SRL latch circuit 30c4 16 receives the +C and the -C output signals, is reset, 17and develops a new output signal therefrom, which is 18 opposite to its previous output signal state. The 19 new output signal energizes NAND gate 30c6, changing 20 its output signal state to a new state. The new 21 state of the output signal from NAND gate 30c6 22 energizes clock driver 30c7. In response to the 23 clock signal "CLK", clock driver 30c7 develops its 24 changed output signal (+C and -C) energizing SRL 25latch circuit 30c8. The latch circuit 30c8 develops 26 its changed output signal which energizes the BSM 27 ops control circuit 30g. 28 Referring to figure 3, lines 30c9 and 64 from the 30 BSM ops control circuit are energized thereby 31 enabling BSM 15 and cache 20b. The clock signal 32 energizing the block circuit 30c from clock 33 generator 20c is in-sync with the clock signal 34energizing IPU 20a from clock generator 20c. 35 Therefore, the clock of processor 20 is in-sync with 36the clock of the BSM controls 30. The "flush" 37 operation may now begin. 38
sensed the existence of the WHEREVER instruction in CS REG 30b and the existence of the FLUSH indication 2 in CS REG 30a. 3 Referring to figure 7, a functional description of 5 the operation of the block circuit 30c will be set 6 forth. In figure 7, the ALT CACHE SEARCH #1 signal 7 from ACS GEN 10d2 energizes the AND gate 30cl while 8 the "BSM busy controls" signal also energizes the 9 AND gate 30cl. The output signal from the AND gate 10 30cl passes through OR gate 30c2 and energizes the 11 clock driver 30c3. In response to the clock signal 12 "CLK", the clock driver 30c3 develops a +C and a -C 13output signal which energizes the +C and the -C 14input terminals of the SRL latch circuit 30c4. The 15 Ll portion of the SRL latch circuit 30c4 is 16 connected internally to an L2 slave portion which is 17 controlled by OR circuit 30c10. See figure 10b for 18 a detailed construction of this SRL latch circuit. 19 The SRL latch circuit 30c4 develops an output signal 21 which energizes invert gate 30c5. As a result, 22 invert gate 30c5 develops an output signal which is 23 fed back to an input terminal of the SRL latch 24 circuit 30c4. An output terminal (L2) of SRL latch 25 circuit 30c4 is connected to one input of AND-invert 26or NAND gate 30c6. The output signal fr~m the 27 stacked op discriminator circuit 30d energizes the 28 other input of NAND gate 30c6. In response, the 29 output of NAND gate 30c6 goes to a "block" state 30 thereby preventing clock driver 30c7 from developing 31 a +C and -C to energize the SRL latch circuit 30c8. 32A detailed construction of the latch circuit 30c8 33 may be found in figure 10b of the drawings. This 34 prevents the latch circuit 30c8 from developing an 35 output signal to energize the BSM ops control 36 circuit 30g. Since the BSM ops control circuit 30g 37 does not become energized, the pending "flush" 38 operation will not start at this time. 39 ~.~3~iS139 Re~?rrirlg o figure 2, it was stated in the above paragraphs that the cache c_ ectG i 20e energizes the sync circuit 20dl via line ~6 simultaneously with the initiation of its search of cache 20b for the modified data. Referring to figure 8, a description of the functional operation of the sync circuit 20dl will be provided.
In figure 8, when the sync circuit 20dl receives the signal from the cache directory 20e via line 46, AND gate lOdl(1) generates an output signal which energizes a FLUSH REQ SRL
latch circuit lOdl(12). The latch circuit is set and an output signal is generated in response thereto. A detailed construction of the latch circuit lOdl(12) is illustrated in figure lOb of the drawings. The output signal from the FLUSH REQ latch circuit energizes the "-flush op" input terminal of the IPU WAIT TRAP SRL latch circuit lOdl(14). A
detailed construction of this latch circuit is illustrated in figure 9 of the drawings. The SRL lOdl~14) develops the "IPU WAIT TRAP REQUEST" output signal which energizes the trap priority circuit 20f. This trap priority circuit determines when a requested trap can be issued and at that time causes the trap to be taken. In this case, ~7hen the IPU wait trap is received by the trap priority circllit 20f, the DIR ~ISS/IPU WAIT TRAP signal is generated therefrom which energizes the clock generator 20c.
Referring to figure 11, a functional description of the clock generator lOc and 20c will be provided. In figure 11, R (lOc5 and 20c5), C (lOc4 and 20c4), S (lOc3 and 20c3) and T (l~c2 and 20c2) are clock ., .
~;~3~i~il39 pulse generation circuits that convert the raw oscillator outputs (O,E,O,E, etc) to various 2 numbered clock pulse sequences (e.g.: 3 R=0,1,2,3,0,1,2,3,etc). In figure 11, when the 4 processor clock module 20cl receives the DIR 5 MISS/IPU WAIT TRAP signal fxom the trap priority 6 circuit 20f, it resets a "run latch" within the S 7 (20c3) and T (20c2) clock pulse generation circuits 8 via line C3(a). This permits these clock pulse 9 generation circuits to cease generating clock pulses 10 when they reach the last numbered clock pulse in the 11 sequence currently in progress. For example, 12 0,1,2,3,4,5 is the S and T clock sequence for the 13 trap microword instruction. When clock pulse 5 is 14 reached, the S (20c3) and T (20c2) clock pulse 15 generation circuits will stop generating clock 16 pulses. The R (20c5) and C (20c4) clock pulse 17 generation circuits are not controlled by line C3 (2) 18 and thus they are free to keep running and producing 19 their 0,1,2,3,0,1,2,3 etc clock pulse sequences. 20 The clock pulse sequences of said R (20c5) and C 21 (20c4) clock pulse generation circuits are always in 22 sync and, furthermore, are always in sync! with the R 23 (lOc5) and C (lOc4) clock pulse generation circuits 24 in clock lOc of processor 0. When pulse 3 is 25 generated from the output of the R (20c5) clock 26 pulse generation circuit, it energizes the S (20c3) 27 clock pulse generation circuit such that its run 28 latch is restored or set to a run state. This 29 allows the S (20c3) clock pulse generatlon circuit 30 to begin generating clock pulse sequences at the 31 next 0 pulse time which will now be coincident with 32 the 0 pulse time being generated by both the R 33 (20c5) and C (20c4) clock pulse generation circuits. 34 In addition, line C3(a) energizes the S (20c3) clock 35 pulse generation circuit such that it will con~inue 36 to produce 0,1,2,3,0,1,2,3 etc clock pulse sequences 37 once it has started. Thus, the output o~ the 38 S(20c3) clock pulse generation circuit is 39 EN9g4023 - 24 -~Z;~5~3~
synchronized with the output of the R(20c5) clock pulse generation circuit. Glven that the outputs of 2 the R (lOc5/20c5) and C (lOc4/20c4) clock pulse 3 generation circuits are always synchronized, the 4 output of the S(20c3) clock pulse generation circuit 5 is now synchronized with the output of the C (lOc4) 6 c:Lock pulse generation circuit which energizes the 7 block circuit 30c. 8 Referring to figure 8, when the trap priority 10 circuit 20f receives the IPU wait trap, it generates 11 the DIR MISS/IPU ~AIT TRAP signal (54) which causes 12 the clock generator 20c energizing IPU 20, to 13 synchronize its clock with the clock energizing the 14 block circuit via line 52. In figure 8, the DIR 15 MISS/IPU WAIT TRAP signal is also received by AND 16 gate lOdl(16) along with an output signal from the 17 FLUSH REQ SRL lOdl(12). AND gate lOdl(16) develops 18 an output signal, energizing clock driver lOdl(18). 19 When energized by the clock signal CLK, the clock 20 driver lOdl(18) develops an output signal which sets 21 the FLUSH GO SRL latch circuit lOdl(20). An output 22 from the the FLUSH GO SRL lOdl(20) energizes the ACS 23 GEN 20d2. The ACS GEN 20d2 energizes the ACS GEN 24 lOd2 and the ACS GEN lOd2 develops the ALT CACHE 25 SEARCH#2 output signal which energizes the block 26 circuit 30c via line 48. The manner in which the 27 ACS GEN 20d2 develops its output signal energizing 28 the ACS GEN lOd2 and the manner in which the ACS GEN 29 lOd2 develops the ALT CACHE SEARCH#2 signal wlll be 30 discussed in the following paragraph with reference 31 to figures 5 and 6 of the drawings. 32 In figure 5, the ICT Control (2) 20d2(a) within the 34 ACS GEN 20d2 develops the "-Y flush XBRD" signal in 35response to the output signal from the FLUSH GO SRL 36 lOdl(20), the "-Y flush XBRD" signal being received 37by the ICT Control(l) lOd2(b) disposed within the 38 ACS GEN lOd2. In figure 6, the receiver (b)4 39 EN98~023 - 25 -~36Si~19 receives the "-~ flush XBRD" signal and generates its output signal which ultimately energizes the OR 2 gate (b)3 via inverter (b)5. The OR gate (b)3 3 generates its output in response thereto which 4 energizes the OR driver (b)7. As a result, the OR 5 driver develops the ALT CACHE SEARCH#2 signal. 6 Referring to figure 7, the ALT CACHE SEARCH#2 signal 8 is generated from the ACS GEN 10d2 and is received 9 by the AND gate 30cl of the block circuit 30c. The 10 other input terminal "BSM busy controls" is still 11 active. The AND gate 30cl develops an output signal 12 which energizes the clock driver 30c3 via OR gate 13 30c2. When the clock signal "CLK" is received by 14 the clock driver 30c3, a +C and a -C output signal 15is generated therefrom. The SRL latch circuit 30c4 16 receives the +C and the -C output signals, is reset, 17and develops a new output signal therefrom, which is 18 opposite to its previous output signal state. The 19 new output signal energizes NAND gate 30c6, changing 20 its output signal state to a new state. The new 21 state of the output signal from NAND gate 30c6 22 energizes clock driver 30c7. In response to the 23 clock signal "CLK", clock driver 30c7 develops its 24 changed output signal (+C and -C) energizing SRL 25latch circuit 30c8. The latch circuit 30c8 develops 26 its changed output signal which energizes the BSM 27 ops control circuit 30g. 28 Referring to figure 3, lines 30c9 and 64 from the 30 BSM ops control circuit are energized thereby 31 enabling BSM 15 and cache 20b. The clock signal 32 energizing the block circuit 30c from clock 33 generator 20c is in-sync with the clock signal 34energizing IPU 20a from clock generator 20c. 35 Therefore, the clock of processor 20 is in-sync with 36the clock of the BSM controls 30. The "flush" 37 operation may now begin. 38
3~i5i8~
When the clocks of IPU 20a are synchronized with the clocks of the block circuit 30c within the BSM 2 controls 30, the desired, modified data is flushed 3 or moved from cache 20b to the BSM 15. The desired 4 modified data is then available for use by the 5 processor 10 during the execution of its 6 instruction. 7 Now that the "flush" operation is complete, the BSM 9 controls 30 must be conditioned and restarted in 10 order to execute the WHEREVER type instruction, 11 originally issued by processor 10 and currently 12 stored in CS REG 30a. However, the CS REG 30b must 13 be reset and the system of figure 3 must be 14 restarted. To accomplish this objective, the output 15 from the stacked op discriminator circuit 30d 16 energizes one input terminal of AND gate 30e. At 17 this point in the sequence of the functional 18 description of the present invention, the other 19 input terminal of AND gate 30e is energized by the 20 "allow reset BSM controls" signal which occurs at 21 the completion of the "flush" operation. Therefore, 22 the AND gate 30e develops an output signal which 23 sets the stacked op latch 30~, the stacked op latch 24 30f developiny an output signal therefrom on lines 25 63 and 62. Line 63 provides a restart signal to the 26 BSM ops control circuit 30g, and line 62 provides a 27 reset signal to the CS REG 30b. Via line 62, the 28 flush indication stored in CS REG 30b is removed; 29 and, via line 63, a restart signal is provided to 30 the BSM ops control circuit 30g. Once CS REG 30b is 31 reset and the flush indication is removed, the 32 stacked op discriminator circuit is de-energized and 33 its output "mask" signal 60 disappears. This 34 "un-masks" the BSM ops control circuit 30g such that 35 it now sees the contents of CS REG 30a which 36 contains the W~EREVER type instruction information 37 for processor 10. Therefore, in response to the 38 restart signal, the BSM ops control circuit 30g 39 ' ~;~3 E;~i8~
develops an output signal on line 30c9, energizing the BSM 15, thereby allowing the execution of the 2 WHEREVER type instruction for processor 10 to begin. 3 The invention being thus described, it will be 5 obvious that the same may be varied in many ways. 6 Such variations are not to be regarded as a 7 departure from the spirit and scope of the 8 invention, and all such modifications as would be 9 obvious to one skilled in the art are intended to be 10 included within the scope of the following claims. 11 EN984023 - 28 ~
When the clocks of IPU 20a are synchronized with the clocks of the block circuit 30c within the BSM 2 controls 30, the desired, modified data is flushed 3 or moved from cache 20b to the BSM 15. The desired 4 modified data is then available for use by the 5 processor 10 during the execution of its 6 instruction. 7 Now that the "flush" operation is complete, the BSM 9 controls 30 must be conditioned and restarted in 10 order to execute the WHEREVER type instruction, 11 originally issued by processor 10 and currently 12 stored in CS REG 30a. However, the CS REG 30b must 13 be reset and the system of figure 3 must be 14 restarted. To accomplish this objective, the output 15 from the stacked op discriminator circuit 30d 16 energizes one input terminal of AND gate 30e. At 17 this point in the sequence of the functional 18 description of the present invention, the other 19 input terminal of AND gate 30e is energized by the 20 "allow reset BSM controls" signal which occurs at 21 the completion of the "flush" operation. Therefore, 22 the AND gate 30e develops an output signal which 23 sets the stacked op latch 30~, the stacked op latch 24 30f developiny an output signal therefrom on lines 25 63 and 62. Line 63 provides a restart signal to the 26 BSM ops control circuit 30g, and line 62 provides a 27 reset signal to the CS REG 30b. Via line 62, the 28 flush indication stored in CS REG 30b is removed; 29 and, via line 63, a restart signal is provided to 30 the BSM ops control circuit 30g. Once CS REG 30b is 31 reset and the flush indication is removed, the 32 stacked op discriminator circuit is de-energized and 33 its output "mask" signal 60 disappears. This 34 "un-masks" the BSM ops control circuit 30g such that 35 it now sees the contents of CS REG 30a which 36 contains the W~EREVER type instruction information 37 for processor 10. Therefore, in response to the 38 restart signal, the BSM ops control circuit 30g 39 ' ~;~3 E;~i8~
develops an output signal on line 30c9, energizing the BSM 15, thereby allowing the execution of the 2 WHEREVER type instruction for processor 10 to begin. 3 The invention being thus described, it will be 5 obvious that the same may be varied in many ways. 6 Such variations are not to be regarded as a 7 departure from the spirit and scope of the 8 invention, and all such modifications as would be 9 obvious to one skilled in the art are intended to be 10 included within the scope of the following claims. 11 EN984023 - 28 ~
Claims (4)
1.A system including a first storage means for storing information therein and a second storage means for storing other information therein, said system comprising:
masking circuit means connected to said first storage means and to said second storage means for sensing the existence of said information stored in said first storage means and the existence of said other information stored in said second storage means and for masking the existence of said information in said first storage means from said system until said other information in said second storage means is executed by said system.
masking circuit means connected to said first storage means and to said second storage means for sensing the existence of said information stored in said first storage means and the existence of said other information stored in said second storage means and for masking the existence of said information in said first storage means from said system until said other information in said second storage means is executed by said system.
2. The system of claim 1, further comprising:
further circuit means connected to said masking circuit means and responsive to an output signal generated therefrom for releasing the mask imposed by said masking circuit means on said first storage means when execution of said other information by said system is complete, said system executing said information stored in said first storage means when said mask is released by said further circuit means.
further circuit means connected to said masking circuit means and responsive to an output signal generated therefrom for releasing the mask imposed by said masking circuit means on said first storage means when execution of said other information by said system is complete, said system executing said information stored in said first storage means when said mask is released by said further circuit means.
3. A multiprocessor system wherein a desired page of data in the cache of a second processor is flushed to and stored in a main memory in response to a clock signal energizing said second processor and a clock signal energizing said main memory, said desired page of data stored in said main memory being utilized by a first processor in the execution of an instruction, said multiprocessor system comprising:
first circuit means for storing information therein associated with said first processor of said multiprocessor system;
second circuit means for storing information therein associated with said second processor of said multiprocessor system; and third circuit means connected to said first and said second circuit means and responsive to output signals developed therefrom for sensing the existence of said information stored in said first circuit means, for sensing the existence of said information stored in said second circuit means and for masking said information stored in one of said first and second circuit means from said multiprocessor system thereby permitting said information stored in the other of said first and second circuit means to be executed by said multiprocessor system.
first circuit means for storing information therein associated with said first processor of said multiprocessor system;
second circuit means for storing information therein associated with said second processor of said multiprocessor system; and third circuit means connected to said first and said second circuit means and responsive to output signals developed therefrom for sensing the existence of said information stored in said first circuit means, for sensing the existence of said information stored in said second circuit means and for masking said information stored in one of said first and second circuit means from said multiprocessor system thereby permitting said information stored in the other of said first and second circuit means to be executed by said multiprocessor system.
4. The multiprocessor system of claim 3, further comprising:
fourth circuit means connected to said third circuit means for releasing the mask associated with said one of said first and second circuit means when said information stored in the other of said first and second circuit means has been executed by said multiprocessor system thereby permitting said information stored in said one of said first and second circuit means to be executed by said multiprocessor system.
fourth circuit means connected to said third circuit means for releasing the mask associated with said one of said first and second circuit means when said information stored in the other of said first and second circuit means has been executed by said multiprocessor system thereby permitting said information stored in said one of said first and second circuit means to be executed by said multiprocessor system.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/664,283 US4713751A (en) | 1984-10-24 | 1984-10-24 | Masking commands for a second processor when a first processor requires a flushing operation in a multiprocessor system |
| US664,283 | 1984-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1236589A true CA1236589A (en) | 1988-05-10 |
Family
ID=24665380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000482000A Expired CA1236589A (en) | 1984-10-24 | 1985-05-21 | Apparatus for masking the contents of a first storage means from a system until the contents of a second storage means is executed by said system |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4713751A (en) |
| EP (1) | EP0185137B1 (en) |
| JP (1) | JPS61101853A (en) |
| CA (1) | CA1236589A (en) |
| DE (1) | DE3588031T2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62237522A (en) * | 1986-04-08 | 1987-10-17 | Nec Corp | Information processor |
| US5088033A (en) * | 1986-04-28 | 1992-02-11 | Xerox Corporation | Data processing system emulation in a window with a coprocessor and I/O emulation |
| US5045996A (en) * | 1986-11-12 | 1991-09-03 | Xerox Corporation | Multiprocessor cache memory housekeeping |
| US4953077A (en) * | 1987-05-15 | 1990-08-28 | International Business Machines Corporation | Accelerated data transfer mechanism using modified clock cycle |
| US6073139A (en) * | 1996-08-15 | 2000-06-06 | Gioquest, A Division Of Schlumberger Technology Corp. | Integrated data communication and data access system including the application data interface |
| US6122711A (en) | 1997-01-07 | 2000-09-19 | Unisys Corporation | Method of and apparatus for store-in second level cache flush |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5841538B2 (en) * | 1975-12-04 | 1983-09-13 | 株式会社東芝 | Multiprocessor system instructions |
| US4268904A (en) * | 1978-02-15 | 1981-05-19 | Tokyo Shibaura Electric Co., Ltd. | Interruption control method for multiprocessor system |
| US4275440A (en) * | 1978-10-02 | 1981-06-23 | International Business Machines Corporation | I/O Interrupt sequencing for real time and burst mode devices |
| FR2474201B1 (en) * | 1980-01-22 | 1986-05-16 | Bull Sa | METHOD AND DEVICE FOR MANAGING CONFLICTS CAUSED BY MULTIPLE ACCESSES TO THE SAME CACH OF A DIGITAL INFORMATION PROCESSING SYSTEM COMPRISING AT LEAST TWO PROCESSES EACH HAVING A CACHE |
| US4400773A (en) * | 1980-12-31 | 1983-08-23 | International Business Machines Corp. | Independent handling of I/O interrupt requests and associated status information transfers |
| US4494193A (en) * | 1982-09-30 | 1985-01-15 | At&T Bell Laboratories | Deadlock detection and resolution scheme |
-
1984
- 1984-10-24 US US06/664,283 patent/US4713751A/en not_active Expired - Lifetime
-
1985
- 1985-05-21 CA CA000482000A patent/CA1236589A/en not_active Expired
- 1985-06-27 JP JP60139265A patent/JPS61101853A/en active Granted
- 1985-08-20 DE DE3588031T patent/DE3588031T2/en not_active Expired - Fee Related
- 1985-08-20 EP EP85110386A patent/EP0185137B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4713751A (en) | 1987-12-15 |
| DE3588031D1 (en) | 1995-07-27 |
| EP0185137B1 (en) | 1995-06-21 |
| EP0185137A2 (en) | 1986-06-25 |
| DE3588031T2 (en) | 1996-02-29 |
| JPS61101853A (en) | 1986-05-20 |
| JPH0460255B2 (en) | 1992-09-25 |
| EP0185137A3 (en) | 1988-12-28 |
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