CA1235800A - Write clock pulse generator used for a time base corrector - Google Patents
Write clock pulse generator used for a time base correctorInfo
- Publication number
- CA1235800A CA1235800A CA000487218A CA487218A CA1235800A CA 1235800 A CA1235800 A CA 1235800A CA 000487218 A CA000487218 A CA 000487218A CA 487218 A CA487218 A CA 487218A CA 1235800 A CA1235800 A CA 1235800A
- Authority
- CA
- Canada
- Prior art keywords
- pulse
- frequency
- signal
- clock
- color burst
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/87—Regeneration of colour television signals
- H04N9/89—Time-base error compensation
- H04N9/896—Time-base error compensation using a digital memory with independent write-in and read-out clock generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A write clock pulse generator is disclosed, in which a horizontal synchronizing signal is separated from an input video signal and supplied to a PLL (phase locked loop) circuit to form a first clock with the frequency of nfH (n is an inte-ger), a color burst signal is separated from the input video signal and used to drive a gate type variable oscillator to thereby form a second clock synchronized in phase with the color burst signal and whose average frequency is nfH, a dif-ference between the pulse widths of the clocks resulting from counting down the first and second clocks to l/M and the fre-quency of the variable oscillator is controlled by the compared output therebetween, whereby to produce a second clock synchro-nized in phase with the color burst signal and the frequency of which is n times the horizontal synchronizing signal.
A write clock pulse generator is disclosed, in which a horizontal synchronizing signal is separated from an input video signal and supplied to a PLL (phase locked loop) circuit to form a first clock with the frequency of nfH (n is an inte-ger), a color burst signal is separated from the input video signal and used to drive a gate type variable oscillator to thereby form a second clock synchronized in phase with the color burst signal and whose average frequency is nfH, a dif-ference between the pulse widths of the clocks resulting from counting down the first and second clocks to l/M and the fre-quency of the variable oscillator is controlled by the compared output therebetween, whereby to produce a second clock synchro-nized in phase with the color burst signal and the frequency of which is n times the horizontal synchronizing signal.
Description
BACKGROUND OF THE INVENTION ~35~
Field of the invention This invention relates generally to a clock generator and more particularly to a write clock generator used for a time base corrector (TBC) which is provided in the reproducing system of a video tape recorder (VTR).
Description of the Prior Art -Generally, a time base corrector is proYided in the reproducing system of a professional VTR and so on in order to remove a jitter in a reproduced video signal or the like.
This time base corrector requires to provide with a write clock generator for generating a write clock pulse which is capable of ~5 accurately following the jitter o~ ~he reproduced ~ideo signal and which is in phase wi~h a color burst signal.
Fig. 1 is a block di.agram showing an example of such prior art write clock pulse generator 10 for use with the time base corrector which is disclosecl more in detail in, for exam-ple, USP. 4, 165, 524 (by the same assingee).
Referring to ~'ig. 1, a reproduced video signal Sv applied to a terminal 1 is supplied to a synchronous separat~
ing circuit 2 in which a horizontal synchronizing signal PH is separated from the reproduced video signal Sv. This horizon-tal synchronizing signal P~ is supplied to a PLL (phase locked loop) circuit 3 which formes a clock CXl of the frequency nfH
(n is an integer and fH is a horizontal frequency) following the frequency fluctuation of the horizontal synchronizing signal PH. In this example, n is selected to be 910 for the NTSC system and 1135 for the PAL system, respectively.
~2358~3~
The reproduced video signal Sv is further supplied to a color burst separating circuit 4 in which a color burst signal Sg is separated from the reproduced video signal Sv.
This color burst signal SB is supplied to an APC (automatic phase control) circuit 5 which synchronizes the phase of the clock CKl supplied thereto. Thus, at a~ output terminal 6 led out from the APC circuit 5, there is developed a write clock CKw synchronized in phase with the color burst signal SB
and the frequency of which is same as that of the clock CRl.
Though not shown, the write clock CKW is used as a sampling clock for analog-to-digital converting the reproduced video signal Sv and also as a write clock for a digital memory.
By the way, when the clock generating circuit 10 is arranged as described above, the APC circuit 5 for phase-syn-chro~ization generally includes a vast number of circuit ele-ments and in which an analog signal processing system and a digital signaL processing system exist therein in a mixed state so that this clock generating circuit 10 is not suitable for being formed as an IC (integrated circuit). Further, this prior art clock generating circuit lO has the analog slgnal processing system so that its temperature characteristic is poor and that its operation is not stabilized.
- 03JECTS AND SUMMARY OF T~E INVENTION
Accordingly, it is an object of this invention to provide a write clock pulse generator the circuit scale of which is miniaturized and which is suitable for being formed into an IC (integrated circuit).
It is another object of this invention to provide 3~
a write clock pulse generator which is small in control error due to temperature fluctuation and hence which is stable in temperature characteristic.
It is a further object of this invention to provide a write cloc~ pulse generatox for use with a TBC (time base cor.rector) or the like which is provided in a reproducing system of a VTR (video tape recorder).
According ~o one aspect of this invention, there is . provided a write clock pulse generator for a time base correc-tor having a phase locked oscillator responsive to a horizontal synchronizing pulse derived from a reproduced video signal for generating a first cloc3c pulse having a ti.me axis change same as that of said horizontal synchronizing pulse, a frequency of said irst clock pulse being n times (~ is an integer) the frequency o~ said horizontal synchronizing pulse, a color burst signal separating circuit for separating a color burst signal from said rep.roduced video signal, and a generating cir-cuit responsive to said ~irst clock pulse and said separated color burst signal ~or generating write clock pulse, the phase and frequency of which are loc}ced to those of said separated color burst signal and said horizontal synchronizing pulse, respectively comprising:
a~ a pulse signal generator responsive to said color burst signal for generating a control pulse signal having a pulse width corresponding to a predetermined wave length of said color burst signal, said control pulse signal be-ing in phase with said color burst signal:
b) a start-stop oscillator responsive to a generation of sald control pulse signal for generating a second cloc]c pulse the phase of which is in phase with said control pulse slgnal;
c) first and second frequency dividers connected to said phase locked oscillator and said start-stop oscillator respectively and for frequency-dividing said irst and second clock pulses;
d~ a synchronous circuit responsive to a generation of said control pulse for synchronizing dividing operations of said first and second frequency dividers;
e) a com~arator for comparing pulse widths of output pulses of said first and second frequency dividers; and f) a control circuit responsive to an output signal of said comparator for controlling a ~requency of said start-stop oscillator.
These and other objects, features and advantages of the write clock pulse generator according to this invention will become apparent from the following detailed description o~ the prefer~ed embodiment taken in conjunction with the accompanying drawings, throughout which like reference numerals designate like elements and parts.
BRIEF DESCRIP~ION OF THE DRAWINGS
Fig. 1 is a block diagram showing an example of a prior art write clock pulse generator;
Fig. 2 is a block diagram showing an embodiment of a write clock pulse generator according to this invention;
Figs. 3A to 3G and Figs. 4A to 4C are respectively waveform diagrams useful for explaining the operation of the write clock pulse generator shown in Fig. 2; and Fig. 5 is a block diagram showing an example of a frequency comparator used in the present invention.
~ 5 --DESCRIPTION OF THE PREFERRED EMBODIMENT
_ Now, an embodiment of the write clock pulse genera-tor according to this invention will hereinafter be described with reference to Figs. 2 to 5 in detail.
Fig. 2 is a block diagram showing an embodiment of the write clock pulse generating circuit or generator accord ing to this invention. In Fig. 2, like parts corresponding to those of Fig. 1 are marked with the same references and will not be described in detail.
Referring to Fig. 2, the reproduced video signal Sv applied to the terminal 1 is supplied to the synchronous sepa-rating cixcuit 2 in which the horizontal synchronizing signal PH .is separated rom the reproduced video signal Sv. This horl-zontal synchronizing signal PH is supplied to the PLL circuit 3 which then forms the clock (first clock) with the frequency nfH
(n is an integer and H is the horizontal frequency) following the frequency 1uctuation of the horizontal synchronizing signal PH as mentioned before. The n is set similarly as described 0 above.
The reproduced video signal Sv is further fed to the color burst signal separating circult 4 which separates the color burst signal SB from ~he reproduced video signal Sv.
The first clock C~1 is supplied to a first counter ~5 (fr`equency di~ider) 11 which is provided in a frequency dif-ference detector ~s0 and thereby counted down to l/M. In this case, M is an integer and a condition of n>M is established.
In this embodiment, M is set to be 512. Accordingly, when this write clock pulsa generator is applied to`the time base corrector of the PAL system, the first counter 11 produces ~3~
a first pulse Pl (see Fig. 3A) the duty ratio of which is substantially about 50%.
The first counter 11 begins its count operation in synchronism with the color burst signal SB. To this end, a start-stop pulse PSs synchronized with the color burst signal SB as will be described later and the first clock Cgl are respectively supplied to a synchronous circuit 12 which extracts therefrom one pulse of the first clock CKl corresponding to one wave of the color burst signal SB, for example, one wave of four to six waves which precisely indicates the phase of the color burst signal. This one pulse is supplied to the first counter 11 as a start pulse Ps (not shown).
The color burst signal SB is supplied to a generat-ing circuit 15 for genera~ing the sta~t-stop pulse Pss or a ~ate type variable oscill~tor 14 and then the generating cir-cuit 15 produces the start-stop pulse PSs which is synchronized with the color burst signal SB. In this embodiment, as shown in Figs. 4A and 4B, the start-stop pulse PSs synchronized with the second wave of the color burst signal SB and for one wave length thereo is formed, by which the oscillation state of the variable oscillator 14 is controlled. The pulse width o~ the start-stop pulse PSs may be 1/2 wave length amount of the color burst signal SB and more preferably be selected in a range from one to several wave lengths amount thereof.
The center oscillation frequency (average frequency) of th~ variable oscillator 14 is selected to be nfH, in which example, at the timing of the falling down edge of the start-stop pulse PSs the oscillation of the variable oscillator 14 begins, while at the timing of the rising up edge thereof the oscillation thereof is stopped.
~ 7 --8~
Accordingly, as shown in Fig. 4C, the clock (the second clock) CKW derived from the variable oscillator 14 appears as an interrupting or intermittent oscillation clock the phase of which is synchronized with the color burst signal SB.
This second clock CKw is developed at the output terminal 6 and will be used as the write clock.
Since the reproduced video signal Sv is written only in its picture portion, even if such intermittent clock is used as the write clock CKW, there occurs no problem.
The second clock CKw is further fed to a second counter (f~equency divider) 16, in which the second clock CKW
is counted down to l/M to thereby form the second pulse P2.
The coùnt operation of the second counter 16 is carried out in synchronism with the burst signal SB. In this case, as shown l~ in Fig. 4, the operation timing of tha second counter 16 is adjusted such that its count operation is started by the color burst signal SB (the color burst signal SB at time point t2) u~der the condition that the second clock CKw obtained in syn-chronism with the falling down edge of the start-stop pulse PSs is supplied to the second counter 16.
As described above, if the second clock CKw with the average frequency nfH is counted down to l/M by the second counter 16, it is possible to obtain the second pulse P2 (see F'ig. 3B) of which the duty ratio is similar to that of the first pulse Pl from the second counter 16. In this case, the first and second pulses Pl and P2 are arranged to have a phase difference of Ta (see Fig. 3).
On the other hand, a pulse width T2 of the second pulse P2 is fluctuated by the oscillation frequency of the variable oscillator 14. When the average frequency of the ~235~
second clock CKw is nfH, the pulse width T2 O- the second pulse P2 is substantially equal to a pulse width Tl of the first pulse Pl. However, if the average frequency becomes lower than nfH, the pulse width T2 becomes larger than the pulse width Tl, or becomes as, for example, shown in Fig. 3E.
That is, the second pulse P2 is dependent on the oscillation requency of the varlable oscillator 14.
While the ~irst pulse Pl is also fluctuated in res-ponse to the jitter of the horizontal scanning ~requency, it is regarded as to be constant for convenience sake of explana-tion.
The first and second pulses Pl and P2 are both sup-plied ~o a pulse width comparator 20. As described above, relative to the first pulse Pl, the second pulse P2 is depend-ent on the oscillation frequen~y o the variable oscillator 14.
Thus, if the interval Ta between the rising up edge of the first and second pulses Pl and P2 is kept constant for conven-ience sake of explanation, the interval Tb (see Fig. 3) between the falling down edges of the first and second pulses Pl and P2 appears as the fluctuation of the variable oscillation frequen-cy. In addition, when the frequency of the second clock CKW is equal to that o the first clock CKl, the pulse widths Tl and T2 becomes equal to each other so that at this time, Tb = Ta should be established.
Accordingly, if the pulse intervals Ta and Tb are detected and in order to achieve the condition of Tb-=-Ta, the oscillation frequency of the variable oscillator 14 is control-led by a control voltage VCTL based on the output PCTL from the pulse width comparator 20, the second clock C~T~ is produced as the write clock with the frequency nfH that is locked to the phase of the burst signal SB.
In this embodiment, in order to achieve the above-described control operat'on, the pulse width comparator 20 is constructed in the following manner.
Fig. 5 is a block diagram showing an example of the pulse width comparator 20. Referrlng to Fig. 5, the first and second pulses Pl and P2 applied to input terminals 21 and 22 are supplied to a pulse interval detecting circuit 23, respec-tively. More specifically, if the second pulse P2 and the first pulse P1 passed through an inverter 24 are both fed to an AND circuit 25, from the AND circuit 25 there is obtained a control pulse Pa (Fig. 3C) with the pulse interval Ta.
If on the other hand the first pulse P1 and the second pulse P2 passed through an inverter 27 are both supplied to an AND
circuit 28, from the AND circuit 28 there is obtained a control pulse Pb (Fig. 3D) with the pulse interval Tb.
A charge pump 40 is controlled by the control pulses Pa and Pb-As is known, the charge pump 40 is formed o a pair of current sources 41 and 42 connected in series between two voltage source +B and -B, and a charging and discharging capac-itor Cp connected between a connection point q of ~he current sources 41, 42 and the ground. Between the connection point q and tha respective current sources 41 and 42, there are con-nected switching elements 44 and 45, respectively. The switch-ing element 44 is controlled to turn on and off by the control pulse Pb, while the other switching element 45 is controlled to turn on and off by the control pulse Pa.
Accordlngly, when the frequency of the second clock CKW is equal to that of the first clock CK1, Ta = Tb is ~3~
established as shown in Figs. 3C and 3D so that the charging and discharging amounts to the capacitor Cp become equal to each other. Accordingly, the terminal voltage across the capacitor Cp at this time is delivered through a buffer ampli-fier 47 to an output terminal 48. Then, its detected voltage PCTL is filtered out bya low-pass filter 17 to become a control voltage VcT~. In this case, the frequency of the variable oscillator 14 is not varied by the control voltage VCTL.
On the other hand, if the frequency of the second clock CKw becomes lowex than, for e~ample, nfH, the pulse inter-val Tb of the control pulse Pb becomes wider than ~he pulse interval Ta Of the control pulse Pa so that the charged amount in the capacitor Cp is increased. In accordance therewith, the control voltage VCTL i5 increased and the reverse bias of the varactor diode (not shown) provided in the variable oscil-- lator 14 becomes deep so that the capacity thereof is decreased and thence the oscillation frequency of the variable oscillator 14 is made high. When the oscillation frequency there.of becomes equal to the frequency of the firstclcc~ CK~, Ta = Tb is estab-lished.
If the oscillation frequency of the variable oscil-lator 14 is higher than nfH, the reverse control operation to the above will be carried out.
B~ the way, since the frequency of the first clock CKl is varied in response to the jitter in the reproduced video signal Sv, the pulse width Tl of the first pulse Pl is v~ried in response to this frequency fluctuationO Further, since the variable oscillator 14 is controlled so as to establish Ta ~ Tb, if the frequency of the first clock CKl is fluctuated, in response to such fluctuation, the variable oscillator 14 is ~. .
~5~
controlled such that the frequency of the second clock CKW
coincides with the frequency of the first clock C~l.
Accordingly, at the output terminal 6, there is pro-duced the write clock CKw having the frequency nfH following S the jitter in the reproduced video signal Sv and the phase of which is synchronized with the phase of the color burst signal SB Of the reproduced video signal Sv.
Whlle even though the switching elements 44 and 45 provided in the charge pump 40 are controlled by the first and second pulses Pl and P2 themselves, the predetermined write clock CKW may be produced. However, if the control pulses Pa and Pb are used as mentioned above rather than the first and second pulses Pl and P2, it is possible to obtain the write clock CKW with the frequency following the first clock frequen-lS cy more precisely.
In other words, although current values Il and I2 of the pair of current sources 41 and 42 used in the charge pump 40 should be equal to each other (Il = I2) inherently, in prac-tice, Il and I2 become Il . I2 due to the scattering of the cir-cuit elements. Therefore, if the control pulses Pa and Pb based on the pulses Pl and P2 are used rather than the pulses Pl and P2 themselves, the operation periods o the current sources 41 and 42 can be reduced so that it becomes possible to reduce the influence by the scattering of the current values much more.
If the influence by the scattering of the current values can be reduced much more, the control accuracy for the variable osclllator 14 is increased by that much. Accordingly, it becomes possible to reduce the error of the write clock frequency relative to the first clock frequency to be small.
For this reason, it ls preferable to control the charge pump 40 by the control pulses Pa and Pb.
As set forth above, according to this invention, in order to detect the pulse width difference between the ~irst clock CKl following the jitter in the reproduced video signal SV and the second clock CKw synchronized with the phase of the color burst signal SB o~ the reproduced video signal Sv~ first and second pulses Pl and P2 having M clock pulse widths are generated and then the frequency of the second clock CKW is controlled based on the detected pulse width difference.
In consequence, according to the circuit arrangement of this invention, the circuit arrangement of the APC system is simplified so that the circuit scale can be miniatuarized considerably. Also, since this APC system includes many cir-cuit elements which process the signals in a digital fashion, .it is easily ~ormed into the IC.
lS Since the variable oscillator 14 can be controlled by the control voltage VcT~ which is obtained on the basis o~
the digital processing, the control error due to the tempera-ture varia~ion is reduced and the stability thereof for tem-perature is increased so that it is possible to form the write clock CXw accurately ~ollowing the input jitter.
Further, when the write clock pulse generator is formed into IC, this write clock pulse generator can be formed as a non-adjusting circuit, and so on.
There~ore, this inventlon is very suitable for the application of the TBC or the likes provided in the reproduc-ing system of the VTR.
The above description is given on a single preferred embodiment of the invention, but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spixits or scope of . - 13 -"~
~35~
the novel concepts of the invention, so that the scope of the inv~ntion should be determined by the appended claims only~
Field of the invention This invention relates generally to a clock generator and more particularly to a write clock generator used for a time base corrector (TBC) which is provided in the reproducing system of a video tape recorder (VTR).
Description of the Prior Art -Generally, a time base corrector is proYided in the reproducing system of a professional VTR and so on in order to remove a jitter in a reproduced video signal or the like.
This time base corrector requires to provide with a write clock generator for generating a write clock pulse which is capable of ~5 accurately following the jitter o~ ~he reproduced ~ideo signal and which is in phase wi~h a color burst signal.
Fig. 1 is a block di.agram showing an example of such prior art write clock pulse generator 10 for use with the time base corrector which is disclosecl more in detail in, for exam-ple, USP. 4, 165, 524 (by the same assingee).
Referring to ~'ig. 1, a reproduced video signal Sv applied to a terminal 1 is supplied to a synchronous separat~
ing circuit 2 in which a horizontal synchronizing signal PH is separated from the reproduced video signal Sv. This horizon-tal synchronizing signal P~ is supplied to a PLL (phase locked loop) circuit 3 which formes a clock CXl of the frequency nfH
(n is an integer and fH is a horizontal frequency) following the frequency fluctuation of the horizontal synchronizing signal PH. In this example, n is selected to be 910 for the NTSC system and 1135 for the PAL system, respectively.
~2358~3~
The reproduced video signal Sv is further supplied to a color burst separating circuit 4 in which a color burst signal Sg is separated from the reproduced video signal Sv.
This color burst signal SB is supplied to an APC (automatic phase control) circuit 5 which synchronizes the phase of the clock CKl supplied thereto. Thus, at a~ output terminal 6 led out from the APC circuit 5, there is developed a write clock CKw synchronized in phase with the color burst signal SB
and the frequency of which is same as that of the clock CRl.
Though not shown, the write clock CKW is used as a sampling clock for analog-to-digital converting the reproduced video signal Sv and also as a write clock for a digital memory.
By the way, when the clock generating circuit 10 is arranged as described above, the APC circuit 5 for phase-syn-chro~ization generally includes a vast number of circuit ele-ments and in which an analog signal processing system and a digital signaL processing system exist therein in a mixed state so that this clock generating circuit 10 is not suitable for being formed as an IC (integrated circuit). Further, this prior art clock generating circuit lO has the analog slgnal processing system so that its temperature characteristic is poor and that its operation is not stabilized.
- 03JECTS AND SUMMARY OF T~E INVENTION
Accordingly, it is an object of this invention to provide a write clock pulse generator the circuit scale of which is miniaturized and which is suitable for being formed into an IC (integrated circuit).
It is another object of this invention to provide 3~
a write clock pulse generator which is small in control error due to temperature fluctuation and hence which is stable in temperature characteristic.
It is a further object of this invention to provide a write cloc~ pulse generatox for use with a TBC (time base cor.rector) or the like which is provided in a reproducing system of a VTR (video tape recorder).
According ~o one aspect of this invention, there is . provided a write clock pulse generator for a time base correc-tor having a phase locked oscillator responsive to a horizontal synchronizing pulse derived from a reproduced video signal for generating a first cloc3c pulse having a ti.me axis change same as that of said horizontal synchronizing pulse, a frequency of said irst clock pulse being n times (~ is an integer) the frequency o~ said horizontal synchronizing pulse, a color burst signal separating circuit for separating a color burst signal from said rep.roduced video signal, and a generating cir-cuit responsive to said ~irst clock pulse and said separated color burst signal ~or generating write clock pulse, the phase and frequency of which are loc}ced to those of said separated color burst signal and said horizontal synchronizing pulse, respectively comprising:
a~ a pulse signal generator responsive to said color burst signal for generating a control pulse signal having a pulse width corresponding to a predetermined wave length of said color burst signal, said control pulse signal be-ing in phase with said color burst signal:
b) a start-stop oscillator responsive to a generation of sald control pulse signal for generating a second cloc]c pulse the phase of which is in phase with said control pulse slgnal;
c) first and second frequency dividers connected to said phase locked oscillator and said start-stop oscillator respectively and for frequency-dividing said irst and second clock pulses;
d~ a synchronous circuit responsive to a generation of said control pulse for synchronizing dividing operations of said first and second frequency dividers;
e) a com~arator for comparing pulse widths of output pulses of said first and second frequency dividers; and f) a control circuit responsive to an output signal of said comparator for controlling a ~requency of said start-stop oscillator.
These and other objects, features and advantages of the write clock pulse generator according to this invention will become apparent from the following detailed description o~ the prefer~ed embodiment taken in conjunction with the accompanying drawings, throughout which like reference numerals designate like elements and parts.
BRIEF DESCRIP~ION OF THE DRAWINGS
Fig. 1 is a block diagram showing an example of a prior art write clock pulse generator;
Fig. 2 is a block diagram showing an embodiment of a write clock pulse generator according to this invention;
Figs. 3A to 3G and Figs. 4A to 4C are respectively waveform diagrams useful for explaining the operation of the write clock pulse generator shown in Fig. 2; and Fig. 5 is a block diagram showing an example of a frequency comparator used in the present invention.
~ 5 --DESCRIPTION OF THE PREFERRED EMBODIMENT
_ Now, an embodiment of the write clock pulse genera-tor according to this invention will hereinafter be described with reference to Figs. 2 to 5 in detail.
Fig. 2 is a block diagram showing an embodiment of the write clock pulse generating circuit or generator accord ing to this invention. In Fig. 2, like parts corresponding to those of Fig. 1 are marked with the same references and will not be described in detail.
Referring to Fig. 2, the reproduced video signal Sv applied to the terminal 1 is supplied to the synchronous sepa-rating cixcuit 2 in which the horizontal synchronizing signal PH .is separated rom the reproduced video signal Sv. This horl-zontal synchronizing signal PH is supplied to the PLL circuit 3 which then forms the clock (first clock) with the frequency nfH
(n is an integer and H is the horizontal frequency) following the frequency 1uctuation of the horizontal synchronizing signal PH as mentioned before. The n is set similarly as described 0 above.
The reproduced video signal Sv is further fed to the color burst signal separating circult 4 which separates the color burst signal SB from ~he reproduced video signal Sv.
The first clock C~1 is supplied to a first counter ~5 (fr`equency di~ider) 11 which is provided in a frequency dif-ference detector ~s0 and thereby counted down to l/M. In this case, M is an integer and a condition of n>M is established.
In this embodiment, M is set to be 512. Accordingly, when this write clock pulsa generator is applied to`the time base corrector of the PAL system, the first counter 11 produces ~3~
a first pulse Pl (see Fig. 3A) the duty ratio of which is substantially about 50%.
The first counter 11 begins its count operation in synchronism with the color burst signal SB. To this end, a start-stop pulse PSs synchronized with the color burst signal SB as will be described later and the first clock Cgl are respectively supplied to a synchronous circuit 12 which extracts therefrom one pulse of the first clock CKl corresponding to one wave of the color burst signal SB, for example, one wave of four to six waves which precisely indicates the phase of the color burst signal. This one pulse is supplied to the first counter 11 as a start pulse Ps (not shown).
The color burst signal SB is supplied to a generat-ing circuit 15 for genera~ing the sta~t-stop pulse Pss or a ~ate type variable oscill~tor 14 and then the generating cir-cuit 15 produces the start-stop pulse PSs which is synchronized with the color burst signal SB. In this embodiment, as shown in Figs. 4A and 4B, the start-stop pulse PSs synchronized with the second wave of the color burst signal SB and for one wave length thereo is formed, by which the oscillation state of the variable oscillator 14 is controlled. The pulse width o~ the start-stop pulse PSs may be 1/2 wave length amount of the color burst signal SB and more preferably be selected in a range from one to several wave lengths amount thereof.
The center oscillation frequency (average frequency) of th~ variable oscillator 14 is selected to be nfH, in which example, at the timing of the falling down edge of the start-stop pulse PSs the oscillation of the variable oscillator 14 begins, while at the timing of the rising up edge thereof the oscillation thereof is stopped.
~ 7 --8~
Accordingly, as shown in Fig. 4C, the clock (the second clock) CKW derived from the variable oscillator 14 appears as an interrupting or intermittent oscillation clock the phase of which is synchronized with the color burst signal SB.
This second clock CKw is developed at the output terminal 6 and will be used as the write clock.
Since the reproduced video signal Sv is written only in its picture portion, even if such intermittent clock is used as the write clock CKW, there occurs no problem.
The second clock CKw is further fed to a second counter (f~equency divider) 16, in which the second clock CKW
is counted down to l/M to thereby form the second pulse P2.
The coùnt operation of the second counter 16 is carried out in synchronism with the burst signal SB. In this case, as shown l~ in Fig. 4, the operation timing of tha second counter 16 is adjusted such that its count operation is started by the color burst signal SB (the color burst signal SB at time point t2) u~der the condition that the second clock CKw obtained in syn-chronism with the falling down edge of the start-stop pulse PSs is supplied to the second counter 16.
As described above, if the second clock CKw with the average frequency nfH is counted down to l/M by the second counter 16, it is possible to obtain the second pulse P2 (see F'ig. 3B) of which the duty ratio is similar to that of the first pulse Pl from the second counter 16. In this case, the first and second pulses Pl and P2 are arranged to have a phase difference of Ta (see Fig. 3).
On the other hand, a pulse width T2 of the second pulse P2 is fluctuated by the oscillation frequency of the variable oscillator 14. When the average frequency of the ~235~
second clock CKw is nfH, the pulse width T2 O- the second pulse P2 is substantially equal to a pulse width Tl of the first pulse Pl. However, if the average frequency becomes lower than nfH, the pulse width T2 becomes larger than the pulse width Tl, or becomes as, for example, shown in Fig. 3E.
That is, the second pulse P2 is dependent on the oscillation requency of the varlable oscillator 14.
While the ~irst pulse Pl is also fluctuated in res-ponse to the jitter of the horizontal scanning ~requency, it is regarded as to be constant for convenience sake of explana-tion.
The first and second pulses Pl and P2 are both sup-plied ~o a pulse width comparator 20. As described above, relative to the first pulse Pl, the second pulse P2 is depend-ent on the oscillation frequen~y o the variable oscillator 14.
Thus, if the interval Ta between the rising up edge of the first and second pulses Pl and P2 is kept constant for conven-ience sake of explanation, the interval Tb (see Fig. 3) between the falling down edges of the first and second pulses Pl and P2 appears as the fluctuation of the variable oscillation frequen-cy. In addition, when the frequency of the second clock CKW is equal to that o the first clock CKl, the pulse widths Tl and T2 becomes equal to each other so that at this time, Tb = Ta should be established.
Accordingly, if the pulse intervals Ta and Tb are detected and in order to achieve the condition of Tb-=-Ta, the oscillation frequency of the variable oscillator 14 is control-led by a control voltage VCTL based on the output PCTL from the pulse width comparator 20, the second clock C~T~ is produced as the write clock with the frequency nfH that is locked to the phase of the burst signal SB.
In this embodiment, in order to achieve the above-described control operat'on, the pulse width comparator 20 is constructed in the following manner.
Fig. 5 is a block diagram showing an example of the pulse width comparator 20. Referrlng to Fig. 5, the first and second pulses Pl and P2 applied to input terminals 21 and 22 are supplied to a pulse interval detecting circuit 23, respec-tively. More specifically, if the second pulse P2 and the first pulse P1 passed through an inverter 24 are both fed to an AND circuit 25, from the AND circuit 25 there is obtained a control pulse Pa (Fig. 3C) with the pulse interval Ta.
If on the other hand the first pulse P1 and the second pulse P2 passed through an inverter 27 are both supplied to an AND
circuit 28, from the AND circuit 28 there is obtained a control pulse Pb (Fig. 3D) with the pulse interval Tb.
A charge pump 40 is controlled by the control pulses Pa and Pb-As is known, the charge pump 40 is formed o a pair of current sources 41 and 42 connected in series between two voltage source +B and -B, and a charging and discharging capac-itor Cp connected between a connection point q of ~he current sources 41, 42 and the ground. Between the connection point q and tha respective current sources 41 and 42, there are con-nected switching elements 44 and 45, respectively. The switch-ing element 44 is controlled to turn on and off by the control pulse Pb, while the other switching element 45 is controlled to turn on and off by the control pulse Pa.
Accordlngly, when the frequency of the second clock CKW is equal to that of the first clock CK1, Ta = Tb is ~3~
established as shown in Figs. 3C and 3D so that the charging and discharging amounts to the capacitor Cp become equal to each other. Accordingly, the terminal voltage across the capacitor Cp at this time is delivered through a buffer ampli-fier 47 to an output terminal 48. Then, its detected voltage PCTL is filtered out bya low-pass filter 17 to become a control voltage VcT~. In this case, the frequency of the variable oscillator 14 is not varied by the control voltage VCTL.
On the other hand, if the frequency of the second clock CKw becomes lowex than, for e~ample, nfH, the pulse inter-val Tb of the control pulse Pb becomes wider than ~he pulse interval Ta Of the control pulse Pa so that the charged amount in the capacitor Cp is increased. In accordance therewith, the control voltage VCTL i5 increased and the reverse bias of the varactor diode (not shown) provided in the variable oscil-- lator 14 becomes deep so that the capacity thereof is decreased and thence the oscillation frequency of the variable oscillator 14 is made high. When the oscillation frequency there.of becomes equal to the frequency of the firstclcc~ CK~, Ta = Tb is estab-lished.
If the oscillation frequency of the variable oscil-lator 14 is higher than nfH, the reverse control operation to the above will be carried out.
B~ the way, since the frequency of the first clock CKl is varied in response to the jitter in the reproduced video signal Sv, the pulse width Tl of the first pulse Pl is v~ried in response to this frequency fluctuationO Further, since the variable oscillator 14 is controlled so as to establish Ta ~ Tb, if the frequency of the first clock CKl is fluctuated, in response to such fluctuation, the variable oscillator 14 is ~. .
~5~
controlled such that the frequency of the second clock CKW
coincides with the frequency of the first clock C~l.
Accordingly, at the output terminal 6, there is pro-duced the write clock CKw having the frequency nfH following S the jitter in the reproduced video signal Sv and the phase of which is synchronized with the phase of the color burst signal SB Of the reproduced video signal Sv.
Whlle even though the switching elements 44 and 45 provided in the charge pump 40 are controlled by the first and second pulses Pl and P2 themselves, the predetermined write clock CKW may be produced. However, if the control pulses Pa and Pb are used as mentioned above rather than the first and second pulses Pl and P2, it is possible to obtain the write clock CKW with the frequency following the first clock frequen-lS cy more precisely.
In other words, although current values Il and I2 of the pair of current sources 41 and 42 used in the charge pump 40 should be equal to each other (Il = I2) inherently, in prac-tice, Il and I2 become Il . I2 due to the scattering of the cir-cuit elements. Therefore, if the control pulses Pa and Pb based on the pulses Pl and P2 are used rather than the pulses Pl and P2 themselves, the operation periods o the current sources 41 and 42 can be reduced so that it becomes possible to reduce the influence by the scattering of the current values much more.
If the influence by the scattering of the current values can be reduced much more, the control accuracy for the variable osclllator 14 is increased by that much. Accordingly, it becomes possible to reduce the error of the write clock frequency relative to the first clock frequency to be small.
For this reason, it ls preferable to control the charge pump 40 by the control pulses Pa and Pb.
As set forth above, according to this invention, in order to detect the pulse width difference between the ~irst clock CKl following the jitter in the reproduced video signal SV and the second clock CKw synchronized with the phase of the color burst signal SB o~ the reproduced video signal Sv~ first and second pulses Pl and P2 having M clock pulse widths are generated and then the frequency of the second clock CKW is controlled based on the detected pulse width difference.
In consequence, according to the circuit arrangement of this invention, the circuit arrangement of the APC system is simplified so that the circuit scale can be miniatuarized considerably. Also, since this APC system includes many cir-cuit elements which process the signals in a digital fashion, .it is easily ~ormed into the IC.
lS Since the variable oscillator 14 can be controlled by the control voltage VcT~ which is obtained on the basis o~
the digital processing, the control error due to the tempera-ture varia~ion is reduced and the stability thereof for tem-perature is increased so that it is possible to form the write clock CXw accurately ~ollowing the input jitter.
Further, when the write clock pulse generator is formed into IC, this write clock pulse generator can be formed as a non-adjusting circuit, and so on.
There~ore, this inventlon is very suitable for the application of the TBC or the likes provided in the reproduc-ing system of the VTR.
The above description is given on a single preferred embodiment of the invention, but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spixits or scope of . - 13 -"~
~35~
the novel concepts of the invention, so that the scope of the inv~ntion should be determined by the appended claims only~
Claims (4)
1. A write clock pulse generator for a time base corrector having a phase locked oscillator responsive to a horizontal synchronizing pulse derived from a reproduced video signal for generating a first clock pulse having a time axis change same as that of said horizontal synchronizing pulse, a frequency of said first clock pulse being n times (n is an integer) the frequency of said horizontal synchroniz-ing pulse, a burst signal separating circuit for separating a color burst signal from said reproduced video signal, and a generating circuit responsive to said first clock pulse and said separated color burst signal for generating a write clock pulse, the phase and frequency of which are locked to those of said separated color burst signal and said horizontal synchronizing pulse, respectively comprising:
a) a pulse signal generator responsive to said color burst signal for generating a control pulse signal having a pulse width corresponding to a predetermined wave length of said color burst signal, said control pulse signal being in phase with said color burst signal:
b) start-stop oscillator responsive to a generation of said control pulse signal for generating a second clock pulse the phase of which is in phase with said control pulse signal;
c) first and second frequency dividers connected to said phase locked oscillator and said start-stop oscil-lator and for frequency-dividing said first and second clock pulses;
d) a synchronous circuit responsive to a generation of said control pulse for synchronizing dividing operations of said first and second frequency dividers;
e) a comparator for comparing pulse widths of output pulses of said first and second frequency dividers;
and f) a control circuit responsive to an output signal of said comparator for controlling a frequency of said start stop oscillator.
a) a pulse signal generator responsive to said color burst signal for generating a control pulse signal having a pulse width corresponding to a predetermined wave length of said color burst signal, said control pulse signal being in phase with said color burst signal:
b) start-stop oscillator responsive to a generation of said control pulse signal for generating a second clock pulse the phase of which is in phase with said control pulse signal;
c) first and second frequency dividers connected to said phase locked oscillator and said start-stop oscil-lator and for frequency-dividing said first and second clock pulses;
d) a synchronous circuit responsive to a generation of said control pulse for synchronizing dividing operations of said first and second frequency dividers;
e) a comparator for comparing pulse widths of output pulses of said first and second frequency dividers;
and f) a control circuit responsive to an output signal of said comparator for controlling a frequency of said start stop oscillator.
2. The write clock pulse generator according to claim 1, in which a dividing ratio of said first frequency divider is equal to that of said second frequency divider.
3. The write clock pulse generator according to claim 2, in which said comparator is of a charge pump type comparator.
4. The write clock pulse generator according to claim 3, in which said charge pump type comparator includes a couple of inverters and AND gates, said output pulse of said first frequency divider is applied to one of said inverters and AND gates, said output pulse of said second frequency divider is applied to the other of said inverters and AND gates, output signals of said inverters are connected to said AND
gates, respectively and first and second current sources for charging and discharging a capacitor in response to output signals of said couple of AND gates.
gates, respectively and first and second current sources for charging and discharging a capacitor in response to output signals of said couple of AND gates.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP115642/84 | 1984-07-28 | ||
| JP1984115642U JPS6133575U (en) | 1984-07-28 | 1984-07-28 | clock formation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1235800A true CA1235800A (en) | 1988-04-26 |
Family
ID=14667691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000487218A Expired CA1235800A (en) | 1984-07-28 | 1985-07-22 | Write clock pulse generator used for a time base corrector |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4613827A (en) |
| EP (1) | EP0170207A3 (en) |
| JP (1) | JPS6133575U (en) |
| AU (1) | AU588239B2 (en) |
| CA (1) | CA1235800A (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60205867A (en) * | 1984-03-30 | 1985-10-17 | Pioneer Electronic Corp | Reproducing device |
| JPH0669230B2 (en) * | 1984-10-22 | 1994-08-31 | ソニー株式会社 | Signal generator for processing reproduced video signal |
| JPS61189094A (en) * | 1985-02-16 | 1986-08-22 | Sony Corp | Read start pulse generating circuit |
| US4757391A (en) * | 1985-02-28 | 1988-07-12 | Victor Company Of Japan, Ltd. | Helical scan type magnetic recording and reproducing apparatus recording multiple signals on multiple axially displaced tape tracks |
| JPS61219286A (en) * | 1985-03-25 | 1986-09-29 | Sony Corp | Write clock generating circuit for time base correcting device |
| JPH06101860B2 (en) * | 1986-04-11 | 1994-12-12 | ソニー株式会社 | Time axis correction device |
| JPH0787596B2 (en) * | 1986-06-20 | 1995-09-20 | 株式会社日立製作所 | Signal processing circuit |
| JPH0620293B2 (en) * | 1986-09-17 | 1994-03-16 | パイオニア株式会社 | Time axis error correction device |
| US4789895A (en) * | 1987-04-30 | 1988-12-06 | Gte Government Systems Corporation | System for synchronizing digital bit stream for telecommunication system |
| US4817150A (en) * | 1987-08-31 | 1989-03-28 | Rca Licensing Corporation | Oscillator frequency control arrangement for a stereo decoder |
| US4847678A (en) * | 1988-01-11 | 1989-07-11 | Eastman Kodak Company | Dual mode gen-lock system which automatically locks to color burst or to sync information |
| JP2635667B2 (en) * | 1988-03-31 | 1997-07-30 | 株式会社東芝 | Automatic frequency control circuit |
| US4905085A (en) * | 1988-09-29 | 1990-02-27 | E. I. Du Pont De Nemours And Company | Synchronous sampling system |
| JPH0722380B2 (en) * | 1988-10-27 | 1995-03-08 | 富士通株式会社 | Phase lock circuit for video signal |
| US5025310A (en) * | 1989-03-23 | 1991-06-18 | Hitachi, Ltd. | Clock pulse generator capable of being switched to process both standard and non-standard television signals |
| US4975767A (en) * | 1989-04-25 | 1990-12-04 | Magni Systems, Inc. | NTSC/PAL subcarrier based H-lock with color framing and detection |
| US5745314A (en) * | 1989-09-27 | 1998-04-28 | Canon Kabushiki Kaisha | Clock generating circuit by using the phase difference between a burst signal and the oscillation signal |
| US5231509A (en) * | 1989-11-27 | 1993-07-27 | Matsushita Electric Industrial Co., Ltd. | Burst gate pulse generating device for use in image signal reproducing system |
| JPH0440783A (en) * | 1990-06-07 | 1992-02-12 | Pioneer Electron Corp | Time axis correcting device |
| NL9002652A (en) * | 1990-12-03 | 1992-07-01 | Philips Nv | TELEVISION RECORDING AND / OR DISPLAY DEVICE AND A ROENTGEN EXAMINATION EQUIPMENT EQUIPPED WITH SUCH A DEVICE. |
| JP3260172B2 (en) * | 1992-09-04 | 2002-02-25 | 旭光学工業株式会社 | Video signal recording and playback device |
| KR970003810B1 (en) * | 1993-04-14 | 1997-03-22 | 삼성전자 주식회사 | Nonvolatile semiconductor integrated circuit having address transition detector circuit |
| JP3643385B2 (en) * | 1993-05-19 | 2005-04-27 | 株式会社東芝 | Semiconductor circuit device |
| US20050113045A1 (en) * | 2003-11-21 | 2005-05-26 | John Santhoff | Bridged ultra-wideband communication method and apparatus |
| US7046618B2 (en) * | 2003-11-25 | 2006-05-16 | Pulse-Link, Inc. | Bridged ultra-wideband communication method and apparatus |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147121A (en) * | 1975-06-12 | 1976-12-17 | Sony Corp | Clock pulse generator |
| JPS5838011B2 (en) * | 1976-07-05 | 1983-08-19 | ソニー株式会社 | oscillation circuit |
| US4120000A (en) * | 1976-07-08 | 1978-10-10 | Sony Corporation | Video time base corrector |
| JPS5444831A (en) * | 1977-09-13 | 1979-04-09 | Nec Corp | Correcting equipment for time-axis error |
| JPS54143017A (en) * | 1978-04-28 | 1979-11-07 | Sony Corp | Time base error correction unit |
| JPS5661873A (en) * | 1979-10-25 | 1981-05-27 | Sony Corp | Digital video signal processor |
| JPS5665309A (en) * | 1979-10-26 | 1981-06-03 | Sony Corp | Time-axis converter |
| DD205799A1 (en) * | 1982-05-17 | 1984-01-04 | Rudolf Irmler | CIRCUIT ARRANGEMENT FOR COMPENSATING FREQUENCY AND PHASE FLAKES |
-
1984
- 1984-07-28 JP JP1984115642U patent/JPS6133575U/en active Granted
-
1985
- 1985-07-18 AU AU45141/85A patent/AU588239B2/en not_active Ceased
- 1985-07-22 CA CA000487218A patent/CA1235800A/en not_active Expired
- 1985-07-24 US US06/758,341 patent/US4613827A/en not_active Expired - Fee Related
- 1985-07-25 EP EP85109317A patent/EP0170207A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6133575U (en) | 1986-02-28 |
| EP0170207A2 (en) | 1986-02-05 |
| AU588239B2 (en) | 1988-09-14 |
| JPH0419907Y2 (en) | 1992-05-07 |
| AU4514185A (en) | 1986-01-30 |
| EP0170207A3 (en) | 1988-06-01 |
| US4613827A (en) | 1986-09-23 |
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