CA1226340A - Bias circuit for multifunction bipolar integrated circuits - Google Patents
Bias circuit for multifunction bipolar integrated circuitsInfo
- Publication number
- CA1226340A CA1226340A CA000453376A CA453376A CA1226340A CA 1226340 A CA1226340 A CA 1226340A CA 000453376 A CA000453376 A CA 000453376A CA 453376 A CA453376 A CA 453376A CA 1226340 A CA1226340 A CA 1226340A
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- current
- bias
- currents
- current mirror
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
Abstract
ABSTRACT
The bias circuit generates fixed and programmable currents for various functions in an integrated circuit from a voltage determined by a band gap reference. Programmable currents are obtained by a single programming resistor for all the functions, which resistor generates a low programming current; after passing through a low current PNP mirror, the programming circuit is raised to the values required by the individual functions of the integ-rated circuit by two stage amplification by means of NPN
current mirror circuits.
The bias circuit generates fixed and programmable currents for various functions in an integrated circuit from a voltage determined by a band gap reference. Programmable currents are obtained by a single programming resistor for all the functions, which resistor generates a low programming current; after passing through a low current PNP mirror, the programming circuit is raised to the values required by the individual functions of the integ-rated circuit by two stage amplification by means of NPN
current mirror circuits.
Description
~2~3~1~
The present invention relates to bipolar integrated circuits, and more particularly it concerns a bias circuit for multifunction integrated circuits (i.e. circuits com-prising a plurality of identical units).
When implementing a bias circuit for a multifunction integrated circuit, it is desirable to obtain all the necessary currents and rererence voltages by a single cir-cuit common to all functions. In the most general case, reference voltages which are fixed and precise despite temperature and supply variations, and which are defined with reference to both the positive and the negative sup-ply, as well as both fixed and programmable currents, ought to be available. In addition, the single bias cir-cuit ought to be realized so as to avoid unwanted inter-action between the various functions provided by the cir-cuit itself.
Bias circuits for multifunction integrated circuits are known in the art, but these circuits do not meet the re-quirements for the most general case and present a number of disadvantages. For instance, the circuit described in the article "Fully Compensated Emitter - Coupled Logic:
Eliminating the Drawbacks of Conventional ECL", by H.H.
Muller, W.K. Owens and P.W.J. Verhofstadt, IEEE Journal of Solid State Circuits, Vol. SC-8, No. 5, October '73, does not supply programmable currents and relies upon the use of NPN transistors operating a high current. Bias circuits for ECL line drivers and receivers, such as the F 10 K series manufactured by Fairchild, do not allow the generation of programmable currents and since they do not have stable reference voltages, they do not provide good thermal performance. Programmability is provided for instance by the LH146 circuit manufactured by National Semiconductors; however stabilized voltages are not oh-tainable and the currents provided are affected by supply voltage variations.
3 ~Z6~
The bias circuit according to the invention can enable stabilized voltages and both flxed and programmable cur-rents to be provided with good decoupling characteristics and reduced power consumption.
According to the invention, a bias circuit for a multiple function integrated circuit comprises a band-gap reference circuit, connections for an external programming resistor passing a relatively small reference current determined by said reference circuit, and first and second current mirror amplifier circuits raising said small reference current to relatively larger values as required by the functions of said integrated circuit.
Further features of the invention will be apparent from the appended claims and from the following description with reference to the accompanying drawings, showing a preferred embodiment of the invention given by way of example and not in a limiting sense, in which:
Figure 1 is a block diagram showing the connection of a bias circuit into an integrated circuit; and Figure 2 is an electrical schematic diagram of the bias circuit.
The following description assumes that the integrated circuit in which the bias circuit P is incorporated com-prises four ECL full duplex transceivers for balanced lines, of the type described the present applicant in its European Patent Application No. 80.106.010.4 published under No. 26921), with a low dissipation driving stage of the type described in Canadian Patent Application No.
441,794, filed on November 24, lg83 in the name of the applicant. The driving circuit described in that Canadian patent application comprises an input stage consisting of a first and a second transistor and of a current generator, ~6;3~3 connected so as to form a first differential ampllfier/
and an output stage comprising a third and a fourth tran-sistor, connected in the emitter follower configuration, whose emitters are connectable to the two wires of the transmission line and whose bases are connected to the collectors ox the first and second transistors. The emit-ters of the third and fourth transistors are connectable to a common bias current generator through a switching circuit, which connects the common generator either to the third or the fourth transistor, depending on which of the transistors is sending a low logic level signal over the line. The common generator may be programmable.
In Figure 1 the Eour transceivers are denoted by references Fl, F2, F3, F~, and the inputs and outputs of the individu-al transceivers are designated INi, OUTi, Li, ~2, 3, 4~, whilst a terminal is provided for an external programming resistor.
Bias circuit P has to meet certain basic requirements:
a) biasing is to be separate for the four transceivers, so that the circuit can maintain good decoupling and avoid interference between the transceiver via their reference voltages and driving currents. This entails a compromise between circuit complexity (and hence chip area and dis-sipated power) and performance (i.e. interference between the different functions of the integrated circuit through the bias circuit); b) fixed and programmable currents are required The fixed currents are for the generators which permit operation of the input and outputECL gates of the transceivers and of the linear differential ampli-fiers subtracting the transmitted signal from the signalpresent:on lines Li, Li. As the logic levels of the cir-cuit are defined by the precision and thermal stability of the collector voltages of the transistors referred to above, the generator currents must depend on internal re-sistances so that voltage drops across the internal ~ti3~0 collector resistances are precise and thermally stable.These fixed currents must be obtained from a precise and stable reference voltage VR and moreover they must not depend on the supply. The programmable currents are required for supplying the active drivers and are obtained from the voltage VR through the external resistor Re; and c) a voltage Vbb is required as a reference with respect to which the ECL levels vary. This voltage must be refer-red to the positive voltage V+ and is obtained from the above reference voltage.
From the above it is evident that the voltages and the currents circuit P is to supply should be derived from a stable and precise reference voltage VR. To ensure this stability an precision, voltage VR is obtained in known manner from a so-called band gap reference (i.e. a refer-ence depending on the energy of the forbidden band which separates the conduction band from the balence band in the semiconductor from which the individual circuit ele-ments are obtained) through a "Widlar mirror" in a self-biasing configuration with a "starter" circuit (i.e. acircuit that will establish its operating point such as to cause a stable and non-null current flow. The band gap reference, which is well known in the art, is repre-sented by transistors Q5, Q6, Q7 and resistors R4, R5, R6, connected respectively to the collectors of Q5, Q6 and to the emitter of Q6. The self bias of the reference is obtained by means of a pair of current mirrors with different current ratios.
The first mirror is a base current compensated PNP mirror which has a current ratio of about 2.5 and is formed by transistors Q8, Q9, Q10 and resistors Rl, R2, connecting the emitters of Q9, Q10 to positive supply V+; the second mirror consists of transistors Q4, Q5 whose emitters are connected to supply I-, and has current ratio 1. This second mirror, with transistors Q6, Q7 and resistors R~, i3~
R5, R6, forms the Widlar mixror.
Diode connected transistors Ql, Q2, Q3, and resistor R3, connected on one side to the base and the collector Q3 and on the other side to V+, form the starter circuit which supplies the current necessary to start the band gap reference and which is automatically inhibited once the reference voltage has been set. The starter current is present at the emitter of Q3.
Diode connected transistor Qll shifts the reference vol-tage VR upward. The raised voltage is supplied to the bases of four identical transistors Ql2, Ql3, Ql4, Q15 supplying reference voltages VRl, VR2, VR3, VR4 current generators of circuits Fl ... F4 (in particular to the current generators of the differential amplifier which in said circuits extract the signal from the line, and to the current generator of the output amplifier).
The arrangement shown using emitter follower transistors permits efficient decoupling between the voltage refer-ences.
The reference voltage VR biases a pair of transistors Q16, Q17 which with transistor Ql8 and resistors R7, R8 (con-nected between the emitters of Q17 and Q16 and the nega-tive supply) and R9 (connected between the collector of Q16 and V+) form the generator of the voltage Vbb with reference to which the ECL signal voltages vary. The vol-tage ebb is extracted from the point common to the emitter of Ql8 and to the collector of Q17. This voltage depends, through VR, on the band gap reference and hence will be stable and precise.
3~ The reference voltage VR, level shifted by Qll, further biases a transistor Ql9 r whose emitter is connectable to one end of the external resistor Re permitting programming of the current on lines Li, Li (Figure l). The currents 3~L~
to be obtained on the lines can have magnitudes reaching some fifteen my, and four currents of such magnitude can-not conveniently be directly obtained because this would require four external resistors. A single external resis-tor is desirable, in order to have as a component countlow as possible outside the intergrated circuit. To ob-tain, using a single resistor Re, all of the desired cur-rents, which are to be obtained from the negative supply, the collector of Q19 is connected to a base current eom-pensated PNP current mirror for low current decoupling.This mirror consists of transistors Q20, Q21, Q22 and of resistors R10, Rll, chosen so that the mirror presents unit gain.
In fact the PNP transistors present maximum gain with an input current of the order of some hundred PA (i.e. with a current just of the order ox that imposed by Re and passing through Ql9). To raise the programming current to the required value, an amplification of about 100 is needed, which is effected in two subsequent steps. The first stage of amplification is effected by the floating NPN mirror consisting of transistors Q23, Q24, Q25 and of resistors R12, R13, which resis-tors have their one ends connected to the emitters of Q24, Q25 and their other ends in common. Taking into account that the collector of Q2~, as shown in Figure 2, is directly connected to the out-put of the PNP mirror of the collection of Q21 so that a current equal to that supplied by the mirror passes into R12, and assuming that the ratio between R13 and R12 is such that Q23 amplifies by 10 the current supplied by Q24, then a current will flow at the junction of R12 and R13 which is about 11 times that supplied by the PNP mirror.
This current is applied to the collector of a transistor Q]7 which, together with transistor Q28 end resistors R14, R15, connected between the emitters of Q26 and Q27 and supply V-, -forms the input element of an NPN multiple output mirror, whose outputs are connected to the four i3~
circuits to be biased and which effects further amplifica-tion. The output elements of this mirror are transistors Q28, Q~9, Q30, Q31 with their emitter resistors R16, R17, R18, Rl9. The ratios between the resistances of R16 to Rl9 and the resistance of R14 determine the level of the programmable currents Ipl, Ip2, Ip3, Ip4 which can there-fore be different.
The two stage amplification permits a considerable saving in the area required for implementation in integrated cir-cuit form and an overal reduction in current consumptioin the bias circuit, as well as causing transistors PNP
Q20 - Q22 to operate in their maximum gain region, as al-ready described.
The circuit is well suited to integration as it uses elements typical of integrated circuit technology, bipolar PNP transistors included; such transistors, being used in a static circuit, do not in any way limit the speed of the circuits to be biased. By a suitable choice of transis-tor geometries in the multiple output mirror, interference between the collectors of Q28 - Q31 is avoided thereby minimizing the effects of distributed base resistance and of junction capacitances.
The present invention relates to bipolar integrated circuits, and more particularly it concerns a bias circuit for multifunction integrated circuits (i.e. circuits com-prising a plurality of identical units).
When implementing a bias circuit for a multifunction integrated circuit, it is desirable to obtain all the necessary currents and rererence voltages by a single cir-cuit common to all functions. In the most general case, reference voltages which are fixed and precise despite temperature and supply variations, and which are defined with reference to both the positive and the negative sup-ply, as well as both fixed and programmable currents, ought to be available. In addition, the single bias cir-cuit ought to be realized so as to avoid unwanted inter-action between the various functions provided by the cir-cuit itself.
Bias circuits for multifunction integrated circuits are known in the art, but these circuits do not meet the re-quirements for the most general case and present a number of disadvantages. For instance, the circuit described in the article "Fully Compensated Emitter - Coupled Logic:
Eliminating the Drawbacks of Conventional ECL", by H.H.
Muller, W.K. Owens and P.W.J. Verhofstadt, IEEE Journal of Solid State Circuits, Vol. SC-8, No. 5, October '73, does not supply programmable currents and relies upon the use of NPN transistors operating a high current. Bias circuits for ECL line drivers and receivers, such as the F 10 K series manufactured by Fairchild, do not allow the generation of programmable currents and since they do not have stable reference voltages, they do not provide good thermal performance. Programmability is provided for instance by the LH146 circuit manufactured by National Semiconductors; however stabilized voltages are not oh-tainable and the currents provided are affected by supply voltage variations.
3 ~Z6~
The bias circuit according to the invention can enable stabilized voltages and both flxed and programmable cur-rents to be provided with good decoupling characteristics and reduced power consumption.
According to the invention, a bias circuit for a multiple function integrated circuit comprises a band-gap reference circuit, connections for an external programming resistor passing a relatively small reference current determined by said reference circuit, and first and second current mirror amplifier circuits raising said small reference current to relatively larger values as required by the functions of said integrated circuit.
Further features of the invention will be apparent from the appended claims and from the following description with reference to the accompanying drawings, showing a preferred embodiment of the invention given by way of example and not in a limiting sense, in which:
Figure 1 is a block diagram showing the connection of a bias circuit into an integrated circuit; and Figure 2 is an electrical schematic diagram of the bias circuit.
The following description assumes that the integrated circuit in which the bias circuit P is incorporated com-prises four ECL full duplex transceivers for balanced lines, of the type described the present applicant in its European Patent Application No. 80.106.010.4 published under No. 26921), with a low dissipation driving stage of the type described in Canadian Patent Application No.
441,794, filed on November 24, lg83 in the name of the applicant. The driving circuit described in that Canadian patent application comprises an input stage consisting of a first and a second transistor and of a current generator, ~6;3~3 connected so as to form a first differential ampllfier/
and an output stage comprising a third and a fourth tran-sistor, connected in the emitter follower configuration, whose emitters are connectable to the two wires of the transmission line and whose bases are connected to the collectors ox the first and second transistors. The emit-ters of the third and fourth transistors are connectable to a common bias current generator through a switching circuit, which connects the common generator either to the third or the fourth transistor, depending on which of the transistors is sending a low logic level signal over the line. The common generator may be programmable.
In Figure 1 the Eour transceivers are denoted by references Fl, F2, F3, F~, and the inputs and outputs of the individu-al transceivers are designated INi, OUTi, Li, ~2, 3, 4~, whilst a terminal is provided for an external programming resistor.
Bias circuit P has to meet certain basic requirements:
a) biasing is to be separate for the four transceivers, so that the circuit can maintain good decoupling and avoid interference between the transceiver via their reference voltages and driving currents. This entails a compromise between circuit complexity (and hence chip area and dis-sipated power) and performance (i.e. interference between the different functions of the integrated circuit through the bias circuit); b) fixed and programmable currents are required The fixed currents are for the generators which permit operation of the input and outputECL gates of the transceivers and of the linear differential ampli-fiers subtracting the transmitted signal from the signalpresent:on lines Li, Li. As the logic levels of the cir-cuit are defined by the precision and thermal stability of the collector voltages of the transistors referred to above, the generator currents must depend on internal re-sistances so that voltage drops across the internal ~ti3~0 collector resistances are precise and thermally stable.These fixed currents must be obtained from a precise and stable reference voltage VR and moreover they must not depend on the supply. The programmable currents are required for supplying the active drivers and are obtained from the voltage VR through the external resistor Re; and c) a voltage Vbb is required as a reference with respect to which the ECL levels vary. This voltage must be refer-red to the positive voltage V+ and is obtained from the above reference voltage.
From the above it is evident that the voltages and the currents circuit P is to supply should be derived from a stable and precise reference voltage VR. To ensure this stability an precision, voltage VR is obtained in known manner from a so-called band gap reference (i.e. a refer-ence depending on the energy of the forbidden band which separates the conduction band from the balence band in the semiconductor from which the individual circuit ele-ments are obtained) through a "Widlar mirror" in a self-biasing configuration with a "starter" circuit (i.e. acircuit that will establish its operating point such as to cause a stable and non-null current flow. The band gap reference, which is well known in the art, is repre-sented by transistors Q5, Q6, Q7 and resistors R4, R5, R6, connected respectively to the collectors of Q5, Q6 and to the emitter of Q6. The self bias of the reference is obtained by means of a pair of current mirrors with different current ratios.
The first mirror is a base current compensated PNP mirror which has a current ratio of about 2.5 and is formed by transistors Q8, Q9, Q10 and resistors Rl, R2, connecting the emitters of Q9, Q10 to positive supply V+; the second mirror consists of transistors Q4, Q5 whose emitters are connected to supply I-, and has current ratio 1. This second mirror, with transistors Q6, Q7 and resistors R~, i3~
R5, R6, forms the Widlar mixror.
Diode connected transistors Ql, Q2, Q3, and resistor R3, connected on one side to the base and the collector Q3 and on the other side to V+, form the starter circuit which supplies the current necessary to start the band gap reference and which is automatically inhibited once the reference voltage has been set. The starter current is present at the emitter of Q3.
Diode connected transistor Qll shifts the reference vol-tage VR upward. The raised voltage is supplied to the bases of four identical transistors Ql2, Ql3, Ql4, Q15 supplying reference voltages VRl, VR2, VR3, VR4 current generators of circuits Fl ... F4 (in particular to the current generators of the differential amplifier which in said circuits extract the signal from the line, and to the current generator of the output amplifier).
The arrangement shown using emitter follower transistors permits efficient decoupling between the voltage refer-ences.
The reference voltage VR biases a pair of transistors Q16, Q17 which with transistor Ql8 and resistors R7, R8 (con-nected between the emitters of Q17 and Q16 and the nega-tive supply) and R9 (connected between the collector of Q16 and V+) form the generator of the voltage Vbb with reference to which the ECL signal voltages vary. The vol-tage ebb is extracted from the point common to the emitter of Ql8 and to the collector of Q17. This voltage depends, through VR, on the band gap reference and hence will be stable and precise.
3~ The reference voltage VR, level shifted by Qll, further biases a transistor Ql9 r whose emitter is connectable to one end of the external resistor Re permitting programming of the current on lines Li, Li (Figure l). The currents 3~L~
to be obtained on the lines can have magnitudes reaching some fifteen my, and four currents of such magnitude can-not conveniently be directly obtained because this would require four external resistors. A single external resis-tor is desirable, in order to have as a component countlow as possible outside the intergrated circuit. To ob-tain, using a single resistor Re, all of the desired cur-rents, which are to be obtained from the negative supply, the collector of Q19 is connected to a base current eom-pensated PNP current mirror for low current decoupling.This mirror consists of transistors Q20, Q21, Q22 and of resistors R10, Rll, chosen so that the mirror presents unit gain.
In fact the PNP transistors present maximum gain with an input current of the order of some hundred PA (i.e. with a current just of the order ox that imposed by Re and passing through Ql9). To raise the programming current to the required value, an amplification of about 100 is needed, which is effected in two subsequent steps. The first stage of amplification is effected by the floating NPN mirror consisting of transistors Q23, Q24, Q25 and of resistors R12, R13, which resis-tors have their one ends connected to the emitters of Q24, Q25 and their other ends in common. Taking into account that the collector of Q2~, as shown in Figure 2, is directly connected to the out-put of the PNP mirror of the collection of Q21 so that a current equal to that supplied by the mirror passes into R12, and assuming that the ratio between R13 and R12 is such that Q23 amplifies by 10 the current supplied by Q24, then a current will flow at the junction of R12 and R13 which is about 11 times that supplied by the PNP mirror.
This current is applied to the collector of a transistor Q]7 which, together with transistor Q28 end resistors R14, R15, connected between the emitters of Q26 and Q27 and supply V-, -forms the input element of an NPN multiple output mirror, whose outputs are connected to the four i3~
circuits to be biased and which effects further amplifica-tion. The output elements of this mirror are transistors Q28, Q~9, Q30, Q31 with their emitter resistors R16, R17, R18, Rl9. The ratios between the resistances of R16 to Rl9 and the resistance of R14 determine the level of the programmable currents Ipl, Ip2, Ip3, Ip4 which can there-fore be different.
The two stage amplification permits a considerable saving in the area required for implementation in integrated cir-cuit form and an overal reduction in current consumptioin the bias circuit, as well as causing transistors PNP
Q20 - Q22 to operate in their maximum gain region, as al-ready described.
The circuit is well suited to integration as it uses elements typical of integrated circuit technology, bipolar PNP transistors included; such transistors, being used in a static circuit, do not in any way limit the speed of the circuits to be biased. By a suitable choice of transis-tor geometries in the multiple output mirror, interference between the collectors of Q28 - Q31 is avoided thereby minimizing the effects of distributed base resistance and of junction capacitances.
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A bias circuit for a multiple function integrated circuit comprising a band gap reference circuit, connec-tions for an external programming resistor passing a relatively small reference current determined by said reference circuit, and first and second current mirror amplifier circuits raising said small reference current to relatively larger values as required by the functions of said integrated circuit.
2. A bias circuit for a multifunction integrated circuit, adapted to generate fixed and programmable currents and voltages required by the functions of the integrated cir-cuit, comprising a common band gap reference which estab-lishes a voltage reference which forms the source of said fixed and programmable currents, means to raise said voltage reference to at least one predetermined level for driving bias circuits, a first bias circuit comprising emitter follower transistors providing sources for bias currents required by the various functions of the integ-rated circuits, means establishing connections to a pro-gramming resistor such that a programming current flows therein determined by said voltage raising means, a first floating NPN current mirror circuit with base current compensation amplifying said current in the programming resistor, and a second multiple output NPN current mirror circuit receiving the output of said first current mirror circuit and raising to the levels required to sink the bias currents required by the integrated circuit functions and sourced by the emitter follower transistors.
3. A bias circuit according to Claim 2, wherein the programming current before being applied to the first current mirror amplifier is processed by a base current compensated PNP current mirror circuit to provide low current decoupling.
4. A bias circuit according to Claim 2, wherein the second NPN current mirror amplifier is arranged to supply different currents at different outputs.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT67531-A/83 | 1983-05-12 | ||
| IT67531/83A IT1162859B (en) | 1983-05-12 | 1983-05-12 | POLARIZATION CIRCUIT FOR MULTIFUNCTION BIPOLAR INTEGRATED CIRCUITS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1226340A true CA1226340A (en) | 1987-09-01 |
Family
ID=11303193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000453376A Expired CA1226340A (en) | 1983-05-12 | 1984-05-02 | Bias circuit for multifunction bipolar integrated circuits |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4673830A (en) |
| EP (1) | EP0125646B1 (en) |
| JP (1) | JPS59225612A (en) |
| CA (1) | CA1226340A (en) |
| DE (2) | DE125646T1 (en) |
| IT (1) | IT1162859B (en) |
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| JPH0833780B2 (en) * | 1985-03-30 | 1996-03-29 | 松下電器産業株式会社 | Bipolar integrated circuit |
| EP0271595A1 (en) * | 1986-12-16 | 1988-06-22 | Deutsche ITT Industries GmbH | On-chip voltage stabiliser |
| GB2217937A (en) * | 1988-04-29 | 1989-11-01 | Philips Electronic Associated | Current divider circuit |
| US4866309A (en) * | 1988-07-18 | 1989-09-12 | Western Digital Corporation | Multiplexed bus architecture for configuration sensing |
| SE502429C2 (en) * | 1994-02-21 | 1995-10-16 | Ellemtel Utvecklings Ab | Signal receiving and signal processing circuit |
| JP2790062B2 (en) * | 1994-11-22 | 1998-08-27 | 日本電気株式会社 | Wireless communication device |
| US6016050A (en) * | 1998-07-07 | 2000-01-18 | Analog Devices, Inc. | Start-up and bias circuit |
| DE10021928A1 (en) * | 2000-05-05 | 2001-11-15 | Infineon Technologies Ag | Current mirror has voltage-controlled current sources providing auxiliary current and additional auxiliary current summed to produce error current drawn from differential output signal |
| US6590441B2 (en) * | 2001-06-01 | 2003-07-08 | Qualcomm Incorporated | System and method for tuning a VLSI circuit |
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-
1983
- 1983-05-12 IT IT67531/83A patent/IT1162859B/en active
-
1984
- 1984-05-02 CA CA000453376A patent/CA1226340A/en not_active Expired
- 1984-05-02 JP JP59087985A patent/JPS59225612A/en active Pending
- 1984-05-10 DE DE198484105324T patent/DE125646T1/en active Pending
- 1984-05-10 DE DE8484105324T patent/DE3467434D1/en not_active Expired
- 1984-05-10 EP EP84105324A patent/EP0125646B1/en not_active Expired
- 1984-05-11 US US06/609,189 patent/US4673830A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0125646B1 (en) | 1987-11-11 |
| JPS59225612A (en) | 1984-12-18 |
| EP0125646A1 (en) | 1984-11-21 |
| DE125646T1 (en) | 1985-05-09 |
| DE3467434D1 (en) | 1987-12-17 |
| IT8367531A0 (en) | 1983-05-12 |
| US4673830A (en) | 1987-06-16 |
| IT1162859B (en) | 1987-04-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |