CA1191960A - Digital matrixing system - Google Patents
Digital matrixing systemInfo
- Publication number
- CA1191960A CA1191960A CA000438173A CA438173A CA1191960A CA 1191960 A CA1191960 A CA 1191960A CA 000438173 A CA000438173 A CA 000438173A CA 438173 A CA438173 A CA 438173A CA 1191960 A CA1191960 A CA 1191960A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- signals
- multiplying
- fraction
- summing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/67—Circuits for processing colour signals for matrixing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/035—Reduction of table size
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
Abstract
ABSTRACT
A digital multiplying apparatus is presented which digitally multiplies a digital signal by a coefficient. The apparatus comprises means for providing a plurality of fraction signals of the digital signal.
The fractions are powers of one-half times the digital signal. Means are provided for multiplying the smallest of these fractions by a factor to obtain a remainder signal representing the value left after expressing the coefficient as a sum of powers of one-half. Finally, means for combining the plurality of fraction signals and the remainder signal are provided.
A digital multiplying apparatus is presented which digitally multiplies a digital signal by a coefficient. The apparatus comprises means for providing a plurality of fraction signals of the digital signal.
The fractions are powers of one-half times the digital signal. Means are provided for multiplying the smallest of these fractions by a factor to obtain a remainder signal representing the value left after expressing the coefficient as a sum of powers of one-half. Finally, means for combining the plurality of fraction signals and the remainder signal are provided.
Description
1- RCA 78,617 DIGITAL MULTIPLYING APPA~ATUS
The present invention rela-tes to apparatus for multiplying a digital signal by a coefficient, and more particularly to such mul-tiplyinq as it occurs in a matrix for video signals.
In television studio equipment it is fxequently desired to generate luminance (Y) and chrominance (I & Q) signals from red ~R), green ~G) and blue (B) signals in accordance with the following matrix equation:
r~- ! ~0.3 0.59 0.1~. R-¦I = 0.6 -0.28 - 0.32 G
lQ 0.21 -0.52 0.31 B
Typical prior approaches use either read only memories (ROM) to perform the multiplication, or shifters and adders to perform the multiplication.
For the approach using ROMs to perform the multiplication, each of the three cham~els to generate the respective Y, I, and Q signals to the required accuracy would comprise 3 ROMs, 2 adders, and 6 latches, for a total of about 33 integrated circuits (IC) for all 3 channels. This number of ICs is relatively expensive and consumes a large amount of power. The approach using shifters and adders to perform the multiplication also requires a large number of ICs to achieve the desired accuracy.
It is therefore desirable to provide a digital multiplier, such as a matrix, that requires a minimum number of components and power.
In accordance wi-th the principles of the present invention, apparatus for digitally multiplying a digital signal by a coefficient, comprises means for providing a plu:rality of fraction signals of the digital signal. The fraction signals are powers o one-half times the digital signal. The apparatus also comprises means for multiplying the smallest of these fraction signals by a factor -to obtain a remainder signal representing the value left
The present invention rela-tes to apparatus for multiplying a digital signal by a coefficient, and more particularly to such mul-tiplyinq as it occurs in a matrix for video signals.
In television studio equipment it is fxequently desired to generate luminance (Y) and chrominance (I & Q) signals from red ~R), green ~G) and blue (B) signals in accordance with the following matrix equation:
r~- ! ~0.3 0.59 0.1~. R-¦I = 0.6 -0.28 - 0.32 G
lQ 0.21 -0.52 0.31 B
Typical prior approaches use either read only memories (ROM) to perform the multiplication, or shifters and adders to perform the multiplication.
For the approach using ROMs to perform the multiplication, each of the three cham~els to generate the respective Y, I, and Q signals to the required accuracy would comprise 3 ROMs, 2 adders, and 6 latches, for a total of about 33 integrated circuits (IC) for all 3 channels. This number of ICs is relatively expensive and consumes a large amount of power. The approach using shifters and adders to perform the multiplication also requires a large number of ICs to achieve the desired accuracy.
It is therefore desirable to provide a digital multiplier, such as a matrix, that requires a minimum number of components and power.
In accordance wi-th the principles of the present invention, apparatus for digitally multiplying a digital signal by a coefficient, comprises means for providing a plu:rality of fraction signals of the digital signal. The fraction signals are powers o one-half times the digital signal. The apparatus also comprises means for multiplying the smallest of these fraction signals by a factor -to obtain a remainder signal representing the value left
-2- RCA 78,617 after expressing -the coefficient as a sum of powers of one-half. E~inally, such apparatus comprises means for combining the plurality of fraction signals and the remainder signal.
In the drawings:
FIGURE 1 illus-tra-tes in block diagram form a simplified system according to t:he principles of the invention' and FIGURE 2 illustrates in block diagram form a system for matrixing television signals using multipliers as illustrated in FIGURE 1.
FIGU~E 1 illustrates a simple system for performing the operation A = 0.73B. The e~uation can be rewritten as A = (0.75 - 0.02)B. The term 0.75 can in turn be expressed as a sum of powers of one-half, i.e., 0.5, 0.25, 0.125,...etc., and thus, 0.75 = 0.5 + 0.25.
Thus A = (0.5 + 0.25 - 0.02)B.
In FIGURE 1 the digital signal B, which will be assumed to be 8 bits wide (256 quantized levels), is received at 8-bit input terminal 10 and applied to provider 12. Provider 12 provides fractional signals in powers of one-half. Each bit in a binary number represents a respective power of 2. To divide by 2 (multiply by one-half) the binary number is shifted one place to the right. Since signal B is a binary signal, the fractional signals can be provided by simply shifting all bits to the right an appropriate number of places and discarding the appropriate number of least significant bits (LSB). In the example, in order to-obtain the seven-bit wide 0.5B signal, the 7 most significant bits (MSB) of the B signal are provided at the 7 LSB outputs, respectively, of output 13, the LSB of the B signal having been discarded. The resulting 0.5B signal is applied to -the 7 LSB inputs of 8-bit input 14 of adder 16 the most significant bit having been set -to '0'. Similarly, at output 18 of provider 12, the 6 MSBs of the B signal are provided a-t the 6 LSB posi-tions of output 18 to provide
In the drawings:
FIGURE 1 illus-tra-tes in block diagram form a simplified system according to t:he principles of the invention' and FIGURE 2 illustrates in block diagram form a system for matrixing television signals using multipliers as illustrated in FIGURE 1.
FIGU~E 1 illustrates a simple system for performing the operation A = 0.73B. The e~uation can be rewritten as A = (0.75 - 0.02)B. The term 0.75 can in turn be expressed as a sum of powers of one-half, i.e., 0.5, 0.25, 0.125,...etc., and thus, 0.75 = 0.5 + 0.25.
Thus A = (0.5 + 0.25 - 0.02)B.
In FIGURE 1 the digital signal B, which will be assumed to be 8 bits wide (256 quantized levels), is received at 8-bit input terminal 10 and applied to provider 12. Provider 12 provides fractional signals in powers of one-half. Each bit in a binary number represents a respective power of 2. To divide by 2 (multiply by one-half) the binary number is shifted one place to the right. Since signal B is a binary signal, the fractional signals can be provided by simply shifting all bits to the right an appropriate number of places and discarding the appropriate number of least significant bits (LSB). In the example, in order to-obtain the seven-bit wide 0.5B signal, the 7 most significant bits (MSB) of the B signal are provided at the 7 LSB outputs, respectively, of output 13, the LSB of the B signal having been discarded. The resulting 0.5B signal is applied to -the 7 LSB inputs of 8-bit input 14 of adder 16 the most significant bit having been set -to '0'. Similarly, at output 18 of provider 12, the 6 MSBs of the B signal are provided a-t the 6 LSB posi-tions of output 18 to provide
-3~ RCA 7~,617 the 0.25B signal to -the 6 LSB inputs o~ 8-bi-t input 20 of adder 16, the 2 LS~ of the B signal, having been discarded and -the two most significan-t inpu-t bits of adder 16 having been set to l0l. Finally, at output 22 of the provider 12, the 2 MSB Gf the B signal provide a 0.015625B signal to the address inpu-ts at ROM 24, the 6 LSBs havi~g been discarded. It will therefore be apprecia~ed that provider 12 cornprises a simple wiring matrix that maps the bi-ts of -the input -to the a~propriate level of significance at each of the bits of the outputs.
In ROM 24 the 0.015625B signal is multiplied by the factor -1.28 to produce a -0.2B signal that is applied to input 26 o adder 16. In ROM 24 the input addresses 00, 01, 10, and 11 respectively provide ou-tput states 000, 001, 011, and 100 corresponding -to -1.28 times the value of the address inputs. These output states are rounded off from fractional values, which for 8-bit digital signals introduces negligible error. The 0.5B, 0.25B, and -0.2B signals are added toge-ther in adder 16 to produce at 8-bit output 28 a 0.73B signal, which is the desired result for signal A.
Alterna-tively, -the 3 MSBs of signal B, representing a 0.03125B signal, could be applied to ROM
24, and multiplied by -0.64 by ROM 24 to produce the required -0.0~B signal for adder 16. In this case, in ROM
24 the input addresses 000, 001, 010, 011, 100, 101, 110, and 111 respectively provide ou-tput states 000, 001, 001, 010, 011, 011, 100, and 100 again with rounding off corresponding to -0.64 times the value of the address inputs. In either case, only a small fraction of the original B signal must be multiplied, thereby reducing the amount of memory required in ROM 24.
FIGURE 2 shows an embodiment ~Ising the principles of the invention to matrix red (R), green (G), and blue (B) television signals into luminance (Y), and two chrominance component (I and Q) signals. For simplicity, the matrix given above is divided by the value
In ROM 24 the 0.015625B signal is multiplied by the factor -1.28 to produce a -0.2B signal that is applied to input 26 o adder 16. In ROM 24 the input addresses 00, 01, 10, and 11 respectively provide ou-tput states 000, 001, 011, and 100 corresponding -to -1.28 times the value of the address inputs. These output states are rounded off from fractional values, which for 8-bit digital signals introduces negligible error. The 0.5B, 0.25B, and -0.2B signals are added toge-ther in adder 16 to produce at 8-bit output 28 a 0.73B signal, which is the desired result for signal A.
Alterna-tively, -the 3 MSBs of signal B, representing a 0.03125B signal, could be applied to ROM
24, and multiplied by -0.64 by ROM 24 to produce the required -0.0~B signal for adder 16. In this case, in ROM
24 the input addresses 000, 001, 010, 011, 100, 101, 110, and 111 respectively provide ou-tput states 000, 001, 001, 010, 011, 011, 100, and 100 again with rounding off corresponding to -0.64 times the value of the address inputs. In either case, only a small fraction of the original B signal must be multiplied, thereby reducing the amount of memory required in ROM 24.
FIGURE 2 shows an embodiment ~Ising the principles of the invention to matrix red (R), green (G), and blue (B) television signals into luminance (Y), and two chrominance component (I and Q) signals. For simplicity, the matrix given above is divided by the value
-4~ RCA 78,617 oE the largest coefficient contained therein (0.6), i.e.
it is "normalized". The resulting matrix e~uation is:
0.5 0.98 0.18 R
I _ 1.0 -0.4~ -0.53 G
.Q~ 0.3S -0.87 0.52 B
Eight-bit P~, G, and B signals are received at 8-bit inputs 30, 32, and 34 respectively. The input R
signal is applied to provider 36 and to subtractor 38.
The output of provider 36 supplies a 7~bit 0.5R signal to adder 40, and to ROM 42. The input G signal is applied to adder 40, subtractor 44, and to provider 46. Provider 46 supplies a 3-bit 0.03125G signal (shown as an 0.03G
signal) to ROMs 48, 50, and 42, and a 7-bit 0.5G signal to subtractor 38. The input B signal is applied to provider 52. Provider 52 supplies a 4-bit 0.0625B signal (shown as an 0.05B signal) to ROM 48, and a 7-bit 0.5B signal to ROM
50 and to subtractor 44.
Considering now the Y output channel, adder 40 provides an 8-bit lG + 0.5R signal -to adder 54. ROM 48 processes the inpu-t 0.03G signal to provide a -0.02G first output signal and also processes the 0.06B input signal to provide a 0.18B second output signal which is added in ROM
48 to the first output signal. The resulting 8-bit 0.18B-0.02G output signal from ROM 48 is applied to adder 54. The output signal from adder 54 is thus an 8-bit 0.5R
+ 0.98G + 0.18B signal which is available at 8~bi-t output 56. This is the Y signal.
In the I channel, subtractor 38 provides an 8-bit lR - 0.05G signal to adder 58. ROM 50 processes the 0.03G input signal to provide an -0.03G signa], and processes the 0.5B input signal to provide a -0.53B
signal. The resul-ting 8-bit -0.03G -0.53B output signal from ROM 50 is applied to adder 58. The output signal from adder 58 is an 8-bit lR -0.47G -0.53B signal, and is present at 8-bit O-ltpUt 60. This is the I signal.
In the O~ channel, ROM 42 processes the 0.5R
input signal to provide a 0.35R output signal, and also Li~''3~iO
~5- RCA 78,617 process -the 0.03G input signal to provide a 0.13G OlltpUt signal. The resulting 8-bit 0.35R + 0.13G output signal from ROM 42 is applied to adder 62. Subtractor 44 provides a -lG + 0.5B output signal to adder 62. The output of adder 62 is an 8-bit 0.35R -0.87G + 0.SB signal which is available at 8-bit output 64. The proportion of B signal should be 0.52 no-t 0.5. The slight error is unobjectionable, but if desired a small ROM can be used at the B signal input of subtractor 44 to obtain the exact value for the B signal.
The above invention can be implemented using 2 adders, 1 ROM and 1 latch (not shown) per channel for a total of about 18 ICs, i.e. about one-half that of the prior art.
It should be understood that a similar matrix using the principles of this invention may be used to generate the R, G and B signals from received Y, I, and Q
signals in a television receiver. The matrix equation has the inverse of the ma-trix given above, in this embodiment.
it is "normalized". The resulting matrix e~uation is:
0.5 0.98 0.18 R
I _ 1.0 -0.4~ -0.53 G
.Q~ 0.3S -0.87 0.52 B
Eight-bit P~, G, and B signals are received at 8-bit inputs 30, 32, and 34 respectively. The input R
signal is applied to provider 36 and to subtractor 38.
The output of provider 36 supplies a 7~bit 0.5R signal to adder 40, and to ROM 42. The input G signal is applied to adder 40, subtractor 44, and to provider 46. Provider 46 supplies a 3-bit 0.03125G signal (shown as an 0.03G
signal) to ROMs 48, 50, and 42, and a 7-bit 0.5G signal to subtractor 38. The input B signal is applied to provider 52. Provider 52 supplies a 4-bit 0.0625B signal (shown as an 0.05B signal) to ROM 48, and a 7-bit 0.5B signal to ROM
50 and to subtractor 44.
Considering now the Y output channel, adder 40 provides an 8-bit lG + 0.5R signal -to adder 54. ROM 48 processes the inpu-t 0.03G signal to provide a -0.02G first output signal and also processes the 0.06B input signal to provide a 0.18B second output signal which is added in ROM
48 to the first output signal. The resulting 8-bit 0.18B-0.02G output signal from ROM 48 is applied to adder 54. The output signal from adder 54 is thus an 8-bit 0.5R
+ 0.98G + 0.18B signal which is available at 8~bi-t output 56. This is the Y signal.
In the I channel, subtractor 38 provides an 8-bit lR - 0.05G signal to adder 58. ROM 50 processes the 0.03G input signal to provide an -0.03G signa], and processes the 0.5B input signal to provide a -0.53B
signal. The resul-ting 8-bit -0.03G -0.53B output signal from ROM 50 is applied to adder 58. The output signal from adder 58 is an 8-bit lR -0.47G -0.53B signal, and is present at 8-bit O-ltpUt 60. This is the I signal.
In the O~ channel, ROM 42 processes the 0.5R
input signal to provide a 0.35R output signal, and also Li~''3~iO
~5- RCA 78,617 process -the 0.03G input signal to provide a 0.13G OlltpUt signal. The resulting 8-bit 0.35R + 0.13G output signal from ROM 42 is applied to adder 62. Subtractor 44 provides a -lG + 0.5B output signal to adder 62. The output of adder 62 is an 8-bit 0.35R -0.87G + 0.SB signal which is available at 8-bit output 64. The proportion of B signal should be 0.52 no-t 0.5. The slight error is unobjectionable, but if desired a small ROM can be used at the B signal input of subtractor 44 to obtain the exact value for the B signal.
The above invention can be implemented using 2 adders, 1 ROM and 1 latch (not shown) per channel for a total of about 18 ICs, i.e. about one-half that of the prior art.
It should be understood that a similar matrix using the principles of this invention may be used to generate the R, G and B signals from received Y, I, and Q
signals in a television receiver. The matrix equation has the inverse of the ma-trix given above, in this embodiment.
Claims (10)
1. A method for digitally multiplying a digital signal by a constant to produce a desired signal comprising the steps of:
dividing said digital signal by powers of two to obtain at least one fraction signal of the type 1/2n of said digital signal, where n is an integer and may include zero;
providing an approximation to said desired signal by summing together x number of said fraction signals, where x may equal one to produce an approximate signal;
multiplying a selected fraction signal by a predetermined constant to produce a remainder signal equal to the difference between said desired signal and said approximate signal; and summing said remainder and approximate signals.
dividing said digital signal by powers of two to obtain at least one fraction signal of the type 1/2n of said digital signal, where n is an integer and may include zero;
providing an approximation to said desired signal by summing together x number of said fraction signals, where x may equal one to produce an approximate signal;
multiplying a selected fraction signal by a predetermined constant to produce a remainder signal equal to the difference between said desired signal and said approximate signal; and summing said remainder and approximate signals.
2. Apparatus for digitally multiplying a digital signal by a constant to produce a desired signal comprising:
means for dividing said digital signal by powers of two to obtain at least one fraction signal of the type 1/2n of said digital signal, where n is an integer and may include zero;
means for providing an approximation to said desired signal by summing together x number of said fraction signals, where x may equal one to produce an approximate signal;
means for multiplying a selected fraction signal by a predetermined constant to produce a remainder signal equal to the difference between said desired signal and said approximate signal; and means for summing said remainder and approximate signals.
means for dividing said digital signal by powers of two to obtain at least one fraction signal of the type 1/2n of said digital signal, where n is an integer and may include zero;
means for providing an approximation to said desired signal by summing together x number of said fraction signals, where x may equal one to produce an approximate signal;
means for multiplying a selected fraction signal by a predetermined constant to produce a remainder signal equal to the difference between said desired signal and said approximate signal; and means for summing said remainder and approximate signals.
3. Apparatus as claimed in Claim 2, wherein said digital signal comprises a video signal.
4. Apparatus as claimed in Claim 2, wherein said multiplying means comprises a ROM.
5. Apparatus as claimed in Claim 2, wherein said summing means comprises an adder or subtractor.
6. A method for forming color television video signal from R, G and B signals, comprising the steps of:
dividing the amplitude of the R signal by two to form a 0.05R signal;
dividing the amplitude of the B signal by the fourth power of two (24) to form a .0625B signal;
dividing the amplitude of the G signal by the fifth power of two (25) to form a 0.03125G signal;
summing said G and 0.5R signals to form a (G+0.5R) signal;
multiplying said 0.0625B signal and said 0.03125G signals by constants to form a Y residue signal;
and summing said Y residue signal with said (G+0.5R) signal to form the Y video signal.
dividing the amplitude of the R signal by two to form a 0.05R signal;
dividing the amplitude of the B signal by the fourth power of two (24) to form a .0625B signal;
dividing the amplitude of the G signal by the fifth power of two (25) to form a 0.03125G signal;
summing said G and 0.5R signals to form a (G+0.5R) signal;
multiplying said 0.0625B signal and said 0.03125G signals by constants to form a Y residue signal;
and summing said Y residue signal with said (G+0.5R) signal to form the Y video signal.
7. A method according to Claim 6, further comprising the steps of:
dividing the amplitude of said G and B signals by the first power of two (21) to form 0.5G and 0.5B
signals;
taking the difference between said R and 0.5G
signals to form a (R-0.5G) signal;
multiplying said 0.03125G signal and said 0.5B
signal by constants to form an I residue signal; and summing said (R-0.5G) signal with said I residue signal to form an I video signal.
dividing the amplitude of said G and B signals by the first power of two (21) to form 0.5G and 0.5B
signals;
taking the difference between said R and 0.5G
signals to form a (R-0.5G) signal;
multiplying said 0.03125G signal and said 0.5B
signal by constants to form an I residue signal; and summing said (R-0.5G) signal with said I residue signal to form an I video signal.
8. A method according to Claim 7, further comprising the steps of:
taking the difference between said 0.5B signal and said G signal to form a (-G+0.5B) signal;
multiplying said 0.5R and 0.03125G signals by constants to form a Q residue signal; and summing said (-G+0.5B) signal with said Q
residue signal to form a video Q signal.
taking the difference between said 0.5B signal and said G signal to form a (-G+0.5B) signal;
multiplying said 0.5R and 0.03125G signals by constants to form a Q residue signal; and summing said (-G+0.5B) signal with said Q
residue signal to form a video Q signal.
9. A method according to Claim 1 wherein said selected fraction signal is the smallest of said fraction signals.
10. Apparatus as claimed in Claim 2 wherein said selected fraction signal is the smallest of said fraction signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US437,263 | 1982-10-28 | ||
| US06/437,263 US4507676A (en) | 1982-10-28 | 1982-10-28 | Digital matrixing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1191960A true CA1191960A (en) | 1985-08-13 |
Family
ID=23735726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000438173A Expired CA1191960A (en) | 1982-10-28 | 1983-09-30 | Digital matrixing system |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US4507676A (en) |
| JP (1) | JPS59108146A (en) |
| KR (1) | KR840006592A (en) |
| AU (1) | AU560272B2 (en) |
| CA (1) | CA1191960A (en) |
| DE (1) | DE3339029A1 (en) |
| ES (1) | ES8502303A1 (en) |
| FR (1) | FR2535567A1 (en) |
| GB (1) | GB2131579B (en) |
| IT (1) | IT1171789B (en) |
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| US4602276A (en) * | 1984-04-12 | 1986-07-22 | Rca Corporation | Digital signal level overload system |
| US4683490A (en) * | 1985-06-05 | 1987-07-28 | Rca Corporation | Video signal processing apparatus |
| JPS62256129A (en) * | 1986-04-30 | 1987-11-07 | Sony Corp | Arithmetic processing unit |
| JP2569691B2 (en) * | 1988-02-16 | 1997-01-08 | ソニー株式会社 | Color difference signal forming circuit |
| US5008739A (en) * | 1989-02-13 | 1991-04-16 | Eastman Kodak Company | Real-time digital processor for producing full resolution color signals from a multi-color image sensor |
| US5001663A (en) * | 1989-05-03 | 1991-03-19 | Eastman Kodak Company | Programmable digital circuit for performing a matrix multiplication |
| JP2938115B2 (en) * | 1990-02-09 | 1999-08-23 | 三菱電機株式会社 | Color signal conversion circuit |
| US5319724A (en) * | 1990-04-19 | 1994-06-07 | Ricoh Corporation | Apparatus and method for compressing still images |
| US5594812A (en) * | 1990-04-19 | 1997-01-14 | Ricoh Corporation | Apparatus and method for compressing still images |
| US5664028A (en) * | 1990-04-19 | 1997-09-02 | Ricoh Corporation | Apparatus and method for compressing still images |
| US5129015A (en) * | 1990-04-19 | 1992-07-07 | Ricoh Company Ltd. | Apparatus and method for compressing still images without multiplication |
| JPH04283831A (en) * | 1991-03-13 | 1992-10-08 | Fujitsu Ltd | Divider |
| SG44931A1 (en) * | 1991-07-05 | 1997-12-19 | Thomson Multimedia Sa | Method and circuit for converting rgb signals to component signals |
| US5625713A (en) * | 1991-08-09 | 1997-04-29 | Ricoh Corporation | Apparatus and method for increasing the throughput of an acoustic or image compression system |
| US5260888A (en) * | 1992-05-28 | 1993-11-09 | Eastman Kodak Company | Shift and add digital signal processor |
| US5510852A (en) * | 1994-04-28 | 1996-04-23 | Winbond Electronics, Corp. | Method and apparatus using symmetrical coding look-up tables for color space conversion |
| US5784050A (en) * | 1995-11-28 | 1998-07-21 | Cirrus Logic, Inc. | System and method for converting video data between the RGB and YUV color spaces |
| JP3435961B2 (en) * | 1996-02-16 | 2003-08-11 | ヤマハ株式会社 | Image data conversion apparatus and image data conversion method |
| US5990876A (en) * | 1996-12-10 | 1999-11-23 | Winbond Electronics Corp. | Method and apparatus with reduced look-up tables for converting RGB color space signals to YCbCr color space signals |
| US5963263A (en) * | 1997-06-10 | 1999-10-05 | Winbond Electronic Corp. | Method and apparatus requiring fewer number of look-up tables for converting luminance-chrominance color space signals to RGB color space signals |
| US6075573A (en) * | 1997-06-10 | 2000-06-13 | Winbond Electronics Corp. | Method and apparatus for converting luminance-chrominance color space signals to RGB color space signals using shared predictive and compensative transformation codes for chrominance components |
| US6049399A (en) * | 1997-11-04 | 2000-04-11 | Winbond Electronics Corp. | Method and apparatus with reduced look-up tables for converting luminance-chrominance color space signals to RGB color space signals |
| DE102004060185B3 (en) * | 2004-12-14 | 2006-05-18 | Infineon Technologies Ag | Multiplication or division operation executing method for e.g. signal-to-noise ratio and interference ratio-estimating circuit, involves calculating correction factor in firmware-evaluation block, and multiplying shifted value with factor |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4160264A (en) * | 1977-07-01 | 1979-07-03 | Eastman Kodak Company | Matrix compensator for color video signals |
| US4208722A (en) * | 1978-01-23 | 1980-06-17 | Data General Corporation | Floating point data processing system |
| US4229800A (en) * | 1978-12-06 | 1980-10-21 | American Microsystems, Inc. | Round off correction logic for modified Booth's algorithm |
| US4344151A (en) * | 1980-04-21 | 1982-08-10 | Rockwell International Corporation | ROM-Based complex multiplier useful for FFT butterfly arithmetic unit |
| US4449194A (en) * | 1981-09-25 | 1984-05-15 | Motorola Inc. | Multiple point, discrete cosine processor |
| FR2517915B1 (en) * | 1981-12-09 | 1986-01-17 | Thomson Brandt | MATRIXING DEVICE FOR COLOR TELEVISION CAMERA AND ENCODER AND CAMERA COMPRISING SUCH A DEVICE |
-
1982
- 1982-10-28 US US06/437,263 patent/US4507676A/en not_active Expired - Fee Related
-
1983
- 1983-09-30 CA CA000438173A patent/CA1191960A/en not_active Expired
- 1983-10-27 KR KR1019830005076A patent/KR840006592A/en not_active Application Discontinuation
- 1983-10-27 ES ES526839A patent/ES8502303A1/en not_active Expired
- 1983-10-27 GB GB08328682A patent/GB2131579B/en not_active Expired
- 1983-10-27 JP JP58200138A patent/JPS59108146A/en active Pending
- 1983-10-27 DE DE19833339029 patent/DE3339029A1/en not_active Withdrawn
- 1983-10-28 IT IT23537/83A patent/IT1171789B/en active
- 1983-10-28 AU AU20802/83A patent/AU560272B2/en not_active Expired - Fee Related
- 1983-10-28 FR FR8317345A patent/FR2535567A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| ES526839A0 (en) | 1984-12-16 |
| ES8502303A1 (en) | 1984-12-16 |
| KR840006592A (en) | 1984-11-30 |
| JPS59108146A (en) | 1984-06-22 |
| IT8323537A0 (en) | 1983-10-28 |
| GB2131579B (en) | 1986-10-01 |
| AU560272B2 (en) | 1987-04-02 |
| GB2131579A (en) | 1984-06-20 |
| FR2535567A1 (en) | 1984-05-04 |
| IT1171789B (en) | 1987-06-10 |
| GB8328682D0 (en) | 1983-11-30 |
| DE3339029A1 (en) | 1984-05-03 |
| US4507676A (en) | 1985-03-26 |
| AU2080283A (en) | 1984-05-03 |
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