CA1185375A - Dual path bus structure for computer interconnection - Google Patents
Dual path bus structure for computer interconnectionInfo
- Publication number
- CA1185375A CA1185375A CA000427599A CA427599A CA1185375A CA 1185375 A CA1185375 A CA 1185375A CA 000427599 A CA000427599 A CA 000427599A CA 427599 A CA427599 A CA 427599A CA 1185375 A CA1185375 A CA 1185375A
- Authority
- CA
- Canada
- Prior art keywords
- path
- bus
- paths
- port
- failure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
- G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Abstract
Abstract of the Disclosure A bus structure for use in a computer network requiring high availabilty and reliability of communications. Multiple bus paths are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly.
Each host device in the network connects to the bus paths through an interface, or port. The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.
Each host device in the network connects to the bus paths through an interface, or port. The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.
Description
53~
Cross Reference to Related Applications . . . ~
The invention which is the subject of this applica-tion is particularly useful in a system incorporating one or more of -the inventions shown in the following commonly assigned applica~
tions, filed on even date herewith:
Canadian Patent Applic~tion Serial No. 427,591, titled INTERFACE FOR SERIAL DATA COMMUNIC~TIONS LINK, in the name(s) of Robert E. Stewart, Robert Giggi and John E. Buzynski; Canadian Patent Applica-tion Serial No. 427,593, titled METHOD AND APPARATUS
FOR DIRECT MEMORY-TO-MEMORY INTERCOMPUTER COMMUNICATION, in -the name(s) of William S-trecker, Robert Stewart, and Samuel Fuller;
and Canadian Patent Application Serial No. 427,594, ti-tled DUAL-COUNT, ROUND-ROBIN DISTRIBUTED ARBITRATION TECHNIQUE FOR CONTENTION-ARBITRATED SERIAL BUSES, in the name(s) of William D. Strecker, John E. Buzynski, and David Thompson, Field of the Invention This invention relates to the field computer system inter-connec-tions; and, more specifically, to an apparatus for transferring information between different compu-ters or computer system elemen-ts in a computer network. It involves -the use of not one, but two or more alternate buses or interconnection subsys-tems to enable the , - 1 3 ~5 different computers in the network ~o communicate with one another~
Background of the Invention In a distributed computer network comprising a system of interconnected computer nodes, information comprising commands, responses and data frequently must be transmitted between two or more nodes and combinations of nodes in order to allow the various components of the network to interact. Generally, a so-called "bus"
connects ~he various nodes and acts as a communications conduit linking them4 Obviouslyl if the bus fails or becomes unavaiiable, communications between nodes will cease.
A "port"; also called an "interface" or "adapter", is the mechanism through which a (host) computer or other device gains access to a bus for communicating with other computers and devices. A port includes a port processor, port buffer, and link components; the roles of these components is explained below.
A "node" comprises a host compu~er and at least one port; a node may also have or use multiple ports and there ports may communicate with each other over the bus.
A "bus" is an interconnection between devices through which informatisn may be transferred from one device to another; it includes a communication channel and associated components and control.
A "network" is a system of nodes interconnec~ed via a common bus.
For many applications, the consequences of a bus failure are serious, as intercomputer communications are essential; a primary design goal for such networks, therefore, is high bus availability ~nd reliability. One approach which has been adopted in the past to enhance availability and reliability of the node-to-node 3 ~3~
interconnection in such networks is to provide two fully redundant bus paths running in parallel from node to node. That way, if one path i5 unavailable the other can be used. Full redundancy, as that term is used herein, implies not only the duplication of cabling between system nodes, but also, at each node and for each port at each node, completely separate processing circuitry and software for handling communications over each of the paths.
Most bus failures however, are not due ~o unreliability of the transmit or receive processing circuitry or software in a node; but, rather, to physical breakdown of a path - i.eO, cabling, connectors~ etc.
Secondarily, failures occur in the circuitry closest to the cabling - e9g., line drivers and receivers, etc.
Consequently, it is needlessly expensive and causes needless complexity to employ full redundancy.
Moreover, full redundancy re~uires that the selection of a path for a particular exchange be made at a point wi~hin or very close to the host-inte~face connection, generally requiring awareness and perhaps even requiring action by the host's software. One way sf addressing the burden this creates is to assign one path primary responsiblity, and to use the other path(s) only when the primary path failsO That, however~ permits failure of the back-up path(s) to go unnoticed for a long time, until such path(s) is (are) not available when needed~
allowing a total failure of communication ability to occur.
~0 Full redundancy also does nothing to protect the integrlty of the logical connection between nodes in the event of bus failure.
Accordingly, it is an object of this invention to provide a high availability and high reliabili~y computer ~ 53'~
interconnection system which i5 more efficient than a single bus pa~h but less cos~ly than a fully redundant bus system.
It is a further object of this invention to provide such a bus system in which each node contains a minimum of redundant parts dedicated to separate b~s paths and a majority of par~s shared by multiple bus paths t to provide higher relia~ility and availability without the cost of a fully redundant dual bus system.
Yet another object of this invention is ~o provide such an interconnection employing two (or morel bus paths wherein both the selection and opera~ion of the bus path, and the failure of a bus path (with resulting switchover), need not be immediately visible to the host computers which communicate over the system~
Still another objec~ of the invention is to provide a multiple path node interconnection network wherein the failure of a path during an exchange does not corrupt the logical connection between the communicating nodes.
Summary of the Invention The foregoing and other o~jects and advantages of the invention are accomplished by a high speed, high availability and high reliability multiple (e.g., dual) path bus structure wherein separate line drivers and receivers are provided for each bus path but a single set of components (e~g., common transmit and receive logic circuits, etc.) is shared be~ween the two paths~ For simplicity, only two bus paths will be shown, it being understood that a greater number may be used in a similar fashion. ~oth paths are used constantlyr with assignment on a random, equal-probability basis, so tha~ a failure is readily found 9 and is not hidden. Path ~sage is monitored at each node, in the bus interface, so that a switch-over can be accomplished from one path to ~he 3~
other if a failure occurs or errors are observed on a particular path.
By keeping the path-selection and switching mechanism close to the paths themselves and away from the host-interface connection, path selec-tion is made transparent to the hosts. That is, the hosts need not (and do not) know which bus path is used for a particular transmission.
Transfers from one node to another, as explained more fully in aforementioned Canadian application serial no. 427,593, titled Method and Apparatus for Direct Memory-to-Memory Intercompu-ter Communication, involve communications from host memory at one node to host memory at another node via, a so called "virtual"
circuit. Virtual circuits are set up between the bus interfaces (also called ports) of the nodes, according to node pairs. Virtual circuit state and path state information are integrated into a common place; therefore, path failure is prevented from causing virtual circuit failure. Thus, there is no loss or duplication of transfers as a result of path failure. On failure of a path in mid-transmission, the failed transmission is simply repeated with the same sequence number. It is automatically rerouted over the alternate path and is seen by the receiver as a repeat of a failed transmission, thus avoiding duplicate delivery. That is, the same virtual circuit is continued over the alternate path.
Multiple bus paths are provided primarily -to enhance reliability of inter-node communications - i.e., such that single component, node or interface failure will not totally prevent communications between other functioning nodes and ports. As an added benefit obtained a-t almost no cost, information throughput may be increased about fifty percent as compared with a single bus pa-th. of course, upon failure of a path, that performance may be degraded until repairs are made.
Each interface is responsible for the multiplexing and demultiplexing of packets on the paths. As explained in aforesaid Canadian application serial no. ~27,593, each interface includes a port processor, packet buffers and a "link" (or data link). Only the data link portion of the interface need be logically duplicated for each path.
Two types of path selection for transmission are provided.
These are designated "Select" and !'Automatic". In Select mode, a host can specify a particular path. This mode is used for cont-roller configuration transactions and requires that packets be returned on the same path in response to a request packet, it is also useEul for diagnostic purposes. The majority of packe-ts, however, are sent in Automatic mode. In -this mcde, the selection of the path for transmission of a packet is made by a -two-way equally probable, statistical choice (i.e., a "coin-flip"). This results in frequent exercising of both paths, for early :Eailure detection. If a transmission fails, all retransmission attempts for the same packet are made on the same bus path until preestab-lished retry limits are reached. A-t that point, the other path can be tried, following the same retransmission algorithms until its retry limits are exceeded. At that point, it is most likely that a hardware failure has occurred or that -the destination interface is not in a state where communications are enabled.
3'7~
Each port maintains a table of path status between itself and all other ports in the network. Such a table indicates whe-ther a path to a given port is correctly functioning or not.
The table values are based on prior transmission results. In Automatic mode, paths are selected from only known good pa-ths as indicated in the path status table. This prevents known bad paths from being selected with any great frequency, since such selections would result in failed transmissions and a consequential waste of available bandwidth. If a known bad path is to be re-tried, to see if it has been repaired, it is selected with muchlower frequency than normal.
In summary, the present invention provides, according to a first aspect, a high reliability and high availability bus structure for providing communications between the nodes of a computer network, wherein each node includes a host device and at least one port, the port being an interface for connecting the host device to the bus, the bus struc-ture comprising: A. the bus including at least a first bus path and a second bus path, said bus paths being independent of each other; and B. for each port i. transmitting means for transmitting signals onto each of the bus paths, ii. receiving means Eor receiving signals from each of the bus paths, iii. path selecting means (e.g., port processor responsive to a signal from the host device which indi-cates that the host device desires to transmit, for selecting one of said bus paths for use for -transmission, iv. means coupled to the path selecting means for enabling the transmitting means to transmit only on the selected path, v. carrier detect means 3 ~i coupled to the receiving means for detecting the presence or absence of signals on each bus path and the beginning of a trans-mission, and vi. means responsive -to the carrier de-tect means for selecting only one of the paths for receive signal processing responsive to the presence of signals -thereon at the beginning of a transmission.
According to another aspect the invention provides in a network for providing communications between multiple computer nodes, and wherein all communications take place via virtual circuits created between pairs of ports, a high reliability and high availability bus structure Eor interconnecting said ports, comprising: A. the bus including at least a first bus path and a second bus path said bus paths being independent of each other;
and B. at each port i. a path status table maintained by the port and containing, for each other port in the network, an i.ndi-cation of virtual circuit state between itself and said other port and an indication of the state of each bus path, and ii.
means for selecting a bus path for a transmission to another port, responsive to the path states shown in the path s-tatus table, whereby virtual circuit state is undisturbed by failure of a bus path if the status of at least one path is good after the failure, so tha-t upon occurrence of such a failure, the means for selecting a bus path chooses a new path and communications continue without -the hosts having to know about or take ac-tion regarding -the failure and the path swi-tchover.
The invention will now be described in greater detail with reference to the accompanying drawings, in which:
-7b- ~ ~r~
Figure 1 is a block diagram of a bus interface according to the inven-tion, configured to utilize a pair of bus paths;
and Figure 2 is a flow chart of the method of selec-ting a bus path for a transmission, in accordance with -this invention.
Single pa-th interfaces also may be connected -to the network, but are not encouraged. All single path ports must be connected to a predesignated one of -the paths, to insure tha-t all nodes in the network may communicate. The danger that arises from the use of too many sing]e-path ports is that path loads (i.e., usage) becomes unqueally distributed to an extent that degrades both performance and reliability.
If a sufficient portion of each port is duplicated phys-ically~ it may be possible to transmit packets on both pa-ths simul-taneously. Due to interdependent retransmissions, the ser~uence of packet arrivals could be different than the sequence of their deli-very to the originating port. To preserve packet sequentiality on a node-to-node basis, which is requiredl -the transmission of a packe-t to a remote port must be completed in its entirety before another packet for the same destination is delivered to -the data link. The receiving port must process the received packets in the order of their real time arrival.
The path selection mode for packet transmission is spec-ified by the value of the Path Select (PS) field of the command.
For example, PS=0 may indicate -the Automatic mode, PS=l may indi-cate the Select mode for path 0, PS=2 may indicate the Select mode for path 1, and PS-3 may be reserved. The pa-th status table is par-t of the Virtual Circuit Descriptor Table maintained by each port and consists of two bi-ts for each interface pair; there is one bit for each of the two paths to indicate "good" or "bad" status for that path. ~lote that the path status table may indicate -that the same path is good for one destination port and bad for another, since status is kept on a port-pair basis. For further discussion and ex-planation of the PS field and the Virtual Circuit Descriptor Table, see aforementioned Canadian patent application serial no. 427,593.
When a co~lmand specifies Automatic mode, the path for each packet of the command is selected individually from the paths marked good in the path status table. If only one of the paths concurrently is marked good, it is used; if both are marked good, oneis selected at random.
In Select mode, the table is ignored for the particular transmission but is updated based on the results ~f the transmission. The status of a path may be changed from bad to good or good to bad by the outcome of the transmission.
At the time of initialization, all pa~h status table entries indicate ~hat all paths are good.
For any interface in ~he network capable of operating only on a single path, only one bit of the path status table is kept, for the same preselected one of the paths in all cases (so that all parts have at least one path in common). In Automatic mode, that path is used, unless the path status table bit indicates that the path is bad; in the latter case, the command fails since communication is impossible.
Attention is now directed to Fig. 1, where a block diagram of relevant por~ions of a bus interface (i.e., a port) 1 is shown as it would be configured to utilize two bus paths ~2A and 2B), according to ~he present invention. Each path, such as path 2A, is, in turn, formed from a transmit line 3A and a receive line 4A tied together by a coupler 5A. The port comprises a port processor 10, transmit and receive packet buffers 20A and 20B, and link 30. Link 309 in turn, is divided into three main subassemblies - a transmitter 40, a receiver 50 and an arbitration circuit S0. The latter may physically be implemented in the port proce~sor, but is shown as functionally isolated.
Taking first the transmit operation, port processor 10 supplies a path selection ~PS) signal on conductor 62 ~o a path select flip-flop 64, the latter being clocked by a transmit clock (XMIT CLK) signal. The output of path select flip-flop 64 controls a pair of driver inhibit circuits 66A and 66B, one each for a first bus ~ rj ~7 rj path (i.e., bus path A) and for a second bus path (i.e., bus path B). The output of the driver inhibit circuits controls the enabling of line drivers 6BA and 68B, respectively. When a path is deselected, its line driver is disabled. Driver inhibit rircuits 66A respond also to an ARBITRATION WON signal supplied on conductor 72 by arbitration circuit 60. In order for a line driver to be enabled, the associated bus pa~h must be selected by the PS signal and the port mus~ have won arbitration nf (i.e., access to) the bus.
Information packets to be transmitted are supplied by transmit packet buffers 20A bit-serially to an encoder 74. The encoder combines the information with a ~ransmit clock, such as ~y the so-called Manchester encoding technique. ~ncoded transmit data is supplied by encoder 74 to line drivers 68A and 68B, for transmission by the enabled driver over the selected bus path.
The PS signal is ~enerated by means fo a path selection algorithm 12 running in port processor 1OD The path selection algorithm evaluates the PX field of the transmit command and chooses a path based on that field, a random number generator and the path status entries of path status ~able 110, which is also maintained in the port processor 10. Fig. 2 provides a more complete understanding of the path selection algorithm.
Turning now to the receiver, signals on bus paths A
and B are detec~ed and amplified by an appropriate one of line receivers B2A and 82B, respectively. Each of the line receivers feeds a multiplexer ~mux) 84 and a carrier detector, B6A and 86B, respectively~ The carrier aetectors feed a carrier switch 88 which, in turn, controls mux 84. More specificlly, carrier switch 8~
causes mux 84 to select the input corresponding to the appropriate bus path on which a transaction is occurrin~
3'~
(i.e., on which a transmit signal - a carrier - is detected). Path switching is done at the beginning of a transmission only, not in the middle. The carriex switch also controls arbitra-tion circuit 60; the latter is described in greater detail in the aforementioned Canadian application serial no. 427,594.
The output of mux 84 is the encoded data transmission re-ceived over the selected bus path. A decoder 92, such as described in aforemen-tioned Canadian application serial no. 427,591, separates out the information signal from the clock and supplies these to -the receive packe-t buffers 20B, for serial-to-parallel conversion of the information bytes.
The outputsfrom decoder 92 also are supplied to an ack-nowledgmen-t decoder 94. The acknowlegment decodcr evaluates the acknowledgment signals received from a destination port and supplies the results to a transmit status register 96. In turn, the trans-mit status register notifies the port processor 10 whether the transmission was successful or unsuccessful and, if the latter, whether a path was found bad, If a path was found bad, the entry of the path s-tatus table is updated to reflect that situation.
The operation of path selection is shown graphically in the flow chart of Figure 2. Upon receipt of a transmi-t command, step 102, the process begins. First, the port processor chooses the path-selection mode (step 10~ e., Select mode (shown on line 106) or Automatic mode (shown on line 108).
Assuming Select mode was chosen, the selected path is obtained next, step 112. The port next arbitrates for bus access, step 118, and transmits after winning 12 ~ ~S~'7~
arbitration, step 120. At the conclusion of a transmission (i.e., retries are exhausted or the .
transmission succeeded, a determination is made whether the transmission was successful, step 121A. If so, the algorithm exits the routinet step 122. If the transmission failed, the path status table is updated to indicate the path is bad, step 121B, and the routine exits, steps 121C and 121D. Note that step 120 retries, if needed. If Automatic mode is selected, the path is chosen as follows (~tep 124): initially, the path selection is made randomlyt on an equal probability basis, sn subsequent a~empts ~o select a path due to prior selection of a bad path, the prior bad selection(s) is (are) excluded and a random pick is made from among remaining paths. If all possiblities are exhausted without finding ~ good path, ~he procedure exits with an appropriate failure indication, step 126. Following each tentative path selection, the status of the chosen path is obtained from the path status table, step 128, and ~ested to see whether it is good or bad, step 130. If bad, an attempt is made ~o find an alternate path (steps 134, 136 and 138); if good, the PS signal i5 generated, to switch the link to the selected path, (step 132) and arbitration is begun, step 118.
From step 121C or step 130~ alternate path selection starts by selecting another path, step 134. The status of this alternate path is obtained from the path status table 110, step 136, and checked to see whether the path is goo~, step 138. If the alternate path is good, control branches to step 132; otherwise, the rou~ine éxits with an indication that all paths are bad, step 126.
Thus, there is no host involvement necessary in making a path selection or switchoYer, both pa~hs are 13 ~q ~
exercised frequently, and minimal hard~are is needed to add the second bus path. It is a simple matter to extend these concepts to more than two paths, of course. The main change would be to add a decision block in Fig. 2 between the "No~ output of step 138 and the exit, step 126, to loop back to step 134 if all paths have not been tried. The path status table would also have to be enlarged.
The foregoing description is limited to a single specific embodiment of this inventionr but it will be apparent that this invention can be practiced in data processing systems having diverse basic construction or in systems using different internal circuitry or design while never~heless achieving some or all of the foregoing objects and advantages of this invention. Therefore, it is the object of the appended claims ~o cover all such variations, modifications and obvious improvement as come within the true spirit and scope of this invention.
Cross Reference to Related Applications . . . ~
The invention which is the subject of this applica-tion is particularly useful in a system incorporating one or more of -the inventions shown in the following commonly assigned applica~
tions, filed on even date herewith:
Canadian Patent Applic~tion Serial No. 427,591, titled INTERFACE FOR SERIAL DATA COMMUNIC~TIONS LINK, in the name(s) of Robert E. Stewart, Robert Giggi and John E. Buzynski; Canadian Patent Applica-tion Serial No. 427,593, titled METHOD AND APPARATUS
FOR DIRECT MEMORY-TO-MEMORY INTERCOMPUTER COMMUNICATION, in -the name(s) of William S-trecker, Robert Stewart, and Samuel Fuller;
and Canadian Patent Application Serial No. 427,594, ti-tled DUAL-COUNT, ROUND-ROBIN DISTRIBUTED ARBITRATION TECHNIQUE FOR CONTENTION-ARBITRATED SERIAL BUSES, in the name(s) of William D. Strecker, John E. Buzynski, and David Thompson, Field of the Invention This invention relates to the field computer system inter-connec-tions; and, more specifically, to an apparatus for transferring information between different compu-ters or computer system elemen-ts in a computer network. It involves -the use of not one, but two or more alternate buses or interconnection subsys-tems to enable the , - 1 3 ~5 different computers in the network ~o communicate with one another~
Background of the Invention In a distributed computer network comprising a system of interconnected computer nodes, information comprising commands, responses and data frequently must be transmitted between two or more nodes and combinations of nodes in order to allow the various components of the network to interact. Generally, a so-called "bus"
connects ~he various nodes and acts as a communications conduit linking them4 Obviouslyl if the bus fails or becomes unavaiiable, communications between nodes will cease.
A "port"; also called an "interface" or "adapter", is the mechanism through which a (host) computer or other device gains access to a bus for communicating with other computers and devices. A port includes a port processor, port buffer, and link components; the roles of these components is explained below.
A "node" comprises a host compu~er and at least one port; a node may also have or use multiple ports and there ports may communicate with each other over the bus.
A "bus" is an interconnection between devices through which informatisn may be transferred from one device to another; it includes a communication channel and associated components and control.
A "network" is a system of nodes interconnec~ed via a common bus.
For many applications, the consequences of a bus failure are serious, as intercomputer communications are essential; a primary design goal for such networks, therefore, is high bus availability ~nd reliability. One approach which has been adopted in the past to enhance availability and reliability of the node-to-node 3 ~3~
interconnection in such networks is to provide two fully redundant bus paths running in parallel from node to node. That way, if one path i5 unavailable the other can be used. Full redundancy, as that term is used herein, implies not only the duplication of cabling between system nodes, but also, at each node and for each port at each node, completely separate processing circuitry and software for handling communications over each of the paths.
Most bus failures however, are not due ~o unreliability of the transmit or receive processing circuitry or software in a node; but, rather, to physical breakdown of a path - i.eO, cabling, connectors~ etc.
Secondarily, failures occur in the circuitry closest to the cabling - e9g., line drivers and receivers, etc.
Consequently, it is needlessly expensive and causes needless complexity to employ full redundancy.
Moreover, full redundancy re~uires that the selection of a path for a particular exchange be made at a point wi~hin or very close to the host-inte~face connection, generally requiring awareness and perhaps even requiring action by the host's software. One way sf addressing the burden this creates is to assign one path primary responsiblity, and to use the other path(s) only when the primary path failsO That, however~ permits failure of the back-up path(s) to go unnoticed for a long time, until such path(s) is (are) not available when needed~
allowing a total failure of communication ability to occur.
~0 Full redundancy also does nothing to protect the integrlty of the logical connection between nodes in the event of bus failure.
Accordingly, it is an object of this invention to provide a high availability and high reliabili~y computer ~ 53'~
interconnection system which i5 more efficient than a single bus pa~h but less cos~ly than a fully redundant bus system.
It is a further object of this invention to provide such a bus system in which each node contains a minimum of redundant parts dedicated to separate b~s paths and a majority of par~s shared by multiple bus paths t to provide higher relia~ility and availability without the cost of a fully redundant dual bus system.
Yet another object of this invention is ~o provide such an interconnection employing two (or morel bus paths wherein both the selection and opera~ion of the bus path, and the failure of a bus path (with resulting switchover), need not be immediately visible to the host computers which communicate over the system~
Still another objec~ of the invention is to provide a multiple path node interconnection network wherein the failure of a path during an exchange does not corrupt the logical connection between the communicating nodes.
Summary of the Invention The foregoing and other o~jects and advantages of the invention are accomplished by a high speed, high availability and high reliability multiple (e.g., dual) path bus structure wherein separate line drivers and receivers are provided for each bus path but a single set of components (e~g., common transmit and receive logic circuits, etc.) is shared be~ween the two paths~ For simplicity, only two bus paths will be shown, it being understood that a greater number may be used in a similar fashion. ~oth paths are used constantlyr with assignment on a random, equal-probability basis, so tha~ a failure is readily found 9 and is not hidden. Path ~sage is monitored at each node, in the bus interface, so that a switch-over can be accomplished from one path to ~he 3~
other if a failure occurs or errors are observed on a particular path.
By keeping the path-selection and switching mechanism close to the paths themselves and away from the host-interface connection, path selec-tion is made transparent to the hosts. That is, the hosts need not (and do not) know which bus path is used for a particular transmission.
Transfers from one node to another, as explained more fully in aforementioned Canadian application serial no. 427,593, titled Method and Apparatus for Direct Memory-to-Memory Intercompu-ter Communication, involve communications from host memory at one node to host memory at another node via, a so called "virtual"
circuit. Virtual circuits are set up between the bus interfaces (also called ports) of the nodes, according to node pairs. Virtual circuit state and path state information are integrated into a common place; therefore, path failure is prevented from causing virtual circuit failure. Thus, there is no loss or duplication of transfers as a result of path failure. On failure of a path in mid-transmission, the failed transmission is simply repeated with the same sequence number. It is automatically rerouted over the alternate path and is seen by the receiver as a repeat of a failed transmission, thus avoiding duplicate delivery. That is, the same virtual circuit is continued over the alternate path.
Multiple bus paths are provided primarily -to enhance reliability of inter-node communications - i.e., such that single component, node or interface failure will not totally prevent communications between other functioning nodes and ports. As an added benefit obtained a-t almost no cost, information throughput may be increased about fifty percent as compared with a single bus pa-th. of course, upon failure of a path, that performance may be degraded until repairs are made.
Each interface is responsible for the multiplexing and demultiplexing of packets on the paths. As explained in aforesaid Canadian application serial no. ~27,593, each interface includes a port processor, packet buffers and a "link" (or data link). Only the data link portion of the interface need be logically duplicated for each path.
Two types of path selection for transmission are provided.
These are designated "Select" and !'Automatic". In Select mode, a host can specify a particular path. This mode is used for cont-roller configuration transactions and requires that packets be returned on the same path in response to a request packet, it is also useEul for diagnostic purposes. The majority of packe-ts, however, are sent in Automatic mode. In -this mcde, the selection of the path for transmission of a packet is made by a -two-way equally probable, statistical choice (i.e., a "coin-flip"). This results in frequent exercising of both paths, for early :Eailure detection. If a transmission fails, all retransmission attempts for the same packet are made on the same bus path until preestab-lished retry limits are reached. A-t that point, the other path can be tried, following the same retransmission algorithms until its retry limits are exceeded. At that point, it is most likely that a hardware failure has occurred or that -the destination interface is not in a state where communications are enabled.
3'7~
Each port maintains a table of path status between itself and all other ports in the network. Such a table indicates whe-ther a path to a given port is correctly functioning or not.
The table values are based on prior transmission results. In Automatic mode, paths are selected from only known good pa-ths as indicated in the path status table. This prevents known bad paths from being selected with any great frequency, since such selections would result in failed transmissions and a consequential waste of available bandwidth. If a known bad path is to be re-tried, to see if it has been repaired, it is selected with muchlower frequency than normal.
In summary, the present invention provides, according to a first aspect, a high reliability and high availability bus structure for providing communications between the nodes of a computer network, wherein each node includes a host device and at least one port, the port being an interface for connecting the host device to the bus, the bus struc-ture comprising: A. the bus including at least a first bus path and a second bus path, said bus paths being independent of each other; and B. for each port i. transmitting means for transmitting signals onto each of the bus paths, ii. receiving means Eor receiving signals from each of the bus paths, iii. path selecting means (e.g., port processor responsive to a signal from the host device which indi-cates that the host device desires to transmit, for selecting one of said bus paths for use for -transmission, iv. means coupled to the path selecting means for enabling the transmitting means to transmit only on the selected path, v. carrier detect means 3 ~i coupled to the receiving means for detecting the presence or absence of signals on each bus path and the beginning of a trans-mission, and vi. means responsive -to the carrier de-tect means for selecting only one of the paths for receive signal processing responsive to the presence of signals -thereon at the beginning of a transmission.
According to another aspect the invention provides in a network for providing communications between multiple computer nodes, and wherein all communications take place via virtual circuits created between pairs of ports, a high reliability and high availability bus structure Eor interconnecting said ports, comprising: A. the bus including at least a first bus path and a second bus path said bus paths being independent of each other;
and B. at each port i. a path status table maintained by the port and containing, for each other port in the network, an i.ndi-cation of virtual circuit state between itself and said other port and an indication of the state of each bus path, and ii.
means for selecting a bus path for a transmission to another port, responsive to the path states shown in the path s-tatus table, whereby virtual circuit state is undisturbed by failure of a bus path if the status of at least one path is good after the failure, so tha-t upon occurrence of such a failure, the means for selecting a bus path chooses a new path and communications continue without -the hosts having to know about or take ac-tion regarding -the failure and the path swi-tchover.
The invention will now be described in greater detail with reference to the accompanying drawings, in which:
-7b- ~ ~r~
Figure 1 is a block diagram of a bus interface according to the inven-tion, configured to utilize a pair of bus paths;
and Figure 2 is a flow chart of the method of selec-ting a bus path for a transmission, in accordance with -this invention.
Single pa-th interfaces also may be connected -to the network, but are not encouraged. All single path ports must be connected to a predesignated one of -the paths, to insure tha-t all nodes in the network may communicate. The danger that arises from the use of too many sing]e-path ports is that path loads (i.e., usage) becomes unqueally distributed to an extent that degrades both performance and reliability.
If a sufficient portion of each port is duplicated phys-ically~ it may be possible to transmit packets on both pa-ths simul-taneously. Due to interdependent retransmissions, the ser~uence of packet arrivals could be different than the sequence of their deli-very to the originating port. To preserve packet sequentiality on a node-to-node basis, which is requiredl -the transmission of a packe-t to a remote port must be completed in its entirety before another packet for the same destination is delivered to -the data link. The receiving port must process the received packets in the order of their real time arrival.
The path selection mode for packet transmission is spec-ified by the value of the Path Select (PS) field of the command.
For example, PS=0 may indicate -the Automatic mode, PS=l may indi-cate the Select mode for path 0, PS=2 may indicate the Select mode for path 1, and PS-3 may be reserved. The pa-th status table is par-t of the Virtual Circuit Descriptor Table maintained by each port and consists of two bi-ts for each interface pair; there is one bit for each of the two paths to indicate "good" or "bad" status for that path. ~lote that the path status table may indicate -that the same path is good for one destination port and bad for another, since status is kept on a port-pair basis. For further discussion and ex-planation of the PS field and the Virtual Circuit Descriptor Table, see aforementioned Canadian patent application serial no. 427,593.
When a co~lmand specifies Automatic mode, the path for each packet of the command is selected individually from the paths marked good in the path status table. If only one of the paths concurrently is marked good, it is used; if both are marked good, oneis selected at random.
In Select mode, the table is ignored for the particular transmission but is updated based on the results ~f the transmission. The status of a path may be changed from bad to good or good to bad by the outcome of the transmission.
At the time of initialization, all pa~h status table entries indicate ~hat all paths are good.
For any interface in ~he network capable of operating only on a single path, only one bit of the path status table is kept, for the same preselected one of the paths in all cases (so that all parts have at least one path in common). In Automatic mode, that path is used, unless the path status table bit indicates that the path is bad; in the latter case, the command fails since communication is impossible.
Attention is now directed to Fig. 1, where a block diagram of relevant por~ions of a bus interface (i.e., a port) 1 is shown as it would be configured to utilize two bus paths ~2A and 2B), according to ~he present invention. Each path, such as path 2A, is, in turn, formed from a transmit line 3A and a receive line 4A tied together by a coupler 5A. The port comprises a port processor 10, transmit and receive packet buffers 20A and 20B, and link 30. Link 309 in turn, is divided into three main subassemblies - a transmitter 40, a receiver 50 and an arbitration circuit S0. The latter may physically be implemented in the port proce~sor, but is shown as functionally isolated.
Taking first the transmit operation, port processor 10 supplies a path selection ~PS) signal on conductor 62 ~o a path select flip-flop 64, the latter being clocked by a transmit clock (XMIT CLK) signal. The output of path select flip-flop 64 controls a pair of driver inhibit circuits 66A and 66B, one each for a first bus ~ rj ~7 rj path (i.e., bus path A) and for a second bus path (i.e., bus path B). The output of the driver inhibit circuits controls the enabling of line drivers 6BA and 68B, respectively. When a path is deselected, its line driver is disabled. Driver inhibit rircuits 66A respond also to an ARBITRATION WON signal supplied on conductor 72 by arbitration circuit 60. In order for a line driver to be enabled, the associated bus pa~h must be selected by the PS signal and the port mus~ have won arbitration nf (i.e., access to) the bus.
Information packets to be transmitted are supplied by transmit packet buffers 20A bit-serially to an encoder 74. The encoder combines the information with a ~ransmit clock, such as ~y the so-called Manchester encoding technique. ~ncoded transmit data is supplied by encoder 74 to line drivers 68A and 68B, for transmission by the enabled driver over the selected bus path.
The PS signal is ~enerated by means fo a path selection algorithm 12 running in port processor 1OD The path selection algorithm evaluates the PX field of the transmit command and chooses a path based on that field, a random number generator and the path status entries of path status ~able 110, which is also maintained in the port processor 10. Fig. 2 provides a more complete understanding of the path selection algorithm.
Turning now to the receiver, signals on bus paths A
and B are detec~ed and amplified by an appropriate one of line receivers B2A and 82B, respectively. Each of the line receivers feeds a multiplexer ~mux) 84 and a carrier detector, B6A and 86B, respectively~ The carrier aetectors feed a carrier switch 88 which, in turn, controls mux 84. More specificlly, carrier switch 8~
causes mux 84 to select the input corresponding to the appropriate bus path on which a transaction is occurrin~
3'~
(i.e., on which a transmit signal - a carrier - is detected). Path switching is done at the beginning of a transmission only, not in the middle. The carriex switch also controls arbitra-tion circuit 60; the latter is described in greater detail in the aforementioned Canadian application serial no. 427,594.
The output of mux 84 is the encoded data transmission re-ceived over the selected bus path. A decoder 92, such as described in aforemen-tioned Canadian application serial no. 427,591, separates out the information signal from the clock and supplies these to -the receive packe-t buffers 20B, for serial-to-parallel conversion of the information bytes.
The outputsfrom decoder 92 also are supplied to an ack-nowledgmen-t decoder 94. The acknowlegment decodcr evaluates the acknowledgment signals received from a destination port and supplies the results to a transmit status register 96. In turn, the trans-mit status register notifies the port processor 10 whether the transmission was successful or unsuccessful and, if the latter, whether a path was found bad, If a path was found bad, the entry of the path s-tatus table is updated to reflect that situation.
The operation of path selection is shown graphically in the flow chart of Figure 2. Upon receipt of a transmi-t command, step 102, the process begins. First, the port processor chooses the path-selection mode (step 10~ e., Select mode (shown on line 106) or Automatic mode (shown on line 108).
Assuming Select mode was chosen, the selected path is obtained next, step 112. The port next arbitrates for bus access, step 118, and transmits after winning 12 ~ ~S~'7~
arbitration, step 120. At the conclusion of a transmission (i.e., retries are exhausted or the .
transmission succeeded, a determination is made whether the transmission was successful, step 121A. If so, the algorithm exits the routinet step 122. If the transmission failed, the path status table is updated to indicate the path is bad, step 121B, and the routine exits, steps 121C and 121D. Note that step 120 retries, if needed. If Automatic mode is selected, the path is chosen as follows (~tep 124): initially, the path selection is made randomlyt on an equal probability basis, sn subsequent a~empts ~o select a path due to prior selection of a bad path, the prior bad selection(s) is (are) excluded and a random pick is made from among remaining paths. If all possiblities are exhausted without finding ~ good path, ~he procedure exits with an appropriate failure indication, step 126. Following each tentative path selection, the status of the chosen path is obtained from the path status table, step 128, and ~ested to see whether it is good or bad, step 130. If bad, an attempt is made ~o find an alternate path (steps 134, 136 and 138); if good, the PS signal i5 generated, to switch the link to the selected path, (step 132) and arbitration is begun, step 118.
From step 121C or step 130~ alternate path selection starts by selecting another path, step 134. The status of this alternate path is obtained from the path status table 110, step 136, and checked to see whether the path is goo~, step 138. If the alternate path is good, control branches to step 132; otherwise, the rou~ine éxits with an indication that all paths are bad, step 126.
Thus, there is no host involvement necessary in making a path selection or switchoYer, both pa~hs are 13 ~q ~
exercised frequently, and minimal hard~are is needed to add the second bus path. It is a simple matter to extend these concepts to more than two paths, of course. The main change would be to add a decision block in Fig. 2 between the "No~ output of step 138 and the exit, step 126, to loop back to step 134 if all paths have not been tried. The path status table would also have to be enlarged.
The foregoing description is limited to a single specific embodiment of this inventionr but it will be apparent that this invention can be practiced in data processing systems having diverse basic construction or in systems using different internal circuitry or design while never~heless achieving some or all of the foregoing objects and advantages of this invention. Therefore, it is the object of the appended claims ~o cover all such variations, modifications and obvious improvement as come within the true spirit and scope of this invention.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A high reliability and high availability bus structure for providing communications between the nodes of a computer network, wherein each node includes a host device and at least one port, the port being an interface for connecting the host device to the bus, the bus structure comprising:
A. the bus including at least a first bus path and a second bus path, said bus paths being independent of each other; and B. for each port i. transmitting means for transmitting signals onto each of the bus paths, ii. receiving means for receiving signals from each of the bus paths, iii. path selecting means (e.g., port processor responsive to a signal from the host device which indicates that the host device desires to transmit, for selecting one of said bus paths for use for transmission, iv. means coupled to the path selecting means for enabling the transmitting means to transmit only on the selected path, v. carrier detect means coupled to the receiving means for detecting the presence or absence of signals on each bus path and the beginning of a transmission, and vi. means responsive to the carrier detect means for selecting only one of the paths for receive signal processing responsive to the presence of signals thereon at the beginning of a transmission.
A. the bus including at least a first bus path and a second bus path, said bus paths being independent of each other; and B. for each port i. transmitting means for transmitting signals onto each of the bus paths, ii. receiving means for receiving signals from each of the bus paths, iii. path selecting means (e.g., port processor responsive to a signal from the host device which indicates that the host device desires to transmit, for selecting one of said bus paths for use for transmission, iv. means coupled to the path selecting means for enabling the transmitting means to transmit only on the selected path, v. carrier detect means coupled to the receiving means for detecting the presence or absence of signals on each bus path and the beginning of a transmission, and vi. means responsive to the carrier detect means for selecting only one of the paths for receive signal processing responsive to the presence of signals thereon at the beginning of a transmission.
2. The apparatus of claim 1 wherein the path selecting means is adapted to select a bus path at random, on an equal probability basis, at least a substantial part of the time, whereby all bus paths are exercised frequently, as a result of which, failure of any bus path will be detected promptly and most probably prior to occurrence of multiple path failures and both paths may be used simultaneously by different pairs of ports, for increased infor-mation throughput relative to a single bus path.
3. The apparatus of claim 1 wherein the means responsive to the carrier detect means includes (a) a multiplexer for receiving as inputs the received signals detected by the receiving means, and for providing as its output one of those signals at a time, responsive to a multiplexer control signal, for subsequent processing by the port; and (b) carrier switch means for providing the multiplexer control signal, the provision of such signal being responsive to the carrier detect means and the path select means, whereby a minimum of redundant parts are employed for processing received signals from multiple buses.
4. The apparatus of claim 3 wherein the multiplexer control signal is provided to cause the multiplexer to select a bus path at the beginning of a transmission only.
5. In a network for providing communications between multiple computer nodes, and wherein all communications take place via virtual circuits created between pairs of ports, a high reliability and high availability bus structure for interconnecting said ports, comprising:
A. the bus including at least a first bus path and a second bus path said bus paths being independent of each other; and B. at each port i. a path status table maintained by the port and containing, for each other port in the network, an indication of virtual circuit state between itself and said other port and an indication of the state of each bus path, and ii. means for selecting a bus path for a transmission to another port, responsive to the path states shown in the path status table, whereby virtual circuit state is undisturbed by failure of a bus path if the status of at least one path is good after the failure, so that upon occurrence of such a failure, the means for selecting a bus path chooses a new path and communications continue without the hosts having to know about or take action regarding the failure and the path switchover.
A. the bus including at least a first bus path and a second bus path said bus paths being independent of each other; and B. at each port i. a path status table maintained by the port and containing, for each other port in the network, an indication of virtual circuit state between itself and said other port and an indication of the state of each bus path, and ii. means for selecting a bus path for a transmission to another port, responsive to the path states shown in the path status table, whereby virtual circuit state is undisturbed by failure of a bus path if the status of at least one path is good after the failure, so that upon occurrence of such a failure, the means for selecting a bus path chooses a new path and communications continue without the hosts having to know about or take action regarding the failure and the path switchover.
6. The bus structure of claim 5 further including means for altering the path state, indications of the path status table responsive to the results of transmissions.
7. Ths bus structure of claim 5 or claim 6 further including means for altering the virtual circuit indications in the path status table responsive to a transmission failing because all paths are bad and unusable.
8. Ths bus structure of claim 5 or claim 6 further including means for altering the virtual circuit indications in the path status table responsive to a transmission failing because all paths are bad and unusable and wherein the means for selecting a bus path is adapted to select a bus path randomly from among the available bus paths whose status is shown as good in the path status table.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/376,068 US4490785A (en) | 1982-05-07 | 1982-05-07 | Dual path bus structure for computer interconnection |
| US376,068 | 1989-07-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1185375A true CA1185375A (en) | 1985-04-09 |
Family
ID=23483574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000427599A Expired CA1185375A (en) | 1982-05-07 | 1983-05-06 | Dual path bus structure for computer interconnection |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4490785A (en) |
| EP (2) | EP0094179B1 (en) |
| JP (1) | JPS5941031A (en) |
| CA (1) | CA1185375A (en) |
| DE (2) | DE3378433D1 (en) |
Families Citing this family (72)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4926315A (en) * | 1981-10-01 | 1990-05-15 | Stratus Computer, Inc. | Digital data processor with fault tolerant peripheral bus communications |
| US6414368B1 (en) | 1982-11-26 | 2002-07-02 | Stmicroelectronics Limited | Microcomputer with high density RAM on single chip |
| US4680698A (en) * | 1982-11-26 | 1987-07-14 | Inmos Limited | High density ROM in separate isolation well on single with chip |
| US5243698A (en) * | 1982-11-26 | 1993-09-07 | Inmos Limited | Microcomputer |
| US4787033A (en) * | 1983-09-22 | 1988-11-22 | Digital Equipment Corporation | Arbitration mechanism for assigning control of a communications path in a digital computer system |
| GB8329510D0 (en) * | 1983-11-04 | 1983-12-07 | Inmos Ltd | Computer apparatus |
| US4695952A (en) * | 1984-07-30 | 1987-09-22 | United Technologies Corporation | Dual redundant bus interface circuit architecture |
| JPH0680492B2 (en) * | 1984-09-29 | 1994-10-12 | 株式会社日立製作所 | Error recovery method |
| GB2165970A (en) * | 1984-10-19 | 1986-04-23 | Burr Brown Corp | Method and apparatus for an expandable remote interface unit |
| US4870704A (en) * | 1984-10-31 | 1989-09-26 | Flexible Computer Corporation | Multicomputer digital processing system |
| EP0189192A1 (en) * | 1985-01-24 | 1986-07-30 | BURROUGHS CORPORATION (a Delaware corporation) | Method of operating a two-wire local area network such that marginal components in the secondary loop are located |
| US4967344A (en) * | 1985-03-26 | 1990-10-30 | Codex Corporation | Interconnection network for multiple processors |
| JPS6226561A (en) * | 1985-07-26 | 1987-02-04 | Toshiba Corp | Personal computer |
| US4837739A (en) * | 1986-07-25 | 1989-06-06 | Ford Aerospace & Communications Corporation | Telemetry data processor |
| CN1008018B (en) * | 1986-09-27 | 1990-05-16 | 徐肇昌 | Cecomputer and its method of cooperation |
| AU596535B2 (en) * | 1987-05-01 | 1990-05-03 | Digital Equipment Corporation | Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor computer system |
| US4937733A (en) * | 1987-05-01 | 1990-06-26 | Digital Equipment Corporation | Method and apparatus for assuring adequate access to system resources by processors in a multiprocessor computer system |
| US4949239A (en) * | 1987-05-01 | 1990-08-14 | Digital Equipment Corporation | System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system |
| US4858116A (en) * | 1987-05-01 | 1989-08-15 | Digital Equipment Corporation | Method and apparatus for managing multiple lock indicators in a multiprocessor computer system |
| US4941083A (en) * | 1987-05-01 | 1990-07-10 | Digital Equipment Corporation | Method and apparatus for initiating interlock read transactions on a multiprocessor computer system |
| US5341510A (en) * | 1987-05-01 | 1994-08-23 | Digital Equipment Corporation | Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor |
| DE3715586C1 (en) * | 1987-05-09 | 1988-09-22 | Gewerkschaft Eisenhuette Westfalia Gmbh, 4670 Luenen, De | |
| US4897833A (en) * | 1987-10-16 | 1990-01-30 | Digital Equipment Corporation | Hierarchical arbitration system |
| US4887076A (en) * | 1987-10-16 | 1989-12-12 | Digital Equipment Corporation | Computer interconnect coupler for clusters of data processing devices |
| US5168572A (en) * | 1989-03-10 | 1992-12-01 | The Boeing Company | System for dynamic selection of globally-determined optimal data path |
| CA2011935A1 (en) * | 1989-04-07 | 1990-10-07 | Desiree A. Awiszio | Dual-path computer interconnect system with four-ported packet memory control |
| US5187780A (en) * | 1989-04-07 | 1993-02-16 | Digital Equipment Corporation | Dual-path computer interconnect system with zone manager for packet memory |
| US5167019A (en) | 1989-06-23 | 1992-11-24 | Digital Equipment Corporation | Apparatus and method for interconnecting a plurality of devices to a single node in a node-limited serial data bus computer network |
| JP2504206B2 (en) * | 1989-07-27 | 1996-06-05 | 三菱電機株式会社 | Bus controller |
| US5193151A (en) | 1989-08-30 | 1993-03-09 | Digital Equipment Corporation | Delay-based congestion avoidance in computer networks |
| US5053947A (en) * | 1989-09-29 | 1991-10-01 | Allegro Microsystems, Inc. | Extended multistation bus system and method |
| US5315708A (en) * | 1990-02-28 | 1994-05-24 | Micro Technology, Inc. | Method and apparatus for transferring data through a staging memory |
| US5388243A (en) * | 1990-03-09 | 1995-02-07 | Mti Technology Corporation | Multi-sort mass storage device announcing its active paths without deactivating its ports in a network architecture |
| US5461723A (en) * | 1990-04-05 | 1995-10-24 | Mit Technology Corp. | Dual channel data block transfer bus |
| JP2753123B2 (en) * | 1990-08-28 | 1998-05-18 | 富士通株式会社 | Control mode selectable communication controller |
| JPH0756644B2 (en) * | 1990-08-31 | 1995-06-14 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Status change notification device and method |
| US5287464A (en) * | 1990-10-24 | 1994-02-15 | Zilog, Inc. | Semiconductor multi-device system with logic means for controlling the operational mode of a set of input/output data bus drivers |
| JP3206006B2 (en) * | 1991-01-25 | 2001-09-04 | 株式会社日立製作所 | Duplex bus control method and device |
| GB2268602A (en) * | 1992-06-25 | 1994-01-12 | Mitac Ltd | Enhancing security of data transfer |
| US5898894A (en) * | 1992-09-29 | 1999-04-27 | Intel Corporation | CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a predetermined time interval |
| US6487626B2 (en) | 1992-09-29 | 2002-11-26 | Intel Corporaiton | Method and apparatus of bus interface for a processor |
| US5809533A (en) * | 1993-02-18 | 1998-09-15 | Unisys Corporation | Dual bus system with multiple processors having data coherency maintenance |
| US5386424A (en) * | 1993-03-31 | 1995-01-31 | Honeywell, Inc. | Apparatus and method for transmitting information between dual redundant components utilizing four signal paths |
| JP3264465B2 (en) * | 1993-06-30 | 2002-03-11 | 株式会社日立製作所 | Storage system |
| US5604487A (en) * | 1993-07-30 | 1997-02-18 | Lockheed Martin Tactical Systems, Inc. | Apparatus and method for user-selective data communication with verification |
| US5515423A (en) * | 1993-12-03 | 1996-05-07 | Canon Kabushiki Kaisha | Two-line telephone controller |
| US5835960A (en) * | 1994-01-07 | 1998-11-10 | Cirrus Logic, Inc. | Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus |
| US5613068A (en) * | 1994-06-17 | 1997-03-18 | International Business Machines Corporation | Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's |
| US5586271A (en) * | 1994-09-27 | 1996-12-17 | Macrolink Inc. | In-line SCSI bus circuit for providing isolation and bi-directional communication between two portions of a SCSI bus |
| KR100197407B1 (en) * | 1995-12-28 | 1999-06-15 | 유기범 | Communication bus architecture between process in the full electronic switching system |
| US5862408A (en) * | 1996-05-13 | 1999-01-19 | Advanced Micro Devices, Inc. | Microprocessor system having multiplexor disposed in first and second read paths between memory CPU and DMA for selecting data from either read path |
| WO1998059464A1 (en) * | 1997-06-20 | 1998-12-30 | Abb Patent Gmbh | Redundant serial bus and method for the operation thereof |
| US6434637B1 (en) * | 1998-12-31 | 2002-08-13 | Emc Corporation | Method and apparatus for balancing workloads among paths in a multi-path computer system based on the state of previous I/O operations |
| US6701432B1 (en) * | 1999-04-01 | 2004-03-02 | Netscreen Technologies, Inc. | Firewall including local bus |
| US6598106B1 (en) | 1999-12-23 | 2003-07-22 | Lsi Logic Corporation | Dual-port SCSI sub-system with fail-over capabilities |
| US6675253B1 (en) * | 2000-04-04 | 2004-01-06 | Hewlett-Packard Development Company, L.P. | Dynamic routing of data across multiple data paths from a source controller to a destination controller |
| US6601128B1 (en) | 2000-05-02 | 2003-07-29 | International Business Machines Corporation | Method, system, program, and data structure for selecting a preferred path to a storage device |
| US7228538B1 (en) | 2000-05-02 | 2007-06-05 | International Business Machines Corporation | Method, system, and program for updating firmware to a storage system comprised of multiple controllers |
| US6393535B1 (en) | 2000-05-02 | 2002-05-21 | International Business Machines Corporation | Method, system, and program for modifying preferred path assignments to a storage device |
| US6874039B2 (en) * | 2000-09-08 | 2005-03-29 | Intel Corporation | Method and apparatus for distributed direct memory access for systems on chip |
| US7318116B2 (en) | 2002-11-08 | 2008-01-08 | International Business Machines Corporation | Control path failover in an automated data storage library |
| JP2005221731A (en) * | 2004-02-05 | 2005-08-18 | Konica Minolta Photo Imaging Inc | Imaging device |
| US7680904B2 (en) * | 2004-08-06 | 2010-03-16 | Logic Controls, Inc. | Diagnostic method and apparatus for detecting and locating computer network discontinuities |
| JP2006260140A (en) * | 2005-03-17 | 2006-09-28 | Fujitsu Ltd | Data processing system |
| US8018844B2 (en) | 2005-08-24 | 2011-09-13 | International Business Machines Corporation | Reliable message transfer over an unreliable network |
| US7602705B1 (en) * | 2005-10-12 | 2009-10-13 | Garrettcom, Inc. | Dual-homing layer 2 switch |
| US8358658B2 (en) | 2010-03-19 | 2013-01-22 | International Business Machines Corporation | Implementing ordered and reliable transfer of packets while spraying packets over multiple links |
| US10313231B1 (en) * | 2016-02-08 | 2019-06-04 | Barefoot Networks, Inc. | Resilient hashing for forwarding packets |
| US10063407B1 (en) | 2016-02-08 | 2018-08-28 | Barefoot Networks, Inc. | Identifying and marking failed egress links in data plane |
| US10404619B1 (en) | 2017-03-05 | 2019-09-03 | Barefoot Networks, Inc. | Link aggregation group failover for multicast |
| US10237206B1 (en) | 2017-03-05 | 2019-03-19 | Barefoot Networks, Inc. | Equal cost multiple path group failover for multicast |
| US10565146B2 (en) * | 2018-01-02 | 2020-02-18 | Arm Limited | Interconnect and method of handling supplementary data in an interconnect |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5057347A (en) * | 1973-09-19 | 1975-05-19 | ||
| US4228496A (en) * | 1976-09-07 | 1980-10-14 | Tandem Computers Incorporated | Multiprocessor system |
| JPS5463634A (en) * | 1977-10-03 | 1979-05-22 | Nec Corp | Bus controller |
| US4195351A (en) * | 1978-01-27 | 1980-03-25 | International Business Machines Corporation | Loop configured data transmission system |
| JPS5513475A (en) * | 1978-07-14 | 1980-01-30 | Nec Corp | Bus selection system |
| JPS5552130A (en) * | 1978-10-11 | 1980-04-16 | Nec Corp | Information processing unit |
| US4245344A (en) * | 1979-04-02 | 1981-01-13 | Rockwell International Corporation | Processing system with dual buses |
| JPS5629731A (en) * | 1979-08-16 | 1981-03-25 | Nec Corp | Multiplex bus control system |
| JPS56114063A (en) * | 1980-02-14 | 1981-09-08 | Mitsubishi Electric Corp | Multiprocessor |
| JPS5816495B2 (en) * | 1980-04-11 | 1983-03-31 | パナフアコム株式会社 | Interface control method for multiple systems |
| US4412281A (en) * | 1980-07-11 | 1983-10-25 | Raytheon Company | Distributed signal processing system |
| JPS57124950A (en) * | 1981-01-27 | 1982-08-04 | Nippon Telegr & Teleph Corp <Ntt> | Duplicated bus connecting system |
-
1982
- 1982-05-07 US US06/376,068 patent/US4490785A/en not_active Expired - Lifetime
-
1983
- 1983-04-28 EP EP83302413A patent/EP0094179B1/en not_active Expired
- 1983-04-28 DE DE8383302413T patent/DE3378433D1/en not_active Expired
- 1983-04-28 DE DE8787112180T patent/DE3382592T2/en not_active Expired - Fee Related
- 1983-04-28 EP EP87112180A patent/EP0282628B1/en not_active Expired - Lifetime
- 1983-05-06 JP JP58079196A patent/JPS5941031A/en active Pending
- 1983-05-06 CA CA000427599A patent/CA1185375A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0282628A2 (en) | 1988-09-21 |
| EP0094179A3 (en) | 1985-01-30 |
| EP0282628A3 (en) | 1989-01-25 |
| JPS5941031A (en) | 1984-03-07 |
| DE3382592T2 (en) | 1993-03-11 |
| EP0094179A2 (en) | 1983-11-16 |
| EP0282628B1 (en) | 1992-07-15 |
| DE3382592D1 (en) | 1992-08-20 |
| EP0094179B1 (en) | 1988-11-09 |
| DE3378433D1 (en) | 1988-12-15 |
| US4490785A (en) | 1984-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1185375A (en) | Dual path bus structure for computer interconnection | |
| US4845722A (en) | Computer interconnect coupler employing crossbar switching | |
| US5084871A (en) | Flow control of messages in a local area network | |
| US4897833A (en) | Hierarchical arbitration system | |
| EP0632913B1 (en) | Fiber optic memory coupling system | |
| US7861110B2 (en) | System, method, and adapter for creating fault-tolerant communication busses from standard components | |
| US7844730B2 (en) | Computer system and method of communication between modules within computer system | |
| EP0391583B1 (en) | Dual-path computer interconnect system with four-ported packet memory control | |
| EP0198020B1 (en) | Data communication network | |
| US20020097672A1 (en) | Redundant control architecture for a network device | |
| JPH086854A (en) | Outboard-file-cache external processing complex | |
| US20020087763A1 (en) | Communication sytem with a communication bus | |
| US5758053A (en) | Fault handling and recovery for system having plural processors | |
| US5544330A (en) | Fault tolerant interconnect topology using multiple rings | |
| WO2003088594A1 (en) | A method for providing redundancy for channel adapter failure | |
| JPH09130408A (en) | Network interface device | |
| Scott | The SCX channel: A new, supercomputer-class system interconnect | |
| US7712004B1 (en) | Method of and system for error checking in a data storage system | |
| JPH11167529A (en) | Method for purging buffer of high-speed serial link and device for implementing same method | |
| GB2378621A (en) | Method and apparatus for improving performance of a loop network by selectively bypassing redundant ports and also bypassing faulty ports | |
| JPS6327741B2 (en) | ||
| KR940002145B1 (en) | Level 3-3 network unit operating apparatus for signal repeating system | |
| KR20000065980A (en) | Apparatus for duplicating and controlling cell bus in ATM system | |
| KR20000042931A (en) | Method for switching duplication according to superiority of errors in board | |
| JPS6213707B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEC | Expiry (correction) | ||
| MKEX | Expiry |