CA1177175A - Digital filter circuits - Google Patents

Abstract

RCA 76,854 ABSTRACT OF THE DISCLOSURE

A digital filter is provided which selectively employs straight binary arithmetic and offset two's complement arithmetic in an adder ladder to protect against signal overflows and underflows, as well as to minimize adder size. Signal overflows and underflows are prevented by performing subtraction and certain additions in offset two's complement notation, while adder sizes are minimized by performing certain other additions in binary notation.
In an alternate embodiment, positively weighted values are combined by binary addition in a first adder ladder, and negatively weighted values are combined by binary addition in a second, parallel adder ladder. At the outputs of the two ladders, the two sums are converted to offset two's complement notation, and the negatively weighted sum is subtracted from the positively weighted sum.

Description

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RCA 76,854 DIGITAL FILTER CIRCUITS
This invention relates to digital filter circuits and, in particular, to digital filter circuits which may be advantageously used to process digitized television signals without overflow and underflow errors.
In the digital processing of video signals in a television receiver, the detected analog video signal is converted to a digital video signal by an analog to digital converter. The A/D conver-ter will typically provide an output signal quan-tized over a dynamic range which is substantially equal to the dynamic range of the analog signal. For instance, if the analog signal has a dynamic range of one volt, an 8-bit A/D converter will quantize the signal into 256 possible levels with a resolution of approximately 4 millivolts. Thus a one bit increment is equal to four millivolts. By preserving the dynamic range of -the input signal in the conversion process, a maximum amount of picture resolution is I retained during digital signal processing.
¦ Once the video signal has been conver-ted to a digital form, it may be separated by comb filtering into its luminance (~) and chrominance (I and Q) components for further processing. Subsequent processing usually involves digital filtering, such as the low pass filtering ¦ conventionally used to separate vertical detail information ! from the combed chrominance signal. The vertical detail ¦ informa-tion may then be recombined with the combed luminance signal to develop a fully restored luminance information slgnal. In addition, an extra measure of detail information may be added back to the combed luminance signal to provide a "peaked" luminance signal.
The extra detail information may be controlled in amount b~ a viewer to produce a picture which is "crisper"
than an image with a nominal amount of detail information.
However, adding the extra component of detail information to the restored luminance signal may overload the digital processing circuits of ~he receiver. Even in the f ~'7î~ 75 i 1 -2- RCA 76,854 ' absence of intentional peaking, the pulse, or step response 3 of a digital filter may have overshoots which are represented by digital numbers outside the original quantization range. For example, assume that the video signal is at the 250th quantization level. If a peaking signal of a 7 quantization level magnitude or greater is added to signal, an 8-bit register containing the signal ' 10 will overfl~w, and "wrap around" to a level at the other extreme of the signal range. For example, the signal at the 1 250th level, increased by a 7 level signal will cause the '~ register to contain a signal at the first level of the signal range. That is, a signal with a value of 111110012 "' 15 (249lo), when added to a signal with a value of 1112 (710) will cause the register to assume a value of 2 (10)' the first level of the 256 level range. The over-flow manifests itself in the reproduced image as a sharp transition from black to white, or vice versa, and is visible as a disturbing spot on the television screen.
Underflow errors occur in a similar manner when a register jumps from a minimum level to a maximum level.
* Overflows may also occur in digital filters, in which delayed video signals are weighted and combined to produce a desired response characteristic. It is possible for intermediate signal combinations (within the ladder struc-ture used therein to combine signals) to cause the same type of overflows and underflows described `~ above. The registers in the filter can momentarily wrap ;i 30 around to the other extreme of the dynamic range of the signal.
This overflow or underflow of a register may be prevented, for example, by extending the register by another bit, so that the overflow described above causes ~' 35 the value 0111110012(2491o) to go to 12 (256lo).
This, however, adds additional cost and complexity to the system, since it is generally necessary to extend the length of subsequent registers also.
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,! Another technique for preventing overflows and underflows is to quantize the signal over a smaller dynamic range than the full range of the A/D converter. For s instance, the top thirty levels and bottom thirty levels of the A/D converter may normally be unused to allow subsequent over and underflows into these levels. This technique, however, limits the dynamic range of the signal at the outset of signal processing, making the technique undesirable.
Final~y, overload detectors may be used to detect the occurrence of overflow and underflow conditions.
These detectors usually respond to overflows and underflows by clamping the digital signal to a nominal level. The clamped signal will usually be at a level corresponding to a shade of gray, which is then visible as a spot in a ~; white or a black picture.
In accordance with the principles of the present invention apparatus is provided for performing binary ~ subtraction of a first and a second binary number by a '!. digital filter comprising:
first means for offset two's complementing said j first binary number;
second means for offset two's complementing and two's complementing said second binary number; and - third means for adding said offset two's ~j complemented first binary number and said offset two's complemented and two's complemented second binary number.
In accordance with a further embodiment, a digital filter is disclosed which provides protection against overflows and underflows by centering signals in ` the middle of the dynamic range of the filter. This is accomplished by converting the data words to offset-two's-- 35 complement form by inverting the most significant bit of the words being processed. The data words may be reconverted to straight binary form by reinverting the most significant bit of each data words. Data words in . , ~,, , .
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1 -4- RCA 76,854 ,7 offset-two's-complement form may be reduced in value ~for the purpose of weighting the words) by shifting the data ~- 5 bits through the least significant bit position and replicating the most significant bit in the vacant most significant bit position of a data register. When two offset-two's-complement data words in the filter are additively combined, carry-out bits may be ignored without causing underflows or overflows.

In another embodiment of the invention, data words in the digital filter are additively combined in a subcircuit such that the words are added in either binary or ~: 15 offset two's complement form, and words are subtractively combined in a subcircuit such that the words are subtracted in offset-two's-complement form.
In accordance with a further aspect of the present invention, positively weighted words are combined in a positive sense in a first ladder network of binary adders, and negatively weighted words are combined in a positive sense in a second ladder network of binary adders. The outputs of the two ladder networks are then converted to offset-two's-complement form and subtractively combined in a further adder by two's complementing the converted output of the second ladder network. This filter arrange-~
- ment advantageously requires only a single subtraction step at the outputs of the two ladder networks.
In the drawings:
FIGURE l illustrates in block diagram form a digital filter used to illustrate the principles of the present invention;
FIGURES 2 and 3 show waveforms illustrating the operation of the filter of FIGURE l using straight binary form data words;
FIGURES 4 and 5 show waveforms illustrating the operation of the filter of FIGURE l using data words in - which the most significant bit has been inverted (offset-~ two's-complement form);

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FIGURES 6 and 7 show sine waveforms illustrating ~;,j the problem of underflow and its prevention in accordance with the principles of the present invention;
~ FIGURE 8 illustrates in block diagram form a ;~ cosine finite impulse response (FIR) filter;
.;, FIGURE 9 illustrates in block diagram form a portion of the cosine FIR filter of FIGURE 8 constructed in accordance with the principles of the present invention;
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FIGURES lOa and lOb illustrate in schematic diagram form the cosine FIR filter portion shown in FIGURE 9;
FIGURE 11 illustrates in block diagram form an alternate arrangement of a portion of the cosine FIR filter of FIGURE 8 constructed in accordance with the principles of the present invention;
FIGURES 1,2a, 12b and 12c i~lustrate in schematic diagram form the cosine FIR filter portion shown in FIGURE
11; and FIGURE 13 illustrates the response characteristic of the cosine FIR filter of FIGURES 8-12.
Referring to FIGURE 1, a digital filter is ~- illustratively shown in block diagram form. Input signals are applied to an inpu-t terminal 10 and pass through a series of delay stages, of which stages 12, 14, 16 and 18 are shown. A tap at the output of stage 12 is coupled to an i input of a coefficient multiplier 22, which multiplies the 1 tapped signal by a coefficient Cl. The output of the delay stage 18 is coupled to an input of a second coefficient multiplier 24, which multiplies the applied signal by a coefficient C2. Outputs of the coefficient multipliers 22 and 24 are coupled to inputs of a combining circuit 20, ~- which subtractively combines the signals applied to it.
To illustrate the principles of the present - invention, it will be assumed that a triangular waveform , ,` ., .; ~ .
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;`l ''' 1 -6- RCA 76,854 signal 8 is digitized, applied to the input terminal 10 of the filter and processed. A delayed version of the ~ 5 signal, A, is produced at the output of stage 12 and is ;~. multiplied by the weighting coefficient Cl, which, in this example, has a value of one-half. A further delayed signal, ~ B, is produced at the output of stage 18 and is multiplied ii~.7 by the weighting coefficient C2, which has a value of one-10 quarter, in this example. The signal at the output of the combining circuit 20 will be of the form (A/2-B/4) with respect to delayed signals A and B at the outputs of stages 12 and 18.
Referring to FIGURE 2, digitized waveforms A
15 and B are shown. The exemplary waveforms of FIGURE 2 will be obtained in response to input waveform 8 of FIGURE 1 when the delay between the output of stage 12 and the ~i output of stage 18 is equal to one-half of the period of the 3 ~ input waveform. Thus, waveform A will be declining from its maximum value of 11112 to its minimum value of 2 at the same time that waveform B is increasing from 2 to 11112. In this example, the waveforms A and B are quantized over the full dynamic range of a system of four-bit words, and are incremented or decremented over the full range in sixteen clock cycles. It is noted that the quantizing system is a four bit straight binary worcl system, ranging from the minimum value of 2 to the maximum of 11112.
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Now referring ~oncurrently to FIGURE 3, waveforms depicting the operation of the filter of FIGURE 1 upon waveforms A and B of FIGURE 2 are illustratively shown.
Waveform A is multiplied by one-half by shifting the binary words representing the values of the levels of waveform A
by one bit poition to the right and replacing the most significant bit with a 0. In order to keep the values with-; in the confines of a four-bit system, bits shifted to the - right of the four-bit word range, which have fractional binary values, are discarded. This process results in the waveform A/2 shown in FIGURE 3, which starts at a level ~l :.

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1 -7- RCA 76,854 of 01112 (which is 11112 shifted to the right by one bit) and declines to a value f 2 at the fifteenth clock cycle. The roundoff error caused by discarding the out sAifted bits causes the A/2 signal to decline one incre-mental level every two clock cycles. That is, shifting 11112 and 11102 to therightby one bit results in a value of 01112 for both words.
The words of the s waveform are multiplied by one-quarter by shifting each data word to the right by two places in a similar manner. In this case, the resultant B/4 waveform changes levels only every four clock cycles f due to the roundoff error. That is, the words 2' 00012, 12 and 00112, when shifted right by two places, 15 result in a value of 2 in each instance.
Waveforms A/2 and B/4 are now subtractively combined to produce the desired results (A/2-s/4).
Subtraction of B/4 from A/2 is accomplished by two's complementing the B/4 data words and then adding the two's ` 20 complemented words to the corresponding A/2 words. Two's complementing a binary number ~either in straight binary or offset-two's-complement~ is the method of generating a binary number having the negative of the value of the - original ~inary number. In binary, as in decimal, sub-25 tracting a first number from a second number is the same 3 aritnmetic operation as adding the negative of the first number to the second number; both methods give the same result. Two's complementing is achieved by inverting all of the bits of a data word (also known as the one's comple-30 ment of a data word), then incrementing the inverted word by one. For example, the value of s/4 over the first four clock cycles is 2 To two's complement this value, the word is first inverted to produce 11112. This inverted word is then incremented by one to produce 100002. This two's 35 complemented word is seen to be a five-bit word where the fifth bit, the most significant bit l, is an overflow bit.
This value is then added to the A/2 values for the first four clock cycles, 01112 and 01102, to produce values of 101112 ;- ` and 101102 for (A/2-B/4) over clock cycle intervals 1-2 and 3-4, respectively.

: ' :' ^J~ t--, 1 -8- RCA 76,854 Calculated values of A/2, B/4, and the output of (A/2-B/4) are shown in Table l (below), as well as graphically .in FIGURE 3. The output values for (A/2-B/4) are plotted as waveform 32 (the thinsolid line), and are seen to descend from a value of 01112 during clock cycle ~ intervals l and 2 to a value of 2 in clock cycle '5~ intervals ll and 12. These values are arrived at by ignor-ing the most significant bit of the 5 bit output words of Table l, which are overflow bits beyond the desired four-~ bit range. At the start of clock cycle interval 13, the !~ output waveform 32 is seen to jump across almost the entire four-bit range as its experiences a transition from 0000 to lllO. The waveform then continues as before to a final value of llOl at clock cycle 16.
The discontinuity exhibited by the signal 32 at the start of clock cycle interval 13 is due to the i restriction of the dynamic range of the system to four bits, which ignores the overflow bit during clock cycles 1-12. When the dynamic range is increased to five bits, as shown above dashed line 30 in FIGURE 3, the output values can be plotted as shown by waveform 34 (the thick solid line), in which the overflow bit is considered. In this extended range system (A/2-B/4) EXT. is seen to be smoothly varying waveform from 101112 to 011012. This is the desired output waveform shape, but it can only be produced by doubling the dynamic range of the system by extending 3 the system to five bits. If the waveform 32 of FIGURE 3 were a filtered video signal, with one end of the four-bit range representative of white-going signals and the other extreme black-going, waveform 32 would produce a sharp undesired discontinuity from black to white, or vice versa.
The undesired discontinuity of waveform 32 of FIGURE 3 can be preven-ted without extending the dynamic range of a four-bit system by using a quantizing system for the filter of FIGURE 1 known as an offset two's comple-` ment system. The straight binary system shown along the `
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, ~7~.7~3 9 RCA 76,854 Clock Intervals 1-2 3~4 5-6 7-8 Binary A1111 1101lOll 1001 ; B0000 00100100 0110 +l +l +l +

i A/2 01110110 0101 0100 + B/4¦ 10000100001111 1111 Outpu~ 1011l1011010100 lO011 15 Clock Intervals9-10 11-12 13-14 15-16 Binary A0111 0101 0011 0001 ; B1000 1010 1100 1110 B/4 ¦TC11011101 1100 1100 +l +l +l +l ~ + B/4 ITC11101110 1101 1101 ~ 25 Output100~0110000 01110~ 0l101 c .

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1 -10- RCA 76,854 _BLE 2 Clock Intervals 1-2 3-4 5-6 7-8 Offset Two's A . 0111 0101 0011 0001 Complement A/2 0011 0010 0001 0000 B/4¦ 0001 0001 0000 0000 TC +l +l +l -~1 n __ _ _ -~ B/4 ¦TC 0010 0010 0001 0001 i Output 0101 0100 0010 0001 .
15 Clock Intervals 9-10 11-12 13-14 15-16 Offset Two's A 1111 1101 1011 1001 ` Complement A/2 1111 1110 1101 1100 B/4 ¦TC11111111 1110 1110 -~1 +1 +1 +1 .

+B/4 ¦TC1000010000 1111 1111 Output1111111110 11100 11011 ~, , .

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RCA 76,854 ordinate of FIGURE 2 iS converted to the offset two's complement system by inverting the most significant bit of 6 each binary word to arrive at the quantizing system shown ~ along the ordinate of FIGURE 4. The result of this conver-;~ sion is a quantizing system with a zero value at the mid-point of the original binary system and a symmetrical distribution of positive and negative values above and 10 below this midpoint. The value DoTC of an offset two~s complement data word is expressed as ~ N-2 Js OTC ( 2r T ) 2N-l T
r=0 15 where N is the number of bits in the word and the rth bit, Tr, is either 0 or l.
When the A and B waveforms of FIGURE 4 are i, quantized in the offset two's complement system and applied to the filter of FIGURE 1, the waveforms of FIGURE 5 are 20 produced. The A/2 waveform is produced by shifting the data words of the A waveform of FIGURE 4 one bit position to the right and replicating the most significant bit in the vacant most significant bit position (as described above). The s/4 waveform is produced by shifting the data ~, 25 words of the B waveform two positions to the right in a similar manner. For instance, when the B waveform word -/ 11002 of cloc~ cycle 5 of FIGURE 4 is shifted to the right by two bit positions, the two most significant bit positions which are vacated by the shift are filled in with ones, the most significant bit of the original 11002 data word. As a result of the shifting and most significant ~- bit replication, the B/4 data word in this case ls 11112.
;' This procedure is followed whether the most significant ~- bit is a zero or a one As in the case of the waveforms of FIGURE 3, the ~' .`:
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1 -12- RCA 76,854 A/2 waveform of FIGURE 5 changes levels every two clock cycles, and the B/4 waveform changes levels every four clock cycles due to the roundoff error.
The resultant output waveform of (A/2-B/4) is produced in FIGURE 5 using the same procedure observed in FIGURE 3. That is, the B/4 data words are two's complemented and added to the A/2 data words. Values for A/2, B/4, two's complemented B/4(B/4¦TC) and the output values of (A/2-B/4) are shown in Table 2 (above). The output values of the (A/2-B/4) function are seen to descend smoothly from a value of 01012 during the first two clock cycle intervals to a value of 10112 during the last two clock cycle intervals. The ~A/2-B/4) waveform of FIGURE 5 has the same form as waveform 34 of FIGURE
3, but it does not extend beyond the dynamic range limits of the four-bit offset two's complement system.
Table 2 and FIGURE 5 also show a further aspect of the offset two's complement filter:
overflow bits in the filter which appear to require an extension of the quantization system by one bit may be safely ignored. For example, the output words produced during clock cycle intervals 9-16 in Table 2 all are five-bit words. However, the most significant bits (overflowbits) of these words are ignored. The remaining ~our bits of each word are plotted in FIGURE 5 as valid four-bit words to produce the desired (A/2-B/4) waveform.
FIGURE 5 illustrates a significant feature of an offset two's complement filter. The three waveforms there shown are seen to be symmetrically located above and below the zero value midpoint of the quan-tizing , .

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-13- RCA 76,854 system for the symmetrical input signal condition. Thus, the signals on the average can vary over half the dynamic range of the quantizing system above and below the midpoint value before an overflow or underflow condition will occur.
The principle of this feature is illustrated in FIGURES 6 and 7. In these FIGURES, smoothed analog waveforms are shown for ease of illustration. In FIGURE 6, the waveform are quantized into the nine available binary levels shown along the ordinate of the drawing. The binary input signal AB is seen to vary over the full dynamic range of the binary quantizing system, from 12 to 2 A BB input signal is not shown, but has the same amplitude as the AB input signal, and is phaseshifted by 180 degrees. These two input signals, when weighted by coefficients of 1/2 and 1/4, will produce the illustrated waveforms AB/2 and BB/4. When these two signals are subtractively combined, a signal of the form (A/2-B/4) is produced. This signal is seen to underflow the quantizing system between points tl and t2, and t3 and t4.
During these intervals, the resultant signal wraps around ;'."!
the register and reappears at the top of the FIGURE as ~ shown at 40 and 42. This is due to the fact that the input signals AB and BB and the intermediate waveforms AB/2 ~ and BB/4 are all referenced to 000 at one end of the dynamic range of the quantizing system. Signals which :1 attempt to go below the 2 reference level will thus wrap around and re-enter the quantizing system from the other extreme of the dynamic range.
- Similar waveforms are shown in FIGURE 7, ~~ quantized in the offset two's complement system. The input signals AOTand BoT (not shown) again occupy the full dynamic range of the system and are l~0 degrees out of phase with respect to each other. The intermediate ..... .

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1 -14- RCA 76,854, waveforms AoT/2 and BoT/4 are seen to vary symmetrically about theO002 midpoint value. The resultant ~AoT/2 BoT~4) waveform also varies about theO002 midpoint but, unlike FIGURE 6, this resultant waveform does not extend beyond the dynamic range limits of the quantizing sys-tem. The resultant waveform thus exhibits no discontinuities, and all waveforms are shown to be referenced to the 2 midpoint value at points tl, t2, t3 and t4.
Referring to FIGURE 8, a linear phase digital cosine filter is shown in block diagram form. The filter includes eight parallel shift registers 50 which are all twenty-one stages long, with symmetrically weighted taps located about a center tap. The frequency response characteristic of the filter is a summation of cosine functions derived from the symmetrically weighted output taps, the signals of which are combined to represent the terms of a cosine series. The center taps at stages 11 of the shift registers provide a term in the series corresponding to a constant in the frequency domain which provides an amplitude offset for the response characteristic.
An eight-bit signal x(n) is applied to the inpu-ts of the shift registers 50, with respective bits bo-b7 applied to respec-tive ones of the parallel shift registers. The eight first stages 1 include output taps (E) coupled in parallel to the input of a weighting function circuit 61. (In FIGURE 8, a broad arrow represents a plurality of parallel signal pa-ths. )Similarly, stages 5 (C), 9(A),ll(K),13(B),17(D) and 21(F) are coupled to the inputs of weighting function circuits 62, 63, 52, 64, 65 and 66, respectively. Weighted signals at the outputs of weighting function circuits 63 and 64 are applied -to the inputs of an adder 70, the output of which is coupled to an input of an adder 56. The outputs of weighting function circui-ts 62 and 65 are coupled to inputs of an adder 72, the output of which is coupled to an input of an adder 58. The outpu-ts of weighting function circuits . 61 and 66 are coupled to inputs of an adder 74, the output -' 40 7 7 ~. 7 r3 1 -15- RC~ 76,85 of which is coupled to a second input of adder 58. The output of adder 58 is coupled to a second input of adder 56, the output of which is coupled to an input of adder 54.
The output of the center tap weighting function circuit 52 is coupled to a second inputof the adder 54.
A filtered output signal ls produced at the output of the final adder 54.
In operation, progressively delayed data words are tapped at respectively delayed stages, weighted, and applied to a ladder network of adders, which combines the tap-weighted signals. Taps located symmetrically with respect to the center stages 11 are equally weighted and applied to the same first adder in the ladder network. For instance, signals at stage locations 9 and 13, referred to as A and B, are both weighted by a factor of 5/16. The weighted signals (5/16)A and (5/16)B are both applied to adder 70, which produces a summed signal (5/16)(A+B). Similar weighting is applied to signals C, D, E, F, and X. All of the tap-weighted signals about the center tap 11 are eventually summed at the output of adder 56, which exhibits a normalized filter response characteristic dependent upon the tap locations and weights. This normalized response is then offset by the center :taP weight value in adder 54 to produce the desired output response characteristic.
It is possible to reduce the number of weighting function circuits 61-66 of FIGURE 8 because of the symmetrical nature of the tap spacing and the tap weight values. That is, since the two tapped signal paths connected to each of adders 70, 72 and 74 in FIGURE 8 are weighted by the same value (e.g., 5/16, -7/64 or 3/64) respectively, the tapped signals may be combined and the su~m weighted. l~or example, tapped signals ~ and B may be applied directly to adder 70 as shown in FIGURE 9, which produces the sum signal (A+B). This sum signal is then weighted to produce the desired signal function 5/16(A+B), the same as obtained in the arrangement of FIGURE 8.

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1 -16- R~A 76,35 Similarly, signals C and D, and signals E and F, are combined in FIGURE 9 by adders 72 and 74, and the sum signals (C+D) and (E+F) are then weighted.
In the FIR filter of FIGURE 8, the weighting function values are all seen to be multiples of negative powers of two. This permits the weighting function circuits to he constructed as shift-and-add mul-tipliers, in which the sum signals are first shifted to divide them by the appropriate powers of two, then added or subtracted to form the desired weighting function. For instance, the 5/16 value of weighting function circuits 63 and 64 may be produced by dividing the (A+B) signal by four and by sixteen, then adding the shifted signals, which produces (l/4)(A+B)+(1/16)(A+B)=(1/4+1/16)(A+B), which is equal to (5/16)(A+B), the desired result.
The ladder network of FIGURE 8 is shown in bloc~
diagram form in the embodiment of FIGURE 9, using shift-and-add multipliers. The A and B signals are applied toadder 70 to produce the sum signal (A+B). The (A+B) signal is applied to a divide-by-four circuit 81 and a divide-by-sixteen circuit 82. The outputs of dividers 81 and 82 are coupled to inputs of an adder 83, ~hich produces an output signal of the form (5/16)(A+B). The output of adder 83 is coupled to an input of adder 56 by way of an offset two's complement (OTC) transform circuit 89.
The C and D signals are summed in adder 72, the output of which is coupled to the input of a circuit 80, which transforms the (C+D) signal into offset two's complement notation. The output of the OTC transform circuit 80 is coupled to the inputs of a divide-by-eight circuit 84 and a divide-by-sixty-four circuit 85. The output of the divider 85 is coupled to the input of a one's complement circuit 86. The outputs of the divider 84 and -the one's complement circuit 86 are coupled to the inputs of an adder 87. The outpu-t of the adder 87 is coupled to the input of a second one's complement circuit 88, the output of which is coupled to an input of an adder 58.
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,~ t75 1 -17- RCA 76,854 The E and F signals are summed hy adder 74, and the sum signal is applied to the input of a third offset two's complement circuit 90. The output of circuit 90 is coupled to the inputs of a divide-by sixteen circuit 91 and a divide-by-sixty-four circuit 92. The output of the divide-by-sixty-four circuit is coupled to the input of a one's complement circuit 93. The outputs of divider 91 and one's complement circuit 93 are coupled to inputs of an adder 94. The output of adder 94 is coupled to the second input of adder 58.
The output of adder 58 is coupled to a second input of adder 56, the output of which is coupled to an input of aader 54 by way of a circuit 96, which converts the OTC output of adder 56 to binary notation; The K signal is coupled to a second input of adder 54 by way of a divide-by-two circuit 52. An output signal y(n) is produced at the output of adder 54.
The weighted function (-7/64) (C+D) is developed from the (C+D) sum signal in a two step procedure. First, (1/8) (C+D) is produced by divider 84 and is added to (-1/64) (C+D) in adder 87. The latter term is produced by dividing the (C+D) sum signal by sixty-four in divider 85, then two's complementing the result by the one's complement circuit 86 and the carry-in bit of adder 87. If a one is input to the carry-in bit of an adder then the sum of the augend and addend are further incremented by one. The combination of a one's complement operation and a further increment by one is a two's complement operation as described above. As indicated in FIGURE 9, the carry-in input (CI) of adder 87 is equal to 1. (It is noted that unless specifically indicated otherwise, the carry-in input equals 0 for all adders.) The output signal of adder 87 is then in a form of (7/64) (C+D). This output signal is then subtracted from the output of adder 94 in adder 58, using one's complement circuit 88 and the carry-in bit of adder 58, causing the output signal of adder 58 to include '7~'-o~

1 -18- RCA 76,854 a term of the form (-7/64) (C+D).
Similarly, the function (3/64) (E+F) is produced by combining (1/16) (E+F) (which is produced by divider 91) with (-1/64) (E+F) (which is produced by divider 92, one's complement circuit 93, and the carry-in bit of adder 94) in adder 94. This signal is then applied to adder 58.
The adder 58 will produce an output signal which can be either positive or negative, depending upon the relative magnitudes of the (C+D) and (E+F) sums. For instance, if (C-~D) iS equal to (E+F), then the output of adder 58 will be:
(-7/64) (C+D) + (3/64) (E+F) = (-4/64) (C+D) =
(-4/64) (E+F) since (-7/64) (C+D) has a greater magnitude negative value than the positive value of (3/64) (E+F).
As a second example, suppose that (E+F) is three times the magnitude of (C+D). The output of adder 58 is then equal to (-7/64) (C+D)+3 (3/64) (C+D) = (2/64) (C+D) which is a positive value.
Since the sign of the output signal of adder 58 is dependent upon the magnitude of the input data and - therefore indeterminate, adder 58 iS operated using offset two's complement numbers to guard against underflows and resultant number systeI~ wrap-arounds, which would occur with binary numbers. The offset two's complement transform circuits 80 and 90 are therefore coupled ahead to adder 58 in the two signal paths leading to that adder. The transform circuits 80 and 90 are shown coupled ahead of the adders 87 and 94, which also perform subtraction, but are not needed for these adders because their output signal signs are determinate. This is because both signal paths to the adders originate from a common data word, and a lesser magnitude value is always subtracted from a greater magnitude value. Adder 87, for instance, is always performing the function (1/8) (C+D) - (1/64) ( C+D) in which the minuend (1/8) (C+D) is always greater than the Ai,;

, . _ .. . ... . . , _ .. . . . . . .... .... . . . . . . . . ... .

~ '7:~7~

1 -19- RCA 76,854 subtrahend (1/64) (C+D). Likewise, adder 94 is always producing a term equal to (1/16) (E+F) - (1/64) (E+F) in which the minuend ( 1/16) (E+F) iS always greater than the subtrahend (1/64) (E+F). Offset two's cornplementing is therefore unnecessary for these adders, but may be used if desired to put the data words in the form required for correct operation of adder 58.
It is not desirable to use offset two's complement numbers throughout the filter of FIGURE 9, however. For instance, adders 70, 72 and 74 each add two eight bit numbers. The resultant sum must be a nine bit number, to prevent overflows when the two summed words are at or near their maximum values. This is true whether the words are offset two's complement words or binary words. When the words are in offset two's complement form, the adder input words must be expanded by most significant bit (MSB) rep-lication to nine bits, since offset two's complement addition requires the lengths of the input words to be equal to or greater than the length of the output word. This would require adders 70, 72 and 74 to be capable of accept-ing nine bit input words. Adders, however, are convention-ally available in multiples of four bits. A typical adder, such as those used in this example, will accept two eight bit input words and produce nine output bits, including a carry out bit as the MSB. Thus, adders 70,72 and 74 may be conventional eight bit adders when operated with straight binary numbers~ and will add two eight bit input words to 30 produce a nine bit output word. The ninth bit is derived from the conventionally available "carry out" output of each adder. The use oE straight binary data words instead of offset two's complement words therefore results in a hardware savings in adders 70, 72 and 74.
A similar hardware savings may be obtained by operating adder 54 with straight binary numbers instead of offset two's complement numbers. The output of adder 56 is therefore converted back to binary notation by binary converter 96, and adder 56 therefore will add two binary . ~ .

'' ' . .

1 -20- RCA 76,854 words to produce an eight bit output word. When this eight bit output word is added to the seven bit K/2 word in adder 54, a nine bit output word is needed to prevent over-flows of this adder. The use of binary data in adder 54 therefore alleviates the need to expand adder 54 to accept nine bit input words, which would be necessary if adder 54 were operated with offset two's complement words.
Adder 56 in this embodiment must be operated using offset two's complement numbers to prevent overflows ! of its output to nine bits. This is because the output J of adder 58 is in OTC form, with data words centered about the middle of a seven bit word system. If the output of adder 58 were converted to a binary form, the minimum value 16 of any output word will be above the zero reference level of the binary numbering system, which causes the words to have larger than necessary absolute magnitudes. When added to l the binary output of adder 83, the output word is subject ;~; to overflowing into a nine bit numbering system, which would 20 cause wrap-arounds in an eight-bit system. These overflows are prevented by converting the output of adder 83 to offset two's complement form, ensuring that the output of adder 56 will not exceed words of eight-bit length.
s, The arrangement of FIGURE 9 is shown schematically in FIGURES 10a and 10b. In FIGURE 10a, the eig~t bit C and D data words are applied to adder 72, which produces a nine ;- bit sum word (C+D) at outputs ~0~~co' where ~co is the carry out bit. The sum word is divided by eight by applying ;-~ only the six most significant bits 3-~Co to the least sign-30 ificant inputs a0-a5 of adder 87, The MSB ~co is inverted by inverter 80 to convert the word to offset two's complement notation.
The (C+D) sum word is divided by sixty-four by applying only the three most significant bits ~6-~co to the ; 35 least significant bit inputs bo-b2 of the adder 87. The bo-b2 input word to adder 87 is converted to offset two's complement form and is one's complemented for subtraction by inverting bits~6 and ~7 by inverters 86 and 86' and not - inverting the MSB ~co The MSB, ~co~ is replicated into , .~
, '7~ 7~

1 -21- RCA 76,854 inputs b3, b4 and b5 of adder 87 for proper offset two's complement addition. A logical "1" is applied to the carry-in input CI of the adder to convert the one's complemented word to a two's complemented word. Adder 87 will thus perform the function of (1/8) ~C+D)-(1/64)(C+D) which produces an output word of the form (7/64)(C+D). This output word is confined to the lower six output bits ~0-5 of adder 87 because 7/64 is less than one-eighth of the nlne bit words (C+D).
Adder 74 functions like adder 72 to add eight bit words E and F, which produces a nine bit sum word (E+F).
The five most significant bits of the (E+F) sum word are applied to inputs aO-a4 of adder 94, with the MSB inverted by inverter 90, to produce (1/16) (E+F) in offset two's complement form. The three most significant bits of the (E+F) word are also applied to adder 94 to provide a word of the form (1/64) (E+F). This word is subtracted from (l/16?
(E+F) in adder 94 by two's complementing it through inver-sion of bits ~6 and ~7 by inverters 93 and 93' and carryingin a logical "1" to the CI input of adder 94. The MSB
~10 is not inverted so that the two's complemented word is in offset two's complement form. The MSB applied to input b2 of the adder 94 is replicated into the higher order inputs b3 and b4 for proper offset t~o's complement addition. Adder 94 thus performs the function of (1/16) (E+F) - (1/64) (E+F), which produces an output word of -the form (3/64) (E+F). This output word is contained within the lower five output bits ~0-~4 of adder 94, since 3/64 is less than one-sixteenth of the nine bit wo~d (E+F).
Adder 58 is then used to subtract (7/64) (C+D) from (3/64) (E+F), which provides the minus sign for the (-7/64) weighting function -term. The output word of adder 87 is twols complemented by inverters 88 and the logical "1" carry in bit applied to input CI of adder 58. The MSB
is replicated into input a6 of adder 58. The output word of adder 94 is applied to the "b" inputs of adder 58, with the MSB replicated into inputs b5 and b6. Adder 58 pro-t~ 7~

1 -22- RCA 76,854 duces an output word of the form (-7/64) (C+D)+(3/64)(E+F).
This output word is contained in seven output bits ~o~ ~6 because it is the sum of ¦7/64¦ plus ¦3/64¦ of a nine bit word, which is equal to 10/64 of a nine bit word.
Since¦10/64¦is less than one-quarter, the word will never exceed seven bits. This output word is applied to the "b"
inputs of adder 56, shown in FIGURE lOb.
In FIGURE lOb, adder 70 adds the A and ~ words to produce the sum word (A+B). The seven most significant bits of this sum word are applied to inputs aO-a6 of adder 83, to form (1/4)(A+B) at these inputs. Similarly, the five most significant bits of the sum word (A+B) are applied to inputs bo-b4 of adder 83, forming (1/16)(A+B) at the "b" inputs. Since this addition is in straight binary and not offset two's complement, O's are inserted into the most significant bits (a7;b5,b6,b7). These two binary words are added to produce an eight bit output word of the form (5/16) (A+B). This output word is converted to offset two's complemented form by inverting the MSB ~7 by inverter 89. The converted word is then added to the binary word from adder 58 in adder 56 to produce an eight bit output word denoted "cosine sum". This word is contained in - eight bits since it is the sum of l5/16l + l7/64l + l3/64l = l30/64l of a nine bit word. Since 30/64 is less than one-half, the cosine sum word is contained within eight bits, which is one-half of a nine bit word.
The eight bit cosine sum word is converted 30 to binary form by inverting the ~ISB ~7 of adder 56 by inverter 96. The binary word is then added to (1/2)K
in adder 54 by applying the cosine sum word to theinputs ao-a7 of the adder and the seven most significant bits of the K word to the bo-b6 inputs of the adder. The 35 resultant output word y(n) is contained within nine bits because the cosine sum word can have a maximum magnitude of one-quarter of a nine bit word system, which is the midpoint of an eight-bit word (and the center of an offset two's complement elght-bit word), plus one-half of its ' L ~ ~J~ 1~ r7~

1 -23- RCA 76,854 maximum magnitude of ¦30/64¦, or l16/64¦ -~ (1/2)¦30/64l =
¦31/64¦. The ei~ht-bit K word is divided by two and thus can have a maximum magnitude of ¦1/4l of a nine-bit number range. The maximum magnitude of the y(n) output word is thus equal to l31/64l + l16/641 = l47/64l of a nine-bit number range. Since 47/64 is greater than one-half, nine bits are needed for the y(n) output word.
An alternative embodiment of the FIR filter of FIGURE 8 is shown in block diagram form in FIGURE 11.
In this embodiment, tne weighting function values are comprised of a summation of inverse powers of two (1/2, 1/4, 1/8, 1/16, 1/32, 1/64), as was done in the arrangement of FIGURE 9. The weighting functïon values are then grouped into a set of positive values and a set of negative values. The positive values are all summed together and the negative values are all summed together, both summations of which may be done in binary notation. The two sums are then converted to offset two's complement form, and the sum of the negative values is subtracted from the sum of the positive values to produce the filter output signal.

2~
In FIGURE 11, as in the arrangement of FIGURE 9, adders 70, 72 and 74 receive signals A and B, signals C
and D, and signals E and F, respectively, in binary form.
The y(n) output signal is again of the form y(n) = K2 + 16(A+B) - ~(C+D) + 64(E+F) This expression may be further broken down into inverse power of two functions y(n) = K2 + 4(A+B) + 16(A+B) - 8(C+D) + 64(C+D) + I~(E+F) -64(E+F) 1 -24- RCA 76,854 Rearranging these terms into groups of positive and neqative values results in y(n) = [2 + 4(A+B) + 16(A+B) + 64 (C+D) -~ 16 (E+F)] -S
[8(C+D) + 64 (E+F)]
which is the subtraction provided by the final adder in the filter. By configuring the filter in this manner, offset two's complement conversion is necessary only at the inputs to the final adder, which performs the only subtraction in the filter.
In the embodiment of FIGURE 11, dividers 81 and 82 and adder 83 receive the (A+B) sum word to produce an output signal of the form (5/16)(A+s), as was done in the arrangement of FIGURE 9. The (C-~D) sum word is again divided by eight and sixty-four by dividers 84 and 85 respectively, and the (E+F) sum word is again divided by sixteen and sixty-four by dividers 91 and 92 respectively.
Since dividers 84 and 92 produce negative terms in the final output signal, their outputs are added together by any adder 116 to produce an output of the form (1/8)(C+D) -~ (1/64) (E+F). The positive terms produced by dividers 85 and 91 are added together by an adder 114 to produce an output of the form (l/64)(C+D) + (1/16) (E+F). The output of adder 114 is coupled to an input of an adder 112, where the positive term (5/16)(A+s) is summed with the output word of adder 114. The output of adder 112 is coupled to an input of an adder 110, where the sum word is combined with the X/2 term. The output of adder 110 contains all of the positive terms of the filter, and is equal to ~2 -~ 516(A+B) + 64(C+D) + 16 (E+F) The output of adder 116, containing the sum of the negative filter terms, is then subtracted from the sum of the positive terms in adder 100. The outputs of adders 110 and 116 are converted to offset two's complement form by circuits 102 and 104, respectively.
i;:.;

-- , , _ , ,,,, _, . . . . . . .

~ 7 ~

1 -25- RCA 76,854 The output of circuit 104 is then one's complemented by inverter 106 and applied to adder 100 along with a carry in "one" to effectively two's complement the output of circuit 104. The output of circuit 102 is also coupled to an input of adder 100, which produces the y(n) output signal in offset two's complement form using only a single, final subtraction step.
The arrangement of FIGURE 11 is shown schematically in FIGURES 12a, 12b and 12c. In FIGURE 12a, eight bit words C and D are added in adder 72 to produce a nine bit sum word (C+D). The six most significant bits of the (C+D) sum word are applied to the six least 15 significant bit "a" inputs of adder 116 to effectively apply (l/8)(C+D) to the adder 116. The three most significant bits of the (C+D) sum word are applied to the three least significant bit "a" inputs of adder 114, effectively applying (l/64)(C+D) to adder 114.
Adder 74 sums eight bit words E and F to produce a nine bit sum word (E+F). The three most significant bits of the (E+F) sum word are applied to the three least significant bi-t "b" inputs of adder 116, which provides an input word of the form (1/64)(E+F).
25 Adder 116 thus produces a seven bit output word of the form [(l/8)(C+D) + (1/64)(E~-F)].
The five most signiflcant bits of the (E+F) sum word are applied to the five least significant "b"
inputs of adder 114. Adder 114 produces a six bit 30 output word of the form (1/64)(C-~D) + (1/16)(E+F).
In FIGURE 12b, adders 70 and 83 are coupled in the same manner as shown in FIGURE lOb to produce an eight bit output word at the outputs of adder 83 of the form (5/16)(A+B). The outputs of adder &3 are coupled to 35 the "a" inputs of adder 112, and the outputs of adder 114 are coupled to the six leas-t significant bit "b" inputs of adder 112. Adder 112 produces an eight bit output word of the form (5/16)(A+B) + (1/64)(C+D) + (1/16)(E+F).

~ ~l 7 7 ~. 7 ~

1 -26- RCA 76,854 In FIGURE 12c, ~dder 110 receives the eight blt output word of adder 112 at its "a" inputs, and the seven most significant bits of the K word at inputs bo-b7.
Adder 110 produces a nine bit output word which is the sum of the positive filter functions and is of the form K/2 + (5/16)(A+B) + (1/64)(C+D) + (1/16) (E+F). The most significant bit of this nine bit word, ~co of adder 110, is inverted by inverter 102 to convert the word to offset two's complement form. The output of inverter 102 is coupled to input a8 of nine-bit adder 100, and outputs ~0 - ~7 of adder 110 are coupled to inputs aO ~ a7 of adder 100, respectively.
Outputs ~0 - ~5 of adder 116 are coupled to inputs of inverters shown at 106, the outputs of which are coupled to inputs bo ~ b5 of adder 100. The mos-t significant bit~ 6 of the output of adder 116 is applied directly to input b6 of adder 100 so that the "b" inputs of adder 100 are receiving a one's complemented ~orm of the output of adder 116 in offset two's complement notation. The MSB ~6 is also replicated into inputs b7 and b8 of adder 100 since the addition is performed in the offset two's complement system. A logical "1" is applied to the carry in input of adder 100 to two's complement the one's complemented output of adder 116 for subtraction.
Adder 100 will then produce an output word, y(n) of the desired form of [K/2 + (5/16)(A+B) + (1/64)(C-~D) + (1/16) (E+F)] -[(1/8)(C+D) + (1/64) (E+F)] = K/2 + (5/l6)(A+s) +
(7/6~)(C+D) -~ (3/64) (E+F) .
The arrangement of FIGURES 12a, 12b and 12c, in which positive and negative terms are separately summed in the positive sense and the two resulting sums subtracted, is seen to use nine adders and seven inverters, compared with the use of nine adders and fourteen inverters in the .. ... . .
. ~ .

~.7'~7~

1 -27- RCA 76,854 arrangement of FIGURES lOa and lOb. If desired, the nine-bit adder 100 of FIGURE 12c can be replaced with a conventional eight-bit adder by truncating or rounding off its two input words to eight bits.
The FIR filter arrangements of FIGURES 8-12 will produce a response characteristic as shown in FIGURE 13 when the shift register 50 is clocked at approximately 14.3 MHz. The characterlstic response exhibits six dB points at approximately 1.8 and 5.3 MHz, which is a desirable characteristic for a low pass luminance or vertical detail filter in a television receiver in the NTSC system. The characteristic response can be simply inverted to provide a desirable response for an NTSC chrominance bandpass filter by subtractively combining the cosine sum term with the K/2 term. This is accomplished by subtracting the output of adder 56 from the K/2 term in adder 54 of FIGURES 8, 9 or lOb using the two's complement of the cosine sum term in offset two's complement form as described above.

.

'

Claims (13)

-28- RCA 76, 854 WHAT IS CLAIMED IS:

1. Apparatus for performing binary subtraction of a first and a second binary number comprising a digital filter having first means for offset two's complementing said first binary number;
second means for offset two's complementing and two's complementing said second binary number; and third means for adding said offset two's complemented first binary number and said offset two's complemented and two's complemented second binary number.

2. The apparatus of Claim 1 wherein said second means comprises:
means fox offset two's complementing said second binary number; and means for two's complementing said offset two's complemented second binary number.

3. The apparatus of Claim 1 wherein said second means comprises:
means for two's complementing said second binary number; and means for offset two's complementing said two's complemented second binary number.

4. The apparatus of Claim 1, wherein said second means comprises:
inverting means for inverting all bits of said second binary number except the most significant bit; and means for adding one to the output of said inverting means.

5. The apparatus of Claim 1 wherein: said digital filter processes a binary signal, and represents negative numbers in two's complemented format, said first and second binary numbers are derived from said binary -29- RCA 76,854 signal; said digital filter comprises means for producing delayed replicas of said binary signal at a plurality of output taps, and a ladder network coupled to said output taps for weighting and combining said delayed binary signals said ladder network including at least one subcircuit connected between two of said plurality of output taps and an output terminal said first and/or said second means includes signal weighting means, said subcircuit comprises:
said first, second and third means coupled to process signals applied to said subcircuit, to produce at said output terminal, an offset two's complemented, summed and weighted manifestation of signals available from said output taps.

6. The apparatus of Claim 5 wherein:
said subcircuit comprises a plurality of weighting function circuits having inputs coupled to respective ones of said output taps for producing weighted binary signals, said third means including a plurality of adders coupled to additively and subtractively combine said weighted signals to produce a filtered digital output signal, said additively combining adders each being responsive to two of said weighted signals in binary form for producing digital sum signals in binary form, and said subtractively combining adders each being responsive to two of said weighted signals, one of which is in two's complement form, for producing digital difference signals and said first means are coupled in the signal paths in series with the inputs of each of said subtractively combining adders, for converting the weighted signals applied thereto to offset two's complement form;
whereby digital additions are performed in binary form and digital subtractions are performed in offset two's complement form.

-30- RCA 76,854

7. The apparatus of Claim 5 wherein:
said subcircuit comprises a first adder having first and second inputs coupled to different ones of said output taps, and an output at which a first binary sum signal is produced, first weighting means having an input and an output, and coupled to the output of said first adder for weighting said first binary sum signal by a given weighting factor, said second means being coupled to said first weighting means for converting said first weighted binary sum signal to offset two's complement form and two's complementing said first offset two's complemented weighted sum signal, a second adder having first and second inputs coupled to different ones of said output taps, and an output at which a second binary sum signal is produced;
second weighting means coupled to the output of said second adder for weighting said second binary sum signal by a given weighting factor, said first means being coupled to said second weighting means for converting said second weighted binary sum signal to offset two's complement form, and said third means including a third adder having inputs coupled to receive said two's complemented first offset two's complemented weighted sum signal and said second offset two's complemented weighted sum signal, and an output at which a difference signal is produced.

8. The apparatus of Claim 5 wherein said ladder network comprises a first signal path having an input coupled to a first one of said output taps and an output at which a first weighted digital signal in binary form is produced, including a first weighting function circuit for weighting applied digital signals, -31- RCA 76,854 a second signal path having an input coupled to a second one of said output taps and an output at which a second weighted digital signal in binary form is produced, including a second weighting function circuit for weighting applied digital signals, and a first adder having a first input coupled to the output of said first signal path, a second input coupled to the output of said second signal path, and an output at which a digital signal in binary form and representative of the sum of said first and second weighted digital signals is produced; and said subcircuit comprises a third signal path having an input coupled to a third one of said output taps and an output at which a third weighted digital signal in offset two's complement form is produced, including a third weighting function circuit for weighting applied digital signals, and said first means for converting digital signals in said third path to offset two's complement form, a fourth signal path having an input coupled to a fourth one of said output taps and an output at which a fourth weighted digital signal in offset two's complement form is produced, including a fourth weighting function circuit for weighting applied digital signals, and said second means for converting digital signals in said fourth path to offset two's complement form and producing a two's complemented version of said fourth weighted digital signal, said third means including an adder having a first input coupled to the output of said third signal-path, a second input coupled to receive said two's complemented version of said fourth weighted digital signal, and an output at which a digital signal representative of the difference between said third and fourth weighted digital signals is produced.

-32- RCA 76,854

9. The apparatus of Claim 5 wherein:
said subcircuit comprises a plurality of signal paths respectively coupled to ones of said output taps for producing weighted delayed binary signals, a first ladder network of adders coupled to a first plurality of said signal paths, and having an output at which a first sum of weighted delayed binary signals is produced, a second ladder network of adders coupled to a second plurality of said signal paths, and having an output at which a second sum of weighted delayed binary signals is produced, said first means including means for converting said first sum to offset two's complement form, said second means including means converting said second sum to offset two's complement form and producing a two's comple-mented replica of said second offset two's complement sum, and said third means including an adder having a first input coupled to receive said first sum in offset two's complement form, and a second input coupled to receive said two's complement second sum in offset two's complement form, and an output at which a filtered digital signal is pro-duced.

10. The apparatus of Claim 7 wherein said ladder network comprises:
third weighting means having an output, and an input coupled to one of said output taps for weighting the binary signal produced thereat;
means, coupled to the output of said third adder, for converting received digital signals to binary form; and a fourth adder, having inputs coupled to the output of said third weighting means and said means coupled to the output of said third adder, for producing an output sum signal.

-33- RCA 76,854

11. The apparatus of Claims 6, 8, or 9 wherein said weighting function circuits weight said applied digital signals by weighting function values equal to multiples of negative powers of two.

12. The apparatus of Claim 2 or 3 wherein said two's complementing means includes means for applying a logical "one" as a carry-in bit to an adder coupled to the output of said two's complementing means.

13. The apparatus of Claim 1, 2 or 3 wherein said offset two's complementing means comprises an inverter coupled to invert the most significant bit of a digital signal to be offset two's complemented.