CA1168316A - Pulse generating circuit - Google Patents
Pulse generating circuitInfo
- Publication number
- CA1168316A CA1168316A CA000394944A CA394944A CA1168316A CA 1168316 A CA1168316 A CA 1168316A CA 000394944 A CA000394944 A CA 000394944A CA 394944 A CA394944 A CA 394944A CA 1168316 A CA1168316 A CA 1168316A
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- CA
- Canada
- Prior art keywords
- transistor
- line
- load
- potential
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
Abstract
RCA 75,006 PULSE GENERATING CIRCUIT
Abstract of the Disclosure The conduction paths of a first, normally on, transistor and a second, normally off, transistor are connected in parallel between an output line and a circuit point at a first value, of potential. When any one of a plurality of normally non-conducting input signal responsive means coupled to the output line, is enabled, it causes the potential on the output line to be driven to a second value of potential. Means are provided responsive to the potential on the output line for applying a turn-off signal to the first transistor followed by a delayed turn-on signal to the second transistor when the potential on the output line is driven towards the second value of potential and for applying a turn-on signal to the first transistor followed by a delayed turn-off signal to the second transistor when the potential on the output line is being restored to the first value of potential.
Abstract of the Disclosure The conduction paths of a first, normally on, transistor and a second, normally off, transistor are connected in parallel between an output line and a circuit point at a first value, of potential. When any one of a plurality of normally non-conducting input signal responsive means coupled to the output line, is enabled, it causes the potential on the output line to be driven to a second value of potential. Means are provided responsive to the potential on the output line for applying a turn-off signal to the first transistor followed by a delayed turn-on signal to the second transistor when the potential on the output line is driven towards the second value of potential and for applying a turn-on signal to the first transistor followed by a delayed turn-off signal to the second transistor when the potential on the output line is being restored to the first value of potential.
Description
1:~6~3:~6 -1- RCA 75,006 PUL~E GENERATING CIRCUIT
This invention rela-tes to circuitry for generatiny a well-defined narrow pulse having sharp leading and -trailing edges.
In the accompanying drawing like reference characters denote like components; and FIGURE lA is a schematic diagram o:E a prior art circuit;
FIGURE lB includes waveform diagrams of a typical output of the circui-t of FIGURE lA and of a desired output signal;
FIGURE 2 is a schematic diagram of a circuit embodying the invention;
FIGURE 3 includes waveform diagrams of a signal applied to, and of an output signal produced by, the circuit of E~IGURE 2, and graphs illus-trating the turn-on and turn-off sequence of load transistors in the circuit of FIGURE 2;
FIGURE 4A is a schematic dia~ram of a delay network suitable for use in the circuit of FIGURE 3;
FIGURE 4B is a diagram of waveforms associated with the circuit of FI~URE 4A; and FIGURE 5 is a schematic diagram of another circuit embodying the invention.
In many applications it is necessary to produce a signal indicating that one or more of a multiplicity of events or conditions has occurred. By way of example, in a high speed memory it is desirable to ~uickly sense (detect) a voltage (or current) change on any of the many word and bit address lines and to then to produce a pulse or signal to precharge various portions of the memory circuit and to perform certain housekeeping functions prior to the read-out of information from the memory or the writing of information into the memory.
A known circuit suitable to perform the desired gating function and which may be characterized as a passive WIRE-OR circui-t is shown in FIGURE lA. The circuit includes a grounded gate transistor Tl, of P-conductivity v. ~ ~-3 ~
This invention rela-tes to circuitry for generatiny a well-defined narrow pulse having sharp leading and -trailing edges.
In the accompanying drawing like reference characters denote like components; and FIGURE lA is a schematic diagram o:E a prior art circuit;
FIGURE lB includes waveform diagrams of a typical output of the circui-t of FIGURE lA and of a desired output signal;
FIGURE 2 is a schematic diagram of a circuit embodying the invention;
FIGURE 3 includes waveform diagrams of a signal applied to, and of an output signal produced by, the circuit of E~IGURE 2, and graphs illus-trating the turn-on and turn-off sequence of load transistors in the circuit of FIGURE 2;
FIGURE 4A is a schematic dia~ram of a delay network suitable for use in the circuit of FIGURE 3;
FIGURE 4B is a diagram of waveforms associated with the circuit of FI~URE 4A; and FIGURE 5 is a schematic diagram of another circuit embodying the invention.
In many applications it is necessary to produce a signal indicating that one or more of a multiplicity of events or conditions has occurred. By way of example, in a high speed memory it is desirable to ~uickly sense (detect) a voltage (or current) change on any of the many word and bit address lines and to then to produce a pulse or signal to precharge various portions of the memory circuit and to perform certain housekeeping functions prior to the read-out of information from the memory or the writing of information into the memory.
A known circuit suitable to perform the desired gating function and which may be characterized as a passive WIRE-OR circui-t is shown in FIGURE lA. The circuit includes a grounded gate transistor Tl, of P-conductivity v. ~ ~-3 ~
-2- RCA 75,006 -type, Eunc-tioning as a passive load, having its conduction path connected between a poin-t of positive operating potential of VDD volts and an owtput l:ine 12.
Transistors N1 through N4, of N-conductivi-ty type, responsive -to respective input signals Sl through S4, have their conduction paths colmected in parallel between line 12 and ground. Transistoxs Nl through N4 are normally turned-off while T1 is biased into conduction to normally main-tain line 12 at, or close to, VDD volts.
When any of transistors N1 through N4 is turned-on, it conducts to ground the c~lrren-t flowing into line 12 via Tl and also discharges capacitance CL towards ground potential. Thus, a nega-tive-going pulse is generated.
When the signal responsive transistors are turned-off, line 12 is recharged -towards VDD volts via T1, terminating the negative-going pulse.
The circui-t of FIGURE lA has been used successfully in many applications but suffers from various problems best explained by reference to the typical output waveform in FIGURE lB.
1. Conduction through T1 slows down the leading (falling) edge of the negative going pulse on the WIRE-OR line when one or more of the signal responsive transistors (Nl-N4) is turned-on.
2. The signal on the WIRE-ON line cannot go all the way to ground, due to the voltage divider action between T1 and the signal responsive transistors N1-N4.
The low level of the output signal is not well defined and circuits responsive to the signal may not be fully or ~uickly turned on or off.
Transistors N1 through N4, of N-conductivi-ty type, responsive -to respective input signals Sl through S4, have their conduction paths colmected in parallel between line 12 and ground. Transistoxs Nl through N4 are normally turned-off while T1 is biased into conduction to normally main-tain line 12 at, or close to, VDD volts.
When any of transistors N1 through N4 is turned-on, it conducts to ground the c~lrren-t flowing into line 12 via Tl and also discharges capacitance CL towards ground potential. Thus, a nega-tive-going pulse is generated.
When the signal responsive transistors are turned-off, line 12 is recharged -towards VDD volts via T1, terminating the negative-going pulse.
The circui-t of FIGURE lA has been used successfully in many applications but suffers from various problems best explained by reference to the typical output waveform in FIGURE lB.
1. Conduction through T1 slows down the leading (falling) edge of the negative going pulse on the WIRE-OR line when one or more of the signal responsive transistors (Nl-N4) is turned-on.
2. The signal on the WIRE-ON line cannot go all the way to ground, due to the voltage divider action between T1 and the signal responsive transistors N1-N4.
The low level of the output signal is not well defined and circuits responsive to the signal may not be fully or ~uickly turned on or off.
3. The trailing (rising) edge of the output pulse has a very long time constant due to the high ON impedance of T1 having to charge up the relatively large capacitance, CL, associated with line 12. In large memories, more transistors, than the four signal responsive transis-tors shown in FIGURE lA by way of example, are normally connected in parallel, fur-ther increasing CL. This ~ ~6~31~
-3 RCA 75,006 results in a very slow rising potential on the WI~E OR
line.
-3 RCA 75,006 results in a very slow rising potential on the WI~E OR
line.
4. The dynamic power dissipation is quite high since Tl is always ONo The problems discussed above arise primarily because of the use of a passive load (i.e. grounded gate transistor Tl). This type of load is used because the input signals (e.g. changes in the voltage level on the address lines) are randomly applied to the system. Thus, it is impractical to clock the load and switch-it o~f prior to the turn--on of the signal responsive transistors.
In a circuit embodying the invention the problems associated with the prior art circuit are eliminated or at least greatly reduced b~ dynamically driving a controlla~le load means on and off as a function of a signal (or voltage) generated at the output oE the circuit. One embodiment of the invention includes an output line to which randomly activated input signal responsive transistors are connected. ~ controllable load means is connected between the output line and a point of operating potential. A means responsive to the signal on the output line is coupled to the load means for:
a) maintaining the load means in a relatively high impedance state when none of the input signal responsive transistors is turned-on;
b) switching the load means to a very high impedance state when an input signal responsive transistor is turned-on; and 0 c) switching the load means to a relatively low impedance state for a given time period some time after an input signal responsive transistor is turned-on.
The circuit of FIGURE 2 includes insulated-gate field-effect transistors (IGFETs) Nl through Nm, of N-conductivity type, having their conduction paths connected in parallel between a WIRE-OR BUS 12 and ground potential. The gate electrode of each one or the transistors Ni, where l ~ i ~ m, is connected to the output of a corresponding transition detector (TDi). 1`he ~ 1683 1 6 -4- RCA 75,006 inp~t of each I~Di is connected to an a~dress line Li to which is applied an adclress signal Ai. ~rhe transition detectors may be, for example, of the type shown in FIGUR~S l or 3 of U.S. patent 4,039,858 titled TRANSITION
DETECTOR, although any suitable transition detector may be used instead. Whenever an address ~i on any one of the address lines changes from a "high" to a "low" or from a "low" to a "high" its corresponding transition detector TDi produces a positive going pulse Si, as shown in FIGURE
3, which is applied to the gate electrode of its corresponding Ni transistor. [The si~nal Si is the inverse or complement of the "C" output shown in FIGURE l of the cited patent.] Thus, a positive going input pulse Si is produced per signal transition on address line Li.
Each input signal responsive transistor Ni is normally turned-off, being turned-on only when its corresponding Si signal is high.
~0 The circuit load includes IGFETs Pl and P2, of P-conductivity type, having their main conduction paths connected in parallel between line 12 and a terminal 16 to which is applied a positive operating potential of VDD
volts. The ON impedance (ZPl) of Pl is substantially greater than the ON impedance (ZP2) of P2. That is, in terms of their geometries, Pl is a smaller device than P2. A circuit 18 connected between line 12 and the gate of Pl produces a signal at the gate of Pl which is the inverse or complement of the signal on line 12. In this embodiment circuit 18 is an inverter Il connected at its input to BUS 12 and at its output to the gate of transistor Pl. Inverter Il produ~es at i~s output a signal which is the complement or inverse oE, and which is only slightly delayed with respect to, the signal at its input. Three inverters I2, I3, and I4 are connected in cascade between the output of inverter Il and the gate electrode of P2. Inverters I2, I3, and I4 ~orm a circuit 20 which functions to delay the ou~put of Il while amplifying and inverting it prior to applying it to the gate of P2. The propagation delay through inverters I2, 11683:~ ~
In a circuit embodying the invention the problems associated with the prior art circuit are eliminated or at least greatly reduced b~ dynamically driving a controlla~le load means on and off as a function of a signal (or voltage) generated at the output oE the circuit. One embodiment of the invention includes an output line to which randomly activated input signal responsive transistors are connected. ~ controllable load means is connected between the output line and a point of operating potential. A means responsive to the signal on the output line is coupled to the load means for:
a) maintaining the load means in a relatively high impedance state when none of the input signal responsive transistors is turned-on;
b) switching the load means to a very high impedance state when an input signal responsive transistor is turned-on; and 0 c) switching the load means to a relatively low impedance state for a given time period some time after an input signal responsive transistor is turned-on.
The circuit of FIGURE 2 includes insulated-gate field-effect transistors (IGFETs) Nl through Nm, of N-conductivity type, having their conduction paths connected in parallel between a WIRE-OR BUS 12 and ground potential. The gate electrode of each one or the transistors Ni, where l ~ i ~ m, is connected to the output of a corresponding transition detector (TDi). 1`he ~ 1683 1 6 -4- RCA 75,006 inp~t of each I~Di is connected to an a~dress line Li to which is applied an adclress signal Ai. ~rhe transition detectors may be, for example, of the type shown in FIGUR~S l or 3 of U.S. patent 4,039,858 titled TRANSITION
DETECTOR, although any suitable transition detector may be used instead. Whenever an address ~i on any one of the address lines changes from a "high" to a "low" or from a "low" to a "high" its corresponding transition detector TDi produces a positive going pulse Si, as shown in FIGURE
3, which is applied to the gate electrode of its corresponding Ni transistor. [The si~nal Si is the inverse or complement of the "C" output shown in FIGURE l of the cited patent.] Thus, a positive going input pulse Si is produced per signal transition on address line Li.
Each input signal responsive transistor Ni is normally turned-off, being turned-on only when its corresponding Si signal is high.
~0 The circuit load includes IGFETs Pl and P2, of P-conductivity type, having their main conduction paths connected in parallel between line 12 and a terminal 16 to which is applied a positive operating potential of VDD
volts. The ON impedance (ZPl) of Pl is substantially greater than the ON impedance (ZP2) of P2. That is, in terms of their geometries, Pl is a smaller device than P2. A circuit 18 connected between line 12 and the gate of Pl produces a signal at the gate of Pl which is the inverse or complement of the signal on line 12. In this embodiment circuit 18 is an inverter Il connected at its input to BUS 12 and at its output to the gate of transistor Pl. Inverter Il produ~es at i~s output a signal which is the complement or inverse oE, and which is only slightly delayed with respect to, the signal at its input. Three inverters I2, I3, and I4 are connected in cascade between the output of inverter Il and the gate electrode of P2. Inverters I2, I3, and I4 ~orm a circuit 20 which functions to delay the ou~put of Il while amplifying and inverting it prior to applying it to the gate of P2. The propagation delay through inverters I2, 11683:~ ~
-5- RCA 75,006 I3 and I4 is, in part, a function of the si~es of the transistors forming the inverters. Inverters Il, I2, I3 and I4 may be formed using transistors of complementary conductivity type, as shown in FIGURE 4A; but alternatively could be formed employing transistors of single conductivity type or be any suitable inverter.
The combination of circuits 18 and 20 functions to provide a signal at the gate electrode of P2 which is of the same polarity as the signal on line 12 but which i5 delayed therefrom by the combined propagation delays of Il, I2, I3 and I4. ~dditional delays could be introduced in circuit 20 (or in circuit 18) so long as the signal at the gate of P2 is delayed with respect to, but of the same polarity as, the signal on line 12 and the signal at the gate of Pl remains the complement of the signal on line 12. As will be evident from the discussion below the out-of-phase signal produced and applied to the gate electrode of Pl by means of Il could as well be produced by any other suitable circuit and the delayed in-phase signal applied to the gate of transistor P2 by means of circuits 18 and 20 could also be produced by any other suitable circuit. Note that a circuit performing the function of circuits 18 and 20 could be connected directly between output line 12 and the gate of P2; where this circuit is independent of the circuit connected between line 12 and the gate of Pl.
The initial or static conditions ~i.e. in the absence of an address change or a considerable time after an address change) of the circuit of FIGURE 2 are as follows: (a) The Ni transistors are turned-off; (b) the voltage, V12, on BUS 12 is high (i.e. at VDD); (c) the output, Vl, of inverter Il is low (i.e. at ground), (d) therefore Pl is turned-on; (e) the output V4, of inverter I4 is high (i.e. at VDD); and (f) P2 is turned-off.
In response to the turn-on of any one of the Ni transistors by means of an Si signal as shown in FIGURE 3, the voltage V12 on BUS 12 starts to go relatively negative, that is, toward ground. When V12 starts going
The combination of circuits 18 and 20 functions to provide a signal at the gate electrode of P2 which is of the same polarity as the signal on line 12 but which i5 delayed therefrom by the combined propagation delays of Il, I2, I3 and I4. ~dditional delays could be introduced in circuit 20 (or in circuit 18) so long as the signal at the gate of P2 is delayed with respect to, but of the same polarity as, the signal on line 12 and the signal at the gate of Pl remains the complement of the signal on line 12. As will be evident from the discussion below the out-of-phase signal produced and applied to the gate electrode of Pl by means of Il could as well be produced by any other suitable circuit and the delayed in-phase signal applied to the gate of transistor P2 by means of circuits 18 and 20 could also be produced by any other suitable circuit. Note that a circuit performing the function of circuits 18 and 20 could be connected directly between output line 12 and the gate of P2; where this circuit is independent of the circuit connected between line 12 and the gate of Pl.
The initial or static conditions ~i.e. in the absence of an address change or a considerable time after an address change) of the circuit of FIGURE 2 are as follows: (a) The Ni transistors are turned-off; (b) the voltage, V12, on BUS 12 is high (i.e. at VDD); (c) the output, Vl, of inverter Il is low (i.e. at ground), (d) therefore Pl is turned-on; (e) the output V4, of inverter I4 is high (i.e. at VDD); and (f) P2 is turned-off.
In response to the turn-on of any one of the Ni transistors by means of an Si signal as shown in FIGURE 3, the voltage V12 on BUS 12 starts to go relatively negative, that is, toward ground. When V12 starts going
-6- RC~ 75,U06 relatively negative, inverter Il amplifies and inverts the change and the output oE Il starts going from low to high. Since Vl i5 going positive the gate-to-source potential oE Pl is reduced and its conduction is significantly reduced. Recall that Pl is, preferably, a very small device and its ON impedance is substantially greater than that of any Ni transistor. As Pl is being turned-off, its impedance increases further and the low current passing through its conduction path into line 12 is further decreased. The positive feedback loop comprising Il and Pl ensures that after the initial drop in V12, Vl rises close to VDD, and the turn-off of Pl is accelerated. Hence, the voltage V12 on line 12 can be quickly discharged towards ground via the turned-on Ni transistor with little counteracting effect via Pl which rapidly cuts off. The result is a fast falling leading edge in waveform V12 of FIGURE 3 from time tl, to t2.
After Pl is turned-off and with P2 off, there is no low impedance path connected between lines 12 and 160 The WIRE-OR bus 12 and its associated capacitance can then be quickly discharged all the way to ground potential via a turned-on Ni transistor conducting in the common source mode as is shown in waveform V12 of FIGURE 3 for time t2 to t5.
After Pl is turned-off P2 will remain turned-off for the period of time that it takes the low-to-high output voltage transition of Il to propagate through I2, I3 and I4. After the propagation delay through I2, I3 and I4, the output of I4 (which is complementary to the output of Il) goes from high-to-low and P2 is turned-on. P2 is, preferably, a relatively large device and when it turns on it very quickly charges or pulls line 12 towards VDD
volts, as is shown in waveform V12 of FIGURE 3 for time t5 to t6. The initiating pulse Si is typically very narrow and normally terminates on or before the time that P2 is turned-on as shown for time t3 to t4 in FIGURE
3. The pulse delay will normally be designed to be slightly greater than the Si pulse width so that it is ~16~3 l6 _7_ RCA 75,006 assumed that P2 does no-t turn-on ~mtil the trhnsistor Ni responsive to Si has turned-o~f. As soon as V12 is driven towards VDD, -the ou-tput of Il begins -to go low and transistor Pl is turned-on, further aidiny in bringing V12 back -towards VDD. The high-to-low output transition of Il is propaga-ted via inverters I2, I3 and I4 causing, af-ter the propaga-tion delay, an amplified positive going signal -to be applied to the gat;e of P2, which -turns P2 off completely. The vol-tage on line 12 is then held at the high (VDD) level only by means of transis-tor P1.
Shortly after an Ni -transis-tor is turned-on (between -time to and tl), P1 is turned-off (at -time t~) while P2 remains turned-off. The turn-off of Pl while P2 is off during the first portion of -the period discussed above enables the WIRE-OR BUS 12 to be discharged very quickly righ-t down to ground (the vol-tage drop across the conduction pa-th of Ni is negligible and may be ignored) potential, via an Ni transistor conducting in the common source mode. Thus, the pulse V12 has a sharp leading (falling) edge. Pl and P2 remain turned-off after the pulse reaches or comes down to, 0 volts for a predetermined period (i.e. time t2 to t5, which corresponds to the propagation delays through I2, I3 and I4). This enables the low or zero level of the output pulse to be well defined. Also since P1 and P2 are turned-off during most of the -time that a negative-going pulse is being generated, there is little power dissipation. After the delay, at time t5, P2 turns-on and, due to its very low ON impedance, very ~uickly charges up the WIRE-OR ~US towards VDD volts causing, very shortly thereafter (at time t6), the turn-on of P1.
If P2 is turned-on after the turn-off of the Ni transistor initiating the precharge cycle there is very little average power dissipation. Although there is a substantial instan-taneous power dissipation (P2-ON
recharging CL), it occurs only for a very short time duration, e.g. where the pulse width is 6 to 10 nanoseconds, P2 will be ON also for 6 to 10 nanoseconds.
~ 16~3 1 6 1 -8- RCA 75,006 There~ore, the circuit has a very low average power dissipation while its output response is extremely fast.
wnere the input signals Si are applied in such a sequence that an Ni transistor is turned-on during the time that P2 is turned-on (from time t5 to t7 in FIGURE 3) the power dissipation in the system increases. But, the time period during which P2 is turned-on is very very short.
Therefore, the average power dissipation remains low.
In order to reduce the time that P2 is ON the delay need not be symmetrical Eor both polarity (i~e.
high-to-low and low-to-high) of signals generated on line 12 as illustrated in E'IGUREs 4A and ~B. Inverters I2, I3 and I4 Eorming delay network 20 are detailed using complementary IGFETs. The P-conductivity type transistors (PI2 and PI4) of inverters I2 and I4 are made larger than their corresponding N-conductivity type transistors (NI2 and NI4), and NI3 of inverter I3 is made large in comparison to PI3. AS a result the delay (TDF) in response to high-to-low (negative-going) transition on line 12 is greater than the delay (TDB) in response to a low-to-high (positive going) transition on line 12.
The invention has been illustrated using two active (dynamicall~ driven) transistors (Pl and P2). But, instead, the circuit could include a single load transistor (or other controllable impedance means) whose impedance or conductance is controlled by the voltage level on line 12. When all the inputs (Ar) are low (defining a static condition) the combination of P2 and Pl functions as a high impedance load connected between line 12 and V~D. The impedance of the load (Pl) durin~ the static condition is designed to compensate for leakage currents (from line 12) to ground and to prevent line 12 from floating. The lOâd impedance can, therefore, be very high. When an Ni transistor is turned-on, an output pulse is produced and Pl is turned-off (P2 already is off). As both Pl and P2 are off, they function as an extremely high impedance load. Following the generation of the output 1~6~3-~6 75,006 ~ ( ol tll irc~d pulse widlh, L~2 is t-lrn(~-on for a s~,ort i~rio~ ime (and Pl is also turnecl--orl) to tetminate the outp~lL p~l-ie an~ to provide a sharp trailing edge (fast returl-l to VI~D). The combll~ation of Pl and P2 then Lunctions as a low ON impedance circuit designed to very quickly restoLe the output line to its original ~static) condition. Then P2 is turned-off and Pl is again turned-on.
This is in sharp contrast to the Prior Art circuit where: a) the leading edge is restricted from falliny sharply; b) the final level of the pulse cannot reach the supply rail; and c) the trailing edge cannot return quickly to its original level.
By dynamically driving the load with a signal generated on the output line of the circuit rather than using a passive pull up transistor (or a resistor) as in the Prior Art, extremely fast operation with low average power dissipation is achieved.
Thus, in circuits embodying the invention, although the input signals (e.g. changes on address lines) are randomly applied to the sys~em, an output pulse or signal is produced very quickly after the occurrence of a change on an address line. The pulse or signal is well defined (i.e. goes from a full "low" to a full "high", or vice versa), has a sharp leading edge to define the start of the precnarge and housekeeping function, and has a sharp trailing edge to terminate the precharge and housekeeping functions and to initiate a read-out or write cycle.
In the circuit of FIGURE 5 three circuits 2a, 2b, and 2c similar to the circuit of FIGURE 2 have their respective outputs V12a, V12b, and V12c connected via lines 12a, 12b and 12c to the gate electrodes of respective inp~t transistors P41, P42 and P43. The number of address inputs (Ala to ~Xa, Alb to ANb, Al to AXc!
applied to circuits 2a, 2b and 2c need not be the same.
Yor example, in the circuit of FIGIJRE 2 a multiplicity (m) of input signals responsive transistors Ni are shown connected at node 12~ In order to minimize the 11~83~
-10- RCA 75,006 capacltallce associated with node 12 and to obtain higher speed of operation it may be advantageous to limit the number of input signals in each subcircuit (2a, 2b, 2c).
In any event, the outputs of two or more circuits of the t~pe shown in FTGURE 2 may be combined or gated in common as si~own in FIGURE 5. The WIRE-OR circuit shown in box 40 is the complementary version of the circuit of FIGURE 2.
The signal responsive transistors are transistors P4i of P-conductivity type having their conduction paths connected in parallel between VDD volts and a WIRE-O~
line 42. The dynamic load includes a transis-tor N41 (corresponding to Pl of FIG~RE 2) and a transistor N42 (corresponding to P2 in FIGURE 2) having their conduction paths connected in parallel between line 42 and ground, An inverter I4l (corresponding to Il) is connected at its input to line 42 and at its output to the gate of N41.
Three inverters Ifi2, I43 and I44 (corresponding to I2, I3 and I4) are connected in cascade between the output of I41 and the gate electrode of N42.
The circuit 40 of FIGURE 5 functions in a complementary but otherwise similar manner to the circuit of FIGUR~ 2 and need not be greatly detailed. Thusl when a negative-going pulse is produced on lines 12a, 12b or 12c a positive going output pulse is produced on output line 42. The pulse produced on line 42 may be directly connected to various portions of a subsequent circuit (not shown), or connected via a buffer to subsequent circuits.
It is evident from the circuit of FIGURE 5 that the input signals can be combined in many different ways in an effort to optimize the system response. The circuit of FIGURE 5 also demonstrates that circuits embodying the invention can easily be combined to perform comb~nation logic.
After Pl is turned-off and with P2 off, there is no low impedance path connected between lines 12 and 160 The WIRE-OR bus 12 and its associated capacitance can then be quickly discharged all the way to ground potential via a turned-on Ni transistor conducting in the common source mode as is shown in waveform V12 of FIGURE 3 for time t2 to t5.
After Pl is turned-off P2 will remain turned-off for the period of time that it takes the low-to-high output voltage transition of Il to propagate through I2, I3 and I4. After the propagation delay through I2, I3 and I4, the output of I4 (which is complementary to the output of Il) goes from high-to-low and P2 is turned-on. P2 is, preferably, a relatively large device and when it turns on it very quickly charges or pulls line 12 towards VDD
volts, as is shown in waveform V12 of FIGURE 3 for time t5 to t6. The initiating pulse Si is typically very narrow and normally terminates on or before the time that P2 is turned-on as shown for time t3 to t4 in FIGURE
3. The pulse delay will normally be designed to be slightly greater than the Si pulse width so that it is ~16~3 l6 _7_ RCA 75,006 assumed that P2 does no-t turn-on ~mtil the trhnsistor Ni responsive to Si has turned-o~f. As soon as V12 is driven towards VDD, -the ou-tput of Il begins -to go low and transistor Pl is turned-on, further aidiny in bringing V12 back -towards VDD. The high-to-low output transition of Il is propaga-ted via inverters I2, I3 and I4 causing, af-ter the propaga-tion delay, an amplified positive going signal -to be applied to the gat;e of P2, which -turns P2 off completely. The vol-tage on line 12 is then held at the high (VDD) level only by means of transis-tor P1.
Shortly after an Ni -transis-tor is turned-on (between -time to and tl), P1 is turned-off (at -time t~) while P2 remains turned-off. The turn-off of Pl while P2 is off during the first portion of -the period discussed above enables the WIRE-OR BUS 12 to be discharged very quickly righ-t down to ground (the vol-tage drop across the conduction pa-th of Ni is negligible and may be ignored) potential, via an Ni transistor conducting in the common source mode. Thus, the pulse V12 has a sharp leading (falling) edge. Pl and P2 remain turned-off after the pulse reaches or comes down to, 0 volts for a predetermined period (i.e. time t2 to t5, which corresponds to the propagation delays through I2, I3 and I4). This enables the low or zero level of the output pulse to be well defined. Also since P1 and P2 are turned-off during most of the -time that a negative-going pulse is being generated, there is little power dissipation. After the delay, at time t5, P2 turns-on and, due to its very low ON impedance, very ~uickly charges up the WIRE-OR ~US towards VDD volts causing, very shortly thereafter (at time t6), the turn-on of P1.
If P2 is turned-on after the turn-off of the Ni transistor initiating the precharge cycle there is very little average power dissipation. Although there is a substantial instan-taneous power dissipation (P2-ON
recharging CL), it occurs only for a very short time duration, e.g. where the pulse width is 6 to 10 nanoseconds, P2 will be ON also for 6 to 10 nanoseconds.
~ 16~3 1 6 1 -8- RCA 75,006 There~ore, the circuit has a very low average power dissipation while its output response is extremely fast.
wnere the input signals Si are applied in such a sequence that an Ni transistor is turned-on during the time that P2 is turned-on (from time t5 to t7 in FIGURE 3) the power dissipation in the system increases. But, the time period during which P2 is turned-on is very very short.
Therefore, the average power dissipation remains low.
In order to reduce the time that P2 is ON the delay need not be symmetrical Eor both polarity (i~e.
high-to-low and low-to-high) of signals generated on line 12 as illustrated in E'IGUREs 4A and ~B. Inverters I2, I3 and I4 Eorming delay network 20 are detailed using complementary IGFETs. The P-conductivity type transistors (PI2 and PI4) of inverters I2 and I4 are made larger than their corresponding N-conductivity type transistors (NI2 and NI4), and NI3 of inverter I3 is made large in comparison to PI3. AS a result the delay (TDF) in response to high-to-low (negative-going) transition on line 12 is greater than the delay (TDB) in response to a low-to-high (positive going) transition on line 12.
The invention has been illustrated using two active (dynamicall~ driven) transistors (Pl and P2). But, instead, the circuit could include a single load transistor (or other controllable impedance means) whose impedance or conductance is controlled by the voltage level on line 12. When all the inputs (Ar) are low (defining a static condition) the combination of P2 and Pl functions as a high impedance load connected between line 12 and V~D. The impedance of the load (Pl) durin~ the static condition is designed to compensate for leakage currents (from line 12) to ground and to prevent line 12 from floating. The lOâd impedance can, therefore, be very high. When an Ni transistor is turned-on, an output pulse is produced and Pl is turned-off (P2 already is off). As both Pl and P2 are off, they function as an extremely high impedance load. Following the generation of the output 1~6~3-~6 75,006 ~ ( ol tll irc~d pulse widlh, L~2 is t-lrn(~-on for a s~,ort i~rio~ ime (and Pl is also turnecl--orl) to tetminate the outp~lL p~l-ie an~ to provide a sharp trailing edge (fast returl-l to VI~D). The combll~ation of Pl and P2 then Lunctions as a low ON impedance circuit designed to very quickly restoLe the output line to its original ~static) condition. Then P2 is turned-off and Pl is again turned-on.
This is in sharp contrast to the Prior Art circuit where: a) the leading edge is restricted from falliny sharply; b) the final level of the pulse cannot reach the supply rail; and c) the trailing edge cannot return quickly to its original level.
By dynamically driving the load with a signal generated on the output line of the circuit rather than using a passive pull up transistor (or a resistor) as in the Prior Art, extremely fast operation with low average power dissipation is achieved.
Thus, in circuits embodying the invention, although the input signals (e.g. changes on address lines) are randomly applied to the sys~em, an output pulse or signal is produced very quickly after the occurrence of a change on an address line. The pulse or signal is well defined (i.e. goes from a full "low" to a full "high", or vice versa), has a sharp leading edge to define the start of the precnarge and housekeeping function, and has a sharp trailing edge to terminate the precharge and housekeeping functions and to initiate a read-out or write cycle.
In the circuit of FIGURE 5 three circuits 2a, 2b, and 2c similar to the circuit of FIGURE 2 have their respective outputs V12a, V12b, and V12c connected via lines 12a, 12b and 12c to the gate electrodes of respective inp~t transistors P41, P42 and P43. The number of address inputs (Ala to ~Xa, Alb to ANb, Al to AXc!
applied to circuits 2a, 2b and 2c need not be the same.
Yor example, in the circuit of FIGIJRE 2 a multiplicity (m) of input signals responsive transistors Ni are shown connected at node 12~ In order to minimize the 11~83~
-10- RCA 75,006 capacltallce associated with node 12 and to obtain higher speed of operation it may be advantageous to limit the number of input signals in each subcircuit (2a, 2b, 2c).
In any event, the outputs of two or more circuits of the t~pe shown in FTGURE 2 may be combined or gated in common as si~own in FIGURE 5. The WIRE-OR circuit shown in box 40 is the complementary version of the circuit of FIGURE 2.
The signal responsive transistors are transistors P4i of P-conductivity type having their conduction paths connected in parallel between VDD volts and a WIRE-O~
line 42. The dynamic load includes a transis-tor N41 (corresponding to Pl of FIG~RE 2) and a transistor N42 (corresponding to P2 in FIGURE 2) having their conduction paths connected in parallel between line 42 and ground, An inverter I4l (corresponding to Il) is connected at its input to line 42 and at its output to the gate of N41.
Three inverters Ifi2, I43 and I44 (corresponding to I2, I3 and I4) are connected in cascade between the output of I41 and the gate electrode of N42.
The circuit 40 of FIGURE 5 functions in a complementary but otherwise similar manner to the circuit of FIGUR~ 2 and need not be greatly detailed. Thusl when a negative-going pulse is produced on lines 12a, 12b or 12c a positive going output pulse is produced on output line 42. The pulse produced on line 42 may be directly connected to various portions of a subsequent circuit (not shown), or connected via a buffer to subsequent circuits.
It is evident from the circuit of FIGURE 5 that the input signals can be combined in many different ways in an effort to optimize the system response. The circuit of FIGURE 5 also demonstrates that circuits embodying the invention can easily be combined to perform comb~nation logic.
Claims (19)
1. In combination with an input signal responsive transistor having its conduction path connected between an output line and a first point of operating potential, said signal responsive transistor, when turned-on, tending to clamp said output line to said first point of potential, means for generating a well defined pulse on said output line having relatively sharp leading and trailing edges in response to the turn-on of said signal responsive transistor, comprising:
a controllable impedance load means connected between said output line and a second point of operating potential; and means responsive to the voltage on said output line coupled to said load means for:
(a) maintaining the impedance of said load means relatively high when said signal responsive transistor is OFF:
(b) switching the impedance of said load means to a very high value and substantially interrupting conduction therethrough for a given predetermined period of time when said signal responsive transistor is turned-on; and (c) switching the impedance of said load means to a very low value and enabling substantial conduction therethrough for a given time following said given predetermined period of time.
a controllable impedance load means connected between said output line and a second point of operating potential; and means responsive to the voltage on said output line coupled to said load means for:
(a) maintaining the impedance of said load means relatively high when said signal responsive transistor is OFF:
(b) switching the impedance of said load means to a very high value and substantially interrupting conduction therethrough for a given predetermined period of time when said signal responsive transistor is turned-on; and (c) switching the impedance of said load means to a very low value and enabling substantial conduction therethrough for a given time following said given predetermined period of time.
2. The combination as claimed in claim 1 wherein said controllable impedance load means includes first and second load transistors, each transistor having a conduction path and a control electrode; and wherein the conduction paths of said first and second load transistors are connected in parallel between said output line and said second point of operating potential.
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3. The combination as claimed in claim 2 wherein the conduction path of said first load transistor, when turned-on, has a higher impedance than that of said second load transistor.
4. The combination as claimed in claim 2 wherein said means responsive to the voltage on said output line coupled to said load means includes:
(a) a first means coupled between said output line and the control electrode of said first load transistor for applying to its control electrode a signal which is out-of-phase with the signal on said output line;
and (b) a second means responsive to the signal on said output line coupled to the control electrode of said second load transistor for applying to it a signal which is of the same polarity as, and delayed with respect to, the signal on said output line.
(a) a first means coupled between said output line and the control electrode of said first load transistor for applying to its control electrode a signal which is out-of-phase with the signal on said output line;
and (b) a second means responsive to the signal on said output line coupled to the control electrode of said second load transistor for applying to it a signal which is of the same polarity as, and delayed with respect to, the signal on said output line.
5. The combination as claimed in claim 4 wherein said first means includes an odd number of inverters connected in cascade between said output line and the control electrode of said first transistor, and wherein said second means includes an additional odd number of inverters connected in cascade between the control electrode of said first load transistor and the control electrode of siad second load transistor.
6. The combination as claimed in claim 5 wherein said signal responsive transistor is normally turned-on by a relatively narrow pulse.
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7. The combination comprising:
a line;
an input signal responsive transistor having its conduction path connected between said line and a first point of potential; said signal responsive transistor when turned-ON tending to clamp said line to said first point of potential;
first and second load transistors, each having a conduction path and a control electrode, said conduction paths being connected in parallel between said line and a second point of potential;
means connected between the control electrodes of said first and second load transistors and said line for applying a first signal to the control electrode of said first load transistor which is the inverse of the signal on said line and for applying a second signal to the control electrode of said second load transistor, responsive to the level on said line, of a polarity and magnitude to turn-on said second load transistor tending to clamp said line to said second point of potential a given time delay after the turn-off of said first load transistor and of a polarity and magnitude to turn-off said second load transistor which the voltage on said line subsequently rises toward said second point of potential.
a line;
an input signal responsive transistor having its conduction path connected between said line and a first point of potential; said signal responsive transistor when turned-ON tending to clamp said line to said first point of potential;
first and second load transistors, each having a conduction path and a control electrode, said conduction paths being connected in parallel between said line and a second point of potential;
means connected between the control electrodes of said first and second load transistors and said line for applying a first signal to the control electrode of said first load transistor which is the inverse of the signal on said line and for applying a second signal to the control electrode of said second load transistor, responsive to the level on said line, of a polarity and magnitude to turn-on said second load transistor tending to clamp said line to said second point of potential a given time delay after the turn-off of said first load transistor and of a polarity and magnitude to turn-off said second load transistor which the voltage on said line subsequently rises toward said second point of potential.
8. The combination as claimed in claim 7 wherein said first load transistor comprises a transistor exhibiting an ON impedance which is significantly greater than the ON impedance of said second load transistor.
9. The combination as claimed in claim 8 wherein said first and second load transistors are of one conductivity type and wherein said input signal responsive transistor is of opposite conductivity to said one conductivity type.
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10. The combination as claimed in claim 8 wherein said means connected between the control electrodes of said first and second load transistors and said line includes a first inverter connected between said line and the control electrode of said first load transistor and an odd number of additional inverters connected in cascade between said output of said first inverter and the control electrode of said second load transistor.
11. The combination comprising:
a line;
a first plurality of transistors having their conduction paths connected in parallel between said line and a first point of potential;
input signal means coupled to said first plurality of transistors for turning them on, each one of said transistors of said first plurality of transistors when turned-ON tending to clamp said line to said first point of potential;
a controllable load means connected between said line and a second point of potential;
means responsive to the voltage level on said line coupled to said controllable load means for:
(a) switching the impedance of said load means to a very high value and substantially interrupting conduction therethrough between said line and said second point of potential for a given predetermined period of time when a signal responsive transistor is turned-on;
(b) switching the impedance of said load means to a very low value and enabling substantial conduction therethrough between said second point of potential and said line for a given period of time following said given predetermined period of time; and (c) setting the impedance of said load means to a relatively high value when all of said first plurality of transistors are non-conducting.
RCA 75,006
a line;
a first plurality of transistors having their conduction paths connected in parallel between said line and a first point of potential;
input signal means coupled to said first plurality of transistors for turning them on, each one of said transistors of said first plurality of transistors when turned-ON tending to clamp said line to said first point of potential;
a controllable load means connected between said line and a second point of potential;
means responsive to the voltage level on said line coupled to said controllable load means for:
(a) switching the impedance of said load means to a very high value and substantially interrupting conduction therethrough between said line and said second point of potential for a given predetermined period of time when a signal responsive transistor is turned-on;
(b) switching the impedance of said load means to a very low value and enabling substantial conduction therethrough between said second point of potential and said line for a given period of time following said given predetermined period of time; and (c) setting the impedance of said load means to a relatively high value when all of said first plurality of transistors are non-conducting.
RCA 75,006
12. The combination comprising:
a line;
an input signal responsive transistor having its conduction path connected between said line and a first point of potential;
input signal means coupled to said input signal responsive transistor for turning it on; said input signal responsive transistor when turned-ON tending to drive the potential on said line to said first point of potential;
first and second transistors, each transistor having a conduction path and a control electrode, means connecting the conduction paths of said first and second transistors in parallel between said line and a second point of potential; and means responsive to the potential on said line coupled to the control electrodes of said first and second transistors for applying a turn-off signal to said first transistor, followed by a delayed turn-on signal to said second transistor when the potential on said line is being driven toward said first point of potential; and for applying a turn-on signal to said first transistor followed by a delayed turn-off signal to said second transistor when the potential on said line is driven towards the potential at said second point.
a line;
an input signal responsive transistor having its conduction path connected between said line and a first point of potential;
input signal means coupled to said input signal responsive transistor for turning it on; said input signal responsive transistor when turned-ON tending to drive the potential on said line to said first point of potential;
first and second transistors, each transistor having a conduction path and a control electrode, means connecting the conduction paths of said first and second transistors in parallel between said line and a second point of potential; and means responsive to the potential on said line coupled to the control electrodes of said first and second transistors for applying a turn-off signal to said first transistor, followed by a delayed turn-on signal to said second transistor when the potential on said line is being driven toward said first point of potential; and for applying a turn-on signal to said first transistor followed by a delayed turn-off signal to said second transistor when the potential on said line is driven towards the potential at said second point.
13. The combination as claimed in claim 12 wherein the ON impedance of said second transistor is significantly less than the ON impedance of said first transistor.
14. The combination as claimed in Claim 13 further including a plurality of input signal responsive transistors having their conduction paths connected in parallel between said line and said first point of potential.
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15. The combination as claimed in Claim 2 wherein said means responsive to the voltage on said output line coupled to said load means includes:
a first means coupled between said output line and the control electrode of said first load transistor for turning-off said first load transistor when said signal responsive transistor is turned-on and for turning-on said first load transistor when the voltage on said line is at or close to the voltage at said second point of operating potential; and a second means responsive to the signal on said output line coupled to the control electrode of said second load transistor for turning-on said second load transistor a given time delay after the turn-off of said first load transistor and for turning-off said second load transistor after the turn-on of said first load transistor.
a first means coupled between said output line and the control electrode of said first load transistor for turning-off said first load transistor when said signal responsive transistor is turned-on and for turning-on said first load transistor when the voltage on said line is at or close to the voltage at said second point of operating potential; and a second means responsive to the signal on said output line coupled to the control electrode of said second load transistor for turning-on said second load transistor a given time delay after the turn-off of said first load transistor and for turning-off said second load transistor after the turn-on of said first load transistor.
16. The combination as claimed in Claim 2 further including additional input signal responsive transistors having their conduction paths connected in parallel with the conduction path of said input signal responsive transistor.
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17. The combination comprising:
first and second terminals for the application therebetween of an operating potential;
an output line;
means connecting the conduction path of an input signal responsive transistor of first conductivity between said output line and said first terminal;
first and second transistors of second conductivity type, each having first and second electrodes defining the ends of a conduction path and a control electrode;
means connecting the conduction paths of said first and second transistors in parallel between said second terminal and said output line;
a first inverter connected at its input to said output line and at its output to the control electrode of said first transistor; and an odd number of inverters connected in cascade between the output of said first inverter and the control electrode of said second transistor.
first and second terminals for the application therebetween of an operating potential;
an output line;
means connecting the conduction path of an input signal responsive transistor of first conductivity between said output line and said first terminal;
first and second transistors of second conductivity type, each having first and second electrodes defining the ends of a conduction path and a control electrode;
means connecting the conduction paths of said first and second transistors in parallel between said second terminal and said output line;
a first inverter connected at its input to said output line and at its output to the control electrode of said first transistor; and an odd number of inverters connected in cascade between the output of said first inverter and the control electrode of said second transistor.
18. The combination as claimed in Claim 17 wherein the ON impedance of said second transistor is substantially less than the ON impedance of said first transistor.
19. The combination as claimed in Claim 18 wherein said odd number of inverters function to delay the turn-on of said second transistor for a predetermined time after the turn-off of said first transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US232,359 | 1981-02-06 | ||
| US06/232,359 US4404474A (en) | 1981-02-06 | 1981-02-06 | Active load pulse generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1168316A true CA1168316A (en) | 1984-05-29 |
Family
ID=22872791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000394944A Expired CA1168316A (en) | 1981-02-06 | 1982-01-26 | Pulse generating circuit |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4404474A (en) |
| JP (1) | JPS57147331A (en) |
| CA (1) | CA1168316A (en) |
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| US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
| US7234070B2 (en) | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
| TWI436371B (en) * | 2010-11-02 | 2014-05-01 | Etron Technology Inc | Wire-or matching circuit with low power consumption |
| CN112054791B (en) * | 2019-06-06 | 2023-11-21 | 台达电子工业股份有限公司 | Hybrid driving circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3772536A (en) * | 1967-09-20 | 1973-11-13 | Trw Inc | Digital cell for large scale integration |
| US3911289A (en) * | 1972-08-18 | 1975-10-07 | Matsushita Electric Ind Co Ltd | MOS type semiconductor IC device |
| US4039858A (en) * | 1976-04-05 | 1977-08-02 | Rca Corporation | Transition detector |
-
1981
- 1981-02-06 US US06/232,359 patent/US4404474A/en not_active Expired - Lifetime
-
1982
- 1982-01-26 CA CA000394944A patent/CA1168316A/en not_active Expired
- 1982-02-03 JP JP57016178A patent/JPS57147331A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US4404474A (en) | 1983-09-13 |
| JPS57147331A (en) | 1982-09-11 |
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| Date | Code | Title | Description |
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| MKEX | Expiry |