CA1167971A - External microcode operation in a multi-level microprocessor - Google Patents

Abstract

Abstract of the Invention A data processing system the central processing unit (CPU) of which is responsive to and executes microinstructions generated by the decoding of macro-instructions so as to provide one or more data processing operations. The sys-tem is arranged so that such microinstructions can be supplied to the CPU from a CPU-resident microcode decoding logic or from one or more external microcode decoding units. Each of the external units can identify a macroinstruction which it is capable of decoding and includes logic for externally providing one or more microinstructions which result from the decoding process. If an exter-nal microcode unit and the CPU-resident decode logic are both capable of such decoding operation. the external unit overrides the CPU decoding logic and con-trols the decoding operation externally. The external microcode unit includes logic for monitoring the number of microinstructions supplied to the CPU which have not yet been executed by the CPU.

Description

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This invention relates to data processing systems using microproces-sors and, more particularly, to systems which use microcode architecture and arecapable of responding to e~ternally supplied microcoded instructions by utili-zing unique interface techni~ues thereorO
Data processing systems have generally been developed to provide sys-tem configurations which range from compact single-board micro-computers ~o morecomplex high per~ormance mini-compute~s. Such systems use microcode architec-ture in which macroinstruc~ions are sui~ably decoded so as to provide access to a microinstruction or to a sequence of more than one microinstruction obtained from a suitable data store thereof.
In order to reduce the data storage space required for the microin-str~uctions and to avoid handling a large number of "wide" instruction words, certain microcode systems have utilized multi-level, in most cases "two-level", microcode store techniques, as opposed to one-level microcode stores, as is known in the art. One such two level microcode system which is used to increase the power of a conventional two-level microcode technique has been described in Canadian Patent Applicatlon Serial No~ 370,565, filed ~ebruary 10~ 1981 and entitled "Data Processing System" as filed by Bernstein et al. and assigned to Data General Corporatlon of Westboro, ~assachusetts.
~ In accordancè with the system described therein, the microcontrol store is formed as an "orthogonal" store in which a firstJ or "vertical", micro-control store provides a "narrow" microinstruction word portion having one fieldcomprising a selected number of vertical microinstruction bits for selecting oneof a plurality of second, or "horizontal"3 microinstructions from a second level~
or horizontalj microcontrol store3 one or more "modifier" fields, as described in such application, and a sequ0ncing field for presenting the address of the ~.
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next ~i.eO~ each successive) vertical microinstruc~ion in a sequence thereof.
As described therein, vertical microinstructions (microcodes) can be fetched either from a CPU-resident vertical control ROM or from one or more external microcontrollers via one or more external microcontroller interface units. The external microcodes can be obtained a~ any one time from one of the plurality of external microcontroller units by the use of suitable time-multiplexing tech-niques using a *ime-multiplexed microcode bus.
While such system has provision for supplying external microcode infor-mation utilizing appropriate software, for example, the most effective way for providing such external microcode information is descri~ed with reerence to the invention disclosed herein. Accordingly, in order ~o achieve effective use of both the CPU-resident microcode information and the external microcode informa-tion, the invention provides for sui~able inter~ace logic which permits the most effective control of the transfer of exteTnal microcode information from an ex-ternal mlcrocode unit. While the invention is applicable to such multi-level mlcrocode systems, its use is not limlted thereto and the principles thereof are -also applicable to~single-level systems.
In accordance with the invention, a unique microcode control interface unit is utilized wherein every macroinstruction supplied, for example, by sof*-nare to the system is simul~aneously decoded by bo~h the CPU-resident microcode control unit and the microcode interface units. A subset of the operational code (OP-CODE) in the macroinstruction identifies which type of microcode control unit ~i.e., an external mlcrocode unit or an internal, i.eO, a CPU-resident, unit) is required to perform the decoding operation in order to produce the required microinstruction or sequence of microinstructions. If the OP-CODE identifies a situation in which both an external and an internal microcode control unit are

-2-i capable of performing the decoding operation, appropriate lagic is provided bythe selected external unit so that the external microcode controller can over-ride the CPU-resident controller and, therefore, can provide the required deco-ding operation.
The external microcontrol interface unit includes logical capability for determining the successive addresses of successive microinstructions in a sequence thereof within the external interface unit itself without the need for any logical operations to be performed by any CPU-resident control logic units.
The external microcontrol interface unit also has unique logic for monitoring the transfer of microinstruc~ions from the external unit to the CPU
and for monitoring the execution thereo by the CPU so that, at any point in time, the external microcontroller unit keeps track of the diference between how many microinstructions have been transferred and how many of such micro-instructions have been executed by the CPU, and, accordingly, how many of the transferred microinstructions have yet to be executed.
Briefly summari~ed, the present invention provides a data processing system comprising a central processor unit including means responsive to a macroinstruction for decoding said macroinstruction to produce a sequence of one or more microinstructions; and processing logic means responsive to said microinstructions for executing said microlnstructions to provide one or more data processing operations; said system further comprising one or more external microcode control units, each including means responsive to a macroinstruction received from said central processor unit for decoding said macroinstruction to produce a sequence of one or more microinstructions; means responsive to sald decod m g means for transmitting said one or more microinstructions to said central processor unit for execution thereby; and said decoding means further . . .
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including means responsive to a macroinstruction received from said central processor unit for determining whether said macroinstruction is one which is to be decoded by a selected one of said external microcode control units or one which is to be decoded by said central processor unit.
The invention can be described more fully with the help of the accom-panying drawings wherein:
Figure 1 shows a broad block diagram of an overall system which utilizes the invention;
Figure 2 shows a more specific block diagram of an exemplary external microcontroller interface unit as used in the system of Figure l;
Figure 3 shows a more specific block diagram of exemplary sequencing logic used in the external microcontroller interface unit of Figure 2; and Figure 4 shows a timing diagram helpful in understanding an exemplary operating sequence of the external microcontroller interface unit of the inven-tion.
An overall system which utilizes the external microcontroller inter-face unit of the invention is shown in Figure 1 wherein a microprocessor unit, identified as a central processor unit or CPU 10 in the figure, is interconnec-ted via an appropriate system bus 11 with a memory system 12, one or more sys-tem input/output ~I/O) units 17, I/O interface units 14 and 14A for interfacing I/0 units via different I/0 bus means 15 and 15A, respectivelyJ and one or more external microcontroller (XMC) interface units 13. In a particular embodiment of the system, for example, the system bus 11 may be in the form of a 16-bit parallel system bus while 16-bit microcode inputs from an external microcontrol-ler unit 13 can be transmitted to the~CPU in a time-multiplexed fashion via an intermediate 8-bit bus 13A and the 8-bit microcode bus 16. Further 16-bit '``

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intermediate system buses llA are provided from the main system bus 11 to the external microcontroller units 13 as shown.

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The system o~ Figure 1 is generally described in the a~orementioned Canadian patent application of Bernstein et al. and the particular operation of the CPU and its operatlonal relationship with the memory and various I/O units and buses is described therein in detail. Pur~her explanation o such detailed operation is not necessary in order to describe this invention and, accordingly, reference may be made to the previously filed Canadian application~ if necessary for an understanding ef the overall system operation. For convenience the in-vention is described as used in such multi_level microcode system although, as mentioned above, its use is not llmited thereto.
In systems which utilize multi-level ~e.g., ~wo-level~ microcode archi-tecture (as in the above referred to application~ and which provide for the supplying of external microcode information, as in the system of Figure 1, the latter information must be supplied through~one or more suitable interface units such as shown by units 13 of the figureO In conventional systems capable of utilizing external microcode operation, the CPU normally requires appropriate logic which responds to software for identifying the macroinstruction to be de-coded as one which requires decoding either by the internal microcode architec-ture or b~ the external microcode architecture. Once the CPU has identified the macroinstruction as requiring an external microcode decoding proced~ure, it supplies the macroinstruction to the designated external microcontroller unit whlch then proceeds to decode the macroinstruction so as to provide ~he initial microinstruction via the microcode bus.
In many such conventional systems once the initial microinstruction has been provided to the CPU rom an external micrccode unit, the CPU then uti-llzes its`own internal se~uencing logic and microcode control store to provide ~he subsequent microinstructions of ~he particular sequence required by the .

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decoded macroinstruction. Control of the macroinstruction decoding process, as well as the process for determ~ning the address Qf each subsequent mlcro~nstruc~
tion required in the sequence~ e~ectlvel~, thereore, resides in the CPU
In contrast, the external microcontrol interface unit of the invention permits control of the macroinstruction decoding and the sequencing of the micro-instructions to reside fully in the external microcontroller unit itself so as to provide a more effective and efficient use of an instruction register "pipe-lining" process which is conventionally utilized in the CYU of such a two-level microcode s~stem of the type described above.
Figure 2 shows an exemplary external microcontroller interface (X~C) unit 13 having a configuration which would be utilized in each of the XMC units 13 shown in Figure 1. In such exemplary unit a macroinstruction is supplied under control of CPU via an intermediate s~stem bus~ llA,~such macroinstruction being defined by a suitable 16-bit word, as shown.
The macrolnstruction is supplied to the X~C instruction register 20 which supplies such macroinstructlon, in a pipe~lined mannerJ LO a decode/matrix unit ~1 which utilizes a sultable lnstruction program logic array ~IPLA~ matrix providing for appropriate decoding of the macroinstruction to produce an initial ~icroinstruction. Such decoding, for example, is of the same nature as is dis-cussed with reference to the CPU-resident decode control PLA unit which is dis-closed in the aforesaid application. The initial microinstruction includes the horizontal address bits field ~ADRH) and the two vertical modifier fields (Vl~
V2~ J the six~bit horizontal address and each of the four-bit vertical modifiers being supplied to the CPU via the X~C bus 16 and intermediate bus 13A through an appropriate multiplexer and buffer unit ?2~ The multiplexer unit supplies such ields as part of two time~multiplexed eight-bit bytes as depicted at the output ~6-. I

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thereof, The IRLA decode unit 21 also supplieg a two-bit "ini~ial next address mode" ~INAM) signal vla a nex~ address ROM unit 23 to the multipl0xer and buffer unit 22 so that a total o~ 16-bits ~ADRH, Vl, V2 and INAM~ are supplied via multiplexer and buffer unit 22 to bus 13A for the initial microinstruction.
The IPLA decode/matrix unit 21 also supplies a next address mode ~NEXT) field of 10 bits and an initial address control ~IADRC) field of 10 bits to the XMC sequence logic unit 24, thc structure and operation of which is explained in more detail with reference to Figure 3.
~ he sequence unit 24 then con~rols ~he supplying of a sequence of hori-lQ ~ontal address and vertical modifier fields via a control program logic array decode ~CPLA) matrix unit 25, as discussed below, each of the sequence of hori-zontal addresses and vertical modifie~s then belng appropriately supplied in sequence via multiplexer/buffer unit 22 to the CPU, following the prior supplying ~hereto of the initial address and modifiers directly from the IPLA decode/matrix unit 21. During a sequence the next address can be supplied to sequence logic 24 from a source external to the microcontroller unit 13 via a dispatch register 26, such addresses being dispatched to the external microcontroller unit 13 via system bus 11 and interconnecting X~C bus llA under the control of appropriate dispatch control logic 27. Suitable timing logic unit 28 is utilized to provlde suitable timing control signals to the various components of the external micro-control unit 13.
Figure 3 depicts in more detail the elements of the external microcon-troller (XMC) sequence logic unlt 24. As can be seen therein, an appropri.ate multiplexer 30 supplies an address input to a program counter 31, such input being selected from either the IRLA decode unit 21 (the IADRC ~ield), the CPLA
matrix unit 25 ~the ADRC field), or the dispatch register 26 ~the DREG field).
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Alternatively, such address can be supplied to program counter 31 as a feedback input from a last in/first out memory s~ack 32. An appropriate control signal ADEC for the multiplexer unit is supplied ~rom an IPLA control logic unit 29 (see Figure 2).
When a request to decode a macroinstruction is issued by the CPU of Figure 1, each macroinstruction includes within it the information which deter-~ines whether such macroinstruction is to be decoded by the internal, i.e., the CPU~resident, decoding uni~s of the processor 10 or by an external microcontrol-ler unit 13. Thus, each macroinstruction is arranged so that i~ has a unique bit pattern which can only be decoded by either the internal decoding units of the processor or the decoding units of a specifled external microcontroller in-terface unit. In certain cases where a particular external microcontroller unitJ
such as shown in Figures 2 and 3, recognizes the bit pat~ern of the macrolnstTuc-tion from the instruction register pipe line as e requiring decoding by itself, the IPLA decodejmatrix`unit 21 indicates such rècognition by asserting a single bit MYTNS ("my instruction") which is supplied to the IPLA control logic 29 to cause the assertion of an ACK ~'tacknowledge") signal for supply to the proc0ssor.
The latte~ signal indicating that the macroinstruction which has been requested for decode ~via a previous assertion of a suitable REQ ("request") signal) will be decoded b~ this particular microcontroller unit.
Should both a specified external microcontroller unit 13 and the CPU-resident decoding units of the processor recognize a macroinstruction bit pat-tern as being one which it is capable of decoding, an acknowledge ~ACK) signal , from the microcontroller mterface unit is alwa~s interpreted by the cent~al processor unit as requiring external microcode decoding, even if the CPU-resident processor decoding units could decode such macroinstruction. Accordingly, de-..... . .

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coding b~ the external unit prevails. Such operation is designated as an "exter-nal microcode override" condition, If no ACK signal is asserted from any exter-nal microcontroller unit, ~he processor utllizes iks o~m internal macrocode decoding units, as discussed in the aforementioned application of eernstein et al, or performing the macroinstruction decoding operation.
In addition, the assertion of a MYINS signal, together with the asser-tion of an appropriate "kri-sta~e enable" ~TSE) signal, will produce a "tri-state" (TS) signal from the IPLA control loglc 29 for con~rolling the operation of the multiplexer/buffer register 22. In each external microcontroller uni~
13, the TS signal is not asserted unless the M~INS signal has been asserted by the IPLA decode/matrix unit 21 to indicate that the particular microcontroller unit 13 in question has been selected for the decoding operation. Accordingly, the XMC bus 16 can be driven only by one external microcontroller unit at a timeso that bus burn-out problems that may occur if multiple external units are attempting to drive the hus simultaneously are avoided.
O~ce the ~XINS signal has been asserted, the IPLA control logic 29 provides an appropriate decode control signal ~ADEC) which in effeck represents a basic initiation signal for operation of the external microcontroller unit so as to permit appropriate decoding of the incoming macroinstruction to proceed.
The macroinstruction is initially decoded by the IPLA decode/matrix unit 21 which receives 32 bits comprising the 16 bit macroinstruction word and the 16 inversion bits thereor via the instruction register pipe line system 20, such system for handling incoming information in a pipe-lined fashion being well known to the art~ The decoded macroinstruction word then selects the cor-rect initial microinstruction word at the decoded address from the IPLA storage matrix which comprises a plurality of stored microinstruction words. The initial ~. ~

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microinstruction uord from the I~LA ma~rlx comprises the following fields as shown below.
6 ~ 4 1 10 10 2 1 __ L ADRH ¦ V1 ¦ V~ 1D~C ¦ IAD~C ¦ NE~r ¦ CNAMX ¦ ~INS

INITIAL r~IcR,oINsTRucTIQN WORD ~LDS

As can be seen, the microinstruction ~ord is 38 bits wide and includes 8 fields.
The ADRH, V1, and V2 fields are effec~lvel~ the same as those described in the aforesaid application o~ Bernsteln e~ al. with reference to the horizontal ad-dress and vertical modifier fields of khe initial microinstruction decoded by the ~PU~resident decoding uni~s, Such fields are appropriately supplied to the horizontal decoder and to the vertlcal modi~ier unit5 respectivel~, in the man-ner discussed in the previously ~iled application. The ~YINS bit has been dis-cussed above.
The DEC field merely indicates which operation mode will be used with respect to ~he next address in the microinstruction sequenceO In the case of the initi~al microinstruction obtained rom the IPLA matrix, the DEC bit signifies either that the next operating mode will require a decoding of the next micro-instruction of a sequence thereo or will require a call for a new macroins~ruc-tion (e.g., if there is only a single microinstruction in the current sequence).
The DEC bit and the four CNAM bits from the CNAM ROM 38 ~Figure 3~ generate the NAM bits vi`a next address logic unit 23, which are transmitted to the CPU with the ADRH, V1 and V2 ields to indicate to the CPU the four operations discussed below. The IADRC field provides the address of one of the microinstructions te~g~, one of 102~ microinstructlons m an;exem~lary embodiment) which are stored in the CPLA matrix unit 25. The selected microinstruction may either be executed next following the execution of ~he current microinstruction, or not, depending .

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on the interpretation of the next address mode ~AM~ ~ield or the next address mode extensions ~CNAMX) field, as discussed below.
The CNA~X field sets a plurality of appropriate flags ~FLAG A, FLAG B
or FLAG C) to their initial state in accordance with the following table:
NOP FLAG A-FLAG B=FLAG C=O
SET A ~LAG A-l, FLAG B-~LAG C-0 SET B FLAG B~ LAG A~LA~ C~0 SET C ,~LAG C=l, ~LAG A_E~LAG B-0 The next address mode (NA~ field indica~es whether the external micro-controller sequencing operation should con~inue with the fetching and execution af the next microinstruction of the sequence or whether it should continue to re-execute the same vertical modifiers in the currently executing microinstruc~
tion in accordance with whether the NAM field indicates a true repeat ~TREPT~ ora false repeat ~PREPT~ condition. The NA~ field further determines whether or not a decode operation should take place as discussed with reference to the vertical sequence unit of the processor as discussed in the aforesaid Bernstein et al. application~ The NAM field conditions are summarized as follows:
NEXT Continue fe~ching and executing microcode TRERT If SKIP-l, re-ex0cute vertical, else NEXT
FREPT If SKIP=0, re-execute vertical, else NEXT
DECODE Same as in CPU-resident vertical sequencer The NEXT field points to ~n address of one of the microinstructions in the CPLA. Such pointer provides the value of the control program counter subse-quent to the current program counter content ~i.e., CPC~l in Figure 3) which is needed by the CNAM micro-order CA~ The CPC~l is not otherwise available with-out the NEXT field since the IPLA decode/matrix unit 21 is not addressed by the ~11 -' .
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control program counter ~instead it is ~he IPLA which initialiæes the control program counter). Thus, the NEXT field in efect pushes a return to the stack ~Pigure 3) so that the s~stem knows ~here to return after a sub-routine has been executed.
Once the initial microinstruction has been decoded and the NAM field indicates that the next microinstruction should be fetched and executed, the next microinstruction, and each subsequent one o a sequence thereof, is supplied by the CPLA matrix unit 25 which selects a microinstruction a~ the selectcd ad-dress therein. The microinstruction that is selected supplies ~he ADRH, Vl and V2 ~ields to the output multiplexer/buffer unit ~2 and, thence, to the external microcode bus 16. The complete field representation for a microinstruction ob-tained from the CPLA matrix unit 25 i9 shown belo~:

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AD~I Vl ¦ V2 CNAM ¦ A~RC CNANX

CPLA MICROINSTRUCTION WORD ~IELDS
. _ _ The ADRHj Vl and V2 fields o~ the 31 bit CPLA microinstruction wordare as discussed above with reference to the IPLA microinstruction word and supply the horizontal address and vertical modifier fields to the processor via microcode bus 16. The ADRC field provides the address of one of the microin-structions in the CPLA matrix unit 25. Such microinstruction may or may not be executed nextdepending on the interpretation of the CNAM and CNAMX fields, the ADRC field specifying both unconditional and condi~ional branch addresses which are to be used in determining the~new control program counter tPC) value.
The CNAM field is a four bit field which specifies one of the following 14 encodings.
JUMp CpC~A~RC
RLNEXT PRE~ADRC J CpC~CpC~l . ~
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~REPT J~p ~REPT JUMP
DECODE STOP S~NPING X~C MICRQCOD~ TO TH~ CPU
CALL PUSH CPC~l 0NTO SUBROUTINE STACK, THEN JU~P
RTRN POP SUBROUTINi~ STACK INTO CPC
TJU~P IF C0NDal, T~E~ JUMP, ~LSE CPC=CPC~l j~JUMP IF COND=0, T1lBN JU~P, EhSE CPC=CPC~l TCALL IF COND~l, THEN CALL, ELSE CPC=CPC-~l FCALL IF COND=0, THEN CALL, ELSE CPC=CPC~l TRTRN IF COND=l~ THEN RTRN, ELSE JUMP
FRTRN I~ CONDaO, ~HEN RTRN, ELSE JUMP
RJUMP CPC=DREG
The first 7 encodings are unconditionals while the rest are condi-tionals~ which condltions are specified b~ the CNAMX field discussed below. In the par~icular embodiment shown, the subroutine stack (shown in Figure 3) is four deep ~stacks ~-3) so that only four nested subroutine calls are possible.
The DREG refers to the dispatch register 26 shown in Figure 2.
The CNAMX ield has 8 encodings ~or ~oth unconditionals:and condition-als as follows:
UNCONDITIONAL
NOP NO OPERATION
CLRX FLAG A=o~ FLAG Ba0, FLAG C=0 SET A FLAG A=l SET B FLAG B=l SET C ~LAG C=l CLRA : FLAG A~0 .. .
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.' ~ '' ' , ' CLRB PLAG BqO
CLRC FLAG C=O
CONDITIONAL
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~AI~ O COND-SKIP
~AI~ 1 COND-SKIR
~AIT 2 CON~SKIR
~AIT 3 COND~SKIR
~LAG A CON~_PLAC A
~LA~ B COND-FLAC B
10 PLAG C CO~D-~LAG C
In the conditional made, waiting ~Wait p-Wai~ 3~ is necessar~ due to the delay bet~een the X~C microlnstructlon fetch by the X~C, ~he X~C microin-struction fetch b~ the CRU, the target horizon~al~s execution by the CPU, and the receipt of SKIP by the X~C unit, or the external loading of the dlspatch register 26. Waiting is not necessary ~hen an~ flag is~specified because the flags are implemented by the XMC unit and are immediately available.
The HTBEC (horizontals~to~be~executed) counter 37 indicates how many microinstructions have been sent to tha CPU but have not yet been executed. The HTBEC counter is incremented by the ACK signai, is decremented by the ~IOREX
signal and is cleared by the ADEC signalO The contents thereof are compared to ;the WAIT request signal from the CNAMX RO~ 35 in the flags/condi~ion logic 36 to assurè that the SKIP signal iS returned for the micro m struction of in~erest ~as discussed in more detail below wi~h respect to the timing diagram of Pigure

4). The flags/condition logic 36 asserts a HOLD signal to hold the operation of the program counter 31 until the above_mentioned comparison indicates that the appropriate SKIP signal has been received. When the HOREX signal for the I ~

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pa~ticular microinstruction of in~er~s~ ~s received in phase II o~ a ~ycle, the SKIP signal for ~ha~ microinstruc~ion ls r~turn~d ln phase I of the follow:ing cycle.

In order to understand the opera~ion of the system shown in ~igures 1-3 it is helpful to set orth a typlcal sequence of ope~ations performed there-by as depicted wlth reference to the ~xemRlary signal timing diagrams shown in Pigure 4 and Chart I shown belo~O Figure ~ depicts various key signals which are asserted durîng the exemplar~ opera~ion ~and shown on ~igures 2 and 3) while Chart I depicts the s~uence o~ s~eps performed in the exemplary opera~ions.
CHART I
APR CNAM CNAMX C~MMENT
:
A: TST NEXT - THIS INSTRUCTION ~ETCHEP PRO~ IPLA
B: MOV NEXT THIS INSTRUCTION ~ETCHED ~RO~ CPLA
: C: ~o~ ~JUMP/J WAI~ 1 TH}S BRANCHES TO J IF TST IN A WAS PALSE
D: TST ~JUMP/W WAIT 3 THIS ~RANCHES TO W IF TST IN D WAS FALSE
E: MOV NEXT THIS INSTRUCTION WILL NOT BE EXECUTED

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JiMOV NEXT - THIS INSTRUCTION WILL NOT BE EXECUTED
I . I

M~V NEXT ~ P ~ILL RRANCH TO HERE
X:~V NEXT . ~ THIS INST~UCTION ~TCHEP ~R~ CRLA
M~Y NEXT ~ THIS INsTRucTIQN pETCHED ~R~M CPLA
z~MQY NEXT ~ THIS ~NSTRUCTI~N pETCHE~ ~RO~ CPLA

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, Each of the CLOCK cycles has two phases ~I and II), a sequence of 15 cycles being shown in the example depicted. Initially, in the example shown~
the CPU requests a macrocode decode operation M by asserting a MACR signal t~
"macrocode~' request) ~uring phase II of cycle 1, immediately followed by a MICR
signal (a "microcode" request) during phase I of cycle 2. If the macrocode is one which can be handled by the par~icular external microcontroller unit, such unit decodes the macroinstruction and asserts its ACK signal to show performance of the decode operation so as to produce the initial microinstruction A at the XMC buso As depicted in Figure 4 such microinstruction is placed on the bus in two portions Al and A2 shown at the C bus at phase II of cycle 2 and at phase I
of cycle 3, while acknowledging the decoding thereof, as mentioned above, by asserting the ACK signal at phase II of cycle 2.
As can be seen in Chart IJ such microinstruction is a test instruction and is fetched from the IPLA decode/matrix unit 21. If the DEC field does not indicate that the decoding of a new macroinstruction is required (as, for exam-ple, when the currently decoded macroinstruction contained only a single micro-instruction), the next microinstruction B is fetched from the CPLA matrix unit 25. Microinstruction Al, A2 is sent on the X~C bus to the CPU for execution while the ~rBEC counter is incremented by "1" to show that a microinstruction has been sent to the CPU for execution but has not yet been execu~ed.
When the next microinstruction B has been fetched from the CPI,A it is ackno~ledged in phase II of cycle 3 and transmitted to the CPU, the ~rBEC being again incremented ~by:l) to "2" at phase I of cycle 4.
The next microinstruction C is then fetched from the CPLA and trans-mitted to the CPUD While this operation would normally increment the HTBEC to "3", by this time the first microinstruction A has been executed and the asser-: -16-.

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tion of the HOREX ~horizontal execu~ed) signal rom the CPU simultaneously decre-ments the IITBEC by 1 so that lt remains at "2".
The CNAMX ROM 35 controls the extension of the time before the next microinstruction can be fetched. Thus, during microinstruction C the CNAMX ROM
asserts a ~AIT value of 1 ~see Char~ I~ which together with the count of the HTBEC and`the ACK signal de~ermines whether the program counter should be held in its current state ~i.e., whether a HOLD signal should be asserted - see pigure 3). If microcode is currentl~ being sent (an ACK is asserted~, the pro-gram counter is held in its current state if ~he WAIT value plus the HTB~C
count is equal to or greater than 30 If microcode is not currentl~ being sent (no ACK is asserted), the program counter is held in its current state if the W~IT value and the HTBEC count is greater than 3. In the example of Chart I and Pigure 4,~the sum of the WAIT value and the HTBEC count during phase II of cycle 4 is equal to 3 and the ACK is present so tha~ the program counter is held in its current state. Durlng phase II of cycle 5, since an ACK is not present and such sum is no~ greater than 3 the program counter is allowed to change from microins~ruction C to microinstruction D.

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In accordance with microinstruction C, the test which is made in micro-instruction A determines whether the microprogram jumps directly to microinstruc-tion J ~when the test is "False") or whether the next sequential microins~ruction D is to be used ~when the test is "True"). In the particular example shown, the SKIP signal defines the test status (SKIP is "true" when high and "false" whe~
ow) and, as shown, is high (true) for microinstruction C. Accordingly, thesequence of operations proceeds to the next microinstruction D of the sequence.
Microinstruction D is then fetched after the above one cycle delay, at which time microinstruction B has been executed so that assertion of the HOREX
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~ ~ ~i'7~3'7 si~nal fr~m the CPU decrements the HTB~C ts "1".
Microinstruction ~ asserts a ~AI~ 3 signal and the sum of the WAIT
value and the HTBEC count is greate~ than 3 thrQugh phase II of cycle 9 so that the program counter is held in its current state through cycle 9, the HOLD signal producing a delay of 3 cycles to permit the test to be made in microinstruction D. Such test determines whether the micr~program jumps to microinstruction W
tSK~P is false) or whether the next se~uential microinstruction E is to be fetched for use ~SKIP is true). In the particular example shown, the test (SKIP
signal) at the end of the three cycle ~ait i5 shown to be false ~SKIP is low~, so that a branch is made to microinstruction W. ~eanwhile HT~EC is decremented to zero to reflect the execution of microinstruction D. The sequence of opera-tions then proceeds with microinstructions W, X, Y, Z . . . as shown.
As mentioned above, the microinstructions are transmitted in the XMC
bus in tl~ 8-bit b~tes (e.g., Al and A2 or microinstruction A) during separate phases of the timing cyclesO The mitial microinstruction A is obtained from the IPLA unit 21, while all subsequent microinstructions are obtained from ~he CPLA unit ~5. The HTBEC shows at all times how many horizontal microinstructionshave been transmitted from the X~C unit ta the processor and are still to be executed by the processor.
While the above description dlscusses the configuration and operation o a particular exemplary embodiment of the invention, modifications thereof ~ithin the spirit and scope o the invention will occur to those in the art.
Hence, the invention is not to be limited to the specific embodimen~ shown and described herein except as defined by the appended claims.

~8-.., ,i - :

Claims (13)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A data processing system comprising a central processor unit inclu-ding means responsive to a macroinstruction for decoding said macroinstruction to produce a sequence of one or more microinstructions; and processing logic means responsive to said microinstructions for executing said micro-instructions to provide one or more data processing operations; said system further comprising one or more external microcode control units, each inclu-ding means responsive to a macroinstruction received from said central processor unit for decoding said macroinstruction to produce a sequence of one or more microinstructions; means responsive to said decoding means for transmitting said one or more microinstructions to said central processor unit for execution thereby; and said decoding means further including means respon-sive to a macroinstruction received from said central processor unit for determining whether said macroinstruction is one which is to be decoded by a selected one of said external microcode control units or one which is to be decoded by said central processor unit.

2, A data processing system in accordance with claim 1 wherein each said external microcode control unit further includes control means responsive to said decoding means for assuring that said macroinstruction is decoded only by said selected external microcode control unit when said macroinstruction is capable of being decoded either by said selected external microcode control unit or by said central processor unit.

3. A data processing system in accordance with claim 1 wherein each said external microcode control unit comprises initial macroinstruction decode means responsive to a macroinstruction for decoding said macroinstruction to produce an initial microinstruction; means for transmitting first selected fields of said initial microinstruction to said central processor unit for execution thereby; further decode means responsive to other selected fields of said initial microinstruction for providing a sequence of one or more successive microinstructions; and means for transmitting first selected fields of said successive microinstructions to said central processor unit for execu-tion thereby.

4. A data processing system in accordance with claim 3 wherein control means of each said external microcode control unit further includes means responsive to said decoding means and to said central processor unit for indicating the number of microinstructions which have been transmitted to said central processor unit and which have not yet been executed by said central processor unit.

5. A data processing system in accordance with claim 4 wherein said first selected fields of said initial microinstruction include one or more execution fields for use by said central processor unit in executing said initial micro-instruction; and a next address mode field for indicating whether the sequence of microinstructions transmitted to said central processor unit from said external microcode control unit is to be continued or is to be completed upon execution of the current microinstruction.

6. A data processing system in accordance with claim 5 wherein said external microcode control unit includes program counter means for supplying an address to said further decode means of the next successive microinstruction of a sequence thereof;
stack means for storing one or more microinstructions for use in a sub-routine execution;
and further wherein said other selected fields of said initial micro-instruction include a first address field capable of providing an address for supply to said program counter means;
a second address field for providing a pointer address in said further decode means for identifying an address in said stack means which provides an incremented value of said program counter means.

7. A data processing system in accordance with claim 6 wherein said ex-ternal microcode control unit further includes means capable of providing an externally generated address for supply to said program counter means.

8. A data processing system in accordance with claim 7 wherein the first selected fields of said successive microinstructions from said further decode means include one or more execution fields for use by said central processor unit in executing said successive microinstructions; and other selected fields of said successive microinstructions include a first address field capable of providing an address for supply to said program counter means, and further including means for selecting for supply to said program counter means a first address, field from said initial microinstruction, a first address field from one of said successive microinstructions, or said externally generated address.

9. A data processing system in accordance with claim 8 wherein said other selected fields of said successive microinstructions include a next address mode field for determining whether the next successive microinstruction in a sequence thereof is to be executed by said central proces-sor unit, whether a portion of said execution fields are to be reexecuted by said central processor unit, or whether a new macroinstruction is to be decoded by said data processing system.

10. A data processing system in accordance with claim 9 wherein said other selected fields of said successive microinstructions include a control field for determining whether the execution cycle of a micro-instruction is to be extended beyond the normal execution cycle therefor.

11. A data processing system in accordance with claims 1 or 2 wherein said transmitting means includes bus means interconnecting said external micro-code control unit and said central processor unit; and driving means for placing a microinstruction produced by said external microcode control unit on to said bus means for transmission to said central processor unit;
and further wherein each said external microcode control unit includes means for activating its own driver means only when said external microcode control unit has been selected to decode said macroinstruction and to provide said sequence of one or more microinstructions.

12. A data processing system in accordance with claim 2 wherein each said external microcode control unit comprises initial macroinstruction decode means responsive to a macroinstruction for decoding said macroinstruction to produce an initial microinstruction;
means for transmitting first selected fields of said initial microin-struction to said central processor for execution thereby;
further decode means responsive to other selected fields of said ini-tial microinstruction for providing a sequence of one or more successive micro-instructions; and means for transmitting first selected fields of said successive micro-instructions to said central processor unit for execution thereby.

13. A data processing system in accordance with claim 12 wherein each said external microcode control unit includes means for indicating the number of microinstructions which have been transmitted to said central processor unit and which have not yet been executed by said central processor unit.